Monitoring Method for Fabrication Process of Semiconductor Gate Structure Layer

Abstract

The present invention provides a monitoring method for a semiconductor gate structure layer manufacturing process, belonging to the field of semiconductors. The monitoring method for the semiconductor gate structure layer manufacturing process includes providing a control wafer and testing to obtain the work function W of the control wafer SI ; non-contact method for testing the dark-field surface contact potential difference V of the control wafer CPDDARK ; non-contact method for testing the bright-field surface contact potential difference V of the control wafer CPDLIGHT ; based on the work function W of the control wafer SI , the dark-field surface contact potential difference V CPDDARK and the bright-field surface contact potential difference V of the control wafer CPDLIGHT to calculate the relative work function of the gate structure layer of the control wafer. By accompanying the patterned wafer to be monitored with the control wafer, the present invention obtains the relative work function of the gate structure layer. When the error between the absolute work function and the relative work function exceeds a certain range, it can be determined that the film quality does not meet the expectation and the process parameters need to be adjusted. By using the control wafer instead of the short-range wafer, wafer scrapping is avoided, which not only reduces the monitoring time but also reduces the monitoring cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for monitoring the manufacturing process of a semiconductor gate structure layer. Background Art

[0002] The work function is an important parameter for the selection of the gate material of a semiconductor device. The work function mainly affects the threshold voltage of the semiconductor device, thereby affecting the performance of the semiconductor device. Therefore, in the field of semiconductor manufacturing, it is particularly important to accurately detect the work function of the gate structure of the fabricated semiconductor device.

[0003] In the prior art, taking the gate of a semiconductor device made of a metal layer as an example, when measuring the work function, a wafer with a patterned gate structure needs to be manufactured by a photomask. After the high-k metal gate short process, tungsten metal coating, and corresponding patterning (lithography and etching) processes, the work function of the gate structure can be measured by the contact capacitance method. When using the contact capacitance method for measurement in the laboratory, one end of a probe is inserted into the area where tungsten metal is located, and the other end of the probe contacts the metal chuck to obtain capacitance and voltage values. When a positive DC bias voltage is applied, the charges between the metal layer and the semiconductor layer are attracted to the metal layer side, forming an accumulation region, and at this time, the capacitance reaches the maximum value. As the bias voltage decreases, the majority carriers are repelled from the gate oxide interface, forming a depletion region, and the capacitance value gradually decreases. When a negative DC bias voltage is applied, the charge carriers deviate the farthest from the oxide layer, forming an inversion region, and at this time, the capacitance value reaches the minimum value, so that the capacitance value curves at different voltages can be obtained. Comparing the obtained capacitance value curves at different voltages with the standard capacitance-voltage curve, the work function of the gate structure can be obtained. However, the existing test method takes a long time because the entire gate structure manufacturing process needs to be completed. The wafer used to complete this contact capacitance method measurement cannot be used anymore, so it also needs to be scrapped.

[0004] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background art of this invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for monitoring the manufacturing process of a semiconductor gate structure layer, so as to solve the problems that the existing gate structure takes a long time to measure the work function and the wafer needs to be scrapped.

[0006] To solve the above technical problems, the present invention provides a method for monitoring the manufacturing process of a semiconductor gate structure layer. The gate structure layer includes a gate layer and a gate dielectric layer, and the gate dielectric layer is located between the channel of the semiconductor device and the gate layer. The monitoring method includes:

[0007] Provide a control chip and test to obtain the work function W of the control chip SI ;

[0008] Together with the patterned wafer to be monitored, form the gate dielectric layer and the gate layer on the surface of the control chip in sequence, and omit the patterning processes of the gate dielectric layer and the gate layer involved in the patterned wafer, wherein the doping type of the gate layer is different from that of the control chip;

[0009] Test the dark-field surface contact potential difference V of the control chip by non-contact method CPDDARK ;

[0010] Test the bright-field surface contact potential difference V of the control chip by non-contact method CPDLIGHT ;

[0011] Based on the work function W of the control chip SI , dark-field surface contact potential difference V CPDDARK and bright-field surface contact potential difference V CPDLIGHT to calculate and obtain the relative work function of the gate structure layer of the control chip.

[0012] Preferably, the calculation method includes:

[0013] The relative work function of the gate structure layer = work function W SI -q surface barrier V SB , where q is the charge constant,

[0014] Surface barrier V SB = dark-field surface contact potential difference V CPDDARK - bright-field surface contact potential difference V CPDLIGHT .

[0015] Preferably, the gate layer is a metal layer and the gate dielectric layer is a high-K dielectric layer.

[0016] Preferably, the work function W of the control chip SI is measured by the non-contact Kelvin large probe method.

[0017] Preferably, the dark-field surface contact potential difference V of the control chip CPDDARK and the bright-field surface contact potential difference V CPDLIGHT are measured by the non-contact Kelvin large probe with surface photovoltage technology.

[0018] Preferably, it further includes:

[0019] Sample the absolute work function data measured by the contact capacitance method corresponding to the process parameters of the gate structure layer of the semiconductor to be monitored;

[0020] Obtain non-contact relative work function data corresponding to the above semiconductor gate structure layer process parameters;

[0021] Based on the absolute work function data and the relative work function data, obtain two work function relational expressions for the process parameters;

[0022] Based on the relational expressions, monitor the semiconductor gate structure layer process parameters through the measurement of the non-contact relative work function.

[0023] Preferably, the semiconductor gate structure layer process parameters include the thickness of the gate layer and / or the gate dielectric layer and the composition ratio of the gate layer, or a combination of the above process parameters.

[0024] Compared with the prior art, the monitoring method of the semiconductor gate structure layer manufacturing process of the present invention has the following advantages:

[0025] Through the above monitoring method, the present invention obtains the relative work function of the gate structure layer. By the relative work function and the relational expressions of the absolute work function and the relative work function corresponding to the process parameters of this gate structure layer obtained previously, it is monitored whether the process parameters of the gate layer and the gate dielectric layer corresponding to the gate structure layer are within the normal range. This monitoring method can be used for timely feedback on the manufacturing processes of the gate layer and the gate dielectric layer and adjustment of process parameters, saving the time for the entire gate structure layer process manufacturing and adjustment and reducing the overall manufacturing cost. This monitoring method can be carried out using a control wafer. After using this control wafer, the control wafer can be recycled, which can further reduce the cost of this monitoring method. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 21 is a schematic structural diagram of measuring the work function of a wafer using a measuring machine having only a Kelvin large probe in an embodiment of the present invention.

[0027] Figure 2 FIG. 25 is a flowchart of a monitoring method for a semiconductor gate structure layer manufacturing process in an embodiment of the present invention.

[0028] Figure 3 FIG. 29 is a schematic structural diagram after depositing an interface layer on the surface of a control wafer in an embodiment of the present invention.

[0029] Figure 4 FIG. 33 is a schematic structural diagram after depositing a high-K gate dielectric layer on the surface of the interface layer in an embodiment of the present invention.

[0030] Figure 5 FIG. 37 is a schematic structural diagram after depositing a metal layer on the surface of the high-K gate dielectric layer in an embodiment of the present invention.

[0031] Figure 6 FIG. 41 is a function relationship diagram between the work function and the metal layer film thickness in an embodiment of the present invention.

[0032] Figure 7 It is a graph showing the functional relationship between the work function and the concentration of the metal layer in an embodiment of the present invention.

[0033] Figure 8 It is a fitting relationship graph between the relative work function and the absolute work function in an embodiment of the present invention.

[0034] Figure 9 It is a fitting relationship graph between the relative work function and the absolute work function in another embodiment of the present invention.

[0035] In the figure, 10 - carrier stage; 20 - Kelvin large probe; 100 - control wafer; 200 - interface layer; 300 - high - K dielectric layer; 400 - metal layer. Detailed implementation manners

[0036] To make the objectives, advantages and features of the present invention clearer, the following further elaborates on the monitoring method for the manufacturing process of the semiconductor gate structure layer proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions and shapes, will be partially determined by the specific application and usage environment. Also, in the following described embodiments, sometimes the same reference numerals are used between different drawings to represent the same part or parts with the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0037] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0038] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0039] The core idea of the present invention is to provide a monitoring method for the manufacturing process of a semiconductor gate structure layer, which, based on existing equipment, shortens the detection time and avoids scrapping wafers. At the same time, it can also achieve the purpose of reducing the detection cost.

[0040] To achieve the above idea, the present invention provides a monitoring method for the manufacturing process of a semiconductor gate structure layer (hereinafter referred to as "monitoring method"). The gate structure layer includes a gate layer and a gate dielectric layer. The gate dielectric layer is located between the channel of the semiconductor device and the gate layer and can be a multi-layer dielectric layer. Similarly, based on different processes and materials of the gate structure, the gate layer can be a single layer or a combination of multi-layers of materials. Refer Figures 1 to 9 A specific implementation manner of the disclosed monitoring method. The monitoring method includes the following steps S1 to S5.

[0041] Step S1: Provide a control wafer 100 and test to obtain the work function W of the control wafer 100 SI .

[0042] Specifically, refer Figure 2 and Figure 3 As shown, a wafer without patterns on its surface is used as the control wafer 100. And the control wafer 100 is used as the substrate. According to the type of the gate in the gate structure layer to be monitored, a substrate of a different type is selected for the control wafer. The work function W of the control wafer 100 SI is measured by means of a non-contact Kelvin large probe. The control wafer 100 is placed on the measuring machine tool to measure the work function W of the control wafer 100 SI . The measuring machine tool is a machine tool with a Kelvin large probe 20, and the machine tool is equipped with a Kelvin large probe 20 with a diameter of 2 mm. By moving the Kelvin large probe 20 above the control wafer 100, the work function W of the control wafer 100 is measured and obtained SI .

[0043] Step S2: The control wafer 100 and the patterned wafer to be monitored are used together to sequentially form a gate dielectric layer and a gate layer on the surface of the control wafer 100, and the patterning processes of the gate dielectric layer and the gate layer involved in the patterned wafer are omitted. The specific patterning processes include photolithography and etching processes in semiconductor manufacturing processes, and of course are not limited thereto, and other processes such as cleaning are also involved. Among them, the fabricated gate layer has a doping type different from that of the control wafer 100.

[0044] Specifically, as shown in Figures 2 to 5 the following steps are performed on the control wafer 100 and the patterned wafer to be monitored together to sequentially form a gate dielectric layer and a gate layer on the surface of the control wafer 100. Among them, the gate dielectric layer includes an interface layer 200 and a high-k dielectric layer 300, and the gate layer is described by taking the metal layer 400 as an example. That is, an interface layer 200, a high-k dielectric layer 300, and a metal layer 400 are sequentially formed on the surface of the control wafer 100. Preferably, before forming the interface layer 200, the control wafer 100 is first cleaned to remove impurity particles or an impurity layer on the surface of the control wafer 100. It should be noted that the control wafer 100 and the patterned wafer to be monitored are used together to perform the above steps while omitting the patterning processes of the gate dielectric layer and the gate layer.

[0045] Before forming the high-k dielectric layer 300, the interface layer 200 can be deposited on the surface of the cleaned control wafer 100. The interface layer 200 provides a good interface foundation for the high-k dielectric layer 300 to be formed later, improves the quality of the formed high-k dielectric layer 300, reduces the interface state density between the high-k dielectric layer 300 and the control wafer 100, and enables the high-k dielectric layer 300 to form a good contact with the control wafer 100. In this embodiment, the material of the interface layer 200 can be silicon oxide, and the material of the high-k dielectric layer 300 is HfO2. In other embodiments, the material of the high-k dielectric layer 300 can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2, etc. Correspondingly, other silicide materials can be selected for the interface layer 200, such as silicon oxide, silicon nitride, silicon oxynitride, and their combinations, etc. In this embodiment, the material of the gate layer can be a stack of one or several materials among TiN, TaN, TaSiN, TiSiN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN, and here Figure 5 it is described by taking the metal layer 400 as an example. Figure 3 、 Figure 4 and Figure 5 are only simple schematic diagrams for illustrating the film layers of the gate structure layer formed on the surface of the control wafer 100, and do not represent the thickness of the film layers in the actual gate structure layer or the specific ratio between the film layer thicknesses. If the gate layer / metal layer in the gate structure layer to be monitored is an N-type material, the control wafer 100 is selected as a P-type substrate. If the gate layer / metal layer to be monitored is a P-type material, the control wafer 100 is an N-type substrate.

[0046] Step S3: Measuring the dark-field surface contact potential difference V of the control chip 100 by a non-contact method CPDDARK .

[0047] Specifically, referring to Figure 2 as shown, a non-contact Kelvin large probe with surface photovoltaic technology is used to measure the dark-field surface contact potential difference V under dark-field conditions CPDDARK . The so-called dark field refers to the surface contact potential difference measured under the condition of no light illumination.

[0048] Step S4: Measuring the bright-field surface contact potential difference V of the control chip 100 by a non-contact method CPDLIGHT .

[0049] Specifically, referring to Figures 1 to 5 as shown. A non-contact Kelvin large probe with surface photovoltaic technology is used to measure the surface contact potential difference V. The so-called bright field refers to the surface contact potential difference measured under the condition of light illumination. The light source can be green light or white light. In order to improve the measurement accuracy, the output power of the light source is greater than or equal to 100 watts. Still taking the test machine with only the Kelvin large probe 20 as an example for illustration. This test machine is equipped with a Kelvin large probe 20 with a diameter of 2 mm. For the measurement of the surface barrier (Vsb) of the control chip 100. First, place the control chip 100 on the carrier table 10, and move the probe above the control chip 100 to measure the control chip 100. When the measurement machine measures, a non-contact Kelvin large probe is used for measurement. During the specific measurement, using the surface photovoltaic technology, carriers are generated by irradiating the wafer with light of a specific wavelength, and by measuring the change in voltage. For example, the bright-field surface contact potential difference V of the control chip 100 can be measured by irradiating the wafer with green light with a wavelength of about 500 nm and without light irradiation respectively CPDLIGHT and the dark-field surface contact potential difference V of the control chip 100 CPDLIGHT . CPDDARK .

[0050] Step S5: Calculating the relative work function of the gate structure layer of the control chip 100 based on the work function W SI 、dark-field surface contact potential difference V CPDDARK and bright-field surface contact potential difference V CPDLIGHT of the control chip 100.

[0051] Specifically, referring to Figures 2 to 5 as shown, calculating the relative work function of the gate structure layer of the control chip 100 based on the work function W SI 、dark-field surface contact potential difference V CPDDARK and bright-field surface contact potential difference V CPDLIGHT of the control chip 100 includes:

[0052] The relative work function of the gate structure layer = work function W SI -q surface barrier V SB where q is the charge constant, and q is preferably 1.6×10 -19 Coulomb. The surface barrier V SB = dark field surface contact potential difference V CPDDARK - bright field surface contact potential difference V CPDLIGHT .

[0053] The relative work function of the control wafer gate structure layer can be obtained from the examples described above. In this measurement method, the gate structure layer of the control wafer 100 does not need to be patterned, the production time of the test control wafer 100 can be shortened, and the requirements for the equipment for measuring the work function are also relatively low. The measurement equipment with surface photovoltage technology and Kelvin probe can meet the requirements.

[0054] In the monitoring method described above, in order to further obtain the process parameters of the specific monitoring layer in the semiconductor gate structure layer to be monitored, it is also necessary to sample the absolute work function data corresponding to this process parameter in advance. The absolute work function measurement method can be obtained according to the contact capacitance method introduced above, or can be measured by other methods, not limited to the above contact capacitance method. Please refer to Figure 6 or Figure 7 , and taking the gate layer body made of a metal layer and the process parameters to be monitored of the gate structure as the metal layer thickness and metal layer concentration as an example for illustrative description.

[0055] Figure 6 The process parameter of the semiconductor gate structure to be monitored shown is the film thickness of the metal layer. When using the measurement method of the relative work function disclosed above, the absolute work function data within the preset process film thickness range can be measured and collected by the laboratory capacitance measurement method. In this embodiment, the metal film thickness is taken as an example, and the relative work function data corresponding to the film thickness collected by the measurement method disclosed in the present invention; establish the mathematical relationship between the relative work function and the absolute work function of the film thickness within the preset range of the metal layer. Figure 6 The dotted line in Figure 6 is the change curve of the relative work function measured by the on-wafer measurement equipment disclosed in the present invention with respect to the metal layer film thickness, and the solid line therein is the change curve of the absolute work function obtained by traditional laboratory capacitance measurement with respect to the metal layer film thickness. As Figure 6 shown, the work function of the metal layer increases with the increase of the metal layer film thickness. The data of the relative work function corresponding to the metal layer film thickness in Figure 8 and the absolute work function corresponding to the metal layer film thickness are fitted to obtain the fitting relationship diagram shown in 2= 0.987. Therefore, in the monitoring of the metal layer film thickness in the subsequent gate structure manufacturing process, it is only necessary to use the method of measuring the relative work function disclosed in the present invention and refer to this relational expression to monitor whether the metal layer film thickness in this process is within the expected process range. This monitoring method of the present invention can effectively shorten the time required by the traditional laboratory capacitance measurement method, avoid traditional destructive tests, and the measured control wafer 100 can be recycled and utilized, saving costs.

[0056] Taking the gate layer main body in the gate structure as the metal layer 400 as an example, the metal layer 400 is not a single-component metal layer 400, and the process parameter to be monitored for the semiconductor gate structure is the concentration of the metal layer 400. Figure 7 is a function relationship diagram of the work function and the metal layer concentration (i.e., the metal layer composition ratio). The metal layer concentration directly affects the electronic structure of the material. The dotted line therein is the change curve of the relative work function obtained by measuring with the on-wafer measurement device disclosed in the present invention as a function of the metal layer concentration, and the solid line therein is the change curve of the absolute work function obtained by traditional laboratory capacitance measurement as a function of the metal layer concentration. From Figure 7 it can be seen that the work function of the metal layer decreases as the concentration of a metal component in the metal layer increases. By Figure 7 fitting the data of the relative work function corresponding to the concentration of a certain metal in the metal layer and the absolute work function of the metal layer corresponding to this metal concentration, a fitting relationship diagram as shown in Figure 9 is obtained, where the linear regression coefficient R 2 = 0.9988. In the monitoring of the metal concentration in the metal layer in the subsequent gate structure manufacturing process, it is only necessary to use the method of measuring the relative work function disclosed in the present invention and refer to this relational expression to monitor whether the metal layer concentration in this process is within the expected process range.

[0057] The above has given a relatively specific description of the monitoring of two process parameters. Of course, the process parameters of the gate structure monitored by the present invention are not limited to the process parameters in the above gate structure. The monitored process parameters may include the thickness of the gate layer and / or the gate dielectric layer and the gate layer composition ratio or a combination of the above process parameters.

[0058] For those skilled in the art, with the change of different process nodes in the manufacturing process, the materials of the gate dielectric layer and the gate layer will have different changes. The gate dielectric layer can be a single layer or a multi-layer stack and combination, and the gate layer can also be a single layer or a multi-layer combination, not limited to the materials involved in the gate structure exemplified above. The manufacturing process of the gate structure layer is extremely important for the manufacturing of the entire semiconductor chip and directly determines the final yield of the chip. Therefore, the monitoring of the process link of the gate structure is particularly important. The traditional contact capacitance measurement method is not suitable for use in the mass production and manufacturing of later products because it takes a long time and is a destructive test.

[0059] The monitoring method disclosed by the present invention can quickly and accurately monitor the parameters of the gate structure layer process only by measuring the relative work function method, without the need for the traditional time-consuming and costly contact capacitance test method for monitoring. As described above, the prerequisite for using this method is to collect the data of the relative work function and the absolute work function corresponding to the parameters to be monitored within the preset process range, and establish the corresponding mathematical function relationship. This monitoring method can be used for timely feedback and process parameter adjustment of the manufacturing processes of the gate layer and the gate dielectric layer, saving the time for the entire gate structure layer process manufacturing and adjustment, and reducing the overall manufacturing cost. This monitoring method can be carried out by using the control chip 100. After using this control chip 100, the control chip 100 can be recycled, which can further reduce the cost of this monitoring method.

[0060] In summary, the above embodiments have described in detail different configurations of the monitoring method for the semiconductor gate structure layer manufacturing process. Of course, the above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the content of the above embodiments. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the protection scope of the claims.

Claims

1. A monitoring method for a manufacturing process of a semiconductor gate structure layer, the gate structure layer including a gate layer and a gate dielectric layer, the gate dielectric layer being located between the channel of a semiconductor device and the gate layer, characterized in that, The monitoring method includes: Provide a control chip and test to obtain the function W of the control chip SI ; Together with the control wafer and the patterned wafer to be monitored, form the gate dielectric layer and the gate layer on the surface of the control wafer in sequence, and omit the patterning process of the gate dielectric layer and the gate layer involved in the patterned wafer, wherein the doping type of the gate layer is different from that of the control wafer; Measuring the contact potential difference V of the control wafer's dark field surface by a non-contact method CPDDARK ; Measuring the surface contact potential difference V of the control wafer in bright field by non-contact method CPDLIGHT ; Based on the work function W of the control wafer SI , the dark-field surface contact potential difference V CPDDARK and the bright-field surface contact potential difference V CPDLIGHT , the relative work function of the gate structure layer of the control wafer is calculated and obtained; The calculation method includes: The relative work function of the gate structure layer = work function W SI -q surface barrier V SB , where q is the charge constant Surface barrier V SB = Dark-field surface contact potential difference V CPDDARK − Bright-field surface contact potential difference V CPDLIGHT ; The work function W of the control film SI is measured by a non-contact Kelvin large probe method; The dark-field surface contact potential difference V of the control wafer CPDDARK and the bright-field surface contact potential difference V CPDLIGHT are measured by a non-contact Kelvin large probe with surface photovoltage technology; It further includes: Sampling the absolute work function data measured by the contact capacitance method corresponding to the process parameters of the semiconductor gate structure layer to be monitored; Obtaining the non-contact relative work function data corresponding to the above process parameters of the semiconductor gate structure layer; Based on the absolute work function data and the relative work function data, obtain two work function relationships of the process parameters; Based on the relationship, monitor the process parameters of the semiconductor gate structure layer by measuring the non-contact relative work function.

2. The monitoring method for the manufacturing process of the semiconductor gate structure layer according to claim 1, characterized in that, The gate layer is a metal layer, and the gate dielectric layer is a high-K dielectric layer.

3. The monitoring method for the manufacturing process of the semiconductor gate structure layer according to claim 1, characterized in that, The process parameters of the semiconductor gate structure layer include the thickness of the gate layer and / or the gate dielectric layer and the composition ratio of the gate layer, or a combination of the above process parameters.

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