Scheduling method and apparatus, semiconductor process equipment, and computer readable storage medium

Abstract

The embodiment of the specification provides a scheduling method. When determining process paths of multiple wafers to be diced, first, a wafer state is acquired, then, according to the wafer state and the process paths of the multiple wafers to be diced, multiple earliest completion times corresponding to multiple theoretical dicing sequences are determined, the shortest earliest completion time in the multiple earliest completion times is taken as a target earliest completion time, and the multiple wafers to be diced are controlled to be diced according to the theoretical dicing sequence corresponding to the target earliest completion time. In this way, by selecting the theoretical dicing sequence with the shortest time as the dicing basis of the multiple wafers to be diced, the time for the multiple wafers to be diced to complete processing is the shortest, which is beneficial to reducing the total time of the multiple wafers to be diced in the semiconductor process equipment after being diced, thereby reducing the idle time of each process chamber in the semiconductor process equipment and improving the utilization rate of the process chamber.

Description

TECHNICAL FIELD

[0001] The present specification relates to the technical field of semiconductor technology, in particular, to the technical field of equipment scheduling in semiconductor technology, and more particularly, to a scheduling method and device, a semiconductor process equipment, and a computer readable storage medium. BACKGROUND

[0002] A cluster tool is a kind of equipment widely used in semiconductor wafer manufacturing. The cluster tool can include an aligner, a robot, a load lock, a load port, and a plurality of process chambers.

[0003] In order to improve the work efficiency of the cluster tool, the cluster tool can be used to process multiple types of wafers. However, in the current scheduling technology for multiple types of wafers in the cluster tool, the utilization rate of the process chambers of the cluster tool is low. SUMMARY

[0004] The embodiments of the present specification provide a scheduling method, device, semiconductor process equipment, and computer readable storage medium to achieve the purpose of providing a scheduling method that improves the utilization rate of the process chambers.

[0005] To achieve the above technical purpose, the embodiments of the present specification provide the following technical solutions:

[0006] In a first aspect, one embodiment of the present specification provides a scheduling method applied to a semiconductor process equipment for determining a processing sequence of multiple types of wafers in the semiconductor process equipment, wherein the semiconductor process equipment includes a wafer load port and a plurality of process chambers, and the scheduling method includes:

[0007] Obtaining a wafer state, wherein the wafer state is used to represent the position and process state of a wafer that has been unloaded in the semiconductor process equipment;

[0008] According to the wafer state and a process path of a plurality of wafers to be unloaded, a plurality of earliest completion times corresponding to a plurality of theoretical unloading sequences are determined, wherein the plurality of wafers to be unloaded includes a plurality of wafers of different types located in the wafer load port, the plurality of theoretical unloading sequences includes permutations and combinations of the unloading sequence of the plurality of wafers to be unloaded, and the earliest completion time is used to represent the time required for the semiconductor process equipment to process the plurality of wafers to be unloaded according to the theoretical unloading sequence corresponding to the earliest completion time;

[0009] Control the multiple to-be-out wafer wafers to be out according to the theoretical wafer-out sequence corresponding to the target earliest completion time; the target earliest completion time is the earliest completion time with the shortest time among multiple earliest completion times.

[0010] In a second aspect, an embodiment of the present specification provides a computing device, comprising: a processor and a memory;

[0011] The memory is connected with the processor, and the memory is used for storing a computer program.

[0012] The processor is used for realizing the above scheduling method by running the computer program stored in the memory.

[0013] In a third aspect, an embodiment of the present specification provides a semiconductor process scheduling device, which is used for scheduling processing sequences of multiple types of wafers in a wafer loading and unloading position, and comprises: a processor and a memory; the memory stores a computer program, and the processor executes the computer program to execute the scheduling method in any of the above aspects, and controls the wafer loading and unloading position to perform wafer-out of the multiple to-be-out wafers.

[0014] In a fourth aspect, an embodiment of the present specification provides a semiconductor process device, comprising: a wafer loading and unloading position and the semiconductor process scheduling device in any of the above aspects.

[0015] The wafer loading and unloading position is configured to set multiple to-be-out wafers of different types;

[0016] The semiconductor process scheduling device is configured to control the wafer loading and unloading position to perform wafer-out of the multiple to-be-out wafers according to the scheduling method in any of the above aspects.

[0017] In a fifth aspect, an embodiment of the present specification provides a computer readable storage medium, which stores a computer program; when the computer program is run by a processor, the scheduling method in the above aspects is realized.

[0018] In a sixth aspect, an embodiment of the present specification provides a computer program product or a computer program, the computer program product comprises a computer program, and the computer program is stored in a computer readable storage medium; the processor of the computer device reads the computer program from the computer readable storage medium, and the processor realizes the steps of the scheduling method in the above aspects when executing the computer program.

[0019] It can be seen from the technical solution that the scheduling method provided by the embodiments of the present specification first acquires the wafer state when determining the process paths of the multiple wafer-out wafers, and then determines multiple earliest completion times corresponding to the multiple theoretical wafer-out sequences according to the wafer state and the process paths of the multiple wafer-out wafers, takes the shortest earliest completion time in the multiple earliest completion times as a target earliest completion time, and controls the multiple wafer-out wafers to be wafered out according to the theoretical wafer-out sequence corresponding to the target earliest completion time. In this way, by selecting the theoretical wafer-out sequence with the shortest time as the wafer-out basis of the multiple wafer-out wafers, the time for the multiple wafer-out wafers to complete processing is the shortest, which is beneficial to reducing the total time of the multiple wafer-out wafers in the semiconductor process equipment after wafering out, thereby reducing the idle time of each process chamber in the semiconductor process equipment and improving the utilization rate of the process chamber.

[0020] When determining the multiple earliest completion times corresponding to the multiple theoretical wafer-out sequences, the multiple earliest completion times can be obtained according to the wafer state and the process paths of the multiple wafer-out wafers, without the need to establish a complex algorithm model, which is beneficial to reducing the complexity of the scheduling algorithm and improving the execution efficiency of the scheduling algorithm.

[0021] In addition, the cleaning time of the process chamber is included in the earliest completion time, so that the cleaning time of the process chamber is taken into account, so that the scheduling method can be applied to a non-steady-state scheduling process. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present specification or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present specification, and those skilled in the art can also obtain other drawings according to the provided drawings without creative labor.

[0023] Figure 1 A structural schematic diagram of a semiconductor process equipment is provided for an embodiment of the present specification.

[0024] Figure 2 A flowchart of a scheduling method is provided for an embodiment of the present specification.

[0025] Figure 3 A flowchart of another scheduling method is provided for an embodiment of the present specification.

[0026] Figure 4 A structural schematic diagram of a scheduling device is provided for an embodiment of the present specification.

[0027] Figure 5Another structural schematic diagram of a semiconductor process equipment is provided for an embodiment of the present specification.

[0028] Figure 6 A structural schematic diagram of a computing device is provided for an embodiment of the present specification. DETAILED DESCRIPTION

[0029] Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present specification shall have the common meaning understood by one of ordinary skill in the art to which the embodiments of the present specification belong. The terms "first", "second", and similar terms used in the embodiments of the present specification do not denote any order, quantity, or importance, but are used to avoid confusion between the components.

[0030] Unless otherwise required by context, "plurality" in the specification means "at least two", and "comprising" is to be interpreted as open, inclusive meaning, i.e. "including but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to mean that the particular feature, structure, material or characteristic associated with that embodiment or example includes in at least one embodiment or example of the specification. The illustrative representation of the above terms does not necessarily refer to the same embodiment or example.

[0031] The technical solutions in the embodiments of the present specification will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present specification. Obviously, the described embodiments are only part of the embodiments of the present specification, not all. Based on the embodiments in the present specification, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present specification.

[0032] SUMMARY

[0033] Reference Figure 1 Still taking the cluster type equipment as an example, Figure 1 A structural schematic diagram of a semiconductor process equipment is shown, which can include a first robot 10, a wafer loading and unloading site 21, a calibration module 22, a cooling disc 23, and a plurality of processing modules 11; wherein,

[0034] Each wafer loading and unloading site 21 can place a wafer box, and each wafer box can place a plurality of wafers.

[0035] The calibration module 22 can include a slot, and the calibration module 22 can calibrate the wafer placed in the slot.

[0036] Processing Module, each processing module 11 has a slot, which can place a piece of wafer for processing.

[0037] Cooler, which is used to cool the wafer after processing.

[0038] The first robot 10 can be a double-arm robot, the two arms of the double-arm robot can be 180° and fixed, each arm has a slot, each slot can place a piece of wafer, generally, the two arms cannot simultaneously perform the operation of taking and placing the wafer; the first robot 10 is responsible for transporting the wafer between the vacuum lock 30 and the plurality of process chambers 11.

[0039] In addition, in some embodiments, the semiconductor process equipment can further include a vacuum lock and a second robot, etc.; the vacuum lock (LoadLock) can have two slots, each slot can place a piece of wafer, the vacuum lock can switch between the atmospheric state and the vacuum state, wherein when the vacuum lock state is converted to the atmospheric state, the wafer located on the side of the second robot can be sent into the vacuum lock; when the vacuum lock is converted to the vacuum state, the wafer located on the side of the first robot can be sent into the vacuum lock. The second robot can be a single-arm robot, the second robot can have a slot, which can place a piece of wafer, the second robot can be responsible for transporting the wafer between the wafer loading and unloading site 11, the calibration module 22 and the vacuum lock.

[0040] The process path of the wafer can include multiple process nodes that the wafer passes through in the semiconductor process equipment and the process time required for each process node. The process path can be specifically formulated by the process personnel according to the wafer process requirements and can be flexibly changed. For example, the wafer process path can include: wafer loading and unloading site -> second robot (3 seconds) -> calibration module (1 second) -> second robot (3 seconds) -> vacuum lock (3 seconds) -> first robot (3 seconds) -> first process chamber (60 seconds) -> first robot (3 seconds) -> second process chamber (120 seconds) -> first robot (3 seconds) -> third process chamber (60 seconds) -> first robot (3 seconds) -> fourth process chamber (60 seconds) -> first robot (3 seconds) -> vacuum lock (3 seconds) -> second robot (3 seconds) -> cooling disc (1 second) -> wafer loading and unloading site. Each step can be referred to as a process node, each process node has a time consumption, and the time marked in the brackets can be the time required for the process node (i.e., the process time). The wafer can be processed in parallel or in series among the process chambers 11. In the above process path example, if the first process chamber to the fourth process chamber are different process chambers, the above process path can be referred to as a serial process path. If at least two of the first process chamber to the fourth process chamber are the same process chamber 11, the above process path can be referred to as a reentrant process path. In addition to the serial process path and the reentrant process path, if a process node has multiple selectable process chambers 11, the process path can be referred to as a parallel process path.

[0041] The serial process path, the parallel process path, and the reentrant process path are illustrated below. For example, the serial process path is as follows: wafer loading and unloading site -> calibration module -> first robot -> first process chamber PM1 -> first robot -> second process chamber PM2 -> first robot -> third process chamber PM3 -> first robot -> fourth process chamber PM4 -> cooling disc -> wafer loading and unloading site. The wafer is sequentially processed in four different process chambers (first process chamber PM1 to fourth process chamber PM4), and thus the path is referred to as a serial process path.

[0042] For example, the parallel process path is as follows: wafer loading and unloading site -> calibration module -> first robot -> first process chamber PM1 / second process chamber PM2 / third process chamber PM3 -> first robot -> cooling disc -> wafer loading and unloading site. The wafer can be processed in one of the process chambers first process chamber PM1 / second process chamber PM2 / third process chamber PM3, and thus the path is referred to as a parallel process path.

[0043] An example of the reentry process path is as follows: wafer loading and unloading station—> calibration module—> first robot—> first process chamber PM1—> first robot—> second process chamber PM2—> first robot—> first process chamber PM1—> first robot—> second process chamber PM2—> first robot—> cooling disc—> wafer loading and unloading station; wherein the wafer is processed twice in the process chamber first process chamber PM1 and twice in the process chamber first process chamber PM2, and thus the path is called a reentry process path.

[0044] When the semiconductor process equipment processes wafers, the process paths of different types (or different varieties) of wafers can be different. The process paths of different types of wafers can occupy the same process chamber (this case belongs to mixed processing of multiple types of wafers with shared chambers), or can not occupy the same process chamber (this case belongs to mixed processing of multiple types of wafers without shared chambers).

[0045] In a processing scenario for multiple types of wafers, the wafer out sequence of the multiple types of wafers is an important factor affecting the utilization rate of process chambers in a semiconductor process equipment. In order to improve the utilization rate of the process chambers in the semiconductor process equipment, the inventors have found, through research, that when determining the process paths of multiple wafers to be out, first, a wafer state representing the position and process state of a wafer that has been out in the semiconductor process equipment is obtained, then, according to the wafer state and the process paths of the multiple wafers to be out, multiple earliest completion times corresponding to multiple theoretical wafer out sequences are determined, and the shortest earliest completion time among the multiple earliest completion times is taken as a target earliest completion time, and the multiple wafers to be out are controlled to be out according to the theoretical wafer out sequence corresponding to the target earliest completion time. In this way, by optimizing the wafer out sequence of the multiple wafers to be out, the processing sequence of the multiple wafers to be out in the process chambers is optimized, so that the time for the multiple wafers to be out to complete processing and return to a wafer loading and unloading position is the shortest, that is, the minimum completion time (the completion time can refer to the time for a wafer to be out from the wafer loading and unloading position, processed in the process chambers, and return to the wafer loading and unloading position). Because the process paths of the wafers have been given, which process chambers need to be processed and the processing time in each process chamber, if the idle time of the process chambers in the process paths is relatively long and the utilization rate is not high, the total time for completing wafer processing will definitely increase, and the completion time is not the minimum value. On the contrary, if the idle time of the process chambers is very short and the utilization rate is very high, the wafers can continuously flow in the process chambers for processing, and the overall completion time is also short. Therefore, by selecting the theoretical wafer out sequence with the shortest time as the wafer out basis for the multiple wafers to be out, the time for the multiple wafers to be out to complete processing is the shortest, which is beneficial to reducing the total time for the multiple wafers to be out in the semiconductor process equipment, thereby reducing the idle time of the process chambers in the semiconductor process equipment and improving the utilization rate of the process chambers.

[0046] When determining the multiple earliest completion times corresponding to the multiple theoretical wafer out sequences, the multiple earliest completion times can be obtained according to the wafer state and the process paths of the multiple wafers to be out, without the need to establish a complex algorithm model, which is beneficial to reducing the complexity of the scheduling algorithm and improving the execution efficiency of the scheduling algorithm.

[0047] In addition, the earliest completion time includes the cleaning time of the process chamber, so that the cleaning time of the process chamber is considered, and the scheduling method can be applied to a non-steady state scheduling process.

[0048] Based on the above inventive concept, the embodiments of the present specification provide a scheduling method, which will be exemplarily described below in combination with the accompanying drawings.

[0049] Exemplary methods

[0050] One embodiment of the present disclosure provides a scheduling method applied to a semiconductor processing equipment for determining a processing sequence of multiple types of wafers in the semiconductor processing equipment, wherein the semiconductor processing equipment comprises a wafer loading and unloading station and multiple processing chambers, such as Figure 2 As shown, the scheduling method comprises:

[0051] S201: obtaining a wafer state, wherein the wafer state is used to represent a position and a processing state of a wafer that has been unloaded from the semiconductor processing equipment;

[0052] S202: determining multiple earliest completion times corresponding to multiple theoretical unloading sequences respectively according to the wafer state and processing paths of multiple wafers to be unloaded, wherein the multiple wafers to be unloaded comprise multiple wafers of different types located in the wafer loading and unloading station, the multiple theoretical unloading sequences comprise permutations and combinations of unloading sequences of the multiple wafers to be unloaded, and the earliest completion time is used to represent a time required for processing the multiple wafers to be unloaded according to the theoretical unloading sequence corresponding to the earliest completion time by the semiconductor processing equipment;

[0053] S203: controlling the multiple wafers to be unloaded according to the theoretical unloading sequence corresponding to a target earliest completion time, wherein the target earliest completion time is the earliest completion time with the shortest time among the multiple earliest completion times.

[0054] Figure 2 In addition, a feasible application scenario of the scheduling method is shown in the present disclosure, wherein during the operation of the semiconductor processing equipment, a semiconductor processing scheduling device of the semiconductor processing equipment can perform steps S201-S203 to control the wafer loading and unloading station. The semiconductor processing scheduling device can be a lower-level machine of the semiconductor processing equipment, and specifically can be a device with computing and communication capabilities, such as a computer or the like.

[0055] In the present embodiment, unloading can refer to an action of entering other modules of the semiconductor processing equipment from the wafer loading and unloading station, and a wafer that has been unloaded can refer to a wafer located in other modules of the semiconductor processing equipment except the wafer loading and unloading station, such as a wafer located in a calibration module 22 or a processing chamber 11 or the like. A wafer to be unloaded can refer to a wafer located in the wafer loading and unloading station.

[0056] The position of the wafer-out wafer in the semiconductor processing equipment can refer to which module in the semiconductor processing equipment the wafer-out wafer is located in, and the process state of the wafer-out wafer in the semiconductor processing equipment can refer to the processing state of the wafer-out wafer in the process chamber 11, which can include at least one of the process time, the processed time, and the remaining processing time of the wafer-out wafer in the process chamber 11. In some embodiments, if there is no wafer-out wafer in the semiconductor processing equipment, the wafer state can be empty, and in step S202, the earliest completion times corresponding to the plurality of theoretical wafer-out sequences can be determined according to the process paths of the plurality of wafer-out wafers.

[0057] In the process of determining the earliest completion times corresponding to the plurality of theoretical wafer-out sequences according to the wafer state and the process paths of the plurality of wafer-out wafers, the time when each wafer-out wafer in the theoretical wafer-out sequence is processed to return to the wafer loading and unloading position (hereinafter referred to as the completion time) can be calculated according to the process path of the wafer-out wafer and the wafer state. It is not difficult to understand that when calculating the completion time required by a wafer-out wafer other than the first wafer-out wafer in the theoretical wafer-out sequence in the semiconductor processing equipment, the influence of other wafer-out wafers with relatively earlier wafer-out sequences on the wafer-out wafer needs to be considered.

[0058] The theoretical wafer-out sequence refers to a permutation and combination of the wafer-out sequences of multiple types of wafers, or in other words, the theoretical wafer-out sequence refers to a theoretically feasible wafer-out sequence of multiple types of wafers. For example, assuming that there are three types of wafer-out wafers, which are A, B, and C, the plurality of theoretical wafer-out sequences can include A-B-C, A-C-B, B-A-C, B-C-A, C-A-B, and C-B-A, a total of six possibilities, and each theoretical wafer-out sequence is a permutation and combination of a wafer-out sequence of wafers A, B, and C. Taking the theoretical wafer-out sequence A-B-C as an example, when calculating the completion time required by the wafer-out wafer B after wafer-out, the influence of the wafer-out wafer A with an earlier wafer-out sequence needs to be considered. Assuming that the process path of the wafer-out wafer A includes: wafer loading and unloading position -> calibration module (1 second) -> first process chamber PM1 (60 seconds) -> first mechanical hand (3 seconds) -> second process chamber PM2 (120 seconds) -> first mechanical hand (3 seconds) -> cooling disc (2 seconds) -> wafer loading and unloading position.

[0059] And the process path of the wafer-out wafer B includes: wafer loading and unloading position -> calibration module (1 second) -> first process chamber PM1 (60 seconds) -> first mechanical hand (3 seconds) -> cooling disc (2 seconds) -> wafer loading and unloading position.

[0060] Since A and B both pass through the process chamber PM1, when considering the finishing time of the to-be-out wafer B after it is out, it needs to consider whether A occupies the process chamber PM1 when B needs to enter the process chamber PM1 for processing, and the waiting time of B for using the process chamber PM1.

[0061] The influence of the wafer state on the earliest finishing time is similar to the above example. Still taking the above process path of the to-be-out wafer A as an example, it is assumed that when calculating the finishing time of the to-be-out wafer A after it is out, there is an out wafer in the semiconductor process equipment, for example, the out wafer C has just started processing in the first process chamber PM1, and the processing time is 100 seconds. When the to-be-out wafer A waits to enter PM1 through the calibration module, it needs to wait for the out wafer C to finish processing in PM1, that is, it needs to wait for 99 seconds (100-1=). Then the finishing time of the to-be-out wafer A is equal to 1+(100-1)+60+3+120+3+2=288 seconds.

[0062] And it is assumed that when calculating the finishing time of the to-be-out wafer A after it is out, there is no out wafer in the semiconductor process equipment. Then the finishing time of the to-be-out wafer A is equal to 1+60+3+120+3+2=189 seconds.

[0063] In the embodiment, when determining the process paths of multiple to-be-out wafers, first, the wafer state is obtained, and then according to the wafer state and the process paths of multiple to-be-out wafers, multiple earliest finishing times corresponding to multiple theoretical out sequences are determined, and the shortest earliest finishing time in multiple earliest finishing times is taken as a target earliest finishing time. The multiple to-be-out wafers are controlled to be out according to the theoretical out sequence corresponding to the target earliest finishing time. In this way, by selecting the theoretical out sequence with the shortest time as the basis for the out of the multiple to-be-out wafers, the time for the multiple to-be-out wafers to complete processing is the shortest, which is beneficial to reduce the total time of the multiple to-be-out wafers after they are out in the semiconductor process equipment, thereby reducing the idle time of each process chamber in the semiconductor process equipment and improving the utilization rate of the process chamber.

[0064] When determining the multiple earliest finishing times corresponding to the multiple theoretical out sequences, the multiple earliest finishing times can be obtained according to the wafer state and the process paths of multiple to-be-out wafers, without the need to establish a complex algorithm model, which is beneficial to reduce the complexity of the scheduling algorithm and improve the execution efficiency of the scheduling algorithm.

[0065] In addition, in some embodiments, the earliest finishing time includes the cleaning time of the process chamber, so that the cleaning time of the process chamber is considered, so that the scheduling method can be applied to a non-steady-state scheduling process.

[0066] In order to achieve more accurate control, so that the completion time of each wafer to be out of the wafer can be as small as possible, in an embodiment of the present specification, the theoretical wafer out sequence corresponding to the target earliest completion time controls the multiple wafers to be out of the wafer includes:

[0067] In the theoretical wafer out sequence corresponding to the target earliest completion time, the first wafer in the multiple wafers to be out of the wafer is controlled to be out of the wafer, and the step of returning to obtain the wafer state is returned.

[0068] Generally, the number of each type of wafer to be out of the wafer in the wafer loading and unloading position can be multiple, and after the first wafer in the multiple wafers to be out of the wafer is controlled to be out of the wafer in the theoretical wafer out sequence corresponding to the target earliest completion time, the step of returning to obtain the wafer state can be returned to the subsequent multiple types of wafer to be out of the wafer. Redesign and planning to make the completion time of each wafer to be out of the wafer as small as possible, and improve the utilization rate of the process chamber.

[0069] For example, assuming that there are three types of wafers to be out of the wafer in the wafer loading and unloading position, the three types of wafers to be out of the wafer are A, B, and C, as described above, the multiple theoretical wafer out sequences of the three types of wafers can include: A-B-C, A-C-B, B-A-C, B-C-A, C-A-B and C-B-A a total of six possibilities, assuming that after calculation, the theoretical wafer out sequence A-B-C corresponds to the target earliest completion time, then control the wafer loading and unloading position to determine a wafer out of the multiple type A wafers, and then the wafer out of the wafer is regarded as a wafer out of the wafer. Return to step S201, re-plan and schedule the three types of wafers to be out of the wafer to make the completion time of each wafer as small as possible under the current state, and improve the utilization rate of the process chamber.

[0070] In an embodiment of the present specification, a feasible calculation method of the earliest completion time is provided, for example, the multiple earliest completion times corresponding to the multiple theoretical wafer out sequences are determined according to the wafer state and the process path of the multiple wafers to be out of the wafer includes:

[0071] In combination with the wafer state, multiple theoretical wafer out sequences are traversed to obtain the first completion time corresponding to each target process chamber in the theoretical wafer out sequence; the target process chamber is the process chamber in the process path of the wafer to be out of the wafer in the theoretical wafer out sequence; the first completion time is the time required for the multiple wafers to be out of the wafer to be processed in the target process chamber and returned to the wafer loading and unloading position;

[0072] The maximum value of the first completion time corresponding to each target process chamber in the theoretical wafer out sequence is taken as the earliest completion time corresponding to the theoretical wafer out sequence.

[0073] As can be seen from the foregoing description, in the process path of the wafer to be unloaded, the processing time of the wafer to be unloaded in the process chamber usually accounts for a large part of the finished time. Therefore, in the embodiment, the target process chamber in the process path is taken as a node, the first finished time corresponding to the target process chamber is calculated, and the maximum value of the first finished time corresponding to each target process chamber in the theoretical unloading sequence is taken as the earliest finished time corresponding to the theoretical unloading sequence, considering the case that the wafer waits outside the chamber due to process chamber occupation. The earliest finished time is calculated by the algorithm, without the need to construct a complex mathematical model, and has the characteristics of being simple and easy to implement.

[0074] Optionally, in an embodiment, the first finished time specifically includes the sum of a first minimum time, a second minimum time, a first chamber cleaning time, and a first process processing time.

[0075] The first minimum time includes the minimum time for the plurality of wafers to be unloaded in the theoretical unloading sequence to enter the target process chamber according to the respective corresponding process path.

[0076] The second minimum time includes the minimum time for the plurality of wafers to be unloaded in the theoretical unloading sequence to return to the wafer loading and unloading position after the processing in the target process chamber is completed according to the respective corresponding process path.

[0077] The first chamber cleaning time includes the chamber cleaning time of the target process chamber in the process of processing the plurality of wafers to be unloaded.

[0078] The first process processing time includes the sum of the time for the target process chamber to process the plurality of wafers to be unloaded according to the respective corresponding process path of the plurality of wafers to be unloaded in the theoretical unloading sequence.

[0079] The first finished time can be calculated according to Formula I as follows.

[0080] T = max k {min i,j (S i,j,k )+∑ i,j D i,j,k +∑ h C h,k +min i,j (E i,j,k )} Formula I

[0081] In the formula one, T represents the earliest completion time, subscript k represents the number of process chamber, i represents the label of wafer to be out of the plate, j represents the number of process node in the process path of wafer to be out of the plate i, and h represents the number of cleaning of process chamber k.

[0082] S i,j,k represents the time for wafer to be out of the plate i to reach process chamber k at the fastest in process node j, and min i,j (S i,j,k ) represents the minimum time for a plurality of wafer to be out of the plate in the theoretical out-of-plate sequence to enter the target process chamber according to the respective corresponding process path, that is, the first minimum time;

[0083] D i,j,k represents the time for process node j of wafer to be out of the plate i to occupy process chamber k, and ∑ i,j D i,j,k represents the first process processing time;

[0084] C h,k represents the time required for process chamber k to perform the hth chamber cleaning, and ∑ h C h,k represents the sum of the time of one or more chamber cleanings required for the process chamber k in the process of processing a plurality of wafer to be out of the plate in the theoretical out-of-plate sequence.

[0085] E i,j,k represents the time required for wafer to be out of the plate i to return to wafer loading and unloading site from process chamber k at the fastest in process node j, and min i,j (E i,j,k ) represents the second minimum time.

[0086] Suppose that there are two types of wafers mixed processing, type A and type B respectively, and there are 10 wafers waiting for processing respectively, the process path of type A is wafer loading and unloading site->calibration module(1 second)->first mechanical hand(3 seconds)->process chamber PM1(60 seconds)->first mechanical hand(3 seconds)->process chamber PM2(120 seconds)->first mechanical hand(3 seconds)->cooling disc(1 second)->wafer loading and unloading site; the process path of type B is wafer loading and unloading site->calibration module(1 second)->first mechanical hand(3 seconds)->process chamber PM1(30 seconds)->first mechanical hand(3 seconds)->process chamber PM3(60 seconds)->first mechanical hand(3 seconds)->cooling disc(1 second)->wafer loading and unloading site; the time in the bracket after each module is the time consumed by this step(process node);

[0087] 1) Different chamber number k, k is 1 for process chamber PM1, k is 2 for process chamber PM2, k is 3 for process chamber PM3; Different wafer number i, i is 1-10 for type A wafer, i is 11-20 for type B wafer; Different process path number j, j is wafer loading and unloading position -> calibration module (j=1) -> first robot (j=2) -> process chamber PM1 (j=3) -> first robot (j=4) -> process chamber PM2 (j=5) -> first robot (j=6) -> cooling disc (j=7) -> wafer loading and unloading position for type A wafer; j is wafer loading and unloading position -> calibration module (j=1) -> first robot (j=2) -> process chamber PM1 (j=3) -> first robot (j=4) -> process chamber PM3 (j=5) -> first robot (j=6) -> cooling disc (j=7) -> wafer loading and unloading position for type B wafer;

[0088] 2) Assuming that all process chamber cleaning settings are process one wafer cleaning once, the cleaning time is 10 seconds; (This parameter is specified in advance by process personnel in actual production)

[0089] 3) When all wafers are not out of the wafer loading and unloading position, the first completion time of type A wafer out of the wafer loading and unloading position is calculated as follows:

[0090] a) For k=1, S i,j,1 is equal to the shortest time from wafer loading and unloading position to process chamber PM1 through calibration module and first robot, which is 1 second (calibration module) + 3 seconds (first robot) = 4 seconds; D i,j,1 is equal to the process time of the wafer in process chamber PM1, which is 60 seconds; E i,j,1 is equal to the total time of the wafer from process completion in process chamber PM1 to return to the wafer loading and unloading position, which is 3 seconds (first robot) + 120 seconds (process chamber PM2) + 3 seconds (first robot) + 1 second (cooling disc) = 127 seconds; The cumulative process wafer number before process chamber PM1 starts process is 0, which will not trigger cleaning, so h=0, C h,1 is equal to 0;

[0091] b) For k=2, S i,j,2 is equal to the shortest time from wafer loading and unloading position to process chamber PM2 through calibration module, first robot, process chamber PM1 and first robot, which is 1 second (Agliner) + 3 seconds (first robot) + 60 seconds (process chamber PM1) + 3 seconds (first robot) = 67 seconds; D i,j,2 is equal to the process time of the wafer in process chamber PM2, which is 120 seconds; E i,j,2Equal to the total time from the end of the process in the process chamber PM2 to the return to the wafer load port, which is 3 seconds (first robot) + 1 second (chill plate) = 4 seconds; the cumulative number of processed wafers before the process starts in the process chamber PM2 is 0, so no cleaning is triggered, and thus h = 0, C h,2 Equal to 0;

[0092] c) The earliest completion time T for this wafer A is equal to max{4 + 60 + 127 + 0, 67 + 120 + 4 + 0} = 191 seconds.

[0093] When all wafers are not out of the wafer load port, the first completion time of a wafer of type B out of the wafer load port is calculated as follows:

[0094] a) For k = 1, S i,j,1 Equal to the shortest time to go from the wafer load port, through the calibration module, the first robot, to the process chamber PM1, which is 1 second (calibration module) + 2 seconds (first robot) = 3 seconds; D i,j,1 Equal to the process time of the wafer B in the process chamber PM1, which is 30 seconds; E i,j,1 Equal to the total time from the end of the process in the process chamber PM1 to the return to the wafer load port, which is 3 seconds (first robot) + 60 seconds (process chamber PM2) + 3 seconds (first robot) + 1 second (chill plate) = 67 seconds; the cumulative number of processed wafers before the process starts in the process chamber PM1 is 0, so no cleaning is triggered, and thus h = 0, C h,1 Equal to 0;

[0095] b) For k = 3, S i,j,2 Equal to the shortest time to go from the wafer load port, through the calibration module, the first robot, the process chamber PM1, the first robot, to the process chamber PM3, which is 1 second (Agliner) + 3 seconds (first robot) + 30 seconds (process chamber PM1) + 3 seconds (first robot) = 37 seconds; D i,j,2 Equal to the process time of the wafer in the process chamber PM3, which is 60 seconds; E i,j,2 Equal to the total time from the end of the process in the process chamber PM3 to the return to the wafer load port, which is 3 seconds (first robot) + 1 second (chill plate) = 4 seconds; the cumulative number of processed wafers before the process starts in the process chamber PM3 is 0, so no cleaning is triggered, and thus h = 0, C h,2 Equal to 0;

[0096] c) The earliest completion time T for this wafer B is equal to max{3 + 30 + 67 + 0, 37 + 60 + 4 + 0} = 101 seconds.

[0097] Using a similar calculation method, we can calculate the earliest completion time for wafer ejection sequence 1 (wafer A to wafer B) and wafer ejection sequence 2 (wafer B to wafer A) when none of the wafers have left the wafer loading / unloading positions. If the earliest completion time of wafer ejection sequence 1 is less than the earliest completion time of wafer ejection sequence 2, then wafer A is ejected according to wafer ejection sequence 1. If the earliest completion time of wafer ejection sequence 2 is less than the earliest completion time of wafer ejection sequence 1, then wafer B is ejected according to wafer ejection sequence 2.

[0098] When a Type A wafer has just entered the process chamber PM1 for processing, and the remaining processing time is 60 seconds, the calculation process for the first completion time of a Type A wafer being removed from the wafer loading / unloading position is as follows:

[0099] a) For k = 1, S i,j,1 The shortest time from wafer ejection from the loading / unloading position, through the calibration module and the first robotic arm, to reaching the process chamber PM1 is 1 second (calibration module) + 3 seconds (first robotic arm) + (60-4=) 56 seconds (waiting for the first type A wafer to be processed) = 60 seconds; D i,j,1 This equals a processing time of 60 seconds for the wafer in process chamber PM1; E i,j,1 This equals the total time from the completion of the process in process chamber PM1 to the return of the wafer to the wafer loading / unloading position, which is 3 seconds (first robot arm) + 120 seconds (process chamber PM2) + 3 seconds (first robot arm) + 1 second (cooling tray) = 127 seconds; the cumulative number of process wafers in process chamber PM1 before the start of the process is 1, triggering 1 cleaning cycle, so h = 1, C h,1 Equals 10 seconds;

[0100] b) For k = 2, S i,j,2 The shortest time from wafer ejection at the loading / unloading position, through the calibration module, the first robotic arm, process chamber PM1, and then to process chamber PM2 is 1 second (Agliner) + 3 seconds (first robotic arm) + (60-4=) 56 seconds (waiting for the first type A wafer to complete processing) + 60 seconds (process chamber PM1) + 3 seconds (first robotic arm) = 123 seconds; D i,j,2 This equals 120 seconds of processing time for the wafer in process chamber PM2; E i,j,2 The total time from the completion of the process in process chamber PM2 to returning to the wafer loading / unloading position is 3 seconds (first robotic arm) + 1 second (cooling tray) = 4 seconds; the cumulative number of process wafers in process chamber PM2 before the start of the process is 1, which will trigger cleaning, so h = 10, C h,2 Equals 10 seconds;

[0101] c) The earliest completion time T of this wafer A is equal to max{60+60+127+10,123+120+4+10}=257 seconds.

[0102] When there is already a wafer of type A in the process chamber PM1 and the remaining processing time is 60 seconds, the first completion time of a wafer of type B from the wafer loading and unloading station is calculated as follows:

[0103] a) for k = 1, S i,j,1 is equal to the shortest time for a wafer to be taken out from the wafer loading and unloading station, pass through the calibration module, the first robot, and reach the process chamber PM1, which is 1 second (calibration module) + 2 seconds (first robot) + 57 seconds (waiting time for the wafer A to finish processing) = 60 seconds; D i,j,1 is equal to the processing time of the wafer B in the process chamber PM1, which is 30 seconds; E i,j,1 is equal to the total time for a wafer to be taken out from the process chamber PM1 and return to the wafer loading and unloading station, which is 3 seconds (first robot) + 60 seconds (process chamber PM2) + 3 seconds (first robot) + 1 second (cooling plate) = 67 seconds; the cumulative number of processed wafers before the process chamber PM1 starts processing is 1, which triggers cleaning, so h = 1, C h,1 is equal to 10 seconds;

[0104] b) for k = 3, S i,j,2 is equal to the shortest time for a wafer to be taken out from the wafer loading and unloading station, pass through the calibration module, the first robot, the process chamber PM1, and the first robot to reach the process chamber PM3, which is 1 second (Agliner) + 3 seconds (first robot) + 57 seconds (waiting time for the wafer A to finish processing) + 30 seconds (process chamber PM1) + 3 seconds (first robot) = 93 seconds; D i,j,2 is equal to the processing time of the wafer in the process chamber PM3, which is 60 seconds; E i,j,2 is equal to the total time for a wafer to be taken out from the process chamber PM3 and return to the wafer loading and unloading station, which is 3 seconds (first robot) + 1 second (cooling plate) = 4 seconds; the cumulative number of processed wafers before the process chamber PM3 starts processing is 0, which does not trigger cleaning, so h = 0, C h,2 is equal to 0;

[0105] c) the earliest completion time T of this wafer B is equal to max{60 + 30 + 67 + 10, 93 + 60 + 4 + 0} = 157 seconds.

[0106] Through the above similar calculation method, the earliest completion time of the wafer out sequence 1: wafer A—wafer B and the earliest completion time of the wafer out sequence 2: wafer B—wafer A can be calculated when there is already a wafer A in the process chamber PM1. If the earliest completion time of the wafer out sequence 1 is less than that of the wafer out sequence 2, then the wafer A is controlled to be taken out according to the wafer out sequence 1. If the earliest completion time of the wafer out sequence 2 is less than that of the wafer out sequence 1, then the wafer B is controlled to be taken out according to the wafer out sequence 2.

[0107] By the method, taking the process chamber as a node, considering the waiting time of the wafer outside the process chamber in the processing process, the first completion time corresponding to each target process chamber and the earliest completion time of the theoretical wafer-out sequence can be quickly calculated, without the need to establish a complex algorithm model, which is beneficial to reduce the complexity of the scheduling algorithm and improve the efficiency of the scheduling method.

[0108] For the process path of the wafer to be out, in order to select the most time-saving process chamber in multiple alternative process chambers, so that the process path of the wafer to be out is relatively time-saving, in an embodiment of the present specification, as shown in Figure 3 The method for determining the earliest completion time corresponding to each theoretical wafer-out sequence according to the wafer state and the process path of the wafer to be out includes:

[0109] S301: If the process path of the wafer to be out includes multiple parallel chambers, determine the processing chamber in the multiple parallel chambers; the multiple parallel chambers are alternative process chambers of the target process node in the process path of the wafer to be out; and the processing chamber is the process chamber determined to execute the target process node.

[0110] In the execution step S301, each process node in the process path of the wafer to be out can be traversed, if a process node in the process path includes multiple alternative process chambers, the multiple alternative process chambers can be called multiple parallel chambers, and the process node can be called a target process node. For example, assuming that the process path of wafer A includes: wafer loading and unloading site—> calibration module—> first mechanical hand—> process chamber PM1 / process chamber PM2 / process chamber PM3—> first mechanical hand—> cooling disc—> wafer loading and unloading site, the fourth process node in the process path includes three parallel chambers (process chamber PM1 / process chamber PM2 / process chamber PM3), that is, the process node can be selected in process chamber PM1 / process chamber PM2 / process chamber PM3, in order to determine the process path of the wafer A, facilitate the calculation of the completion time of the subsequent other wafers, it is necessary to determine the processing chamber of the target process node (i.e. to determine the process chamber executing the target process node).

[0111] Therefore, in the present embodiment, in order to facilitate the calculation of the earliest completion time corresponding to each theoretical wafer-out sequence of the multiple wafers to be out, the processing chamber needs to be determined in the case that the process path of each wafer to be out includes multiple parallel chambers before calculating the earliest completion time.

[0112] It can be understood that for the parallel process path, after the processing chamber is determined according to step S301, the calculation of the earliest completion time can be continued; and for other types of process paths, the calculation of the earliest completion time can be directly performed.

[0113] Specifically, in one embodiment of the present specification, the determining a processing chamber in the plurality of parallel chambers comprises:

[0114] In combination with the wafer state, a second completion time corresponding to the parallel chamber is calculated, the second completion time being a time required for the wafer to be out of the sheet to be processed in the parallel chamber and returned to the wafer loading and unloading site;

[0115] The parallel chamber corresponding to the minimum value of the plurality of second completion times is determined as the processing chamber of the target process node in the process path of the wafer to be out of the sheet.

[0116] Similar to the calculation of the first completion time, in combination with the wafer state, the second completion time corresponding to the parallel chamber can be calculated, and from the second completion time corresponding to each parallel chamber, the second completion time with the least required time is found, and the parallel chamber corresponding to the second completion time with the least required time is determined as the processing chamber of the target process node. In this way, the target process node of each process path of the wafer to be out of the sheet can select the process chamber with the least time consumption as the chamber for executing the node, thereby reducing the time consumption required by the process path of the wafer to be out of the sheet.

[0117] Optionally, in one embodiment of the present specification, the second completion time specifically comprises the sum of a third minimum time, a fourth minimum time, a second chamber cleaning time and a second process processing time;

[0118] The third minimum time comprises the minimum time required for the wafer to be out of the sheet to enter the parallel chamber according to the process path corresponding thereto;

[0119] The fourth minimum time comprises the minimum time required for the wafer to be out of the sheet to return to the wafer loading and unloading site after being processed in the parallel chamber according to the process path corresponding thereto;

[0120] The second chamber cleaning time comprises the chamber cleaning time required by the parallel chamber before processing the wafer to be out of the sheet;

[0121] The second process processing time comprises the time required for processing a plurality of wafers to be out of the sheet according to the process path corresponding thereto.

[0122] Similarly, the third minimum time, the fourth minimum time, the second chamber cleaning time and the second process processing time can be calculated according to Formula One. By this method, the second completion time of each parallel chamber can be quickly calculated by taking the parallel chamber as a node and considering the waiting time of the wafer outside the process chamber during processing, which is beneficial to improve the efficiency of the scheduling method.

[0123] In an optional embodiment, before step S301, the method can further include selecting a wafer with the highest priority as a to-be-out wafer of each type of wafer according to wafer priorities of the wafers of each type, so that a plurality of to-be-out wafers can be determined. The wafer priority of each type of wafer is negatively related to the ID of the slot where the wafer is located, that is, the larger the ID of the slot where the wafer is located, the lower the wafer priority. Of course, in some embodiments, the wafer priority of the wafer of the same type can also be determined in other ways, which is not limited in the present specification.

[0124] The specific executable manner of step S203 can include: controlling the first to-be-out wafer in the theoretical out sequence corresponding to the target earliest completion time to be out, and returning to step S301 to schedule the remaining to-be-out wafers according to the scheduling method. For example, assuming that the theoretical out sequence corresponding to the target earliest completion time includes wafer B, wafer C and wafer A, then wafer B is controlled to be out, and the step of obtaining the wafer state is returned to, and the remaining to-be-out wafers are scheduled according to the current wafer state, so that the theoretical out sequence corresponding to each wafer when it is out can correspond to the target earliest completion time.

[0125] Exemplary apparatus and devices

[0126] In an exemplary embodiment of the present specification, a scheduling device is also provided, which is applied to a semiconductor process equipment and used to determine the processing sequence of multiple types of wafers in the semiconductor process equipment. The semiconductor process equipment includes a wafer loading and unloading site and multiple process chambers, such as Figure 4 As shown, the scheduling device includes:

[0127] The state acquisition module 401 is configured to acquire a wafer state, and the wafer state is used to represent the position and process state of the out wafer in the semiconductor process equipment.

[0128] The time calculation module 402 is used to determine multiple earliest completion times corresponding to multiple theoretical wafer unloading sequences based on the wafer state and the process paths of multiple wafers to be unloaded; the multiple wafers to be unloaded include multiple wafers of different types located in the wafer loading and unloading positions; the multiple theoretical wafer unloading sequences include the permutation and combination of the wafer unloading sequences of the multiple wafers to be unloaded; the earliest completion time is used to characterize the time required for the semiconductor process equipment to process the multiple wafers to be unloaded according to the theoretical wafer unloading sequence corresponding to the earliest completion time, and the earliest completion time includes the cleaning time of the process chamber;

[0129] The wafer output control module 403 is used to control the output of the plurality of wafers to be output according to the theoretical wafer output order corresponding to the target earliest completion time; the target earliest completion time is the earliest completion time with the shortest time among the plurality of earliest completion times.

[0130] Specific limitations regarding the scheduling device can be found in the limitations regarding the scheduling method above, and will not be repeated here. Each module in the aforementioned scheduling device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0131] In another exemplary embodiment of this specification, a semiconductor process scheduling device is also provided, characterized in that it is used to schedule the processing order of multiple types of wafers in a wafer loading and unloading station. The semiconductor process scheduling device includes a processor and a memory; the memory stores a computer program, and when the processor executes the computer program, it executes the scheduling method described above to control the wafer loading and unloading station to unload the multiple wafers to be unloaded.

[0132] like Figure 5 As shown, in an exemplary embodiment of this specification, a semiconductor process apparatus 100 is also provided, including: a semiconductor process scheduling apparatus 30 and a wafer loading / unloading station 21;

[0133] The wafer loading / unloading position 21 is configured to hold multiple wafers to be unloaded.

[0134] The semiconductor process scheduling device 30 is configured to control the wafer loading / unloading position to unload the plurality of wafers to be unloaded, according to the scheduling method described in any of the above embodiments.

[0135] In some embodiments, the semiconductor process scheduling device 30 can collect information of the controlled module 40 and control the controlled module 40 to work cooperatively. The controlled module 40 can include part or all of the first robot 10 and the plurality of processing modules 11 in addition to the wafer loading and unloading station 21. In some embodiments, the controlled module 40 can further include the second robot, the calibration module 22, the cooling disc 23, etc.

[0136] In some embodiments, the semiconductor process scheduling device 30 is a lower-level machine of the semiconductor process device 100, which is not limited in the specification and can be determined according to actual conditions.

[0137] Exemplary computing devices

[0138] Another embodiment of the present application further provides a computing device, as shown in Figure 6 An example embodiment of the present specification further provides a computing device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the steps of the scheduling method according to various embodiments of the present specification described in the above embodiments of the present specification.

[0139] The internal structure of the computing device can be as shown in Figure 6 The computing device includes a processor, a memory, a network interface and an input device connected through a system bus. The processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computing device is used to communicate with an external terminal through a network connection. The computer program is executed by the processor to perform the steps of the scheduling method according to various embodiments of the present specification described in the above embodiments of the present specification.

[0140] The processor can include a main processor and can further include a baseband chip, a modem, etc.

[0141] The memory stores programs for executing the technical solutions of the present application, and can also store an operating system and other key services. Specifically, the program can include program code, and the program code includes computer operation instructions. More specifically, the memory can include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash, etc.

[0142] The processor can be a general purpose processor, such as a central processing unit (CPU), a microprocessor, or the like, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs of the solutions of the present application. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components.

[0143] The input device can include a device that receives data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor, etc.

[0144] The output device can include a device that allows information to be output to a user, such as a display screen, a printer, a speaker, etc.

[0145] The communication interface can include a device using any transceiver to communicate with other devices or communication networks, such as an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0146] The processor executes the programs stored in the memory and calls other devices, which can be used to implement each step of any one of the scheduling methods provided by the above-mentioned embodiments of the present application.

[0147] The computing device can also include a display component, which can be a liquid crystal display or an electronic ink display, and a voice component. The input device of the computing device can be a touch layer overlaid on the display component, or a key, trackball, or touchpad provided on the housing of the computing device, or an external keyboard, touchpad, or mouse, etc.

[0148] Those skilled in the art can understand that, Figure 6 The structure shown in the figure is only a block diagram of part of the structure related to the solutions of the present application, and does not constitute a limitation on the computing device to which the solutions of the present application are applied. A specific computing device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0149] Exemplary computer program products and storage media

[0150] In addition to the above methods and devices, the scheduling method provided by the embodiments of the present application can also be a computer program product, which includes computer program instructions that, when executed by a processor, cause the processor to perform the steps of the scheduling method according to the various embodiments of the present application described in the above "Exemplary Methods" section.

[0151] The computer program product can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server. The embodiments of the present disclosure can be a method, an apparatus, system, and computer program product.

[0152] The computer program product can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server. The embodiments of the present disclosure can be a method, an apparatus, system, and computer program product.

[0153] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, databases, or other media in this specification shall include non-volatile and / or volatile memory. Non-volatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0154] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the specification.

[0155] The above embodiments only express several implementation manners of the present specification, which are described in a more specific and detailed manner, but cannot be understood as a limitation on the scope of the solutions provided by the embodiments of the present specification. It should be noted that, for those skilled in the art, without departing from the concept of the present specification, a number of modifications and improvements can be made, which all belong to the protection scope of the present specification. Therefore, the protection scope of the patent of the present specification should be subject to the appended claims.

Claims

1. A scheduling method, characterized in that, An application to semiconductor process equipment, used to determine the processing sequence of multiple types of wafers in the semiconductor process equipment, the semiconductor process equipment including wafer loading / unloading positions and multiple process chambers, the scheduling method includes: The wafer status is obtained, which is used to characterize the position and process status of the wafer that has been shipped out in the semiconductor process equipment; Based on the wafer state and the process paths of multiple wafers to be unloaded, multiple earliest completion times corresponding to multiple theoretical wafer unloading sequences are determined; the multiple wafers to be unloaded include multiple wafers of different types located in the wafer loading / unloading positions; the multiple theoretical wafer unloading sequences include the arrangement and combination of the wafer unloading sequences of the multiple wafers to be unloaded; the earliest completion time is used to characterize the time required for the semiconductor process equipment to process the multiple wafers to be unloaded according to the theoretical wafer unloading sequence corresponding to the earliest completion time; According to the theoretical wafer output sequence corresponding to the target earliest completion time, the multiple wafers to be output are controlled to be output; the target earliest completion time is the earliest completion time with the shortest time among the multiple earliest completion times.

2. The method according to claim 1, characterized in that, The step of controlling the wafer output of the plurality of wafers to be output according to the theoretical wafer output order corresponding to the earliest target completion time includes: According to the theoretical wafer output sequence corresponding to the earliest target completion time, the first wafer among the multiple wafers to be output is controlled to be output, and the process returns to the step of obtaining the wafer status.

3. The method according to claim 1, characterized in that, The earliest completion time includes the cleaning time of the process chamber.

4. The method according to claim 1, characterized in that, The determination of the earliest completion times corresponding to the multiple theoretical wafer unloading sequences based on the wafer state and the process paths of the multiple wafers to be unloaded includes: Based on the wafer state, multiple theoretical wafer exit sequences are traversed to obtain the first completion time corresponding to each target process chamber in the theoretical wafer exit sequence; the target process chamber is the process chamber in the process path of the wafer to be exited in the theoretical wafer exit sequence; the first completion time is the time required for multiple wafers to be exited to be processed in the target process chamber and return to the wafer loading / unloading position; The maximum value among the first completion times corresponding to each target process chamber in the theoretical wafer output sequence is taken as the earliest completion time corresponding to the theoretical wafer output sequence.

5. The method according to claim 4, characterized in that, The first completion time specifically includes: the sum of the first minimum time, the second minimum time, the first chamber cleaning time, and the first process processing time; Wherein, the first minimum time includes the minimum time for multiple wafers to be unwound in the theoretical wafer unwound sequence to enter the target process chamber according to their respective process paths; The second minimum time includes the minimum time from the completion of processing of multiple wafers to be unloaded in the theoretical wafer unloading sequence, according to their respective corresponding process paths, from the time they are processed in the target process chamber to the time they return to the wafer loading / unloading position. The first chamber cleaning time includes the chamber cleaning time of the target process chamber during the processing of multiple wafers to be unloaded; The first process processing time includes the sum of the time taken for the target process chamber to process multiple wafers to be unwound according to their respective process paths in accordance with the theoretical wafer unwound sequence.

6. The method according to claim 1, characterized in that, The determination of the earliest completion times corresponding to the multiple theoretical wafer unloading sequences based on the wafer state and the process paths of the multiple wafers to be unloaded includes: If the process path of the wafer to be produced includes multiple parallel chambers, then a processing chamber is determined among the multiple parallel chambers; the multiple parallel chambers are candidate process chambers for the target process node in the process path of the wafer to be produced; the processing chamber is the process chamber determined to execute the target process node.

7. The method according to claim 6, characterized in that, Determining the processing chamber among the plurality of parallel chambers includes: Based on the wafer state, calculate the second completion time corresponding to the parallel chamber. The second completion time is the time required for the wafer to be unloaded to be processed in the parallel chamber and returned to the wafer loading / unloading position. The parallel chamber corresponding to the minimum value among multiple second completion times is determined as the processing chamber of the target process node in the process path of the wafer to be produced.

8. The method according to claim 7, characterized in that, The second completion time specifically includes: the sum of the third minimum time, the fourth minimum time, the second chamber cleaning time, and the second process processing time; The third minimum time includes the minimum time required for the wafer to be unloaded to enter the parallel chamber according to its corresponding process path; The fourth minimum time includes the minimum time from when the wafer to be unloaded is completed in the parallel chamber to when it returns to the wafer loading / unloading position according to its corresponding process path; The second chamber cleaning time includes the chamber cleaning time required for the parallel chamber before processing the wafer to be unwound; The second process processing time includes the time required to process multiple wafers according to their corresponding process paths.

9. A semiconductor process scheduling device, characterized in that, The semiconductor process scheduling device is used to schedule the processing order of multiple types of wafers in the wafer loading and unloading station. The device includes a processor and a memory. The memory stores a computer program. When the processor executes the computer program, it executes the scheduling method according to any one of claims 1 to 8 and controls the wafer loading and unloading station to unload the multiple wafers to be unloaded.

10. A semiconductor process apparatus, characterized in that, include: Wafer loading / unloading station and semiconductor process scheduling equipment as described in claim 9; The wafer loading / unloading position is configured to accommodate multiple different types of wafers to be unloaded. The semiconductor process scheduling equipment is configured to control the wafer loading / unloading position to unload the plurality of wafers to be unloaded according to the scheduling method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the scheduling method as described in any one of claims 1-8.

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