Semiconductor structure

Abstract

A semiconductor structure includes a first substrate and a second substrate stacked on each other, a first passive element located in the first substrate, and a second passive element located in the second substrate, a first conductive layer located on a top surface of the first substrate and electrically connected to the first passive element, and a conductive pad located on a top surface of the first substrate and electrically connected to the second passive element. And a first conductive layer located on a bottom surface of the second substrate and directly contacting the first conductive layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure with stacked passive components (such as deep trench capacitors). Background Art

[0002] With the development of semiconductor technology, the size of various electronic components is getting smaller and smaller. How to accommodate more electronic components in a limited unit space is a continuous development direction and goal in this field. Capacitor structure has the function of storing charge, so it is often used as one of the main components of various semiconductor electronic devices such as memory.

[0003] The existing planar capacitor structure includes a three-layer structure, which is an insulating layer sandwiched between two metal layers. However, with the development of technology, the requirements for the storage charge of capacitors are gradually increasing. If you want to make a capacitor that can store more charge, you also need to increase the area of ​​the capacitor, that is, increase the area of ​​the above-mentioned metal layer and insulating layer, but this will also cause the capacitor to occupy a larger area of ​​the semiconductor component, which is not conducive to the miniaturization of the product. Summary of the invention

[0004] The present invention provides a semiconductor structure, comprising a first substrate and a second substrate stacked on each other, a first passive element located in the first substrate, and a second passive element located in the second substrate, a first conductive layer located on a top surface of the first substrate and electrically connected to the first passive element, and a first conductive pad located on a bottom surface of the second substrate and directly contacting the first conductive layer.

[0005] The present invention further provides a semiconductor structure, comprising a first substrate and a second substrate stacked on each other, a first passive element located in the first substrate, and a second passive element located in the second substrate, a first conductive layer located on a top surface of the first substrate and electrically connected to the first passive element, a first conductive pad located on a bottom surface of the second substrate, and a conductive bump located between the first substrate and the second substrate and directly contacting the first conductive layer and the conductive pad.

[0006] The present invention is characterized in that it provides a semiconductor passive component, such as a stacking structure of a deep trench capacitor (DTC). In order to increase the charge that the capacitor structure can accommodate per unit area, at least two or more substrates containing deep trench capacitors are stacked and electrically connected to each other. The stacking method may include stacking multiple substrates with heterogeneous contacts (hybrid bond) or conductive bumps. The structure provided by the present invention is compatible with the prior art and does not require redesigning the size of the deep trench capacitor. Since the area or height of the original deep trench capacitor is not changed, there will be no problem of occupying too much area to affect other components, or too much height to make silicon vias difficult to form. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional structure diagram of a passive component of the present invention;

[0008] Figure 2 It is a schematic cross-sectional structure diagram of a stacked structure of two passive components according to an embodiment of the present invention;

[0009] Figure 3 It is a schematic cross-sectional structure diagram of a stacked structure of multiple passive components according to an embodiment of the present invention;

[0010] Figure 4 is a schematic cross-sectional structural diagram of a stacked structure of two passive components according to another embodiment of the present invention;

[0011] Figure 5 FIG. 4 is a schematic cross-sectional structure diagram of an electronic component according to an embodiment of the present invention.

[0012] Explanation of symbols

[0013] 10: First base

[0014] 10A: Top surface

[0015] 10B: Bottom

[0016] 12: The first passive component

[0017] 14: First dielectric layer

[0018] 16: First conductor layer

[0019] 20: Second base

[0020] 20A: Top surface

[0021] 20B: Bottom

[0022] 22: Second passive component

[0023] 24: Second dielectric layer

[0024] 25: Bottom dielectric layer

[0025] 26: Second conductor layer

[0026] 28: Conductive bump

[0027] 29: Conductive bump (solder ball)

[0028] 30: Filling layer

[0029] 40: Electronic components (chips)

[0030] 100: Passive components

[0031] 110: Base

[0032] 112: first electrode layer

[0033] 114: Insulation layer

[0034] 116: second electrode layer

[0035] B: Conductive bump

[0036] CU: Capacitor Unit

[0037] P: Conductive pad

[0038] S: Circuit board

[0039] V: Conductive column

[0040] V2: Conductive column DETAILED DESCRIPTION

[0041] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0042] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.

[0043] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic cross-sectional view of a passive component of the present invention. Figure 1As shown, a passive component 100 is provided. The passive component is located in a substrate 110. The substrate 110 is, for example, a silicon substrate. The passive component described in this embodiment is, for example, a deep trench capacitor (DTC). The manufacturing method thereof includes forming a plurality of trenches on the substrate 110 by exposure, development and etching. The trenches are preferably arranged in parallel with each other, and then sequentially forming a first electrode layer 112, an insulating layer 114 and a second electrode layer 116 in the trenches to form a deep trench capacitor. Subsequently, a conductive wire layer may be formed to electrically connect the passive component 100. The conductive wire layer is not drawn for simplicity of the drawings. In this embodiment, the material of the first electrode layer 112 and the second electrode layer 116 includes a conductive material, such as copper (Cu), chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), silver (Ag) and other metals or alloys of the above materials, but is not limited thereto. The material of the insulating layer 114 includes insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, but is not limited thereto. Therefore, the first electrode layer 112, the insulating layer 114 and the second electrode layer 116 constitute a deep trench capacitor. Compared with a general planar capacitor, the depth of the trench is used to create a larger capacitor area (i.e., the sidewall and bottom surface of the trench can be used as part of the capacitor area), so it has a larger capacitance value.

[0044] However, with the continuous advancement of technology, the requirements for the capacitance value of electronic components are gradually increasing. Figure 1 The passive component 100 (e.g., deep trench capacitor) shown may gradually face the situation that it is not enough to meet the use demand. In order to increase the capacitance value of the deep trench capacitor, there are two possible improvement directions, one of which is to increase the occupied area of ​​the deep trench capacitor (i.e., to form more trenches and expand the plane area of ​​the deep trench capacitor), and the other direction is to increase the depth of each trench, that is, to form a deeper trench to increase the contact area of ​​the capacitor.

[0045] However, both of the above two methods of possibly increasing the capacitance value have their limitations. First, increasing the plane area of ​​the capacitor will increase the area occupied by the capacitor structure in the entire semiconductor element, and may even reduce the formation space of other elements. If the depth of each groove is increased, the aspect ratio of each groove will also increase, and the filling ability of each material layer will be reduced, which will increase the difficulty of the manufacturing process. In addition, while increasing the groove depth, it is also necessary to provide a thicker substrate 110. If the thickness of the substrate 110 is too large, it is not conducive to the formation of a subsequent silicon via structure that penetrates the substrate.

[0046] Therefore, the present invention provides a semiconductor structure that improves the overall capacitance value without changing the size of each passive component (such as a deep trench capacitor), as shown in detail below.

[0047] Please refer to Figure 2 , Figure 2 FIG. 2 is a schematic cross-sectional view of a stacked structure of two passive components according to an embodiment of the present invention. Figure 2 As shown, a first substrate 10 and a second substrate 20 are provided, wherein the first substrate 10 includes a first passive component 12, and the second substrate 20 includes a second passive component 22. The first passive component 12 and the second passive component 22 are, for example, the above-mentioned Figure 1 The deep trench capacitor shown in FIG. 1 includes a first electrode layer, an insulating layer, and a second electrode layer stacked in sequence in the trench. Figure 2 The detailed structure of the deep trench capacitor is not shown in the figure for simplicity, but the structure can be referred to Figure 1 The structure shown.

[0048] In the present embodiment, the first substrate 10 and the second substrate 20 include a silicon substrate, and the first substrate 10 and the second substrate 20 are connected to each other through a heterogeneous contact, so that the first passive element 12 and the second passive element 22 therein are electrically connected to each other. More specifically, the first substrate 10 includes a top surface 10A and a bottom surface 10B, and the second substrate 20 includes a top surface 20A and a bottom surface 20B, wherein the top surface 10A of the first substrate 10 includes a first dielectric layer 14, that is, the first dielectric layer 14 contacts the top surface 10A of the first substrate 10 and the bottom surface 20B of the second substrate 20. In addition, the top surface 20A of the second substrate 20 includes a second dielectric layer 24. The materials of the first dielectric layer 14 and the second dielectric layer 24 described here include, for example, silicon oxide, silicon nitride, or silicon oxynitride, but are not limited thereto.

[0049] In addition, the first conductive layer 16 is located in the first dielectric layer 14, the second conductive layer 26 is located in the second dielectric layer 24, and the conductive pad P is located in the first dielectric layer 14 and contacts the bottom surface 20B of the second substrate 20. The contact column V is located in the second substrate 20 and the second dielectric layer 24, and the contact column V penetrates the second substrate 20 and the second dielectric layer 24. The main materials of the first conductive layer 16, the second conductive layer 26, the conductive pad P and the contact column V mentioned here include metals with good conductivity, such as copper (Cu), chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), silver (Ag) and other metals or alloys of the above materials, but not limited thereto. The main purpose of forming the above components is to electrically connect the first passive component 12 and the second passive component 22 respectively included in the first substrate 10 and the second substrate 20 to each other.

[0050] In more detail, Figure 2 As shown, the first conductive layer 16 is located on the top surface 10A of the first substrate 10, directly contacts and electrically connects to the first passive component 12. Similarly, the second conductive layer 26 is located on the top surface 20A of the first substrate 20, directly contacts and electrically connects to the second passive component 22. The conductive pad P is directly in contact with and electrically connected to the first conductive layer 16, the contact column V is directly in contact with and electrically connected to the second conductive layer 26, and the conductive pad P is directly in contact with and electrically connected to the contact column V. Therefore, the first passive component 12 and the second passive component 22 can be electrically connected to each other through the first conductive layer 16, the second conductive layer 26, the conductive pad P and the contact column V. If the first passive component 12 and the second passive component 22 are deep trench capacitors, they can be connected in parallel and their capacitance values ​​can be added together, that is, a component with a larger capacitance value can be formed in a limited space.

[0051] In addition, Figure 2 In the embodiment, the top surface of the second conductive layer 26 can form a conductive bump 28, and the conductive bump 28 can be used to electrically connect the first passive component 12 and the second passive component 22 connected in parallel to other components, for example, it can be electrically connected to a chip including a processor or a memory formed later. In addition, the first conductive layer 16 electrically connects the first passive component 12, which should refer to the conductive wires in the first conductive layer 16 electrically connecting the first electrode layer (lower electrode) and the second electrode layer (upper electrode) of the first passive component 12 respectively. Similarly, the second conductive layer 26 electrically connects the second passive component 22, which should refer to the conductive wires in the second conductive layer 26 electrically connecting the first electrode layer (lower electrode) and the second electrode layer (upper electrode) of the second passive component 22 respectively, and then the first conductive layer 16 and the second conductive layer 26 are directly or indirectly electrically connected to the conductive bump 28 or other voltage sources for the capacitor structure to store charge.

[0052] exist Figure 2 In the embodiment, the first passive component 12 and the second passive component 22 respectively included in the first substrate 10 and the second substrate 20 are electrically connected to each other. Capacitor units CU can be defined first, wherein each capacitor unit at least includes a portion of the substrate, a passive component, a portion of the dielectric layer and a wire. In other words, Figure 2 The structure shown can be regarded as two capacitor units CU stacked on each other and electrically connected. More specifically, the first substrate 10, the first passive component 12, the first dielectric layer 14 and the first wire layer 16 can be regarded as a capacitor unit CU, and the second substrate 20, the second passive component 22, the second dielectric layer 24 and the second wire layer 26 can be regarded as another capacitor unit CU, and the two capacitor units CU stacked up and down can be electrically connected to each other through the conductive pad P and the contact column V. In addition, in other embodiments, more capacitor units CU can also be stacked, for example, instead of forming the conductive bump 28 above the second wire layer 26, another conductive pad P is formed, so that other capacitor units (not shown) can be stacked above the second substrate 20.

[0053] For example, Figure 3 FIG. 1 is a schematic cross-sectional view of a stacked structure of multiple passive components according to an embodiment of the present invention. Figure 2 In this embodiment, more capacitor units CU can be stacked and electrically connected to each other, wherein the internal structure of each capacitor unit CU is similar or the same as Figure 2 The capacitor unit CU shown in the figure, the other same components are not repeated here. In addition, for the sake of simplicity, Figure 3 Some components are not marked with component symbols, but these components belong to the capacitor unit CU, and their detailed structures can be referred to in Figure 2 .according to Figure 2 and Figure 3 The concept shown in the figure is that the structure provided by the present invention can stack more passive components on each other according to the needs, thereby improving the performance of the product without changing the size of each product and without occupying more area.

[0054] It is worth noting that in the above embodiment, the electrical connection is achieved by directly contacting the conductive pad P through the contact column V. This technology of electrical connection through direct contact between the conductive pad and other adjacent components (such as wires) is also called heterogeneous contact (hybrid bond) technology. Heterogeneous contact technology allows higher density components to be bonded to each other. In this embodiment, heterogeneous contacts are combined with multiple deep trench capacitors so that each passive component can be stacked and electrically connected to each other. When the passive component is a deep trench capacitor, the capacitance values ​​of each deep trench capacitor component can be added.

[0055] The following will describe different implementations of the semiconductor structure of the present invention, and for simplicity, the following description will mainly describe the differences between the embodiments, and will not repeat the same parts. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0056] In addition to stacking and electrically connecting the passive components with each other using heterogeneous contact technology, the present invention can also stack and electrically connect the passive components with each other using other methods. For example, Figure 4 A cross-sectional schematic diagram of a stacked structure of two passive components according to another embodiment of the present invention is shown. Compared with the first embodiment, this embodiment also includes a first substrate 10 and a second substrate 20 stacked on each other, and the first substrate 10 includes a first passive component 12 (such as a deep trench capacitor), and the second substrate 20 includes a second passive component 22 (such as a deep trench capacitor), and the first passive component 12 and the second passive component 22 are electrically connected to each other. Most of the components not mentioned in this embodiment are related to Figure 2 The elements shown are similar or identical, and thus identical elements are not described repeatedly herein.

[0057] This embodiment and Figure 2 The difference between the embodiment shown is that the present embodiment does not use hybrid bond technology to bond the two substrates to each other, but connects the two substrates to each other through conductive bumps. For more details, please continue to refer to Figure 4 A bottom dielectric layer 25 is formed on the bottom surface 20B of the second substrate 20. The material of the bottom dielectric layer 25 is, for example, silicon oxide, but is not limited thereto. The conductive pad P is formed in the bottom dielectric layer 25. In addition, the present embodiment further includes a conductive bump B located between the first substrate 10 and the second substrate 20. More specifically, the conductive bump B is located between the first dielectric layer 14 and the bottom dielectric layer 25 and extends from the bottom dielectric layer 25 to the bottom dielectric layer 25. Figure 4 From the perspective of FIG. 1 , the conductive bump P directly contacts the conductive pad P above and the first conductive layer 16 below, so the first passive component 12 and the second passive component 22 can be electrically connected to each other through the path of the first conductive layer 16, the conductive bump B, the conductive pad P, the conductive column V and the second conductive layer 26. The conductive bump B described here can also be called a solder ball, and the two conductive components are connected to each other through the solder ball. In addition, a filling layer 30 is also included between the first dielectric layer 14 and the bottom dielectric layer 25. The material of the filling layer 30 can include epoxy resin, but is not limited to this. The filling layer 30 may be filled from the side gap of the component through capillary phenomenon, the purpose of which is to fix the conductive bump B to enhance the stability of the structure.

[0058] in addition, Figure 4The embodiment shown uses conductive bumps B to bond two substrates to each other and electrically connect the passive components therein. In other embodiments of the present invention, more substrates (more than 2 substrates) and the passive components therein may be stacked and electrically connected to each other through conductive bumps B. Figure 3 In the embodiment shown, the plurality of passive components are electrically connected by conductive bumps B instead of by heterogeneous contact technology. This variation also falls within the scope of the present invention.

[0059] In practical applications, Figure 2 , Figure 3 or Figure 4 The structure of the embodiments is formed on a circuit substrate, and then other electronic components such as memory or chips are connected to the capacitor structure. Figure 5 As shown, Figure 5 A schematic cross-sectional structure diagram of an electronic component according to an embodiment of the present invention is shown. Figure 5 The structure shown in the figure includes two capacitor units CU stacked on top of each other and electrically connected to each other. Figure 2 The structures shown are the same and therefore will not be described again. Figure 2 The two capacitor units CU shown are formed on a circuit substrate S, and also include an electronic component 40 located on the upper capacitor unit CU and electrically connected thereto. More specifically, the circuit substrate S described herein is, for example, a printed circuit board (PCB) used in the art, and the material is, for example, glass fiber and plastic, etc., that is, the material of the circuit substrate S is different from the first substrate 10 or the second substrate 20 (the material is, for example, silicon) mentioned above. In addition, the electronic component 40 is, for example, a chip, such as a single system chip (System on chip) including components such as a processor and a memory, but is not limited thereto. The electronic component 40 can be provided by Figure 2 The conductive bumps 28 or 29 are electrically connected to the capacitor unit CU, and the circuit substrate S below can be electrically connected to the capacitor unit CU through other conductive bumps 29. The conductive bumps 28 and 29 described here are, for example, solder bumps or conductive wire layers, but are not limited thereto.

[0060] Therefore, the first substrate 10 and the second substrate 20 in the present invention are arranged between the circuit substrate S (such as a printed circuit board) and the electronic component 40 (such as a chip), and can be used as an interposer between the two. In general technology, the interposer includes a conductor layer or a conductive column used to conduct current, and its function is to connect the pins of a chip with a small size to the pins of a circuit board with a larger size, and usually does not include other components. A feature of this embodiment is that the interposer (the first substrate 10 and the second substrate 20) includes a capacitor unit CU and a conductive column V2 for connecting the upper electronic component 40 or the lower circuit substrate S, wherein the conductive column V2 electrically connects the conductive bump 29 (such as a solder bump) and the electronic component 40 or the circuit substrate S. In other words, the first substrate 10 and the second substrate 20 in the present invention are used as an interposer, so they do not include active components such as transistors.

[0061] Above Figure 5 The capacitor unit CU stacking structure included in the embodiment shown is Figure 2 The structure shown is the same, but it is understandable that the capacitor unit CU stacking structure of other embodiments of the present invention can also be applied to Figure 5 In the illustrated embodiment, the capacitor unit CU stacking structure of each embodiment can be connected to the circuit substrate S and the electronic component 40 respectively, and the above various changes are all within the scope of the present invention.

[0062] It is also worth noting that in each embodiment of the present invention, the passive components are formed in the silicon substrate. That is to say, in the actual manufacturing process, the manufacturing process of the passive components can be first performed on the same wafer (silicon substrate) to form a plurality of passive components such as deep trench capacitors, and then the wafer is cut to form a similar Figure 1 The substrate shown includes passive components. These substrates are subsequently stacked on each other and electrically connected. In other words, in each embodiment of the present invention, the first passive component 12, the second passive component 22 or other passive components with the same structure can be formed simultaneously in the same manufacturing process step. Therefore, each passive component preferably has the same size. Since the size of each deep trench capacitor can also be the same as the prior art, there is no need to change the area or depth of each deep trench capacitor, so the aforementioned problem of reduced yield of semiconductor components due to excessive occupied area or deep capacitor depth can be avoided.

[0063] In summary, the present invention provides a semiconductor structure, comprising a first substrate 10 and a second substrate 20 stacked on each other, a first passive component 12 located in the first substrate 10, and a second passive component 22 located in the second substrate 20, a first conductive layer 16 located on a top surface 10A of the first substrate 10 and electrically connected to the first passive component 12, and a conductive pad ( Figure 2 The conductive pad P located between the first conductive layer 16 and the second substrate 20 is located on a bottom surface 20B of the second substrate 20 and directly contacts the first conductive layer 16 (see Figure 2 structure shown).

[0064] In some embodiments of the present invention, the first substrate 10 and the second substrate 20 include silicon substrates.

[0065] In some embodiments of the present invention, the first passive component 12 and the second passive component 22 include deep trench capacitors.

[0066] In some embodiments of the present invention, the deep trench capacitor includes a first electrode layer 112 , an insulating layer 114 and a second electrode layer 116 , which are located in a plurality of parallel trenches in the first substrate 10 or the second substrate 20 .

[0067] Some embodiments of the present invention further include a first dielectric layer 14 located between the first substrate 10 and the second substrate 20 , wherein the first conductive line layer 16 and the conductive pad P are located in the first dielectric layer 14 .

[0068] Some embodiments of the present invention further include a circuit substrate S located below the first base 10 and electrically connected to the first passive component 12 .

[0069] Some embodiments of the present invention further include an electronic component 40 , such as a chip, which is located above the second substrate 20 and electrically connected to the second passive component 22 .

[0070] In some embodiments of the present invention, a conductive column V penetrates through the second substrate 20 and is electrically connected to the conductive pad P.

[0071] In some embodiments of the present invention, a second conductive line layer 26 is further included on the top surface of the second substrate 20 , wherein the second conductive line layer 26 is electrically connected to the second passive component 22 and the conductive pillar V.

[0072] The present invention further provides a semiconductor structure, comprising a first substrate 10 and a second substrate 20 stacked on each other, a first passive element 12 located in the first substrate 10, and a second passive element 22 located in the second substrate 20, a first conductive layer 16 located on a top surface 10A of the first substrate 10 and electrically connected to the first passive element 12, a conductive pad ( Figure 4 A conductive pad P located between the conductive bump B and the second substrate 20) is located on a bottom surface 20B of the second substrate 20, and a conductive bump B is located between the first substrate 10 and the second substrate 20 and directly contacts the first conductive layer 16 and the conductive pad P (please refer to Figure 4 structure shown).

[0073] Some embodiments of the present invention further include a first dielectric layer 14 located on the top surface 10A of the first substrate 10 , wherein the first conductive line layer 16 is located in the first dielectric layer 14 .

[0074] Some embodiments of the present invention further include a bottom dielectric layer 25 located on the bottom surface 20B of the second substrate 20 , wherein the conducting pad P is located in the bottom dielectric layer 25 .

[0075] Some embodiments of the present invention further include a filling layer 30 located between the first dielectric layer 10 and the bottom dielectric layer 25 , wherein the conductive bumps B are located in the filling layer 30 .

[0076] In some embodiments of the present invention, a conductive column V penetrates through the second substrate 20 and is electrically connected to the conductive bump B through the conductive pad P.

[0077] In some embodiments of the present invention, a second conductive line layer 26 is further included on a top surface 20A of the second substrate 20 , wherein the second conductive line layer 26 is electrically connected to the conductive pillars V.

[0078] The present invention is characterized in that it provides a semiconductor passive component, such as a stacking structure of a deep trench capacitor (DTC). In order to increase the charge that the capacitor structure can accommodate per unit area, at least two or more substrates containing deep trench capacitors are stacked and electrically connected to each other. The stacking method may include stacking multiple substrates with heterogeneous contacts (hybrid bond) or conductive bumps. The structure provided by the present invention is compatible with the prior art and does not require redesigning the size of the deep trench capacitor. Since the area or height of the original deep trench capacitor is not changed, there will be no problem of occupying too much area to affect other components, or too much height to make silicon vias difficult to form.

[0079] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure comprising: The first substrate and the second substrate are stacked on each other; A first passive element is located in the first substrate, and a second passive element is located in the second substrate; A first conductive line layer is located on the top surface of the first substrate and is electrically connected to the first passive component; as well as The first conducting pad is located on the bottom surface of the second substrate and directly contacts the first conducting wire layer. 2 . The semiconductor structure as claimed in claim 1 , wherein the first substrate and the second substrate comprise silicon substrates. 3 . The semiconductor structure as claimed in claim 1 , wherein the first passive element and the second passive element comprise deep trench capacitors. 4 . The semiconductor structure as claimed in claim 3 , wherein the deep trench capacitor comprises a first electrode layer, an insulating layer and a second electrode layer, and is located in a plurality of parallel trenches in the first substrate or the second substrate. 5 . The semiconductor structure as claimed in claim 1 , further comprising a first dielectric layer located between the first substrate and the second substrate, wherein the first conductive line layer and the first conducting pad are located in the first dielectric layer. 6 . The semiconductor structure as claimed in claim 1 , further comprising a circuit substrate, located below the first base and electrically connected to the first passive component. 7 . The semiconductor structure as claimed in claim 1 , further comprising a chip located above the second substrate and electrically connected to the second passive component. 8 . The semiconductor structure as claimed in claim 1 , further comprising a conductive column penetrating the second substrate and electrically connected to the second conductive pad. 9 . The semiconductor structure as claimed in claim 8 , further comprising a second conductive line layer located on a top surface of the second substrate, wherein the second conductive line layer is electrically connected to the second passive component and the conductive pillar.

10. A semiconductor structure comprising: The first substrate and the second substrate are stacked on each other; A first passive element is located in the first substrate, and a second passive element is located in the second substrate; A first conductive line layer is located on the top surface of the first substrate and is electrically connected to the first passive component; A first conducting pad, located on the bottom surface of the second substrate; as well as The conductive bump is located between the first substrate and the second substrate and directly contacts the first conductive line layer and the conductive pad. The semiconductor structure as claimed in claim 10 , wherein the first substrate and the second substrate comprise silicon substrates. 12 . The semiconductor structure of claim 10 , wherein the first passive device and the second passive device comprise deep trench capacitors. 13 . The semiconductor structure as claimed in claim 12 , wherein the deep trench capacitor comprises a first electrode layer, an insulating layer and a second electrode layer, and is located in a plurality of parallel trenches in the first substrate or the second substrate. 14 . The semiconductor structure as claimed in claim 10 , further comprising a first dielectric layer located on the top surface of the first substrate, wherein the first conductive line layer is located in the first dielectric layer. 15 . The semiconductor structure as claimed in claim 14 , further comprising a bottom dielectric layer located on the bottom surface of the second substrate, wherein the first conducting pad is located in the bottom dielectric layer. 16 . The semiconductor structure as claimed in claim 15 , further comprising a filling layer located between the first dielectric layer and the bottom dielectric layer, wherein the conductive bump is located in the filling layer. 17 . The semiconductor structure as claimed in claim 10 , further comprising a circuit substrate, located below the first base and electrically connected to the first passive component. 18 . The semiconductor structure as claimed in claim 10 , further comprising a chip located above the second substrate and electrically connected to the second passive component. 19 . The semiconductor structure as claimed in claim 10 , further comprising a conductive column penetrating the second substrate and electrically connected to the conductive bump through a second conductive pad. 20 . The semiconductor structure as claimed in claim 19 , further comprising a second conductive line layer located on a top surface of the second substrate, wherein the second conductive line layer is electrically connected to the conductive pillar.

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