ESD protection circuit, semiconductor chip, base station, and mobile device

Abstract

The invention relates to an ESD protection circuit, a semiconductor chip, a base station and a mobile device. The ESD protection circuit includes: a first node for coupling to an I / O node of the semiconductor chip; a first conductive path coupled to the first node via at least one first diode, the first conductive path configured to be at a first voltage level, the first voltage level being higher than or equal to a voltage level of a first supply voltage of the semiconductor chip; and a second conductive path coupled to the first node via at least one second diode. The second conductive path is configured to be at a second voltage level, the second voltage level is lower than or equal to a voltage level of a second supply voltage of the semiconductor chip, and the voltage level of the second supply voltage is lower than the voltage level of the first supply voltage; and the second node is used for being coupled to a grounding node of the semiconductor chip or used for providing a power supply node of the semiconductor chip of the second power supply voltage.

Description

Technical Field

[0001] The present disclosure relates to electrostatic discharge (ESD) protection. Specifically, examples of the present disclosure relate to an ESD protection circuit for a semiconductor chip, a semiconductor chip, a base station, and a mobile device. Background Art

[0002] Electronic components and devices need to be protected from damage or failure caused by ESD. For example, the signal swing received by the base station of modern communication protocols (such as 5G or 6G) may significantly exceed the supply voltage and ground voltage provided at the semiconductor chip that houses the transceiver or receiver circuit of the base station. Robust ESD protection for transceiver or receiver circuits is required. At the same time, the transceiver or receiver circuit requires ESD protection with low load. Therefore, improved ESD protection may be required. Summary of the invention

[0003] According to a first aspect of the present disclosure, an electrostatic discharge (ESD) protection circuit for a semiconductor chip is provided, the ESD protection circuit comprising: a first node for coupling to an I / O node of the semiconductor chip; a first conductive path coupled to the first node via at least one first diode, wherein the first conductive path is configured to be at a first voltage level, which is higher than or equal to the voltage level of a first power supply voltage of the semiconductor chip; a second conductive path coupled to the first node via at least one second diode, wherein the second conductive path is configured to be at a second voltage level, which is lower than or equal to the voltage level of a second power supply voltage of the semiconductor chip, the voltage level of the second power supply voltage being lower than the voltage level of the first power supply voltage; and a second node for coupling to a ground node of the semiconductor chip or a power supply node of the semiconductor chip for providing the second power supply voltage, wherein the first conductive path is coupled to the second node via at least one capacitor, and the second conductive path is coupled to the second node via at least one other capacitor.

[0004] According to a second aspect of the present disclosure, a semiconductor chip is provided, comprising: an I / O node; an electrostatic discharge (ESD) protection circuit according to the first aspect of the present disclosure, wherein a first node of the ESD protection circuit is coupled to the I / O node; and a signal processing circuit coupled to the I / O node, wherein the semiconductor chip is configured to provide the first power supply voltage and the second power supply voltage to the signal processing circuit.

[0005] According to a third aspect of the present disclosure, a base station is provided, comprising: a semiconductor chip according to the second aspect of the present disclosure; and at least one antenna coupled to an I / O node of the semiconductor chip.

[0006] According to a fourth aspect of the present disclosure, a mobile device is provided, comprising: the semiconductor chip according to the second aspect of the present disclosure; and at least one antenna coupled to an I / O node of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Some examples of apparatus and / or methods will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0008] Figure 1 A first example of an ESD protection circuit is illustrated;

[0009] Figure 2 A second example of an ESD protection circuit is illustrated;

[0010] Figure 3 illustrates an exemplary charge device model (CDM) discharge path in a second example of an ESD protection circuit;

[0011] Figure 4 A third example of an ESD protection circuit is illustrated;

[0012] Figure 5 A fourth example of an ESD protection circuit is illustrated;

[0013] Figure 6 A fifth example of an ESD protection circuit is illustrated;

[0014] Figure 7 A system including an ESD protection circuit is illustrated;

[0015] Figure 8 An exemplary comparison of linearity and input power of different ESD protection circuits is illustrated;

[0016] Fig. 9 An exemplary comparison of diode transients under different reverse bias conditions is illustrated;

[0017] Fig.10 An exemplary comparison of return loss versus signal frequency for different reverse bias conditions is illustrated;

[0018] Fig.11 illustrates an example of a base station; and

[0019] Fig.12 An example of a mobile device is illustrated. DETAILED DESCRIPTION

[0020] Some examples are now described in more detail with reference to the accompanying drawings. However, other possible examples are not limited to the features of these embodiments described in detail. Other examples may include modifications to these features, as well as the equivalents and substitutions of these features. In addition, the terms used herein to describe certain examples should not limit other possible examples.

[0021] Throughout the description of the drawings, the same or similar reference numerals refer to the same or similar elements and / or features, which may be the same or implemented in a modified form while providing the same or similar functions. The thickness of the lines, layers and / or regions in the drawings may also be exaggerated for clarity.

[0022] When two elements A and B are combined using "or", this should be understood to disclose all possible combinations, i.e., only A, only B and A and B, unless otherwise explicitly defined in individual cases. As an alternative wording for the same combination, "at least one of A and B" or "A and / or B" can be used. This applies equally to combinations of more than two elements.

[0023] If singular forms such as "a", "an" and "the" are used, and there is no explicit or implicit limitation that only a single element is mandatory, other examples may also use several elements to achieve the same function. If a function is described below as being implemented using multiple elements, other examples may use a single element or a single processing entity to achieve the same function. It is also understood that the terms "comprises" and / or "comprising" when used describe the presence of specified features, integers, steps, operations, processes, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or groups thereof.

[0024] Figure 1 An exemplary ESD protection circuit 100 for a semiconductor chip is illustrated. The ESD protection circuit 100 comprises a first node 110 for coupling (configured to be coupled) to an input / output (I / O) node 101 of the semiconductor chip.

[0025] The I / O node 101 is a physical interface of the semiconductor chip, for example, a pad or bump for receiving an input signal (e.g., a radio frequency RF input signal) from an external device and / or outputting an output signal (e.g., an RF output signal) to an external device. The processing circuit 102 (e.g., a transceiver or a receiver) of the semiconductor chip is coupled to the I / O 101 node for processing the input signal and / or the output signal. The ESD protection circuit 100 is provided to protect the processing circuit 102 and optionally protect other circuits of the semiconductor chip from damage or failure caused by ESD at the I / O node 101.

[0026] The ESD protection circuit 100 includes a first conductive path (trace) 120 coupled to a first node 110 via at least one first diode 130. Figure 1 In the example of , exactly one first diode 130 is illustrated. However, it should be noted that in other examples, multiple first diodes coupled in series (in other words, stacked diodes) may be used instead to reduce the capacitance of the ESD protection circuit 100 and increase the ESD hardness. For example, the first conductive path 120 may alternatively be coupled to the first node 110 via two, three, or four first diodes 130 coupled in series. The first conductive path 120 is configured to be at a first voltage level that is higher than or equal to the voltage level of the first supply voltage of the semiconductor chip. For example, if the voltage level of the first supply voltage of the semiconductor chip is V DD , then the first voltage level can be V DD_virtual ≥V DD In other words, for the processing circuit 102 and optionally for further circuits of the semiconductor chip, the voltage level of the first conductive path 120 is at least the voltage level of the positive supply voltage of the semiconductor chip. The at least one first diode 130 is reverse biased by the first voltage level. For example, the at least one first diode 130 may be a p-type diode (i.e., a diode of the first conductivity type).

[0027] In addition, the ESD protection circuit 100 includes a second conductive path 140 coupled to the first node 110 via at least one second diode 150. Figure 1 In the example of , exactly one second diode 150 is illustrated. However, it should be noted that in other examples, multiple second diodes coupled in series (in other words, stacked diodes) may be used instead to reduce the capacitance of the ESD protection circuit 100 and increase the ESD hardness. For example, the second conductive path 140 may alternatively be coupled to the first node 110 via two, three, or four second diodes 150 coupled in series. The second conductive path 140 is configured to be at a second voltage level that is lower than or equal to the voltage level of the second power supply voltage of the semiconductor chip. The voltage level of the second power supply voltage is lower than the voltage level of the first power supply voltage. For example, if the voltage level of the second power supply voltage of the semiconductor chip is V SS , then the second voltage level can be V SS_virtual ≤V SS. In other words, for the processing circuit 102 and optionally for the further circuits of the semiconductor chip, the voltage level of the second conductive path 140 is at most the voltage level of the negative supply voltage of the semiconductor chip. The at least one second diode 150 is reverse biased by the second voltage level. For example, the at least one second diode 150 can be an n-type diode (i.e., a diode of the second conductivity type). In other embodiments, the at least one first diode 130 and the at least one second diode 150 can both be p-type diodes (i.e., diodes of the first conductivity type) or n-type diodes (i.e., diodes of the second conductivity type).

[0028] The number of the first diode(s) 130 and the number of the second diode(s) 150 may be the same as or different from each other.

[0029] In addition, the ESD protection circuit 100 includes a second node 160 for coupling to a ground node of the semiconductor chip or a power supply node of the semiconductor chip for providing a second power supply voltage. Figure 1 In the example of FIG. 1 , an exemplary node 103 is illustrated, which is a ground node of the semiconductor chip or a supply node of the semiconductor chip for providing a second supply voltage. The ground node is a node of the semiconductor chip for coupling to a (local) ground (potential) of the semiconductor chip 100 .

[0030] The first conductive path 120 is coupled to the second node 160 via at least one (first) capacitor 180. Figure 1 In the example of , exactly one capacitor 180 is illustrated. Note, however, that in other examples, multiple capacitors coupled in series (in other words, stacked capacitors) may instead be used to reduce the voltage drop at each capacitor between the first conductive path 120 and the second node 160 (e.g., to a voltage below 2 V at each capacitor as required by modern semiconductor technology nodes).

[0031] The second conductive path 140 is coupled to the second node 160 via at least one other (ie, second) capacitor 190. Figure 1 In the example of , exactly one other capacitor 190 is illustrated. Note, however, that in other examples, multiple capacitors coupled in series (in other words, stacked capacitors) may instead be used to reduce the voltage drop at each capacitor between the second conductive path 140 and the second node 160 (e.g., to a voltage below 2 V at each capacitor as required by modern semiconductor technology nodes).

[0032] At least one capacitor 180 and at least one other capacitor 190 are coupled in series between the first conductive path 120 and the second conductive path 140. The second node 160 is coupled between the at least one capacitor 180 and the at least one other capacitor 190. The number of the capacitors 180 and the number of the other capacitors 190 may be as Figure 1 For example, the first conductive path 120 may alternatively be coupled to the second node 160 via two capacitors 180 (coupled in series), and the second conductive path 140 may be coupled to the second node 160 via one other capacitor 190.

[0033] At least one capacitor 180 and at least one other capacitor 190 may be placed near the I / O node 101 or may also be distributed over the entire chip area of ​​the semiconductor chip.

[0034] The ESD protection circuit 100 is a low capacitance protection circuit for an overvoltage and undervoltage tolerant I / O node, such as the I / O node 101. The at least one first diode 130 is connected to a voltage level at least equal to a voltage level of a positive supply voltage of a semiconductor chip (e.g., equal to or higher than a common V DD Similarly, the at least one second diode 150 is connected to a voltage level that is at most equal to the voltage level of the negative supply voltage of the semiconductor chip (eg, equal to or lower than the common V SS level). Under normal signal conditions at the I / O node 101, this avoids forward biasing of the at least one first diode 130 and the at least one second diode 150 for larger signal amplitudes, thereby avoiding signal clipping. The pre-biasing of the diode junctions of the at least one first diode 130 and the at least one second diode 150 improves linearity and reduces the equivalent capacitance of the diodes, which also improves high-speed performance. Under unbiased ESD conditions, the diodes 130 and 150 enter forward bias at low voltages, thereby improving clamping capabilities. In addition, the reverse biased diode junctions of the at least one first diode 130 and the at least one second diode 150 provide lower capacitance, thereby additionally reducing the capacitive load from the I / O node 101 of the ESD protection circuit 100.

[0035] The second node 160 is connected to ground or a second supply voltage (eg, a global V SS) are closed by capacitors 180 and 190. Capacitors 180 and 190 implement clamping between the first conductive path 120 and the second conductive path 140. In addition, a corresponding discharge path is provided from the I / O node 101 to the second node 160 via one of the first conductive path 120 and the second conductive path 140. Since the second node 160 is stacked tapped between capacitors 180 and 190, all discharge paths in the CDM and the human body model (HBM) are covered. In addition, the appropriate voltage required for device reliability in modern semiconductor technology nodes can be guaranteed. For example, the transistor formed in the semiconductor chip can be a gate-all-around field-effect transistor (GAAFET) with a nanosheet or a complementary field-effect transistor (CFET) with a nanosheet. Such a modern semiconductor technology node has a low ESD victim breakdown voltage (e.g., less than 3V) and only allows a limited supply voltage. The ESD protection circuit 100 accommodates the demanding requirements of these modern semiconductor technology nodes and allows for robust ESD protection with low capacitive loading for overvoltage and undervoltage tolerant I / O nodes of semiconductor chips manufactured in modern semiconductor technology nodes.

[0036] The capacitance of at least one capacitor 180 and at least one other capacitor 190 may be equal to or different from each other. For example, the respective capacitance of at least one capacitor 180 and at least one other capacitor 190 may be greater than 500pF, 1nF, 5nF, 50nF, or 100nF. In some examples, the respective capacitance of at least one capacitor 180 may be greater than the respective capacitance of at least one other capacitor 190. For example, the respective capacitance of at least one capacitor 180 may be at least 100nF, while the respective capacitance of at least one other capacitor 190 may be at least 50nF.

[0037] The voltage levels of the first and second conductive paths 120 and 140 may be generated by additional circuits of the ESD protection circuit 100, locally in the semiconductor chip by circuits external to the ESD protection circuit 100, off-chip (i.e., by circuits external to the semiconductor chip), or a combination thereof.

[0038] For example, the ESD protection circuit 100 may optionally further include a bias circuit ( Figure 1(not shown in the figure). The bias circuit is configured to bias the first conductive path 120 to a first voltage level and bias the second conductive path 140 to a second voltage level. The bias circuit may, for example, include at least one charge pump, at least one low dropout regulator, or a combination thereof. However, it should be noted that the bias circuit is not limited thereto. Other components may also be used.

[0039] The voltage level(s) of the first conductive path 120 and / or the second conductive path 140 may be static or dynamic. In the case where the first conductive path 120 and / or the second conductive path 140 have (one or more) dynamic voltage levels, the bias circuit may, for example, be configured to receive a control signal and dynamically adjust at least one of the first voltage level and the second voltage level based on the control signal. The control signal is provided from a circuit external to the ESD protection circuit 100. Dynamically adjusting at least one of the first voltage level and the second voltage level may allow for optimal high-speed performance at the I / O node 101, for example by reducing the capacitance of the ESD protection circuit 100 presented to the I / O node 101, and improving linearity while minimizing the voltage required to bias the first conductive path 120 and / or the second conductive path 140. The control signal may, for example, be generated by a circuit external to the ESD protection circuit 100 in a self-calibrating manner using a metric for high-speed performance at the I / O node 101. For example, a circuit external to the ESD protection circuit 100 may select one or more specific voltage level settings for the first voltage level and / or the second voltage level based on a target value or characteristic of high-speed performance at the I / O node 101 (e.g., a signal-to-noise ratio (SNR) or a third-order intercept point (IP3)), and generate a control signal accordingly.

[0040] If the voltage levels of the first conductive path 120 and the second conductive path 140 are generated locally on the semiconductor chip by a circuit external to the ESD protection circuit 100 or generated off-chip (i.e., generated by a circuit external to the semiconductor chip), the first conductive path 120 may be coupled to (configured to be coupled to, coupleable to) a node of the semiconductor chip to connect the first conductive path 120 to a voltage source ( Figure 1 The first and second conductive paths 140 and 141 may be coupled to (configured to be coupled to, coupleable to) a node of the semiconductor chip to couple the second conductive path with a voltage source circuit to provide a second voltage level. The voltage source is located outside the ESD protection circuit 100. For example, one or both of the voltage sources may be implemented (integrated) in the semiconductor chip, or may be outside the chip.

[0041] In some examples, conductive paths 120 and 140 can be coupled to circuits external to ESD protection circuit 100 via respective nodes providing first / second voltage levels, and additionally coupled to bias circuits.

[0042] Regardless of the source(s) of the first and second voltage levels, the ESD protection circuit 100 may include a third node ( Figure 1 ), which is used to couple to another power supply node of the semiconductor chip for providing the first power supply voltage. Similarly, the ESD protection circuit 100 may include a fourth node ( Figure 1 The first conductive path 120 is connected to the power supply node of the semiconductor chip (the fourth node is separated from the second node 160). The first conductive path 120 is connected to the power supply node of the semiconductor chip via a resistor, an inductor or a transmission gate ( Figure 1 Similarly, the second conductive path 140 is coupled to the third node via at least one of another resistor, another inductor, or another transmission gate (not shown). Figure 1 The resistor and the further resistor may, for example, exhibit a resistance of at least 10 kΩ, 50 kΩ, or 100 kΩ, respectively. Placing at least one of the respective resistor, inductor, or transmission gate between the respective conductive path 120 or 140 and the respective one of the power supply node and the further power supply node allows minimizing leakage current from the respective conductive path 120 or 140 to the respective one of the power supply node and the further power supply node. By coupling the respective resistors in series with the transmission gates, the respective transmission gates may be protected under ESD.

[0043] The third node and the fourth node may be connected via (by) a power clamp (ESD clamp circuit; Figure 1120 and the second conductive path 140. In other words, the power clamp is coupled between the first conductive path 120 and the second conductive path 140. A power clamp is an electronic device or circuit that limits the voltage and / or current between the first conductive path 120 and the second conductive path 140 during an ESD event. The power clamp can have many different variations. Specifically, the power clamp can be a static or transient power clamp. A static clamp provides a static or steady-state current and voltage response. A fixed voltage level activates the static clamp. As long as the voltage is above this level, the clamp conducts current. For example, a static clamp may be diode-based, metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field-Effect Transistor, MOSFET)-based, or semiconductor controlled rectifier (Semiconductor Controlled Rectifier, SCR)-based. On the other hand, a transient clamp takes advantage of the rapid changes in voltage and / or current that accompany an ESD event. During this transient, the element is turned on very quickly and turned off slowly. This type of clamp conducts for a fixed time when it is triggered.

[0044] In some examples, the first power clamp (first ESD clamp circuit; Figure 1 The first power clamp is coupled in parallel with at least one capacitor 180. Similarly, the second power clamp (second ESD clamp circuit; Figure 1 A second power clamp (not shown) may be additionally coupled between the second conductive path 140 and the second node 160. The second power clamp is coupled in parallel with at least one other capacitor 190. The first and second power clamps allow minimizing the leakage current from the respective conductive path 120 or 140 to the second node 160, thereby reducing the leakage current to the ground or supply node 103 of the semiconductor chip.

[0045] According to some examples, the ESD protection circuit 100 may additionally include a first flyback diode (first freewheeling diode; Figure 1 The first flyback diode is coupled in parallel with at least one capacitor 180 and the first power clamp. Similarly, the second flyback diode (second freewheeling diode; Figure 1 A second flyback diode (not shown) may be coupled between the second conductive path 140 and the second node 160. The second flyback diode is coupled in parallel with at least one other capacitor 190 and the second power clamp.

[0046] Figure 2Another exemplary ESD protection circuit 200 is illustrated. The ESD protection circuit 200 is based on the ESD protection circuit 100 described above.

[0047] Compared to the ESD protection circuit 100, the ESD protection circuit 200 includes two capacitors 180-1 and 180-2 coupled in series between the first conductive path 120 and the second node 160, rather than a single capacitor. Figure 2 In the example of FIG. 1 , the first conductive path 120 is coupled to the second node 160 via two capacitors 180-1 and 180-2, and the second conductive path 140 is coupled to the second node 160 via another capacitor 190. The use of additional capacitors allows the voltage drop of each capacitor between the first conductive path 120 and the second node 160 to be reduced compared to the ESD protection circuit 100.

[0048] The respective capacitance of capacitors 180-1 and 180-2 may be greater than the capacitance of other capacitors 190. For example, the respective capacitance of capacitors 180-1 and 180-2 (eg, 100 nF each) may be at least twice the capacitance of other capacitors 190 (eg, 50 nF).

[0049] In addition, the ESD protection circuit 200 further includes a third node 185 for coupling to another power supply node 104 of the semiconductor chip for providing the first power supply voltage. The first conductive path 120 is coupled to the third node 185 via at least one of a resistor, an inductor, or a transmission gate. Figure 2 In the example of , an exemplary element 175 is illustrated, which is a resistor, an inductor, a transmission gate, or a combination thereof. The ESD protection circuit 200 also includes a fourth node 195 for coupling to the power supply node 103 of the semiconductor chip (the fourth node 195 is separated from the second node 160). The second conductive path 140 is coupled to the fourth node 195 via at least one of another resistor, another inductor, or another transmission gate. Figure 2 In the example of , an exemplary element 170 is illustrated, which is another resistor, another inductor, another transmission gate, or a combination thereof. The resistor and the other resistor may, for example, exhibit a resistance of at least 10 kΩ, 50 kΩ, or 100 kΩ, respectively. Placing at least one of the respective resistors, inductors, or transmission gates 170, 175 between the respective conductive path 120 or 140 and the respective one of the supply node 103 and the further supply node 104 allows minimizing the leakage current from each conductive path 120 or 140 to the respective one of the supply node 103 and the further supply node 104.

[0050] The third node 185 and the fourth node 195 are coupled via (by) the power clamp 115. The power clamp is also coupled between the third node 185 and each of the second node 160 and the power supply node 103.

[0051] Figure 2 The lower left portion of FIG. 1 further illustrates the effect of the reverse bias of the at least one first diode 130 and the at least one second diode 150. With respect to the at least one second diode 150, the second voltage level V SS_virtual The exemplary reverse bias voltage V R , the junction capacitance C of at least one second diode 150 is plotted Junction .from Figure 2 It can be seen that the polarization of at least one second diode 150 in the reverse direction causes its junction capacitance C Junction The junction capacitance of the at least one second diode 150 is reduced (e.g., reduced by 15% or more). The junction capacitance of the at least one second diode 150 is reduced, which improves the bandwidth of the I / O node 101, for example, for high-speed signals (e.g., the bandwidth can be from 400 MHz to 8.4 GHz or even wider). Similarly, the polarization of the at least one first diode 130 in the reverse direction causes its junction capacitance to be reduced, which in turn improves the bandwidth and input matching of the I / O node 101 (due to the reduction of input return loss).

[0052] For example, Figure 2 As shown in the upper left portion of , if the I / O node 101 is required to operate with a signal at a 0.6V baseline, and the nominal signal swing is between -1.3V and 2.5V, and the fail-safe overvoltage is 4.5V, then the ESD protection circuit 200 may be used.

[0053] By setting the first voltage level of the first conductive path 120 to a voltage greater than 2.5V, i.e., the maximum voltage of the signal swing under normal operating conditions, the at least one first diode 130 is prevented from conducting even in the event of an overvoltage. In other words, the first conductive path 120 is configured to be at a first voltage level that is higher than the nominal maximum signal voltage of the signal received by the I / O node 101 (higher than the target maximum signal voltage of the signal received by the I / O node 101 under normal operating conditions). This improves signal integrity. For example, the first voltage level may be set to V DD_virtual =2.85V. Assume that the first power supply voltage of the semiconductor chip is V DD=1.2V, the at least one first diode 130 is reverse biased due to the first voltage level of the first conductive path 120, which results in a reduction in junction capacitance of the at least one first diode 130 (e.g., a reduction of 15% or more in this example). The reduced junction capacitance improves the bandwidth and input matching (due to a reduction in input return loss) of the I / O node 101, especially for high-speed signals.

[0054] Similarly, by setting the second voltage level of the second conductive path 140 to a voltage lower than -1.3V, i.e., the minimum voltage of the signal swing under normal operating conditions, the at least one second diode 150 is prevented from conducting even in an undervoltage condition. In other words, the second conductive path 140 is configured to be at a second voltage level that is lower than the nominal minimum signal voltage of the signal received by the I / O node 101 (lower than the target minimum signal voltage of the signal received by the I / O node 101 under normal operating conditions). This improves signal integrity. For example, the second voltage level may be set to V SS_virtual =-1.65V. Assume that the second power supply voltage of the semiconductor chip is V SS =0V, the at least one second diode 150 is reverse biased due to the second voltage level of the second conductive path 140, which results in a reduction in the junction capacitance of the at least one second diode 150 (e.g., a reduction of 15% or more in this example). The reduced junction capacitance improves the bandwidth and input matching (due to the reduction in input return loss) of the I / O node 101, especially for high-speed signals.

[0055] The first conductive path 120 is coupled to a first supply voltage provided by the other supply node 104 via the element 175. During, for example, power-on, the first supply voltage provides a voltage bias for a first voltage level of the first conductive path 120. The second conductive path 140 is coupled to a second supply voltage provided by the supply node 103 via the element 170. During, for example, power-on, the second supply voltage provides a voltage bias for a second voltage level of the second conductive path 140.

[0056] The voltage levels of the first conductive path 120 and the second conductive path 140 can be determined by the bias circuit ( Figure 2 For example, Figure 2 In the example of , the bias circuit may be coupled to the left ends of the first conductive path 120 and the second conductive path 140. Additionally or alternatively, the voltage levels of the first conductive path 120 and the second conductive path 140 may be generated locally in the semiconductor chip by a circuit external to the ESD protection circuit 100, and / or generated off-chip (i.e., by a circuit external to the semiconductor chip), similar to the above description of Figure 1The left ends of the first conductive path 120 and the second conductive path 140 may be coupled to (one or more) sources of the first / second voltage level, respectively.

[0057] Figure 3 Exemplary CDM discharge paths 301, 302, and 303 in ESD protection circuit 200 are illustrated in FIG. Under CDM stress, the semiconductor chip is powered off, all power supplies are floating, and CDM discharge occurs at I / O node 101 toward the capacitively charged package and ground plane.

[0058] Under negative CDM (ie, positive current at I / O node 101), current is forced into the I / O node toward the second supply voltage V SS A high current (e.g., 1A, 2A, 3A, 4A, 5A, or greater) of short duration (e.g., less than 10ns, 5ns, or 1ns) may occur. The current flows via at least one first diode 130, the first conductive path 120, and the two capacitors 180-1 and 180-2, such as Figure 3 The capacitance of capacitors 180-1 and 180-2 can be selected (set in size) to provide a first voltage level of the first conductive path 120 to a second supply voltage V under CDM pressure. SS Low resistance coupling of voltage levels.

[0059] Under positive CDM (negative current at I / O node 101), a negative current is forced at I / O node 101 toward the second supply voltage V SS A high current (e.g., 1A, 2A, 3A, 4A, 5A, or greater) of short duration (e.g., less than 10ns, 5ns, or 1ns) may occur. The current flows via at least one second diode 150, the second conductive path 140, and the other capacitor 190, such as Figure 3 The capacitance of the other capacitor 190 can be selected (set in size) to provide the second voltage level of the second conductive path 140 to the second supply voltage V under CDM pressure. SS Low resistance coupling of voltage levels.

[0060] In V DD or V SS Under CDM pressure, the current flows through the power clamp 115 at the first supply voltage V DD The voltage level and the second supply voltage V SSAs shown in discharge path 303. The remaining charge stored in I / O node 101 can be discharged via capacitors 180-1, 180-2, and 190, which connect the voltage levels V of I / O node 101 and first conductive path 120 and second conductive path 140. DD_virtual and V SS_virtual coupled to the first and second supply voltages V provided by supply nodes 103 and 104 DD and V SS voltage level.

[0061] The first supply voltage V DD The voltage level and the second supply voltage V SS The power clamp 115 is placed between the voltage levels of V DD The power clamp further implements HBM protection for the following items: the power supply or HBM pressure at the I / O node 101 is relative to the first power supply voltage V provided by another power supply node 104. DD The voltage level of the HBM pressure at the I / O node 101 is relative to the second supply voltage V provided by the supply node 103. SS In addition, the power clamp 115 allows the first power supply voltage V provided from the I / O node 101 or from another power supply node 104 to be DD The voltage level to Figure 3 Any stress from other power domains or signals not specified in the drive HBM current.

[0062] During HBM stress on I / O node 101, current flows similarly to CDM stress. Diodes 130 and 150 and capacitors 180-1, 180-2, and 190 shunt current from I / O node 101 to a second supply voltage V provided by supply node 103. SS Depending on the HBM pressure combination, the current sink or current source can be at the first supply voltage V DD The voltage level of the second supply voltage V SS voltage level, or Figure 3 Any other node in the same or different power domain not specified in .

[0063] Figure 4 Another exemplary ESD protection circuit 400 is illustrated. The ESD protection circuit 400 is based on the ESD protection circuit 200 described above.

[0064] Compared to the ESD protection circuit 200, the ESD protection circuit 400 does not include the power clamp 115. In addition, the other power supply node 104 is arranged on the left side of the ESD protection circuit instead of the right side. Therefore, the element 175 representing at least one of a resistor, an inductor or a transmission gate is arranged on the left side of the ESD protection circuit 400.

[0065] and Figures 1 to 3 different, Figure 4 The bias circuit 410 for biasing the first conductive path 120 and the second conductive path 140 is explicitly shown. The bias circuit 410 is coupled to the first conductive path 120 and the second conductive path 140 via respective optional resistors. As described above, the bias circuit 410 is configured to bias the first conductive path 120 to a first voltage level V DD_virtual , and biases the second conductive path 140 to a second voltage level V SS_virtual . Figure 4 An exemplary design of bias circuit 410 is shown. Note that the present disclosure is not limited to Figure 4 The specific design of the bias circuit 410 is shown in FIG.

[0066] The bias circuit 410 includes a low-dropout (LDO) regulator 412 and two charge pumps 411 and 413. The LDO regulator 412 is configured to receive a supply voltage, such as a first supply voltage V DD , and the first supply voltage V DD The charge pumps 411 and 413 are configured to receive the pump supply voltage and convert it to a first voltage level V DD_virtual and the second voltage level V SS_virtual Specifically, the charge pump 411 is configured to convert the pump supply voltage from the LDO regulator 412 into a second voltage level V SS_virtual The power supply signal is used to bias the second conductive path 140 to the second voltage level V SS_virtual Similarly, the charge pump 411 is configured to convert the pump supply voltage from the LDO regulator 412 to a first voltage level V DD_virtual The power supply signal is used to bias the first conductive path 120 to a first voltage level V DD_virtual The charge pumps 411 and 413 are configured to convert the pump supply voltage based on received (eg, spread spectrum) clock signals 414 - 1 , 414 - 2 (the clock signals may be the same or different from each other).

[0067] For example, Figure 4As shown in the upper left portion of , if the I / O node 101 is required to operate with a signal at a 0.6V baseline, and the nominal signal swing is between -1.65V and 2.85V, and the fail-safe overvoltage is 4.5V, then the ESD protection circuit 400 may be used.

[0068] By using the bias circuit 410 to set the first voltage level V of the first conductive path 120 DD_virtual The first voltage level may be set to a voltage greater than 2.85 V, which is the maximum voltage of the signal swing under normal operating conditions, and prevents the at least one first diode 130 from conducting even in the event of an overvoltage. This improves signal integrity. For example, the first voltage level may be set to V DD_virtual =3.2V. Assume that the first power supply voltage of the semiconductor chip is V DD =1.2V, the at least one first diode 130 is reverse biased due to the first voltage level of the first conductive path 120, which results in a reduction in junction capacitance of the at least one first diode 130 (e.g., a reduction of 15% or more in this example). The reduced junction capacitance improves the bandwidth, input matching (due to a reduction in input return loss), and linearity (e.g., third-order input intercept point, IP3) of the I / O node 101, especially for high-speed signals.

[0069] Similarly, by setting the second voltage level of the second conductive path 140 to a voltage lower than -1.65V, i.e., the minimum voltage of the signal swing under normal operating conditions, by means of the bias circuit 410, the at least one second diode 150 is prevented from conducting even in an undervoltage condition. This improves signal integrity. For example, the second voltage level may be set to V SS_virtual =-2.0V. Assume that the second power supply voltage of the semiconductor chip is V SS =0V, the at least one second diode 150 is reverse biased due to the second voltage level of the second conductive path 140, which results in a reduction in the junction capacitance of the at least one second diode 150 (e.g., a reduction of 15% or more in this example). The reduced junction capacitance improves the bandwidth, input matching (due to a reduction in input return loss), and linearity (e.g., IP3) of the I / O node 101, especially for high-speed signals.

[0070] exist Figure 4 The discharge paths 401 and 402 of positive and negative CDM ESD stresses are further illustrated in FIG.

[0071] For example, if the ESD protection circuit 400 is used in a modern semiconductor technology node using a GAAFET (e.g., RibbonFET transistor) with a nanosheet or a CFET with a nanosheet, the chip area used for clamping with the capacitors 180-1, 180-2, and 190 may be smaller than in conventional technology. The capacitors 180-1, 180-2, and 190 may be realized (formed, implemented) as dense metal-insulator-metal capacitors placed on the back side of the chip so that they do not consume chip area.

[0072] Figure 5 There is illustrated another ESD protection circuit 500. The ESD protection circuit 500 is a variation of the ESD protection circuit 400 described above.

[0073] Compared to the ESD protection circuit 400 , the ESD protection circuit 500 includes two first diodes 130 - 1 and 130 - 2 and two second diodes 150 - 1 and 150 - 2 to improve ESD hardness. In addition, the ESD protection circuit 400 includes only a single capacitor 180 coupled between the first conductive path 120 and the second node 160 .

[0074] Figure 6 Another ESD protection circuit 600 is illustrated for protecting a processing circuit 102 of a semiconductor chip. As with the above example, the ESD protection circuit 600 includes a first node 110 for coupling to an I / O node 101 of the semiconductor chip.

[0075] At the first voltage level V DD_virtual The first conductive path 120 is coupled to the first node 110 via two first diodes 130-1 and 130-2, similar to what is described above for some other examples. SS_virtual The second conductive path 140 is coupled to the first node 110 via two second diodes 150-1 and 150-2. The first conductive path 120 is coupled to the second node 160 via a capacitor 180, and the second conductive path 140 is coupled to the second node 160 via another capacitor 190, similar to what is described above for some other examples. For example, capacitors 180 and 190 can be metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitors or MIM-metal finger capacitors (MIM-Metal Finger Capacitor, MIM-MFC). The second node 160 is coupled to the power supply node 103, which provides a ground or a second supply voltage V SS .

[0076] exist Figure 6In the example of , the first power clamp (first ESD clamp circuit) 620 is additionally coupled between the first conductive path 120 and the second node 160. The first power clamp 620 is coupled in parallel with the capacitor 180. Similarly, the second power clamp (second ESD clamp circuit) 625 is additionally coupled between the second conductive path 140 and the second node 160. The second power clamp 625 is coupled in parallel with another capacitor 190. The first and second power clamps 620 and 625 allow to minimize the leakage current from each conductive path 120 or 140 to the second node 160, thereby reducing the leakage current to the ground or power supply node 103 of the semiconductor chip.

[0077] In addition, the ESD protection circuit 600 additionally includes a first flyback diode (first freewheeling diode) 630 coupled between the first conductive path 120 and the second node 160. The first flyback diode 630 is coupled in parallel with the capacitor 180 and the first power clamp 620. Similarly, a second flyback diode (second freewheeling diode) 635 is coupled between the second conductive path 140 and the second node 160. The second flyback diode 635 is coupled in parallel with another capacitor 190 and the second power clamp 625. It is noted that the flyback diodes 630 and 635 are optional and may be omitted according to examples of the present disclosure.

[0078] Additionally, the above-described ESD protection circuit may include power clamps and flyback diodes similar to the power clamps 620 and 624 and the flyback diodes 630 and 635 of the ESD protection circuit 600 .

[0079] The ESD protection circuit 600 further includes a bias circuit 610 for biasing the first conductive path 120 and the second conductive path 140. The bias circuit 610 is coupled to the first conductive path 120 and the second conductive path 140. As described above, the bias circuit 610 is configured to bias the first conductive path 120 to a first voltage level V DD_virtual , and biases the second conductive path 140 to a second voltage level V SS_virtual Similar to the above-mentioned bias circuit 410 , the bias circuit 610 includes two charge pumps 611 and 613 .

[0080] The charge pumps 611 and 613 are configured to receive respective pump supply voltages 616-1, 616-2 and convert them to a first voltage level V DD_virtual and the second voltage level V SS_virtual Specifically, the charge pump 611 is configured to convert the pump supply voltage 616-2 into a second voltage level V SS_virtual The power supply signal is used to bias the second conductive path 140 to the second voltage level V SS_virtualSimilarly, the charge pump 613 is configured to convert the pump supply voltage 616-1 to a first voltage level V DD_virtual The power supply signal is used to bias the first conductive path 120 to a first voltage level V DD_virtual The charge pumps 611 and 613 are configured to convert the pump supply voltage based on respective (eg, spread spectrum) pump clock signals 617 - 1 , 617 - 2 (the clock signals may be the same or different from each other).

[0081] The pump supply voltage 616-1 and the pump clock signal 617-1 are generated by a first control circuit 614 for controlling the charge pump 613. The first control circuit 614 is configured to receive a reference voltage signal 601 (e.g., at a voltage level of 0.5V) and a first (e.g., spread spectrum) clock signal 615-1. In addition, the first control circuit 614 is coupled to the output of the charge pump 614 via a feedback loop 618 to receive a first voltage level V at the first conductive path 120. DD_virtual The first control circuit 614 is configured to generate a pump supply voltage 616-1 based on a comparison of the reference voltage signal 601 and the first feedback signal. In addition, the first control circuit 614 is configured to generate a pump clock signal 617-1 based on the first clock signal 615-1.

[0082] The pump supply voltage 616-2 and the pump clock signal 617-2 are generated by a second control circuit 612 for controlling the charge pump 611. The second control circuit 612 is configured to receive the reference voltage signal 601 and the second (e.g., spread spectrum) clock signal 615-2. In addition, the second control circuit 612 is coupled to the output of the charge pump 613 via a feedback loop 619 to receive a second voltage level V at the second conductive path 140. SS_virtual The second control circuit 612 is configured to generate a pump supply voltage 616-2 based on a comparison of the reference voltage signal 601 and the second feedback signal. In addition, the second control circuit 612 is configured to generate a pump clock signal 617-2 based on the first clock signal 615-2.

[0083] like Figure 6 As shown in the reference symbol 602 in FIG. 1 , the charge pumps 611 and 613 and the control circuits 612 and 614 are provided with a first power supply voltage V DD .

[0084] The bias circuit 610 uses a servo loop to control the charge pumps 611 and 613 to improve the bandgap accuracy.

[0085] As described above, the first voltage level V can be dynamically adjusted DD_virtual and the second voltage level V SS_virtual . Figure 7The diagram shows a method for dynamically adjusting the first voltage level V DD_virtual and the second voltage level V SS_virtual An exemplary system 700 is provided. The system includes the ESD protection circuit 600 described above.

[0086] exist Figure 7 In the example of , processing circuit 102 is one of the RF receivers of the RF transceiver. Processing circuit 102 receives an analog RF receive signal from I / O node 101. I / O node 101 is protected by ESD protection circuit 600 as described above. Processing circuit 102 generates a digital receive signal 701 based on the analog RF receive signal.

[0087] The digital receive signal 701 is received by a control circuit 710 outside the ESD protection circuit 600. The control circuit 710 may be integrated into a semiconductor chip, or may be outside the chip. The control circuit 710 is configured to analyze the digital receive signal 701 using a measure of high-speed performance at the I / O node 101. For example, the control circuit 710 may select one or more specific voltage level settings for the first voltage level and / or the second voltage level based on a target value or characteristic of high-speed performance at the I / O node 101, such as an SNR or IP3 of the digital receive signal 701. The control circuit 710 generates a control signal 711 indicating one or more voltage level settings selected for the first voltage level and / or the second voltage level, and outputs the control signal 711 to the bias circuit 610.

[0088] Control circuits 612 and 614 control charge pumps 611 and 613 based on control signal 711 to adjust output bias voltages of first and second conductive paths 120 and 140 to one or more voltage level settings of the first voltage level and / or the second voltage level indicated by control signal 711 .

[0089] Dynamically adjusting the first voltage level and the second voltage level may allow for optimal high speed performance at the I / O node 101, for example by reducing the capacitance of the ESD protection circuit 600 presented to the I / O node 101 and improving linearity while minimizing the voltage required to bias the first conductive path 120 and / or the second conductive path 140.

[0090] The above-mentioned bias circuits 410 and 610 can be optionally used for the above-mentioned Figures 1 to 3 The ESD protection circuit is described in

[0091] Figure 8Schematic diagram 800 is illustrated, highlighting an exemplary comparison of linearity and input power of different ESD protection circuits coupled to an I / O node of a semiconductor chip. The abscissa of schematic diagram 800 represents input power to the I / O node. The ordinate represents third-order intermodulation distortion (3 rd order InterModulation Distortion, IMD3), as a measure of linearity.

[0092] Curve 810 shows the history of IMD3 of the first ESD protection circuit. The first ESD protection circuit is a conventional ESD protection circuit that uses a single diode between the I / O node and each conductive path. Curve 820 shows the history of IMD3 of the second ESD protection circuit. The second ESD protection circuit is a conventional ESD protection circuit that uses two stacked diodes. Curve 830 shows the history of IMD3 of the third ESD protection circuit. The third ESD protection circuit is a conventional ESD protection circuit that uses three stacked diodes.

[0093] For an ideal linear I / O node, IMD3 and input power should form a straight line. As can be seen from curve 810, for the first ESD protection circuit, linearity is only maintained within a small input power range. By increasing the number of stacked diodes, the linearity of the I / O node can be extended to higher input powers, as can be seen from curves 820 and 830.

[0094] Curve 840 shows an ESD protection circuit (eg, Figures 1 to 4 or Figure 7 840). It is apparent from curve 840 that the ESD protection circuit according to the present disclosure provides improved linearity and lower IMD3 over the input power spectrum. Reverse biasing of the diode according to the proposed architecture improves linearity and reduces the equivalent capacitance of the diode, which also improves high speed performance.

[0095] Fig. 9 Further illustrating schematic diagram 900, highlighting Figure 2 900 shows an exemplary comparison of diode transients under different reverse bias conditions in the ESD protection circuit 200. The abscissa of the graph 900 represents time. The ordinate represents the diode current into the diode.

[0096] Transient 910 is a first voltage level V at the conductive path. DD_virtual1 and the second voltage level V SS_virtual1 The transient state 920 is a first voltage level V at the conductive path. DD_virtual3and the second voltage level V SS_virtual2 The transient state 930 is a first voltage level V at the conductive path. DD_virtual3 and the second voltage level V SS_virtual3 What was obtained.

[0097] The first voltage level is as follows: V DD_virtual1 <V DD_virtual2 <V DD_virtual3

[0098] The second voltage level is as follows: V SS_virtual3 <V SS_virtual2 <V SS_virtual1

[0099] As can be seen from transient 910, for smaller values ​​of the first and second voltage levels (e.g., if the first voltage level is not higher than the voltage level of the first supply voltage, and the second voltage level is not lower than the voltage level of the second supply voltage), a rectifying effect occurs. By increasing the reverse bias of the diode, the rectifying effect of the diode disappears, as can be seen from transients 920 and 930 (only the diode capacitance effect remains). Due to the higher reverse bias, the harmonic content in the signal is minimized. Since the diode remains reverse biased during operation, the current is reduced to a minimum when a higher reverse bias is used.

[0100] Fig.10 The diagram shows Figure 2 1000 shows an exemplary comparison of return loss and signal frequency under different reverse bias conditions in the ESD protection circuit 200 shown in FIG. The abscissa of the schematic diagram 1000 represents the frequency of the signal input to the I / O node. The ordinate represents the S11 parameter as a measure of the return loss.

[0101] Curve 1020 is a graph showing a first voltage level V at the conductive path. DD_virtual1 and the second voltage level V SS_virtual1 Curve 1030 is a graph showing a first voltage level V at the conductive path. DD_virtual3 and the second voltage level V SS_virtual2 Curve 1040 is a graph showing the first voltage level V at the conductive path. DD_virtual3 and the second voltage level V SS_virtual3 What was obtained.

[0102] The first voltage level is as follows: V DD_virtual1 <V DD_virtual2 <V DD_virtual3

[0103] The second voltage level is as follows: V SS_virtual3 <V SS_virtual2 <V SS_virtual1

[0104] As can be seen from transients 1020, 1030, and 1040, the S11 parameter, and therefore the return loss, improves significantly as the reverse bias of the diode increases.

[0105] For reference, curve 1010 illustrates the history of the S11 parameter for a conventional ESD protection circuit using a single diode between an I / O node and each conductive path.

[0106] The proposed ESD protection circuit can achieve cost reduction because no external matching network with an inductor is required. In addition, an on-chip matching network at the I / O node is not required. Therefore, coupling of external distortion and degradation of signal integrity can be avoided. Due to the reverse biased junction of the ESD diode, the capacitive load of the I / O node can be reduced (e.g., reduced by more than 15%), which additionally allows the bandwidth of the I / O node to be improved in operation (e.g., the bandwidth can be from 400MHz to 8.4GHz or even higher). Even for overvoltage / undervoltage at the I / O node (e.g., overvoltage / undervoltage at the I / O node>2V for supply voltages of 1.2V and 0V), the signal integrity of the I / O node can still be maintained. In addition, the return loss is also significantly improved (e.g., 1.5dB at 8.4GHz). The proposed ESD protection circuit can be used with any semiconductor technology node (specifically, a node using a GAAFET (e.g., a RibbonFET transistor) with a nanosheet, or a node using a CFET with a nanosheet).

[0107] exist Fig.11 An example of an implementation method using the following ESD protection circuit is illustrated in FIG. Figures 1 to 7 One or more aspects of the architecture described or related to the above Figures 1 to 7 One or more examples of the description. Fig.11 An example of a radio base station 1100 (eg for a femtocell, picocell, microcell or macrocell) comprising the proposed ESD protection circuit 1130 is schematically illustrated.

[0108] The base station 1100 includes at least one antenna element 1160. The antenna element 1160 is coupled to an I / O node 1111 of the semiconductor chip 1110. The semiconductor chip 1110 may be coupled to the antenna element 1160 via one or more intermediate elements, such as one or more of a signal line, a filter, an up-converter (mixer), a down-converter (mixer), a power amplifier (PA), and the like.

[0109] The semiconductor chip 1110 includes a signal processing circuit 1140 coupled to the I / O node 1111. The semiconductor chip 1110 is configured to provide the first power supply voltage and the second power supply voltage as described above to the signal processing circuit 1140. The signal processing circuit 1140 may, for example, include an RF transceiver or be an RF transceiver. Additionally or alternatively, the signal processing circuit 1140 may include or may be at least one of an RF transmitter and an RF receiver.

[0110] The baseband processing circuit (eg, baseband processor) 1150 is coupled to the signal processing circuit 1140 of the semiconductor chip 1100. The baseband processing circuit 1150 may be Fig.11 1100 is located outside the chip as shown in , or can be integrated into the semiconductor chip 1110. Depending on the type of the signal processing circuit 1140, the baseband processing circuit 1150 is configured to send digital transmission data to the signal processing circuit 1140, and / or receive digital reception data from the signal processing circuit 1140. For example, if the signal processing circuit 1140 includes or is an RF receiver, the baseband processing circuit 1150 is configured to receive digital reception data from the signal processing circuit 1140. If the signal processing circuit 1140 includes or is an RF transmitter, the baseband processing circuit 1150 is configured to send digital transmission data to the signal processing circuit 1140. If the signal processing circuit 1140 includes or is an RF transceiver, the signal processing circuit 1140 is configured to send digital transmission data to the signal processing circuit 1140, and receive digital reception data from the signal processing circuit 1140.

[0111] The baseband processing circuit 1150 is configured to perform baseband processing on the digital received data. Similarly, the baseband processing circuit 1150 is configured to generate digital transmit data by performing baseband processing on the data to be wirelessly transmitted. The RF transmitter or RF transceiver can generate an RF transmit signal based on the digital transmit data, and use the antenna element 1160 or another antenna element (not shown) of the base station 1100 to radiate the RF transmit signal into the environment. Similarly, the RF receiver or RF transceiver can receive an RF receive signal received from the antenna element 1160 or another antenna element (not shown) of the base station 1100, and generate digital receive data based on the RF receive signal.

[0112] The signal processing circuit 1140 may include various additional elements, such as one or more of a low-noise amplifier (Low-Noise Amplifier, LNA), a filter, an attenuator, and the like.

[0113] In addition, ESD protection circuit 1130 is coupled to I / O node 1111. Specifically, a first node of ESD protection circuit 1130 is coupled to I / O node 1111 to protect signal processing circuit 1140 and optionally other circuits of semiconductor chip 1110 from damage or failure caused by ESD at I / O node 1111.

[0114] To this end, a base station with improved ESD protection capability may be provided, thereby allowing the base station to achieve higher linearity and higher bandwidth (eg, the bandwidth may be from 400 MHz to 8.4 GHz or even wider).

[0115] The semiconductor chip 1110 (and optionally other elements of the base station 1100) can be manufactured in modern semiconductor technology nodes using GAAFETs (e.g., RibbonFET transistors) with nanosheets or CFETs with nanosheets. In other words, the transistors formed in the semiconductor chip 1100 can be GAAFETs with nanosheets or CFETs with nanosheets.

[0116] The base station 1100 may include additional elements, such as an application processor, memory, a network controller, a user interface, a power management circuit, a satellite navigation receiver, a network interface controller, or a power tee circuit.

[0117] In some aspects, the application processor may include one or more central processing unit (CPU) cores, and one or more of the following: cache memory, LDO voltage regulator, interrupt controller, such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (IC), etc. 2 C) or a general purpose programmable serial interface module, a real-time clock (RTC), timer-counters including interval and watchdog timers, general purpose input-output (IO), a memory card controller such as a Secure Digital (SD) / MultiMedia Card (MMC), a Universal Serial Bus (USB) interface, a Mobile Industry Processor Interface Alliance (MIPI) interface, and a Joint Test Access Group (JTAG) test access port.

[0118] In some aspects, baseband processing circuit 1150 may be implemented as, for example, a solder-in substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more integrated circuits.

[0119] In some aspects, the memory may include one or more of the following: volatile memory, including dynamic random access memory (DRAM) and / or synchronous dynamic random access memory (SDRAM); and non-volatile memory (NVM), including high-speed electrically erasable memory (commonly referred to as flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), and / or three-dimensional cross point (3D XPoint) memory. The memory may be implemented as one or more of the following: a solder-in packaged integrated circuit, a socketed memory module, and a plug-in memory card.

[0120] In some aspects, the power management (integrated) circuit may include one or more of the following: a voltage regulator, a surge protector, a power alarm detection circuit, and one or more backup power sources such as batteries or capacitors. The power alarm detection circuit may detect one or more of a brownout (undervoltage) and a surge (overvoltage) condition.

[0121] In some aspects, a power tee circuit can provide power drawn from a network cable to provide both power supply and data connectivity to a base station using a single cable.

[0122] In some aspects, the network controller may provide connectivity to the network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection that is one of electrical (commonly referred to as a copper interconnect), optical, or wireless.

[0123] In some aspects, a satellite navigation receiver may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), Galileo, and / or BeiDou. The receiver may provide data to an application processor, which may include one or more of position data or time data. The application processor may use the time data to synchronize operations with other radio base stations.

[0124] In some aspects, the user interface may include one or more of: a physical or virtual button, such as a reset button; one or more indicators, such as a Light Emitting Diode (LED); and a display screen.

[0125] exist Fig.12 Another example of an implementation method using the following ESD protection circuit is illustrated in FIG. Figures 1 to 7 One or more aspects of the architecture described or related to the above Figures 1 to 7 One or more examples of the description. Fig.12 An example of a mobile device 1200 (eg, a mobile phone, a smartphone, a tablet computer, or a laptop computer) comprising the proposed ESD protection circuit 1230 is schematically illustrated.

[0126] The mobile device 1200 includes at least one antenna element 1260. The antenna element 1260 is coupled to an I / O node 1211 of the semiconductor chip 1210. The semiconductor chip 1210 may be coupled to the antenna element 1260 via one or more intermediate elements, such as one or more of a signal line, a filter, an up-converter (mixer), a down-converter (mixer), a PA, and the like.

[0127] The semiconductor chip 1210 includes a signal processing circuit 1240 coupled to the I / O node 1211. The semiconductor chip 1210 is configured to provide the first power supply voltage and the second power supply voltage as described above to the signal processing circuit 1240. The signal processing circuit 1240 may, for example, include an RF transceiver or be an RF transceiver. Additionally or alternatively, the signal processing circuit 1240 may include or may be at least one of an RF transmitter and an RF receiver.

[0128] The baseband processing circuit (eg, baseband processor) 1250 is coupled to the signal processing circuit 1240 of the semiconductor chip 1200. The baseband processing circuit 1250 may be Fig.1212 is located outside the chip as shown in , or can be integrated into the semiconductor chip 1210. Depending on the type of the signal processing circuit 1240, the baseband processing circuit 1250 is configured to send digital transmission data to the signal processing circuit 1240, and / or receive digital reception data from the signal processing circuit 1240. For example, if the signal processing circuit 1240 includes or is an RF receiver, the baseband processing circuit 1250 is configured to receive digital reception data from the signal processing circuit 1240. If the signal processing circuit 1240 includes or is an RF transmitter, the baseband processing circuit 1250 is configured to send digital transmission data to the signal processing circuit 1240. If the signal processing circuit 1240 includes or is an RF transceiver, the signal processing circuit 1240 is configured to send digital transmission data to the signal processing circuit 1240, and receive digital reception data from the signal processing circuit 1240.

[0129] The baseband processing circuit 1250 is configured to perform baseband processing on the digital received data. Similarly, the baseband processing circuit 1250 is configured to generate digital transmit data by performing baseband processing on the data to be wirelessly transmitted. The RF transmitter or RF transceiver can generate an RF transmit signal based on the digital transmit data, and use the antenna element 1260 or another antenna element (not shown) of the mobile device 1200 to radiate the RF transmit signal into the environment. Similarly, the RF receiver or RF transceiver can receive an RF receive signal received from the antenna element 1260 or another antenna element (not shown) of the mobile device 1200, and generate digital receive data based on the RF receive signal.

[0130] The signal processing circuit 1240 may include various additional elements, such as one or more of an LNA, a filter, an attenuator, and the like.

[0131] In addition, ESD protection circuit 1230 is coupled to I / O node 1211. Specifically, a first node of ESD protection circuit 1230 is coupled to I / O node 1211 to protect signal processing circuit 1240 and optionally other circuits of semiconductor chip 1210 from damage or failure caused by ESD at I / O node 1211.

[0132] To this end, a mobile device with improved ESD protection capability may be provided, thereby allowing the mobile device to achieve higher linearity and higher bandwidth (eg, bandwidth may be from 400 MHz to 8.4 GHz or even wider).

[0133] The semiconductor chip 1210 (and optionally other elements of the mobile device 1200) can be manufactured in modern semiconductor technology nodes using GAAFETs (e.g., RibbonFET transistors) with nanosheets or CFETs with nanosheets. In other words, the transistors formed in the semiconductor chip 1200 can be GAAFETs with nanosheets or CFETs with nanosheets.

[0134] The mobile device 1200 may include additional elements, such as an application processor, memory, a connectivity module, a Near Field Communication (NFC) controller, an audio driver, a camera driver, a touch screen, a display driver, a sensor, a removable memory, a power management integrated circuit, or a smart battery.

[0135] In some aspects, the application processor may include, for example, one or more CPU cores and one or more of the following: cache memory, LDO regulators, interrupt controllers such as SPI, I 2 C or general purpose programmable serial interface module, RTC, timer-counters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as SD / MMC, USB interface, MIPI interface, and JTAG test access port.

[0136] In some aspects, baseband processing circuit 1250 may be implemented as, for example, a solder-in substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and / or a multi-chip module containing two or more integrated circuits.

[0137] A wireless communication circuit using ESD protection according to the proposed architecture or one or more of the examples described above may be configured to operate according to one of the 3rd Generation Partnership Project (3GPP) standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, the 5th Generation New Radio (5G). thGeneration New Radio (5G NR), Long-Term Evolution (LTE), LTE-Advanced (LTE-A), High Speed ​​Packet Access (HSPA), Universal Mobile Telecommunication System (UMTS) or UMTS Terrestrial Radio Access Network (UTRAN), Evolved UTRAN (e-UTRAN), Global System for Mobile communication (GSM), Enhanced Data rates for GSM Evolution (EDGE) network, or GSM / EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuit can be configured to operate according to mobile communication networks with different standards, such as the Worldwide Inter-operability for Microwave Access (WIMAX) network IEEE 802.16 or the Wireless Local Area Network (WLAN) IEEE 802.11, generally orthogonal frequency division multiple access (OFDMA) network, time division multiple access (TDMA) network, code division multiple access (CDMA) network, wideband-CDMA (WCDMA) network, frequency division multiple access (FDMA) network, spatial division multiple access (SDMA) network, and the like.

[0138] The ESD protection circuit according to the proposed architecture is described above in the context of a wireless communication circuit. However, it is to be noted that the ESD protection circuit is not limited to wireless communication applications. The ESD protection circuit according to the proposed architecture can be used to protect any kind of processing circuit in a semiconductor chip from damage or failure caused by ESD at the I / O nodes of the semiconductor chip (the ESD protection circuit and the processing circuit are coupled to the I / O nodes of the semiconductor chip).

[0139] The examples described in this article can be summarized as follows:

[0140] An example (e.g., Example 1) relates to an electrostatic discharge (ESD) protection circuit for a semiconductor chip, the ESD protection circuit comprising a first node for coupling to an I / O node of the semiconductor chip, a first conductive path coupled to the first node via at least one first diode, wherein the first conductive path is configured to be at a first voltage level, which is higher than or equal to the voltage level of a first power supply voltage of the semiconductor chip, a second conductive path coupled to the first node via at least one second diode, wherein the second conductive path is configured to be at a second voltage level, which is lower than or equal to the voltage level of a second power supply voltage of the semiconductor chip, the voltage level of the second power supply voltage being lower than the voltage level of the first power supply voltage, and a second node for coupling to a ground node of the semiconductor chip or a power supply node of the semiconductor chip for providing the second power supply voltage, wherein the first conductive path is coupled to the second node via at least one capacitor, and the second conductive path is coupled to the second node via at least one other capacitor.

[0141] Another example (e.g., Example 2) relates to the previous example (e.g., Example 1) or any other example, and also includes the first conductive path being coupled to the first node via two first diodes coupled in series, and wherein the second conductive path is coupled to the first node via two second diodes coupled in series.

[0142] Another example (e.g., Example 3) relates to the previous example (e.g., one of Examples 1 or 2) or any other example, and also includes a bias circuit coupled to the first conductive path and the second conductive path, wherein the bias circuit is configured to bias the first conductive path to the first voltage level and bias the second conductive path to the second voltage level.

[0143] Another example (eg, Example 4) relates to the previous example (eg, Example 3) or any other example, and further includes that the bias circuit includes at least one charge pump, at least one low dropout regulator, or a combination of these.

[0144] Another example (e.g., Example 5) relates to the previous example (e.g., one of Examples 3 or 4) or any other example, and also includes the bias circuit being configured to receive a control signal and dynamically adjust at least one of the first voltage level and the second voltage level based on the control signal.

[0145] Another example (e.g., Example 6) relates to a previous example (e.g., one of Examples 1 to 5) or any other example, and also includes the first conductive path coupled to a node of the semiconductor chip, which is used to couple the first conductive path with a voltage source outside the ESD protection circuit for providing the first voltage level, wherein the second conductive path is coupled to a node of the semiconductor chip, which is used to couple the second conductive path with a voltage source outside the ESD protection circuit for providing the second voltage level.

[0146] Another example (e.g., Example 7) relates to the previous example (e.g., one of Examples 1 to 6) or any other example, and also includes a third node for coupling to another power supply node of the semiconductor chip for providing the first power supply voltage, and a fourth node for coupling to the power supply node of the semiconductor chip, wherein the first conductive path is coupled to the third node via a resistor, an inductor or a transmission gate, and wherein the second conductive path is coupled to the fourth node via another resistor, another inductor or another transmission gate.

[0147] Another example (eg, Example 8) relates to the previous example (eg, Example 7) or any other example, further including that the resistor and the another resistor each exhibit a resistance of at least 10 kΩ.

[0148] Another example (eg, Example 9) relates to the previous example (eg, one of Examples 7 or 8) or any other example, further including the third node and the fourth node being coupled via a power clamp.

[0149] Another example (e.g., Example 10) relates to a previous example (e.g., one of Examples 1 to 9) or any other example, and also includes the at least one first diode being reverse biased by the first voltage level, wherein the at least one second diode is reverse biased by the second voltage level.

[0150] Another example (e.g., Example 11) relates to the previous example (e.g., one of Examples 1 to 10) or any other example, and also includes the first conductive path being coupled to the second node via two capacitors, and wherein the second conductive path is coupled to the second node via another capacitor.

[0151] Another example (e.g., Example 12) relates to the previous example (e.g., one of Examples 1 to 11) or any other example, and also includes the at least one capacitor and the at least one other capacitor being coupled in series, wherein the second node is coupled between the at least one capacitor and the at least one other capacitor.

[0152] Another example (e.g., Example 13) relates to the previous example (e.g., one of Examples 1 to 12) or any other example, and also includes that the respective capacitances of the at least one capacitor and the at least one other capacitor are greater than 500 pF.

[0153] Another example (e.g., Example 14) relates to the previous example (e.g., one of Examples 1 to 13) or any other example, and also includes the respective capacitance of the at least one capacitor being greater than the respective capacitance of the at least one other capacitor.

[0154] Another example (e.g., Example 15) relates to the previous example (e.g., one of Examples 1 to 14) or any other example, and also includes a first power clamp coupled between the first conductive path and the second node, wherein the first power clamp is coupled in parallel with the at least one capacitor, and a second power clamp coupled between the second conductive path and the second node, wherein the second power clamp is coupled in parallel with the at least one other capacitor.

[0155] Another example (e.g., Example 16) relates to the previous example (e.g., Example 15) or any other example, and also includes a first flyback diode coupled between the first conductive path and the second node, wherein the first flyback diode is coupled in parallel with the at least one capacitor and the first power clamp, and a second flyback diode coupled between the second conductive path and the second node, wherein the second flyback diode is coupled in parallel with the at least one other capacitor and the second power clamp.

[0156] An example (e.g., Example 17) relates to a semiconductor chip comprising an I / O node, an electrostatic discharge (ESD) protection circuit as described in a previous example (e.g., one of Examples 1 to 16) or any other example, wherein a first node of the ESD protection circuit is coupled to the I / O node, and a signal processing circuit coupled to the I / O node, wherein the semiconductor chip is configured to provide the first supply voltage and the second supply voltage to the signal processing circuit.

[0157] Another example (eg, Example 18) relates to the previous example (eg, Example 17) or any other example, and further includes the signal processing circuit including at least one of a radio frequency transceiver, a radio frequency transmitter, and a radio frequency receiver.

[0158] Another example (e.g., Example 19) relates to a previous example (e.g., one of Examples 17 or 18) or any other example, and further includes that the transistor formed in the semiconductor chip is a gate-all-around field-effect transistor (GAAFET) with nanosheets or a complementary field-effect transistor (CFET) with nanosheets.

[0159] One example (e.g., Example 20) relates to a base station that includes a semiconductor chip according to a previous example (e.g., one of Examples 17 to 19) or any other example, and at least one antenna coupled to the I / O nodes of the semiconductor chip.

[0160] Another example (e.g., Example 21) relates to a previous example (e.g., Example 20) or any other example, and further includes a baseband processing circuit coupled to the signal processing circuit of the semiconductor chip, wherein the baseband processing circuit is configured to send digital transmission data to the signal processing circuit and / or receive digital reception data from the signal processing circuit.

[0161] One example (e.g., Example 22) relates to a mobile device that includes a semiconductor chip according to a previous example (e.g., one of Examples 17 to 19) or any other example, and at least one antenna coupled to the I / O nodes of the semiconductor chip.

[0162] Another example (e.g., Example 23) relates to a previous example (e.g., Example 22) or any other example, and further includes a baseband processing circuit coupled to the signal processing circuit of the semiconductor chip, wherein the baseband processing circuit is configured to send digital transmission data to the signal processing circuit and / or receive digital reception data from the signal processing circuit.

[0163] Aspects and features described herein in connection with a particular one of the previous examples can also be combined with one or more additional examples to replace the same or similar features of the additional example or to introduce features additionally into the additional example.

[0164] It should also be understood that the disclosure of several steps, processes, operations, or functions in the specification or claims should not be construed as implying that these operations must follow the described order, unless explicitly stated in an individual case or necessary for technical reasons. Therefore, the previous description does not limit the execution of several steps or functions to a certain order. Additionally, in further examples, a single step, function, process, or operation can include and / or be decomposed into several sub-steps, sub-functions, sub-processes, or sub-operations.

[0165] If aspects have been described in connection with a device or system, these aspects should also be understood as descriptions of the corresponding methods. For example, blocks, devices, or functional aspects of the device or system may correspond to features of the corresponding methods, such as method steps. Therefore, aspects described in connection with a method should also be understood as descriptions of corresponding blocks, corresponding elements, attributes, or functional features of the corresponding device or corresponding system.

[0166] The attached claims are hereby incorporated into the detailed description, where each claim may stand alone as a separate example. It should also be noted that although in the claims, a dependent claim refers to a specific combination with one or more other claims, other examples may also include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are explicitly proposed here, unless it is stated in an individual case that a specific combination is not intended. In addition, features of a claim should also be included for any other independent claim, even if the claim is not directly defined as dependent on the other independent claim.

Claims

1. An electrostatic discharge (ESD) protection circuit for a semiconductor chip, the ESD protection circuit comprising: A first node, for coupling to an I / O node of the semiconductor chip; a first conductive path coupled to the first node via at least one first diode, wherein the first conductive path is configured to be at a first voltage level that is higher than or equal to a voltage level of a first supply voltage of the semiconductor chip; a second conductive path coupled to the first node via at least one second diode, wherein the second conductive path is configured to be at a second voltage level that is lower than or equal to a voltage level of a second supply voltage of the semiconductor chip, the voltage level of the second supply voltage being lower than the voltage level of the first supply voltage; as well as a second node, for coupling to a ground node of the semiconductor chip or a power supply node of the semiconductor chip for providing the second power supply voltage, Therein, the first conductive path is coupled to the second node via at least one capacitor, and the second conductive path is coupled to the second node via at least one other capacitor.

2. The ESD protection circuit according to claim 1, wherein: The first conductive path is coupled to the first node via two first diodes coupled in series, and wherein the second conductive path is coupled to the first node via two second diodes coupled in series.

3. The ESD protection circuit of claim 1 or claim 2, further comprising a bias circuit coupled to the first conductive path and the second conductive path, wherein the bias circuit is configured to: biasing the first conductive path to the first voltage level; and The second conductive path is biased to the second voltage level.

4. The ESD protection circuit according to claim 3, wherein: The bias circuit includes: at least one charge pump, at least one low dropout regulator, or a combination thereof.

5. The ESD protection circuit according to claim 3, wherein: The bias circuit is configured as: receiving a control signal; and At least one of the first voltage level and the second voltage level is dynamically adjusted based on the control signal.

6. The ESD protection circuit according to claim 1 or claim 2, wherein: The first conductive path is coupled to a node of the semiconductor chip, which is used to couple the first conductive path with a voltage source outside the ESD protection circuit for providing the first voltage level, and wherein the second conductive path is coupled to a node of the semiconductor chip, which is used to couple the second conductive path with a voltage source outside the ESD protection circuit for providing the second voltage level.

7. The ESD protection circuit according to claim 1 or claim 2, further comprising: a third node, configured to be coupled to another power supply node of the semiconductor chip for providing the first power supply voltage; as well as a fourth node, for coupling to a power supply node of the semiconductor chip, wherein the first conductive path is coupled to the third node via a resistor, an inductor or a transmission gate, and The second conductive path is coupled to the fourth node via another resistor, another inductor or another transmission gate.

8. The ESD protection circuit according to claim 7, wherein: The resistor and the further resistor each exhibit a resistance of at least 10 k GHz.

9. The ESD protection circuit according to claim 7, wherein: The third node and the fourth node are coupled via a power clamp.

10. The ESD protection circuit according to claim 1 or claim 2, wherein: The at least one first diode is reverse biased by the first voltage level, and wherein the at least one second diode is reverse biased by the second voltage level.

11. The ESD protection circuit according to claim 1 or claim 2, wherein: The first conductive path is coupled to the second node via two capacitors, and wherein the second conductive path is coupled to the second node via one other capacitor.

12. The ESD protection circuit according to claim 1 or claim 2, wherein: The at least one capacitor and the at least one other capacitor are coupled in series, and wherein the second node is coupled between the at least one capacitor and the at least one other capacitor.

13. The ESD protection circuit according to claim 1 or claim 2, wherein: The at least one capacitor and the at least one other capacitor each have a capacitance greater than 500 pF.

14. The ESD protection circuit according to claim 1 or claim 2, wherein: The respective capacitance of the at least one capacitor is greater than the respective capacitance of the at least one other capacitor.

15. The ESD protection circuit according to claim 1 or claim 2, further comprising: a first power clamp coupled between the first conductive path and the second node, wherein the first power clamp is coupled in parallel with the at least one capacitor; as well as A second power clamp is coupled between the second conductive path and the second node, wherein the second power clamp is coupled in parallel with the at least one other capacitor.

16. The ESD protection circuit of claim 15, further comprising: a first flyback diode coupled between the first conductive path and the second node, wherein the first flyback diode is coupled in parallel with the at least one capacitor and the first power clamp; as well as A second flyback diode is coupled between the second conductive path and the second node, wherein the second flyback diode is coupled in parallel with the at least one other capacitor and the second power clamp.

17. A semiconductor chip, comprising: I / O node ； The electrostatic discharge (ESD) protection circuit according to claim 1 or claim 2, wherein the first node of the ESD protection circuit is coupled to the I / O node; as well as A signal processing circuit is coupled to the I / O node, wherein the semiconductor chip is configured to provide the first power supply voltage and the second power supply voltage to the signal processing circuit.

18. The semiconductor chip according to claim 17, wherein: The signal processing circuit includes at least one of a radio frequency transceiver, a radio frequency transmitter, and a radio frequency receiver.

19. The semiconductor chip according to claim 17, wherein: The transistor formed in the semiconductor chip is a gate all around field effect transistor (GAAFET) with a nanosheet or a complementary field effect transistor (CFET) with a nanosheet.

20. A base station, comprising: The semiconductor chip according to claim 17; as well as At least one antenna is coupled to an I / O node of the semiconductor chip.

21. The base station of claim 20, further comprising: A baseband processing circuit is coupled to the signal processing circuit of the semiconductor chip, wherein the baseband processing circuit is configured to transmit digital transmit data to the signal processing circuit and / or receive digital receive data from the signal processing circuit.

22. A mobile device, comprising: The semiconductor chip according to claim 17; as well as At least one antenna is coupled to an I / O node of the semiconductor chip.

23. The mobile device of claim 22, further comprising: A baseband processing circuit is coupled to the signal processing circuit of the semiconductor chip, wherein the baseband processing circuit is configured to transmit digital transmit data to the signal processing circuit and / or receive digital receive data from the signal processing circuit.

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