IO application-based ESD protection circuit, protection method and chip
By designing an ESD protection circuit based on IO application, the substrate potential of the PMOS tube is controlled to change with the IO signal, which solves the power sinking problem caused by excessive signal voltage of the chip external interface, and realizes high safety, high reliability and high reusability chip IO ESD protection.
Patent Information
- Application Number
- CN202311569714.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-22
- Publication Date
- 2025-05-23
AI Technical Summary
In ESD protection, existing chips have the problem of excessive external interface signal voltage pouring into the chip power supply, which causes the chip to fail to power down normally, increasing the limitations of application scenarios and manufacturing costs.
A ESD protection circuit based on IO application is designed. Through the combination of the IO transmission control port, ESD protection module, IO push-pull output module and potential control logic module, the substrate potential of the control PMOS tube is not fixed on the power supply, but is always connected to the highest potential according to the voltage level of the IO signal.
Effectively prevent the chip's external interface signal voltage from being too high and powered to the chip's power supply, improve the chip's power down problem under the conditions of continuous application of external interface signals, enhance the reusability of the IO interface, and reduce the chip area and manufacturing costs.
Smart Images
Figure CN120033644A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of ESD protection, and relates to an ESD protection circuit, and in particular to an ESD protection circuit, a protection method, and a chip based on IO applications. Background Art
[0002] For chips, ESD (Electro Static discharge) is a very serious problem, because electrostatic discharge may cause the chip's transient voltage to exceed the device's tolerance, causing chip damage or performance degradation. During chip manufacturing, transportation, and use, ESD has always been one of the important factors restricting chip performance reliability and lifespan.
[0003] In order to protect the chip from ESD damage, a series of ESD protection mechanisms are usually adopted in chip design. One common mechanism is to use ESD protection devices on the chip input / output (I / O) pins. The ESD device will clamp the potential of the IO pin at GND-0.7v~VDD+0.7v. Once the potential of the IO exceeds this range, the ESD circuit is activated, and the PN junction of the diode is forward biased until the potential of the IO pin falls back to the GND-0.7v~VDD+0.7v range; under normal working conditions, the potential of the ESD can be discharged instantly, but if the voltage of the external signal itself exceeds VDD+0.7v, the IO pin will charge the internal voltage of the chip through the diode, and the chip will not be able to power off, which will limit the application environment of the chip, bring greater application power consumption to the chip, increase the application cost of the chip, and reduce product competitiveness.
[0004] In addition to chip ESD reliability protection, as chip application scenarios become more and more diverse, the requirements for IO functional compatibility and reusability are also getting higher and higher. In order to meet different chip application scenarios, the general chip will be configured with different application IO interfaces, and each IO needs to be equipped with corresponding ESD devices, which will greatly increase the chip area and increase the chip manufacturing cost. Because the IO ESD device itself occupies a very large area in the chip for better protection, this requires that when designing the chip, when meeting multiple application interface scenarios, the number of IO pins can be minimized, that is, the higher the IO functional compatibility and reusability, the more it can reduce the number of chip IOs, reduce the chip area, thereby reducing manufacturing costs and improving the market competitiveness of the product. However, during the reuse process, due to the fixed potential of the ESD device substrate, the chip has certain defects in the application scenario. Summary of the invention
[0005] The present application provides an ESD protection circuit, a protection method and a chip based on IO applications, which are used to solve the problem of how to effectively prevent the chip external interface signal voltage from being too high to feed power to the chip power supply while ensuring the ESD protection performance of the IO circuit.
[0006] In the first aspect, the present application provides an ESD protection circuit based on IO application, the circuit comprising: an IO transmission control port; an ESD protection module, connected to the IO transmission control port, for ESD protection of the IO circuit; an IO push-pull output module, which has a common PMOS tube and NMOS tube with the ESD protection module, for push-pull output of the IO circuit; a potential control logic module, respectively connected to the IO transmission control port, the ESD protection module and the IO push-pull output module, for determining the substrate connection mode of the PMOS tube in the ESD protection module under the switching control of different modes of the IO circuit, so that the substrate potential is not fixed on the power supply, but changes with the voltage of the IO signal, and is always connected to the highest potential.
[0007] In an implementation of the first aspect, the IO transmission control port includes an input terminal for an IO signal to the inside of a chip, an output terminal for an IO output signal to the outside, an input and output control terminal of an IO circuit, an input pull-up control signal terminal of an IO circuit, and an input pull-down control signal terminal of an IO circuit.
[0008] In an implementation of the first aspect, the ESD protection module includes a first PMOS tube, a second PMOS tube, a first NMOS tube, and a second NMOS tube; in response to the IO circuit being in input mode, the gates of the first NMOS tube and the second NMOS tube are at a low level and are in an on state, the first PMOS tube and the second PMOS tube are in an off state, and the substrate potentials of the first PMOS tube and the second PMOS tube are at a highest potential.
[0009] In an implementation manner of the first aspect, the IO push-pull output module includes the second PMOS transistor, the second NMOS transistor, a third PMOS transistor and a third NMOS transistor.
[0010] In an implementation of the first aspect, in response to the IO circuit being in a push-pull output mode, the second NMOS tube and the second PMOS tube are controlled by the IO output signal to output data to an external output terminal, the substrate potential of the first PMOS tube and the second PMOS tube is the power supply potential, and the first PMOS tube is in an ESD protection device state.
[0011] In an implementation of the first aspect, the IO transmission control port also includes an open drain mode control terminal; in response to the IO circuit being in open drain mode, the second NMOS tube is controlled by the IO output signal to output data to an external output terminal, and the second PMOS tube is in an ESD protection device state.
[0012] In an implementation of the first aspect, in response to the IO circuit being in a push-pull output mode, substrate potentials of the first PMOS tube and the second PMOS tube are power supply potentials, and the second NMOS tube and the second PMOS tube serve as IO push-pull output driver tubes.
[0013] In an implementation of the first aspect, in response to the IO circuit being in input mode, the gate of the second NMOS tube is grounded and is in an on state, the first PMOS tube and the second PMOS tube are in an off state, and the substrate potentials of the first PMOS tube and the second PMOS tube are the highest potential.
[0014] In the second aspect, the present application provides an ESD protection method based on IO application, which is applied to the circuit; the method includes: connecting with the IO transmission control port, the ESD protection module and the IO push-pull output module respectively through the potential control logic module; under the switching control of different modes of the IO circuit, determining the connection mode of the PMOS tube substrate in the ESD protection module; making the substrate potential not fixed on the power supply, but changing with the voltage of the IO signal, and always connecting to the highest potential.
[0015] In a third aspect, the present application provides a chip, wherein the chip includes the circuit.
[0016] As described above, the ESD protection circuit, protection method and chip based on IO application described in this application have the following beneficial effects:
[0017] The present application provides a highly secure, highly reliable, and widely applicable chip IO ESD protection circuit, which optimizes the limitations of the chip IO circuit application scenarios while maintaining the ESD protection performance of traditional circuits, effectively preventing the chip external interface signal voltage from being too high to feed power to the chip power supply, improving the situation where the chip cannot be powered off normally under the condition of continuous application of the external interface signal, and enhancing the reusability of the IO interface, which can effectively reduce the chip area and reduce the chip design and manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 Shown is a schematic diagram of the structural connection of an ESD protection circuit based on IO application described in an embodiment of the present application.
[0019] Figure 2Shown is a circuit diagram of an ESD protection circuit based on IO application described in an embodiment of the present application.
[0020] Figure 3 Shown is a circuit diagram of an ESD protection circuit based on IO application according to another embodiment of the present application.
[0021] Figure 4 Shown is a principle flow chart of the ESD protection method based on IO application described in an embodiment of the present application.
[0022] Figure 5 Shown is a schematic diagram of the structure of the chip described in an embodiment of the present application.
[0023] Component number description
[0024] 1 ESD protection circuit based on IO application
[0025] 11 IO transmission control port
[0026] 12 ESD protection module
[0027] 13 IO push-pull output module
[0028] 14 Potential control logic module
[0029] Steps S41 to S43 DETAILED DESCRIPTION
[0030] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0031] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0032] The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the drawings in the embodiments of the present application.
[0033] See also Figure 1 , which is a schematic diagram showing the structural connection of the ESD protection circuit based on IO application described in the embodiment of the present application. Figure 1 As shown in the figure, this embodiment provides an ESD protection circuit 1 based on IO applications, specifically including: an IO transmission control port 11, an ESD protection module 12, an IO push-pull output module 13, and a potential control logic module 14.
[0034] The ESD protection module 12 is connected to the IO transmission control port 11 and is used for ESD protection of the IO circuit.
[0035] The IO push-pull output module 13 shares PMOS and NMOS transistors with the ESD protection module 12 and is used for push-pull output of the IO circuit.
[0036] The potential control logic module 14 is respectively connected to the IO transmission control port 11, the ESD protection module 12, and the IO push-pull output module 13, and is used to determine the substrate connection method of the PMOS transistor in the ESD protection module 12 under the switching control of different modes of the IO circuit, so that the substrate potential is not fixed on the power supply, but changes with the voltage level of the IO signal and is always connected to the highest potential.
[0037] Thus, this application changes the connection method of the ESD device substrate. The potential of the substrate of the ESD device flowing to VDD is controlled by a logic circuit. When the external voltage on the IO pin is greater than the operating voltage of the chip VDD + 0.7v (the forward bias conduction voltage of the PN junction), the substrate potential of the PMOS transistor of the ESD device will rise to the same potential as the IO pin signal. At this time, a forward bias PN junction conduction circuit will not be formed from the IO pin signal to VDD, preventing the generation of additional power consumption in the application environment and the problem that the chip cannot be powered off normally; when the potential of the IO pin signal drops to VDD or below, the substrate of the PMOS transistor of the ESD device will be connected to VDD. From beginning to end, the substrate of the PMOS transistor will be connected to the end with the highest potential, enabling the MOS transistor to operate in a normal state.
[0038] In one embodiment, the IO transmission control port includes an input end for IO signals to the inside of the chip, an output end for IO output signals to the outside, an input / output control end of the IO circuit, an input pull-up control signal end of the IO circuit, and an input pull-down control signal end of the IO circuit.
[0039] Please refer to Figure 2 , which shows the circuit diagram of the ESD protection circuit based on IO applications described in one embodiment of this application. As Figure 2 shown, D is the input end for IO signals to the inside of the chip; A is the output end for IO output signals to the outside; E is the input / output control end of the IO circuit; PU is the input pull-up control signal end of the IO circuit; PD is the input pull-down control signal end of the IO circuit.
[0040] In one embodiment, the ESD protection module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor. Figure 2 The first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2.
[0041] In one embodiment, the IO push-pull output module includes the second PMOS transistor, the second NMOS transistor, the third PMOS transistor and the third NMOS transistor. Figure 2 The second PMOS tube P2, the second NMOS tube N2, the third PMOS tube P3 and the third NMOS tube N3 in the circuit. Among them, the P2 tube and the N2 tube are push-pull output drive tubes of the IO; the P3 tube is the pull-up control device of the IO, and the N3 tube is the pull-down control device of the IO.
[0042] like Figure 2 As shown, the potential control logic module includes P4, P5, P6, P7, P8, P9, and P10. P4-P10 are the potential control logic of the substrate B terminal and the gate terminal G of the ESD device in the circuit of the present application.
[0043] In response to the IO circuit being in input mode, the gates of the first NMOS tube and the second NMOS tube are at a low level and are in an on state, the first PMOS tube and the second PMOS tube are in an off state, and the substrate potentials of the first PMOS tube and the second PMOS tube are at the highest potential.
[0044] like Figure 2As shown in the figure, when E is 0, the IO circuit is in input mode. At this time, the gate of N2 is at a low level, and the connection state of N2 is consistent with that of N1, both of which are used as ESD protection devices. The gate terminals G of P4 and P5 are at a high level, and P4 and P5 are cut off. At this time, the substrate potential S2 of the ESD device P is in a floating state, and there is no fixed voltage path. Because the gate G, source S, and drain D of the PMOS tube have parasitic capacitance to the substrate B, the potential S2 of the substrate B will change with the change of the highest potential of the three terminals G, S, and D, that is, the potential of S2 will be equal to the highest potential of the terminal with the highest potential. If the voltage on IO_PAD is greater than VDD+Vth, that is, the potential of S3 is greater than VDD+Vth, P5 tube is turned on, the potential of S1 is equal to the potential of S3, P4 tube is turned off, and the potential of S2 is still in a floating state, that is, the potentials of S1, S2, and S3 are the same, which are all greater than VDD+Vth, which is the IO interface signal. At the same time, P6 tube, P7 tube, and P9 tube are turned on, that is, the potential S1=S2=S3=S4=S5=S6, the ESD devices P1 tube and P2 tube are in the cut-off state, and the substrate potential is also the highest level. The PN junction forward path cannot be formed from the IO_PAD port to VDD, and there will be no power injection phenomenon.
[0045] In response to the IO circuit being in push-pull output mode, the second NMOS tube and the second PMOS tube are controlled by the IO output signal to output data to the external output terminal, the substrate potential of the first PMOS tube and the second PMOS tube is the power supply potential, and the first PMOS tube is in the ESD protection device state.
[0046] like Figure 2 As shown in the figure, when E is 1, the IO circuit is in push-pull output mode. At this time, N2 and P2 tubes are controlled by the output data of terminal A, P10 and P11 tubes are turned on, the potential of S1 is low, P4 is turned on, P5 is turned off, the substrate potential S2 of the ESD device PMOS is VDD high level, S3 is the output data, P6, P7, and P9 tubes are turned off, P8 tube is turned on, that is, S5 is VDD high level, and P1 tube is in the normal ESD protection device state.
[0047] See also Figure 3 , which is a circuit diagram of an ESD protection circuit based on IO application described in another embodiment of the present application. Figure 3 The circuit in Figure 2 The design adds an open-drain OD mode based on the circuit, which can be used for push-pull mode applications as well as OD mode applications, making the IO circuit suitable for more application scenarios and improving the reusability of IO. Figure 3 As shown, the IO transmission control port also includes an open-drain mode control terminal PAD_OD_ENB.
[0048] In response to the IO circuit being in open-drain mode, the second NMOS tube is controlled by the IO output signal to output data to an external output terminal, and the second PMOS tube is in an ESD protection device state.
[0049] like Figure 3 As shown in the figure, when E is 1 and PAD_OD_ENB is 0, the IO circuit turns on the OD mode. At this time, the N2 tube is controlled by the output data A; the P10 tube is turned on, and the gate G of the P2 tube is high level, which is in the pure ESD protection device state. Only the N2 tube works in the entire output. In the OD mode, the IO interface is connected to the external power supply through an external pull-up resistor. If the power supply is greater than VDD+Vth, the principle is the same as Figure 2 As shown in the circuit, the potential on IO_PAD will not supply power to the internal power supply VDD of the chip.
[0050] In response to the IO circuit being in push-pull output mode, the substrate potentials of the first PMOS tube and the second PMOS tube are the power supply potential, and the second NMOS tube and the second PMOS tube serve as IO push-pull output driving tubes.
[0051] like Figure 3 As shown in the figure, when E is 1 and PAD_OD_ENB is 1, the IO circuit starts the push-pull output. At this time, P4 is turned on, the PMOS tube substrate is connected to VDD, and the N2 tube and P2 tube are IO push-pull output driver tubes.
[0052] In response to the IO circuit being in input mode, the gate of the second NMOS tube is grounded and is in an on state, the first PMOS tube and the second PMOS tube are in an off state, and the substrate potentials of the first PMOS tube and the second PMOS tube are the highest potential.
[0053] like Figure 3 As shown, when E is 0 and PAD_OD_ENB is 0, the IO circuit turns on the input mode, the gate of the N2 tube is grounded, the P4 tube is cut off, and the substrate potential S2 of the PMOS tube becomes suspended. At this time, the working principle is the same as the circuit Figure 2 Input mode. No power supply path is formed from the IO_PAD interface to the VDD power supply.
[0054] exist Figure 2 and Figure 3In the embodiment of the present application, the logical relationship of the substrate potential of the IO ESD device PMOS tube is modified and designed, and the original method of fixing the substrate potential of the ESD device PMOS tube is changed, so that the potential is not fixed on the VDD power supply, but is always connected to the highest potential as the voltage of the IO signal changes. If the IO signal voltage does not exceed the VDD voltage, the substrate potential of the PMOS tube is VDD; if the IO signal voltage exceeds VDD+Vth (the threshold voltage of the PMOS tube), the substrate potential of the PMOS tube is the IO potential; therefore, when the IO signal potential exceeds VDD+0.7v, a PN junction path will not be formed from the D end to the B end of the ESD device PMOS tube, thus solving the problem of the IO potential flowing back to VDD. In this way, the open-drain OD mode and the push-pull mode of the IO circuit can be integrated into one IO circuit (such as Figure 3 As shown), the number of IOs used is saved; because the external power supply of the OD mode is generally greater than the chip working power supply, if the chip has OD application requirements, a separate OD IO circuit must be added, and this application Figure 3 The design can meet multiple application requirements through one IO circuit.
[0055] The circuit design in this application does not change the ESD protection performance of the IO, because ESD is an instantaneous high-voltage discharge. During this process, the substrate potential of the PMOS tube of the ESD device will not change suddenly, and there is still a normal high-voltage discharge path.
[0056] See also Figure 4 , which is a principle flow chart of the ESD protection method based on IO application described in the embodiment of the present application. Figure 4 As shown, this embodiment provides an ESD protection method based on IO application, which is applied to the above-mentioned ESD protection circuit based on IO application; the method specifically includes the following steps:
[0057] S41, respectively connecting with the IO transmission control port, the ESD protection module and the IO push-pull output module through the potential control logic module;
[0058] S42, under the switching control of different modes of the IO circuit, determining the connection mode of the PMOS tube substrate in the ESD protection module.
[0059] S43, the substrate potential is not fixed on the power supply, but changes with the voltage of the IO signal and is always connected to the highest potential.
[0060] The protection scope of the ESD protection method based on IO application described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.
[0061] The ESD protection circuit based on IO application described in the embodiment of the present application can implement the ESD protection method based on IO application described in the present application, but the implementation device of the ESD protection method based on IO application described in the present application includes but is not limited to the structure of the ESD protection circuit based on IO application listed in the present embodiment. All structural deformations and replacements of the prior art made according to the principles of the present application are included in the protection scope of the present application.
[0062] See also Figure 5 , which is a schematic diagram of the structure of the chip described in the embodiment of the present application. Figure 5 As shown, the present application provides a chip, which includes the ESD protection circuit based on IO application. The circuit includes: an IO transmission control port; an ESD protection module, which is connected to the IO transmission control port and is used for ESD protection of the IO circuit; an IO push-pull output module, which has a common PMOS tube and NMOS tube with the ESD protection module, and is used for push-pull output of the IO circuit; a potential control logic module, which is respectively connected to the IO transmission control port, the ESD protection module and the IO push-pull output module, and is used to determine the substrate connection mode of the PMOS tube in the ESD protection module under the switching control of different modes of the IO circuit, so that the substrate potential is not fixed on the power supply, but changes with the voltage of the IO signal, and is always connected to the highest potential.
[0063] In the several embodiments provided in the present application, it should be understood that the disclosed system, device or method can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules or units, which can be electrical, mechanical or other forms.
[0064] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, the functional modules / units in the various embodiments of the present application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.
[0065] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0066] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.
[0067] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.
Claims
1. An ESD protection circuit based on IO application, It is characterized in that The circuit comprises: IO transmission control port; An ESD protection module, connected to the IO transmission control port, for ESD protection of the IO circuit; An IO push-pull output module, which shares a PMOS tube and an NMOS tube with the ESD protection module and is used for push-pull output of the IO circuit; The potential control logic module is respectively connected to the IO transmission control port, the ESD protection module and the IO push-pull output module, and is used to determine the connection mode of the PMOS tube substrate in the ESD protection module under the switching control of different modes of the IO circuit, so that the substrate potential is not fixed on the power supply, but changes with the voltage of the IO signal and is always connected to the highest potential.
2. The circuit according to claim 1, Features: The IO transmission control port includes an input terminal for IO signals to the inside of the chip, an output terminal for IO output signals to the outside, an input and output control terminal of the IO circuit, an input pull-up control signal terminal of the IO circuit, and an input pull-down control signal terminal of the IO circuit.
3. The circuit according to claim 1, It is characterized in that The ESD protection module includes a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube; In response to the IO circuit being in input mode, the gates of the first NMOS tube and the second NMOS tube are at a low level and are in an on state, the first PMOS tube and the second PMOS tube are in an off state, and the substrate potentials of the first PMOS tube and the second PMOS tube are at the highest potential.
4. The circuit according to claim 3, Features: The IO push-pull output module includes the second PMOS transistor, the second NMOS transistor, a third PMOS transistor and a third NMOS transistor.
5. The circuit according to claim 4, Features: In response to the IO circuit being in push-pull output mode, the second NMOS tube and the second PMOS tube are controlled by the IO output signal to output data to the external output terminal, the substrate potential of the first PMOS tube and the second PMOS tube is the power supply potential, and the first PMOS tube is in the ESD protection device state.
6. The circuit according to claim 4, It is characterized in that The IO transmission control port also includes an open-drain mode control terminal; In response to the IO circuit being in open-drain mode, the second NMOS tube is controlled by the IO output signal to output data to an external output terminal, and the second PMOS tube is in an ESD protection device state.
7. The circuit according to claim 6, Features: In response to the IO circuit being in push-pull output mode, the substrate potentials of the first PMOS tube and the second PMOS tube are the power supply potential, and the second NMOS tube and the second PMOS tube serve as IO push-pull output driving tubes.
8. The circuit according to claim 6, Features: In response to the IO circuit being in input mode, the gate of the second NMOS tube is grounded and is in an on state, the first PMOS tube and the second PMOS tube are in an off state, and the substrate potentials of the first PMOS tube and the second PMOS tube are the highest potential.
9. An ESD protection method based on IO application, It is characterized in that Applicable to the circuit according to any one of claims 1 to 8; the method comprising: The potential control logic module is respectively connected with the IO transmission control port, the ESD protection module and the IO push-pull output module; Under the switching control of different modes of the IO circuit, determining the connection mode of the PMOS tube substrate in the ESD protection module; The substrate potential is not fixed on the power supply, but changes with the voltage of the IO signal and is always connected to the highest potential.
10. A chip, It is characterized in that The chip comprises the circuit according to any one of claims 1 to 8.