Load impedance adjustment circuit and RF chip

Abstract

The application is suitable for the field of wireless communication technology, and particularly relates to a load impedance adjusting circuit and a radio frequency chip. The load impedance adjusting circuit comprises a power amplifier, a load mismatch detection circuit, an adjustable output matching circuit and a directional coupler. The load mismatch detection circuit is used for detecting the voltage of a coupling end of the directional coupler and the voltage of an isolation end of the directional coupler in real time, and calculating the reflection coefficient of the load impedance of the power amplifier according to the voltage of the coupling end and the voltage of the isolation end, and judging whether the phase in the reflection coefficient exceeds a preset linearity range. If yes, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit, and the adjustable output matching circuit adjusts the impedance of the power amplifier according to the control signal. The application can adjust the phase with poor linearity in the reflection coefficient, thereby reducing the sensitivity of the performance of the power amplifier to the change of the load impedance, and effectively improving the efficiency of the power amplifier.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a load impedance adjustment circuit and a radio frequency chip. Background Technology

[0002] A power amplifier (PA) is an electronic device used to amplify the power of an input signal to drive loads such as speakers and antennas.

[0003] Because the linearity of a power amplifier is highly sensitive to load impedance, under load mismatch, the linearity of some phases at the back-end reflection coefficients of the power amplifier improves, while the linearity of others deteriorates. Existing power amplifier technologies address the issue of ensuring the linearity of the worst-performing phase meets communication specifications under load mismatch primarily through two methods: The first method involves increasing the 50-ohm margin of the load value to allow sufficient room for linearity degradation under load mismatch, thus ensuring that the worst-performing phase meets specifications, further increasing the margin for the phases with improved linearity. However, for power amplifiers, linearity and current are contradictory parameters, which will lead to a further increase in the power amplifier's current, affecting its battery life and performance. The second method uses the output signal of the power amplifier and the reverse signal reflected from the load to the directional coupler as adjustment coefficients. The impedance of the power amplifier is adjusted according to the adjustment coefficients. However, this method does not consider the impact of different phases on the performance of the power amplifier. It only makes uniform adjustments to all phases and only adjusts the load impedance after the power amplifier circuit back end is mismatched. It cannot always keep the linearity of the power amplifier within the communication specifications, cannot reduce the sensitivity of the power amplifier's linearity to the load impedance, and has limited effect on improving the linearity of the power amplifier.

[0004] Therefore, there is an urgent need for a new load impedance adjustment circuit and RF chip to solve the above-mentioned technical problems. Summary of the Invention

[0005] This invention provides a load impedance adjustment circuit and an RF chip, which aim to reduce the sensitivity of power amplifiers to load impedance and improve the efficiency of power amplifiers.

[0006] In a first aspect, the present invention provides a load impedance adjustment circuit, the load impedance adjustment circuit comprising a power amplifier, a load mismatch detection circuit, an adjustable output matching circuit, and a directional coupler;

[0007] The input terminal of the power amplifier serves as the input terminal of the load impedance adjustment circuit for receiving input signals, and the output terminal of the power amplifier is connected to the first input terminal of the adjustable output matching circuit.

[0008] The first input terminal and the second input terminal of the load mismatch detection circuit are respectively connected to the coupling terminal and the isolation terminal of the directional coupler, and the output terminal of the load mismatch detection circuit is connected to the second input terminal of the adjustable output matching circuit.

[0009] The output terminal of the adjustable output matching circuit is connected to the input terminal of the directional coupler, and the adjustable output matching circuit is used to adjust the load impedance of the power amplifier.

[0010] The output terminal of the directional coupler serves as the output terminal of the load impedance adjustment circuit, and is used to connect to the back-end components.

[0011] The load mismatch detection circuit is used to detect the coupling terminal voltage and the isolation terminal voltage of the directional coupler in real time, and calculate the reflection coefficient of the load impedance of the power amplifier based on the coupling terminal voltage and the isolation terminal voltage. It then determines whether the phase in the reflection coefficient exceeds a preset linearity range. If so, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit. The adjustable output matching circuit adjusts the impedance of the power amplifier according to the control signal to adjust the phase in the reflection coefficient that exceeds the preset linearity range to the preset linearity range.

[0012] Preferably, the adjustable output matching circuit includes a transformer, a first inductor, a first capacitor, a second inductor, a second capacitor, and a first switch; the input terminal of the transformer serves as the first input terminal of the adjustable output matching circuit, the output terminal of the transformer is connected to the first terminal of the first inductor, the second terminal of the first inductor is connected to the first terminal of the second inductor, the first terminal of the first capacitor is connected to the second terminal of the first inductor, the second terminal of the first capacitor is grounded, the second terminal of the second inductor serves as the output terminal of the adjustable output matching circuit, the first terminal of the second capacitor is connected to the second terminal of the second inductor, the second terminal of the second capacitor is connected to the control terminal of the first switch, and the output terminal of the first switch is grounded.

[0013] Preferably, the load mismatch detection circuit includes an amplitude detection unit and a phase detection unit; the first input terminal of the amplitude detection unit and the first input terminal of the phase detection unit are connected and together serve as the first input terminal of the load mismatch detection circuit; the second input terminal of the amplitude detection unit and the second input terminal of the phase detection unit are connected and together serve as the second input terminal of the load mismatch detection circuit; the output terminal of the amplitude detection unit and the output terminal of the phase detection unit are connected and together serve as the output terminal of the load mismatch detection circuit; the amplitude detection unit is used to detect the amplitude of the load impedance of the power amplifier, and the phase detection unit is used to detect the phase of the load impedance of the power amplifier.

[0014] The amplitude detection unit includes a first adjustable attenuation network, a second adjustable attenuation network, a first power detection circuit, a second power detection circuit, and a first voltage conversion circuit. The input terminal of the first adjustable attenuation network serves as the first input terminal of the amplitude detection unit, and the input terminal of the second adjustable attenuation network serves as the second input terminal of the amplitude detection unit. The output terminal of the first adjustable attenuation network is connected to the input terminal of the first power detection circuit, and the output terminal of the second adjustable attenuation network is connected to the input terminal of the second power detection circuit. The output terminal of the first power detection circuit is connected to the first input terminal of the first voltage conversion circuit, and the output terminal of the second power detection circuit is connected to the second input terminal of the first voltage conversion circuit. The output terminal of the first voltage conversion circuit serves as the output terminal of the amplitude detection unit. The phase detection unit includes a third adjustable attenuation network, a fourth adjustable attenuation network, a third power detection circuit, a fourth power detection circuit, and a second voltage conversion circuit. The input terminal of the third adjustable attenuation network serves as the first input terminal of the phase detection unit, and the input terminal of the fourth adjustable attenuation network serves as the second input terminal of the phase detection unit. The output terminal of the third adjustable attenuation network is connected to the input terminal of the third power detection circuit, and the output terminal of the fourth adjustable attenuation network is connected to the input terminal of the fourth power detection circuit. The output terminal of the third power detection circuit is connected to the first input terminal of the second voltage conversion circuit, and the output terminal of the fourth power detection circuit is connected to the second input terminal of the second voltage conversion circuit. The output terminal of the second voltage conversion circuit serves as the output terminal of the phase detection unit.

[0015] Preferably, the first power detection circuit, the second power detection circuit, the third power detection circuit, and the fourth power detection circuit have the same circuit structure; the first power detection circuit includes a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first transistor, a second transistor, and a third transistor;

[0016] The first terminal of the third capacitor serves as the input terminal of the first power detection circuit. The second terminal of the third capacitor is connected to the first terminal of the first resistor, the first terminal of the second resistor, and the collector of the first transistor. The second terminal of the first resistor is connected to a first external power supply voltage. The second terminal of the second resistor and the base of the first transistor are connected to the first terminal of the third resistor. The emitter of the first transistor is grounded. The second terminal of the third resistor is connected to the base of the second transistor. The first terminal of the fourth capacitor is connected to the second terminal of the third resistor. The second terminal of the fourth capacitor is grounded. The emitter of the second transistor is grounded. The collector of the second transistor is connected to the first terminal of the fourth resistor and the base of the third transistor. The second terminal of the fourth resistor is connected to a first external power supply voltage. The collector of the third transistor is connected to a second external power supply voltage. The emitter of the third transistor serves as the output terminal of the first power detection circuit. The first terminal of the fifth resistor and the first terminal of the fifth capacitor are connected to the emitter of the third transistor. The second terminal of the fifth resistor and the second terminal of the fifth capacitor are connected to each other and then grounded.

[0017] Preferably, the first voltage conversion circuit includes a first voltage-to-current circuit, a second voltage-to-current circuit, a first amplifier circuit, and a first current comparison circuit;

[0018] The input terminal of the first voltage-to-current circuit serves as the first input terminal of the first voltage conversion circuit. The first output terminal of the first voltage-to-current circuit is connected to the first input terminal of the first current comparison circuit, and the second output terminal of the first voltage-to-current circuit is connected to the second input terminal of the first current comparison circuit. The input terminal of the second voltage-to-current circuit serves as the second input terminal of the first voltage conversion circuit. The first output terminal of the second voltage-to-current circuit is connected to the first input terminal of the first amplifier circuit, and the second output terminal of the second voltage-to-current circuit is connected to the second input terminal of the first amplifier circuit. The output terminal of the first amplifier circuit is connected to the third input terminal of the first current comparison circuit. The output terminal of the first current comparison circuit serves as the output terminal of the first voltage conversion circuit.

[0019] The first voltage-to-current conversion circuit includes a first operational amplifier, a first MOSFET, and a sixth resistor. The negative input terminal of the first operational amplifier serves as the input terminal of the first voltage-to-current conversion circuit. The positive input terminal of the first operational amplifier is connected to the drain of the first MOSFET and the first terminal of the sixth resistor. The second terminal of the sixth resistor is grounded. The output terminal of the first operational amplifier is connected to the gate of the first MOSFET and serves as the first output terminal of the first voltage-to-current conversion circuit. The source of the first MOSFET is used to connect to a second external power supply voltage and serves as the second output terminal of the first voltage-to-current conversion circuit.

[0020] The second voltage-to-current conversion circuit includes a second operational amplifier, a second MOSFET, and a seventh resistor. The negative input terminal of the second operational amplifier serves as the input terminal of the second voltage-to-current conversion circuit. The positive input terminal of the second operational amplifier is connected to the drain of the second MOSFET and the first terminal of the seventh resistor. The second terminal of the seventh resistor is connected to the gate of the second operational amplifier. The output terminal of the second operational amplifier is connected to the gate of the second MOSFET and serves as the first output terminal of the second voltage-to-current conversion circuit. The source of the second MOSFET is used to connect to a second external power supply voltage and serves as the second output terminal of the second voltage-to-current conversion circuit.

[0021] The first amplifier circuit includes a third MOS transistor and a fourth MOS transistor; the gate of the third MOS transistor serves as the first input terminal of the first amplifier circuit, the source of the third MOS transistor serves as the second input terminal of the first amplifier circuit, the source of the third MOS transistor is used to connect to a second external power supply voltage, the drain of the third MOS transistor is connected to the drain of the fourth MOS transistor and the gate of the fourth MOS transistor respectively, the source of the fourth MOS transistor is grounded, and the gate of the fourth MOS transistor serves as the output terminal of the first amplifier circuit.

[0022] The first current comparator circuit includes a fifth MOSFET, a sixth MOSFET, a first inverter, and a second inverter. The gate of the fifth MOSFET serves as the first input terminal of the first current comparator circuit, the source of the fifth MOSFET serves as the second input terminal of the first current comparator circuit, the source of the fifth MOSFET is connected to a second external power supply voltage, and the drain of the fifth MOSFET is connected to the input terminal of the first inverter. The gate of the sixth MOSFET serves as the third input terminal of the first current comparator circuit, the source of the sixth MOSFET is grounded, the drain of the sixth MOSFET is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the first current comparator circuit.

[0023] Preferably, the second voltage conversion circuit includes a third voltage-to-current circuit, a fourth voltage-to-current circuit, a second amplifier circuit, a current subtraction circuit, and a second current comparison circuit.

[0024] The input terminal of the third voltage-to-current circuit serves as the first input terminal of the second voltage conversion circuit. The first output terminal of the third voltage-to-current circuit is connected to the first input terminal of the current subtraction circuit, and the second output terminal of the third voltage-to-current circuit is connected to the second input terminal of the current subtraction circuit. The input terminal of the fourth voltage-to-current circuit serves as the second input terminal of the second voltage conversion circuit. The first output terminal of the fourth voltage-to-current circuit is connected to the first input terminal of the second amplifier circuit, and the second output terminal of the fourth voltage-to-current circuit is connected to the second input terminal of the second amplifier circuit. The output terminal of the second amplifier circuit is connected to the third input terminal of the current subtraction circuit, and the output terminal of the current subtraction circuit is connected to the input terminal of the second current comparator circuit. The output terminal of the second current comparator circuit serves as the output terminal of the second voltage conversion circuit.

[0025] The third voltage-to-current conversion circuit includes a third operational amplifier, a seventh MOS transistor, and an eighth resistor. The negative input terminal of the third operational amplifier serves as the input terminal of the third voltage-to-current conversion circuit. The positive input terminal of the third operational amplifier is connected to the drain of the seventh MOS transistor and the first terminal of the eighth resistor. The second terminal of the eighth resistor is grounded. The output terminal of the third operational amplifier is connected to the gate of the seventh MOS transistor, serving as the first output terminal of the third voltage-to-current conversion circuit. The source of the seventh MOS transistor serves as the second output terminal of the third voltage-to-current conversion circuit, and the source of the seventh MOS transistor is used to connect to a second external power supply voltage.

[0026] The fourth voltage-to-current conversion circuit includes a fourth operational amplifier, an eighth MOS transistor, and a ninth resistor. The negative input terminal of the fourth operational amplifier serves as the input terminal of the fourth voltage-to-current conversion circuit. The positive input terminal of the fourth operational amplifier is connected to the drain of the eighth MOS transistor and the first terminal of the ninth resistor. The second terminal of the ninth resistor is grounded. The output terminal of the fourth operational amplifier is connected to the gate of the eighth MOS transistor, serving as the first output terminal of the fourth voltage-to-current conversion circuit. The source of the eighth MOS transistor serves as the second output terminal of the fourth voltage-to-current conversion circuit. The source of the eighth MOS transistor is used to connect to a second external power supply voltage.

[0027] The second amplifier circuit includes a ninth MOS transistor and a tenth MOS transistor; the gate of the ninth MOS transistor serves as the first input terminal of the second amplifier circuit, the source of the ninth MOS transistor serves as the second input terminal of the second amplifier circuit, the source of the ninth MOS transistor is used to connect to a second external power supply voltage, the drain of the ninth MOS transistor is connected to the drain of the tenth MOS transistor and the gate of the tenth MOS transistor respectively, the source of the tenth MOS transistor is grounded, and the gate of the tenth MOS transistor serves as the output terminal of the second amplifier circuit.

[0028] The current subtraction circuit includes an eleventh MOSFET, a twelfth MOSFET, and a thirteenth MOSFET. The gate of the eleventh MOSFET serves as the first input terminal of the current subtraction circuit, and the source of the eleventh MOSFET serves as the second input terminal of the current subtraction circuit. The source of the eleventh MOSFET is connected to a second external power supply voltage, and the drain of the eleventh MOSFET is connected to the drain of the twelfth MOSFET. The gate of the twelfth MOSFET serves as the third input terminal of the current subtraction circuit. The source of the twelfth MOSFET is grounded, and the drain of the twelfth MOSFET is connected to both the drain and gate of the thirteenth MOSFET. The source of the thirteenth MOSFET is grounded, and the gate of the thirteenth MOSFET serves as the output terminal of the current subtraction circuit.

[0029] The second current comparator circuit includes a current source, a fourteenth MOSFET, a third inverter, and a fourth inverter. The input terminal of the current source is connected to a second external power supply voltage, and the output terminal of the current source is connected to the input terminal of the third inverter. The gate of the fourteenth MOSFET serves as the input terminal of the second current comparator circuit, the source of the fourteenth MOSFET is grounded, the drain of the fourteenth MOSFET is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter serves as the output terminal of the second current comparator circuit.

[0030] Preferably, the coupling terminal voltage is defined as Vcpl, the isolation terminal voltage as Viso, and the reflection coefficient as ΓL. The reflection coefficient is calculated by combining the coupling terminal voltage and the isolation terminal voltage according to the following rules:

[0031] .

[0032] Preferably, the preset linearity range is less than -33dBc.

[0033] Preferably, the back-end component is a filter device.

[0034] Secondly, the present invention also provides a radio frequency chip, the radio frequency chip including a load impedance adjustment circuit as described in any of the above embodiments.

[0035] Compared to existing technologies, this invention uses a load mismatch detection circuit to detect the coupling terminal voltage and isolation terminal voltage of the directional coupler in real time. Based on these voltages, it calculates the reflection coefficient of the power amplifier's load impedance and determines whether the phase in the reflection coefficient exceeds a preset linearity range. If so, the load mismatch detection circuit outputs a control signal to an adjustable output matching circuit. The adjustable output matching circuit then adjusts the impedance of the power amplifier according to the control signal to bring the phase in the reflection coefficient that exceeds the preset linearity range within that range. In this way, this invention can specifically adjust the phase with poor linearity in the reflection coefficient, thereby reducing the sensitivity of the power amplifier's performance to changes in load impedance and effectively improving the power amplifier's efficiency. Attached Figure Description

[0036] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0037] Figure 1 This is a schematic diagram of the circuit structure of the load impedance adjustment circuit provided in an embodiment of the present invention;

[0038] Figure 2 This is a comparison chart of simulation results of the load impedance adjustment circuit provided in the embodiment of the present invention with a power amplifier that does not perform load impedance adjustment in related technologies.

[0039] Figure 3 This is a Smith chart of the load impedance adjustment circuit provided in the embodiments of the present invention;

[0040] Figure 4 This is a schematic diagram of the load impedance adjustment principle of the load impedance adjustment circuit provided in the embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram illustrating the load impedance adjustment principle of a power amplifier in related technologies;

[0042] Figure 6 This is a schematic diagram of the circuit structure of the adjustable output matching circuit of the load impedance adjustment circuit provided in the embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram of the circuit structure of the amplitude detection unit of the load mismatch detection circuit of the load impedance adjustment circuit provided in the embodiment of the present invention.

[0044] Figure 8 This is a schematic diagram of the circuit structure of the phase detection unit of the load mismatch detection circuit of the load impedance adjustment circuit provided in the embodiment of the present invention.

[0045] Figure 9 This is a schematic diagram of the circuit structure of the first power detection circuit of the load impedance adjustment circuit provided in the embodiment of the present invention;

[0046] Figure 10 This is a schematic diagram of the circuit structure of the first voltage conversion circuit of the load impedance adjustment circuit provided in the embodiment of the present invention;

[0047] Figure 11 This is a schematic diagram of the circuit structure of the second voltage conversion circuit of the load impedance adjustment circuit provided in the embodiment of the present invention.

[0048] In the diagram, 100 is the load impedance adjustment circuit, 1 is the power amplifier, 2 is the adjustable output matching circuit, 3 is the load mismatch detection circuit, 31 is the amplitude detection unit, 311 is the first adjustable attenuation network, 312 is the first power detection circuit, 313 is the second adjustable attenuation network, 314 is the second power detection circuit, 315 is the first voltage conversion circuit, 3151 is the first voltage to current conversion circuit, 3152 is the second voltage to current conversion circuit, 3153 is the first amplification circuit, 3154 is the first current comparison circuit, 32 is the phase detection unit, 321 is the third adjustable attenuation network, 322 is the third power detection circuit, 323 is the fourth adjustable attenuation network, 324 is the fourth power detection circuit, 325 is the second voltage conversion circuit, 3251 is the third voltage to current conversion circuit, 3252 is the fourth voltage to current conversion circuit, 3253 is the second amplification circuit, 3254 is the current subtraction circuit, 3255 is the second current comparison circuit, 4 is the directional coupler, and 5 is the back-end component. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0050] Example 1

[0051] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of the load impedance adjustment circuit provided in an embodiment of the present invention. The present invention provides a load impedance adjustment circuit 100, which includes a power amplifier 1, a load mismatch detection circuit 3, an adjustable output matching circuit 2, and a directional coupler 4.

[0052] The input terminal of the power amplifier 1 serves as the input terminal of the load impedance adjustment circuit 100 for receiving input signals, and the output terminal of the power amplifier 1 is connected to the first input terminal of the adjustable output matching circuit 2.

[0053] The first input terminal and the second input terminal of the load mismatch detection circuit 3 are respectively connected to the coupling terminal and the isolation terminal of the directional coupler 4, and the output terminal of the load mismatch detection circuit 3 is connected to the second input terminal of the adjustable output matching circuit 2.

[0054] The output terminal of the adjustable output matching circuit 2 is connected to the input terminal of the directional coupler 4, and the adjustable output matching circuit 2 is used to adjust the load impedance of the power amplifier 1.

[0055] The output terminal of the directional coupler 4 serves as the output terminal of the load impedance adjustment circuit 100 and is used to connect to the back-end component 5.

[0056] The load mismatch detection circuit 3 is used to detect the coupling terminal voltage and the isolation terminal voltage of the directional coupler 4 in real time, and calculate the reflection coefficient of the load impedance of the power amplifier 1 based on the coupling terminal voltage and the isolation terminal voltage, and determine whether the phase in the reflection coefficient exceeds the preset linearity range. If so, the load mismatch detection circuit 3 outputs a control signal to the adjustable output matching circuit 2, and the adjustable output matching circuit 2 adjusts the impedance of the power amplifier 1 according to the control signal to adjust the phase in the reflection coefficient that exceeds the preset linearity range to the preset linearity range.

[0057] Specifically, the reflection coefficient corresponding to the load impedance is detected by the load mismatch detection circuit 3, and a control signal is output to the adjustable output matching circuit 2. The adjustable output matching circuit 2 adjusts the impedance, ensuring that the phase of the reflection coefficient remains within a preset linearity range. This effectively reduces the sensitivity of the power amplifier 1's linearity to the load impedance, significantly improving the efficiency of the power amplifier 1. In this embodiment, the coupling terminal voltage is defined as Vcpl, the isolation terminal voltage as Viso, and the reflection coefficient as ΓL. The reflection coefficient is calculated from the coupling terminal voltage and the isolation terminal voltage according to the following rules:

[0058] .

[0059] Specifically, since the reflection coefficient satisfies ΓL=V- / V+, where V+ and V- represent the voltage of the incident wave transmitted to the load and the voltage of the reflected wave, respectively, for the directional coupler 4, its coupling terminal voltage satisfies Vcpl=C*V+, and the isolation terminal voltage satisfies Viso=C*V-, where C is the coupling coefficient of the directional coupler 4, the reflection coefficient can be characterized by the signals at the isolation terminal and the coupling terminal of the directional coupler 4.

[0060] In this embodiment of the invention, the preset linearity range is less than -33dBc. It should be noted that the preset linearity range can be set according to actual conditions and is not limited to -33dBc; other values ​​are also feasible.

[0061] For details, please refer to Figure 2 This is a comparison chart of simulation results of the load impedance adjustment circuit provided in the embodiment of the present invention with load impedance adjustment and power amplifiers in related technologies without load impedance adjustment. Figure 2 The figure shows a comparison of simulation results between a power amplifier using the load impedance adjustment circuit 100 provided by this invention and a power amplifier in related technologies without load impedance adjustment, when the voltage standing wave ratio (VSWR) is 2:1 and the phase varies from 0 to 360°. As can be seen from the figure, when the load impedance is adjusted using the load impedance adjustment circuit 100 provided by this invention, the linearity, i.e., the adjacent channel power ratio (ACPR), is improved by 7 dB in the phase range of 0°-180°. In contrast, the power amplifier in related technologies, without load impedance adjustment, significantly exceeds the preset linearity range in the phase range of 0°-180°. Therefore, the load impedance adjustment circuit 100 proposed by this invention can significantly improve the sensitivity of the power amplifier 1 to load impedance, effectively improving the efficiency of the power amplifier 1.

[0062] Please refer to Figure 3 , Figure 3 This is a Smith chart of the load impedance adjustment circuit provided in an embodiment of the present invention. Figure 3 It is known that the performance of power amplifier 1 changes significantly with phase when the reflection coefficient is equal. On the circuit with equal reflection coefficients, both the adjacent channel leakage ratio (ACLR) and current dissipation (ICC) (where a smaller ACLR value corresponds to a larger ICC value) change. This invention can adjust the linearity of different phases when the reflection coefficients are equal, and its principle is as follows: Figure 4 As shown, Figure 4 This is a schematic diagram of the load impedance adjustment principle of the load impedance adjustment circuit provided in the embodiment of the present invention. Figure 4 Regions 1, 2, and 3 are marked (the extent, size, and number of regions are for illustrative purposes only). The outer ring formed by regions 2 and 3 has the same reflection coefficient, but the performance of power amplifier 1 differs significantly between the two regions. For example, power amplifier 1 performs better in region 2 than in region 3, and the linearity of power amplifier 1 in region 3 does not conform to the preset linearity range (region 3 can be understood as...). Figure 2 The phase shown exceeds -33dBc in the 0°-180° region (i.e., the phase in region 3 is a phase with poor linearity and requires impedance adjustment to bring the phase in region 3 back to region 1). In related technologies, such as... Figure 5 As shown, Figure 5 This is a schematic diagram illustrating the load impedance adjustment principle of a power amplifier in related technologies. When adjusting the impedance, it is necessary to... Figure 5 The inner and outer circles (i.e.) Figure 5 A large circle composed of dots, such as Figure 5 Point m1 in the diagram represents a node with a reflection coefficient of S(1,1) = 0.67 / 1.80E2 and an impedance of 10.00 + j2.94E-15. The value of the reflection coefficient is adjusted to the inner circle (i.e., Figure 5 Small circles made up of dots, such as Figure 5 Point m2 in the diagram represents a node with a reflection coefficient of S(1,1) = 0.33 / 1.80E2 and an impedance of 24.96 + j2.94E-15. This requires simultaneous adjustment of each phase, but this method cannot effectively distinguish between phases with poor linearity and phases with good linearity. The method proposed in this invention can specifically adjust the phases with poor linearity in power amplifier 1, and its adjustment effect is better.

[0063] In this embodiment of the invention, the back-end component 5 is a filter device. The output terminal of the back-end component 5 is connected to an antenna, and the load impedance of the power amplifier 1 changes with the position of the antenna.

[0064] In the embodiments of the present invention, please refer to Figure 6 , Figure 6 This is a schematic diagram of the adjustable output matching circuit of the load impedance adjustment circuit provided in this embodiment of the invention. The adjustable output matching circuit 2 includes a transformer, a first inductor L1, a first capacitor C1, a second inductor L2, a second capacitor C2, and a first switch SW. The input terminal of the transformer serves as the first input terminal of the adjustable output matching circuit 2. The output terminal of the transformer is connected to the first terminal of the first inductor L1. The second terminal of the first inductor L1 is connected to the first terminal of the second inductor L2. The first terminal of the first capacitor C1 is connected to the second terminal of the first inductor L1, and the second terminal of the first capacitor C1 is grounded. The second terminal of the second inductor L2 serves as the output terminal of the adjustable output matching circuit 2. The first terminal of the second capacitor C2 is connected to the second terminal of the second inductor L2, and the second terminal of the second capacitor C2 is connected to the control terminal of the first switch SW. The output terminal of the first switch SW is grounded. Specifically, the first switch SW is used as the second input terminal of the adjustable output matching circuit 2. The first switch SW is turned on or off according to the control signal from the load mismatch detection circuit 3 to adjust the load impedance of the power amplifier 1.

[0065] In the embodiments of the present invention, please refer to Figures 7-8 , Figure 7 This is a schematic diagram of the circuit structure of the amplitude detection unit of the load mismatch detection circuit of the load impedance adjustment circuit provided in the embodiment of the present invention. Figure 8 This is a schematic diagram of the phase detection unit of the load mismatch detection circuit in the load impedance adjustment circuit provided in this embodiment of the invention. The load mismatch detection circuit 3 includes an amplitude detection unit 31 and a phase detection unit 32; the first input terminal of the amplitude detection unit 31 and the first input terminal of the phase detection unit 32 are connected and together serve as the first input terminal of the load mismatch detection circuit 3; the second input terminal of the amplitude detection unit 31 and the second input terminal of the phase detection unit 32 are connected and together serve as the second input terminal of the load mismatch detection circuit 3; the output terminal of the amplitude detection unit 31 and the output terminal of the phase detection unit 32 are connected and together serve as the output terminal of the load mismatch detection circuit 3; the amplitude detection unit 31 is used to detect the amplitude of the load impedance of the power amplifier 1, and the phase detection unit 32 is used to detect the phase of the load impedance of the power amplifier 1.

[0066] Specifically, when the amplitude detection result of the amplitude detection unit 31 exceeds the preset range, an enable signal is sent to drive the phase detection unit 32 to perform phase detection. When the detection results of the amplitude detection unit 31 and the phase detection unit 32 both exceed the preset range, control signals (i.e., Vcrtl1 and Vcrtl2) are sent to the first switch SW, causing the first switch SW to close.

[0067] The amplitude detection unit 31 includes a first adjustable attenuation network 311, a second adjustable attenuation network 313, a first power detection circuit 312, a second power detection circuit 314, and a first voltage conversion circuit 315. The input terminal of the first adjustable attenuation network 311 serves as the first input terminal of the amplitude detection unit 31, and the input terminal of the second adjustable attenuation network 313 serves as the second input terminal of the amplitude detection unit 31. The output terminal of the first adjustable attenuation network 311 is connected to the input terminal of the first power detection circuit 312, and the output terminal of the second adjustable attenuation network 313 is connected to the input terminal of the second power detection circuit 314. The output terminal of the first power detection circuit 312 is connected to the first input terminal of the first voltage conversion circuit 315, and the output terminal of the second power detection circuit 314 is connected to the second input terminal of the first voltage conversion circuit 315. The output terminal of the first voltage conversion circuit 315 serves as the output terminal of the amplitude detection unit 31.

[0068] The phase detection unit 32 includes a third adjustable attenuation network 321, a fourth adjustable attenuation network 323, a third power detection circuit 322, a fourth power detection circuit 324, and a second voltage conversion circuit 325. The input terminal of the third adjustable attenuation network 321 serves as the first input terminal of the phase detection unit 32, and the input terminal of the fourth adjustable attenuation network 323 serves as the second input terminal of the phase detection unit 32. The output terminal of the third adjustable attenuation network 321 is connected to the input terminal of the third power detection circuit 322, and the output terminal of the fourth adjustable attenuation network 323 is connected to the input terminal of the fourth power detection circuit 324. The output terminal of the third power detection circuit 322 is connected to the first input terminal of the second voltage conversion circuit 325, and the output terminal of the fourth power detection circuit 324 is connected to the second input terminal of the second voltage conversion circuit 325. The output terminal of the second voltage conversion circuit 325 serves as the output terminal of the phase detection unit 32.

[0069] In this embodiment of the invention, the first power detection circuit 312, the second power detection circuit 314, the third power detection circuit 322, and the fourth power detection circuit 324 have the same circuit structure; the first adjustable attenuation network 311, the second adjustable attenuation network 313, the third adjustable attenuation network 321, and the fourth adjustable attenuation network 323 have the same circuit structure.

[0070] In the embodiments of the present invention, please refer to Figure 9 , Figure 9 This is a schematic diagram of the circuit structure of the first power detection circuit of the load impedance adjustment circuit provided in the embodiment of the present invention. The first power detection circuit 312 includes a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first transistor T1, a second transistor T2, and a third transistor T3;

[0071] The first terminal of the third capacitor C3 serves as the input terminal of the first power detection circuit 312. The second terminal of the third capacitor C3 is connected to the first terminal of the first resistor R1, the first terminal of the second resistor R2, and the collector of the first transistor T1. The second terminal of the first resistor R1 is connected to the first external power supply voltage Vbias. The second terminal of the second resistor R2 and the base of the first transistor T1 are respectively connected to the first terminal of the third resistor R3. The emitter of the first transistor T1 is grounded. The second terminal of the third resistor R3 is connected to the base of the second transistor T2. The first terminal of the fourth capacitor C4 is connected to the second terminal of the third resistor R3. The second terminal of capacitor C4 is grounded, the emitter of the second transistor T2 is grounded, the collector of the second transistor T2 is connected to the first terminal of the fourth resistor R4 and the base of the third transistor T3, the second terminal of the fourth resistor R4 is connected to the first external power supply voltage Vbias, the collector of the third transistor T3 is connected to the second external power supply voltage Vat, the emitter of the third transistor T3 serves as the output terminal of the first power detection circuit 312, the first terminal of the fifth resistor R5 and the first terminal of the fifth capacitor C5 are connected to the emitter of the third transistor T3, and the second terminals of the fifth resistor R5 and the fifth capacitor C5 are connected to each other and then grounded. It should be noted that the values ​​of the first external power supply voltage Vbias and the second external power supply voltage Vat can be set according to actual conditions.

[0072] In the embodiments of the present invention, please refer to Figure 10 , Figure 10This is a schematic diagram of the circuit structure of the first voltage conversion circuit of the load impedance adjustment circuit provided in this embodiment of the invention. The first voltage conversion circuit 315 includes a first voltage-to-current circuit 3151, a second voltage-to-current circuit 3152, a first amplifier circuit 3153, and a first current comparison circuit 3154; wherein, the first voltage-to-current circuit 3151 is used to convert the received voltage into current (e.g., ...). Figure 10 V1); the second voltage-to-current circuit 3152 is used to convert the received voltage into current (e.g., V1); Figure 10 (V2 in the first amplifier circuit 3153 amplifies the current output by the second voltage-to-current circuit 3152; the first current comparison circuit 3154 is used to determine whether the received current exceeds a preset threshold.)

[0073] The input terminal of the first voltage-to-current circuit 3151 serves as the first input terminal of the first voltage conversion circuit 315. The first output terminal of the first voltage-to-current circuit 3151 is connected to the first input terminal of the first current comparison circuit 3154, and the second output terminal of the first voltage-to-current circuit 3151 is connected to the second input terminal of the first current comparison circuit 3154. The input terminal of the second voltage-to-current circuit 3152 serves as the second input terminal of the first voltage conversion circuit 315. The first output terminal of the second voltage-to-current circuit 3152 is connected to the first input terminal of the first amplifier circuit 3153, and the second output terminal of the second voltage-to-current circuit 3152 is connected to the second input terminal of the first amplifier circuit 3153. The output terminal of the first amplifier circuit 3153 is connected to the third input terminal of the first current comparison circuit 3154. The output terminal of the first current comparison circuit 3154 serves as the output terminal of the first voltage conversion circuit 315.

[0074] The first voltage-to-current conversion circuit 3151 includes a first operational amplifier OPA1, a first MOSFET M1, and a sixth resistor R6. The negative input terminal of the first operational amplifier OPA1 serves as the input terminal of the first voltage-to-current conversion circuit 3151. The positive input terminal of the first operational amplifier OPA1 is connected to the drain of the first MOSFET M1 and the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is grounded. The output terminal of the first operational amplifier OPA1 is connected to the gate of the first MOSFET M1 and serves as the first output terminal of the first voltage-to-current conversion circuit 3151. The source of the first MOSFET M1 is used to connect to the second external power supply voltage Vbat and serves as the second output terminal of the first voltage-to-current conversion circuit 3151.

[0075] The second voltage-to-current conversion circuit 3152 includes a second operational amplifier OPA2, a second MOSFET M2, and a seventh resistor R7. The negative input terminal of the second operational amplifier OPA2 serves as the input terminal of the second voltage-to-current conversion circuit 3152. The positive input terminal of the second operational amplifier OPA2 is connected to the drain of the second MOSFET M2 and the first terminal of the seventh resistor R7. The second terminal of the seventh resistor R7 is connected to the gate of the second MOSFET M2. The output terminal of the second operational amplifier OPA2 is connected to the gate of the second MOSFET M2. The output terminal of the second operational amplifier OPA2 serves as the first output terminal of the second voltage-to-current conversion circuit 3152. The source of the second MOSFET M2 is used to connect to the second external power supply voltage Vbat. The source of the second MOSFET M2 serves as the second output terminal of the second voltage-to-current conversion circuit 3152.

[0076] The first amplifier circuit 3153 includes a third MOSFET M3 and a fourth MOSFET M4; the gate of the third MOSFET M3 serves as the first input terminal of the first amplifier circuit 3153, the source of the third MOSFET M3 serves as the second input terminal of the first amplifier circuit 3153, the source of the third MOSFET M3 is used to connect to a second external power supply voltage Vbat, the drain of the third MOSFET M3 is connected to the drain of the fourth MOSFET M4 and the gate of the fourth MOSFET M4, the source of the fourth MOSFET M4 is grounded, and the gate of the fourth MOSFET M4 serves as the output terminal of the first amplifier circuit 3153;

[0077] The first current comparator circuit 3154 includes a fifth MOSFET M5, a sixth MOSFET M6, a first inverter INV1, and a second inverter INV2. The gate of the fifth MOSFET M5 serves as the first input terminal of the first current comparator circuit 3154, the source of the fifth MOSFET M5 serves as the second input terminal of the first current comparator circuit 3154, the source of the fifth MOSFET M5 is connected to a second external power supply voltage Vbat, and the drain of the fifth MOSFET M5 is connected to the input terminal of the first inverter INV1. The gate of the sixth MOSFET M6 serves as the third input terminal of the first current comparator circuit 3154, the source of the sixth MOSFET M6 is grounded, the drain of the sixth MOSFET M6 is connected to the input terminal of the first inverter INV1, the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 serves as the output terminal of the first current comparator circuit 3154.

[0078] In the embodiments of the present invention, please refer to Figure 11 , Figure 11This is a schematic diagram of the circuit structure of the second voltage conversion circuit 325 of the load impedance adjustment circuit provided in this embodiment of the invention. The second voltage conversion circuit 325 includes a third voltage-to-current circuit 3251, a fourth voltage-to-current circuit 3252, a second amplifier circuit 3253, a current subtraction circuit 3254, and a second current comparison circuit 3255; wherein, the third voltage-to-current circuit 3251 is used to convert the received voltage into current (e.g., ...). Figure 11 V3); the fourth voltage-to-current circuit 3252 is used to convert the received voltage into current (e.g., V3); Figure 11 The second amplifier circuit 3253 amplifies the current output by the third voltage-to-current circuit 3251; the current subtraction circuit 3254 is used to control the magnitude of the received current; and the second current comparison circuit 3255 is used to determine whether the received current exceeds a preset threshold.

[0079] The input terminal of the third voltage-to-current circuit 3251 serves as the first input terminal of the second voltage conversion circuit 325. The first output terminal of the third voltage-to-current circuit 3251 is connected to the first input terminal of the current subtraction circuit 3254, and the second output terminal of the third voltage-to-current circuit 3251 is connected to the second input terminal of the current subtraction circuit 3254. The input terminal of the fourth voltage-to-current circuit 3252 serves as the second input terminal of the second voltage conversion circuit 3255. The first output terminal of the fourth voltage-to-current circuit 3252 is connected to the first input terminal of the second amplifier circuit 3253, and the second output terminal of the fourth voltage-to-current circuit 3252 is connected to the second input terminal of the second amplifier circuit 3253. The output terminal of the second amplifier circuit 3253 is connected to the third input terminal of the current subtraction circuit 3254, and the second output terminal of the current subtraction circuit 3254 is connected to the input terminal of the second current comparison circuit 3255. The output terminal of the second current comparison circuit 3255 serves as the output terminal of the second voltage conversion circuit 325.

[0080] The third voltage-to-current conversion circuit 3251 includes a third operational amplifier OPA3, a seventh MOSFET M7, and an eighth resistor R8. The negative input terminal of the third operational amplifier OPA3 serves as the input terminal of the third voltage-to-current conversion circuit 3251. The positive input terminal of the third operational amplifier OPA3 is connected to the drain of the seventh MOSFET M7 and the first terminal of the eighth resistor R8. The second terminal of the eighth resistor R8 is grounded. The output terminal of the third operational amplifier OPA3 is connected to the gate of the seventh MOSFET M7, serving as the first output terminal of the third voltage-to-current conversion circuit 3251. The source of the seventh MOSFET M7 serves as the second output terminal of the third voltage-to-current conversion circuit 3251. The source of the seventh MOSFET M7 is used to connect to the second external power supply voltage Vbat.

[0081] The fourth voltage-to-current conversion circuit 3252 includes a fourth operational amplifier OPA4, an eighth MOSFET M8, and a ninth resistor R9. The negative input terminal of the fourth operational amplifier OPA4 serves as the input terminal of the fourth voltage-to-current conversion circuit 3252. The positive input terminal of the fourth operational amplifier OPA4 is connected to the drain of the eighth MOSFET M8 and the first terminal of the ninth resistor R9. The second terminal of the ninth resistor R9 is grounded. The output terminal of the fourth operational amplifier OPA4 is connected to the gate of the eighth MOSFET M8, serving as the first output terminal of the fourth voltage-to-current conversion circuit 3252. The source of the eighth MOSFET M8 serves as the second output terminal of the fourth voltage-to-current conversion circuit 3252. The source of the eighth MOSFET M8 is used to connect to the second external power supply voltage Vbat.

[0082] The second amplifier circuit 3253 includes a ninth MOSFET M9 and a tenth MOSFET M10; the gate of the ninth MOSFET M9 serves as the first input terminal of the second amplifier circuit 3253, the source of the ninth MOSFET M9 serves as the second input terminal of the second amplifier circuit 3253, the source of the ninth MOSFET M9 is used to connect to a second external power supply voltage Vbat, the drain of the ninth MOSFET M9 is connected to the drain of the tenth MOSFET M10 and the gate of the tenth MOSFET M10, the source of the tenth MOSFET M10 is grounded, and the gate of the tenth MOSFET M10 serves as the output terminal of the second amplifier circuit 3253;

[0083] The current subtraction circuit 3254 includes an eleventh MOSFET M11, a twelfth MOSFET M12, and a thirteenth MOSFET M13. The gate of the eleventh MOSFET M11 serves as the first input terminal of the current subtraction circuit 3254, and the source of the eleventh MOSFET M11 serves as the second input terminal of the current subtraction circuit 3254. The source of the eleventh MOSFET M11 is connected to a second external power supply voltage Vbat, and the drain of the eleventh MOSFET M11 is connected to the drain of the twelfth MOSFET M12. The gate of the twelfth MOSFET M12 serves as the third input terminal of the current subtraction circuit, the source of the twelfth MOSFET M12 is grounded, the drain of the twelfth MOSFET M12 is connected to both the drain and the gate of the thirteenth MOSFET M13, the source of the thirteenth MOSFET M13 is grounded, and the gate of the thirteenth MOSFET M13 serves as the output terminal of the current subtraction circuit 3254.

[0084] The second current comparator circuit 3255 includes a current source Iref, a fourteenth MOSFET M14, a third inverter INV3, and a fourth inverter INV4. The input terminal of the current source Iref is connected to a second external power supply voltage Vbat, and the output terminal of the current source Iref is connected to the input terminal of the third inverter INV3. The gate of the fourteenth MOSFET M14 serves as the input terminal of the second current comparator circuit 3255, the source of the fourteenth MOSFET M14 is grounded, the drain of the fourteenth MOSFET M14 is connected to the input terminal of the third inverter INV3, the output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4, and the output terminal of the fourth inverter INV4 serves as the output terminal of the second current comparator circuit.

[0085] Compared to existing technologies, this invention uses a load mismatch detection circuit to detect the coupling terminal voltage and isolation terminal voltage of the directional coupler in real time. Based on these voltages, it calculates the reflection coefficient of the power amplifier's load impedance and determines whether the phase in the reflection coefficient exceeds a preset linearity range. If so, the load mismatch detection circuit outputs a control signal to an adjustable output matching circuit. The adjustable output matching circuit then adjusts the impedance of the power amplifier according to the control signal to bring the phase in the reflection coefficient that exceeds the preset linearity range within that range. In this way, this invention can specifically adjust the phase with poor linearity in the reflection coefficient, thereby reducing the sensitivity of the power amplifier's performance to changes in load impedance and effectively improving the power amplifier's efficiency.

[0086] Example 2

[0087] This invention also provides a radio frequency (RF) chip, which includes the load impedance adjustment circuit 100 as described in the above embodiments and can achieve the same technical effect. Please refer to the description in the above embodiments, which will not be repeated here.

[0088] Compared to existing technologies, this invention uses a load mismatch detection circuit to detect the coupling terminal voltage and isolation terminal voltage of the directional coupler in real time. Based on these voltages, it calculates the reflection coefficient of the power amplifier's load impedance and determines whether the phase in the reflection coefficient exceeds a preset linearity range. If so, the load mismatch detection circuit outputs a control signal to an adjustable output matching circuit. The adjustable output matching circuit then adjusts the impedance of the power amplifier according to the control signal to bring the phase in the reflection coefficient that exceeds the preset linearity range within that range. In this way, this invention can specifically adjust the phase with poor linearity in the reflection coefficient, thereby reducing the sensitivity of the power amplifier's performance to changes in load impedance and effectively improving the power amplifier's efficiency.

[0089] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0090] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A load impedance adjustment circuit, characterized in that, The load impedance adjustment circuit includes a power amplifier, a load mismatch detection circuit, an adjustable output matching circuit, and a directional coupler. The input terminal of the power amplifier serves as the input terminal of the load impedance adjustment circuit for receiving input signals, and the output terminal of the power amplifier is connected to the first input terminal of the adjustable output matching circuit. The first input terminal and the second input terminal of the load mismatch detection circuit are respectively connected to the coupling terminal and the isolation terminal of the directional coupler, and the output terminal of the load mismatch detection circuit is connected to the second input terminal of the adjustable output matching circuit. The output terminal of the adjustable output matching circuit is connected to the input terminal of the directional coupler, and the adjustable output matching circuit is used to adjust the load impedance of the power amplifier. The output terminal of the directional coupler serves as the output terminal of the load impedance adjustment circuit, and is used to connect to the back-end components. The load mismatch detection circuit is used to detect the coupling terminal voltage and the isolation terminal voltage of the directional coupler in real time, and calculate the reflection coefficient of the load impedance of the power amplifier based on the coupling terminal voltage and the isolation terminal voltage. It then determines whether the phase in the reflection coefficient exceeds the preset linearity range. If so, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit. The adjustable output matching circuit adjusts the impedance of the power amplifier according to the control signal to adjust the phase in the reflection coefficient that exceeds the preset linearity range to the preset linearity range. The adjustable output matching circuit includes a transformer, a first inductor, a first capacitor, a second inductor, a second capacitor, and a first switch; the input terminal of the transformer serves as the first input terminal of the adjustable output matching circuit, the output terminal of the transformer is connected to the first terminal of the first inductor, the second terminal of the first inductor is connected to the first terminal of the second inductor, the first terminal of the first capacitor is connected to the second terminal of the first inductor, the second terminal of the first capacitor is grounded, the second terminal of the second inductor serves as the output terminal of the adjustable output matching circuit, the first terminal of the second capacitor is connected to the second terminal of the second inductor, the second terminal of the second capacitor is connected to the control terminal of the first switch, and the output terminal of the first switch is grounded; The load mismatch detection circuit includes an amplitude detection unit and a phase detection unit; the first input terminal of the amplitude detection unit and the first input terminal of the phase detection unit are connected and together serve as the first input terminal of the load mismatch detection circuit; the second input terminal of the amplitude detection unit and the second input terminal of the phase detection unit are connected and together serve as the second input terminal of the load mismatch detection circuit; the output terminal of the amplitude detection unit and the output terminal of the phase detection unit are connected and together serve as the output terminal of the load mismatch detection circuit; the amplitude detection unit is used to detect the amplitude of the load impedance of the power amplifier, and the phase detection unit is used to detect the phase of the load impedance of the power amplifier; The amplitude detection unit includes a first adjustable attenuation network, a second adjustable attenuation network, a first power detection circuit, a second power detection circuit, and a first voltage conversion circuit. The input terminal of the first adjustable attenuation network serves as the first input terminal of the amplitude detection unit, and the input terminal of the second adjustable attenuation network serves as the second input terminal of the amplitude detection unit. The output terminal of the first adjustable attenuation network is connected to the input terminal of the first power detection circuit, and the output terminal of the second adjustable attenuation network is connected to the input terminal of the second power detection circuit. The output terminal of the first power detection circuit is connected to the first input terminal of the first voltage conversion circuit, and the output terminal of the second power detection circuit is connected to the second input terminal of the first voltage conversion circuit. The output terminal of the first voltage conversion circuit serves as the output terminal of the amplitude detection unit. The phase detection unit includes a third adjustable attenuation network, a fourth adjustable attenuation network, a third power detection circuit, a fourth power detection circuit, and a second voltage conversion circuit. The input terminal of the third adjustable attenuation network serves as the first input terminal of the phase detection unit, and the input terminal of the fourth adjustable attenuation network serves as the second input terminal of the phase detection unit. The output terminal of the third adjustable attenuation network is connected to the input terminal of the third power detection circuit, and the output terminal of the fourth adjustable attenuation network is connected to the input terminal of the fourth power detection circuit. The output terminal of the third power detection circuit is connected to the first input terminal of the second voltage conversion circuit, and the output terminal of the fourth power detection circuit is connected to the second input terminal of the second voltage conversion circuit. The output terminal of the second voltage conversion circuit serves as the output terminal of the phase detection unit.

2. The load impedance adjustment circuit as described in claim 1, characterized in that, The first power detection circuit, the second power detection circuit, the third power detection circuit, and the fourth power detection circuit have the same circuit structure; the first power detection circuit includes a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first transistor, a second transistor, and a third transistor; The first terminal of the third capacitor serves as the input terminal of the first power detection circuit. The second terminal of the third capacitor is connected to the first terminal of the first resistor, the first terminal of the second resistor, and the collector of the first transistor. The second terminal of the first resistor is connected to a first external power supply voltage. The second terminal of the second resistor and the base of the first transistor are connected to the first terminal of the third resistor. The emitter of the first transistor is grounded. The second terminal of the third resistor is connected to the base of the second transistor. The first terminal of the fourth capacitor is connected to the second terminal of the third resistor. The second terminal of the fourth capacitor is grounded. The emitter of the second transistor is grounded. The collector of the second transistor is connected to the first terminal of the fourth resistor and the base of the third transistor. The second terminal of the fourth resistor is connected to a first external power supply voltage. The collector of the third transistor is connected to a second external power supply voltage. The emitter of the third transistor serves as the output terminal of the first power detection circuit. The first terminal of the fifth resistor and the first terminal of the fifth capacitor are connected to the emitter of the third transistor. The second terminal of the fifth resistor and the second terminal of the fifth capacitor are connected to each other and then grounded.

3. The load impedance adjustment circuit as described in claim 1, characterized in that, The first voltage conversion circuit includes a first voltage-to-current circuit, a second voltage-to-current circuit, a first amplifier circuit, and a first current comparison circuit; The input terminal of the first voltage-to-current circuit serves as the first input terminal of the first voltage conversion circuit. The first output terminal of the first voltage-to-current circuit is connected to the first input terminal of the first current comparison circuit, and the second output terminal of the first voltage-to-current circuit is connected to the second input terminal of the first current comparison circuit. The input terminal of the second voltage-to-current circuit serves as the second input terminal of the first voltage conversion circuit. The first output terminal of the second voltage-to-current circuit is connected to the first input terminal of the first amplifier circuit, and the second output terminal of the second voltage-to-current circuit is connected to the second input terminal of the first amplifier circuit. The output terminal of the first amplifier circuit is connected to the third input terminal of the first current comparison circuit. The output terminal of the first current comparison circuit serves as the output terminal of the first voltage conversion circuit. The first voltage-to-current conversion circuit includes a first operational amplifier, a first MOSFET, and a sixth resistor. The negative input terminal of the first operational amplifier serves as the input terminal of the first voltage-to-current conversion circuit. The positive input terminal of the first operational amplifier is connected to the drain of the first MOSFET and the first terminal of the sixth resistor. The second terminal of the sixth resistor is grounded. The output terminal of the first operational amplifier is connected to the gate of the first MOSFET and serves as the first output terminal of the first voltage-to-current conversion circuit. The source of the first MOSFET is used to connect to a second external power supply voltage and serves as the second output terminal of the first voltage-to-current conversion circuit. The second voltage-to-current conversion circuit includes a second operational amplifier, a second MOSFET, and a seventh resistor. The negative input terminal of the second operational amplifier serves as the input terminal of the second voltage-to-current conversion circuit. The positive input terminal of the second operational amplifier is connected to the drain of the second MOSFET and the first terminal of the seventh resistor. The second terminal of the seventh resistor is connected to the gate of the second operational amplifier. The output terminal of the second operational amplifier is connected to the gate of the second MOSFET and serves as the first output terminal of the second voltage-to-current conversion circuit. The source of the second MOSFET is used to connect to a second external power supply voltage and serves as the second output terminal of the second voltage-to-current conversion circuit. The first amplifier circuit includes a third MOS transistor and a fourth MOS transistor; the gate of the third MOS transistor serves as the first input terminal of the first amplifier circuit, the source of the third MOS transistor serves as the second input terminal of the first amplifier circuit, the source of the third MOS transistor is used to connect to a second external power supply voltage, the drain of the third MOS transistor is connected to the drain of the fourth MOS transistor and the gate of the fourth MOS transistor respectively, the source of the fourth MOS transistor is grounded, and the gate of the fourth MOS transistor serves as the output terminal of the first amplifier circuit. The first current comparison circuit includes a fifth MOSFET, a sixth MOSFET, a first inverter, and a second inverter; The gate of the fifth MOS transistor serves as the first input terminal of the first current comparator circuit, the source of the fifth MOS transistor serves as the second input terminal of the first current comparator circuit, the source of the fifth MOS transistor is used to connect to the second external power supply voltage, and the drain of the fifth MOS transistor is connected to the input terminal of the first inverter; the gate of the sixth MOS transistor serves as the third input terminal of the first current comparator circuit, the source of the sixth MOS transistor is grounded, the drain of the sixth MOS transistor is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the first current comparator circuit.

4. The load impedance adjustment circuit as described in claim 1, characterized in that, The second voltage conversion circuit includes a third voltage-to-current circuit, a fourth voltage-to-current circuit, a second amplifier circuit, a current subtraction circuit, and a second current comparison circuit; The input terminal of the third voltage-to-current circuit serves as the first input terminal of the second voltage conversion circuit. The first output terminal of the third voltage-to-current circuit is connected to the first input terminal of the current subtraction circuit, and the second output terminal of the third voltage-to-current circuit is connected to the second input terminal of the current subtraction circuit. The input terminal of the fourth voltage-to-current circuit serves as the second input terminal of the second voltage conversion circuit. The first output terminal of the fourth voltage-to-current circuit is connected to the first input terminal of the second amplifier circuit, and the second output terminal of the fourth voltage-to-current circuit is connected to the second input terminal of the second amplifier circuit. The output terminal of the second amplifier circuit is connected to the third input terminal of the current subtraction circuit, and the output terminal of the current subtraction circuit is connected to the input terminal of the second current comparator circuit. The output terminal of the second current comparator circuit serves as the output terminal of the second voltage conversion circuit. The third voltage-to-current conversion circuit includes a third operational amplifier, a seventh MOS transistor, and an eighth resistor. The negative input terminal of the third operational amplifier serves as the input terminal of the third voltage-to-current conversion circuit. The positive input terminal of the third operational amplifier is connected to the drain of the seventh MOS transistor and the first terminal of the eighth resistor. The second terminal of the eighth resistor is grounded. The output terminal of the third operational amplifier is connected to the gate of the seventh MOS transistor, serving as the first output terminal of the third voltage-to-current conversion circuit. The source of the seventh MOS transistor serves as the second output terminal of the third voltage-to-current conversion circuit, and the source of the seventh MOS transistor is used to connect to a second external power supply voltage. The fourth voltage-to-current conversion circuit includes a fourth operational amplifier, an eighth MOS transistor, and a ninth resistor. The negative input terminal of the fourth operational amplifier serves as the input terminal of the fourth voltage-to-current conversion circuit. The positive input terminal of the fourth operational amplifier is connected to the drain of the eighth MOS transistor and the first terminal of the ninth resistor. The second terminal of the ninth resistor is grounded. The output terminal of the fourth operational amplifier is connected to the gate of the eighth MOS transistor, serving as the first output terminal of the fourth voltage-to-current conversion circuit. The source of the eighth MOS transistor serves as the second output terminal of the fourth voltage-to-current conversion circuit. The source of the eighth MOS transistor is used to connect to a second external power supply voltage. The second amplifier circuit includes a ninth MOS transistor and a tenth MOS transistor; the gate of the ninth MOS transistor serves as the first input terminal of the second amplifier circuit, the source of the ninth MOS transistor serves as the second input terminal of the second amplifier circuit, the source of the ninth MOS transistor is used to connect to a second external power supply voltage, the drain of the ninth MOS transistor is connected to the drain of the tenth MOS transistor and the gate of the tenth MOS transistor respectively, the source of the tenth MOS transistor is grounded, and the gate of the tenth MOS transistor serves as the output terminal of the second amplifier circuit. The current subtraction circuit includes an eleventh MOSFET, a twelfth MOSFET, and a thirteenth MOSFET. The gate of the eleventh MOSFET serves as the first input terminal of the current subtraction circuit, and the source of the eleventh MOSFET serves as the second input terminal of the current subtraction circuit. The source of the eleventh MOSFET is connected to a second external power supply voltage, and the drain of the eleventh MOSFET is connected to the drain of the twelfth MOSFET. The gate of the twelfth MOSFET serves as the third input terminal of the current subtraction circuit, and the source of the twelfth MOSFET is grounded. The drain of the twelfth MOSFET is connected to both the drain and the gate of the thirteenth MOSFET, and the source of the thirteenth MOSFET is grounded. The gate of the thirteenth MOSFET serves as the output terminal of the current subtraction circuit. The second current comparator circuit includes a current source, a fourteenth MOSFET, a third inverter, and a fourth inverter. The input terminal of the current source is connected to a second external power supply voltage, and the output terminal of the current source is connected to the input terminal of the third inverter. The gate of the fourteenth MOSFET serves as the input terminal of the second current comparator circuit, the source of the fourteenth MOSFET is grounded, the drain of the fourteenth MOSFET is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter serves as the output terminal of the second current comparator circuit.

5. The load impedance adjustment circuit as described in claim 1, characterized in that, Define the coupling terminal voltage as Vcpl, the isolation terminal voltage as Viso, and the reflection coefficient as ΓL. Calculate the reflection coefficient by combining the coupling terminal voltage and the isolation terminal voltage according to the following rules: ΓL 。 6. The load impedance adjustment circuit as described in claim 1, characterized in that, The preset linearity range is less than -33dBc.

7. The load impedance adjustment circuit as described in claim 1, characterized in that, The back-end component is a filter device.

8. A radio frequency chip, characterized in that, The radio frequency chip includes the load impedance adjustment circuit as described in any one of claims 1-7.

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