Electric fuse state reading circuit, electronic equipment and electronic chip

Abstract

The embodiment of the invention provides an electric fuse state reading circuit, a chip and equipment, and the circuit comprises the steps: generating a first control signal to a first switch module according to a clock signal, so as to control the conduction time sequence of each switch unit of the first switch module, and generating a second control signal to a second switch module, so as to control the conduction mode of the second switch module, a first control signal is generated to the first switch module to change the switch unit electrically connected with the first resistor unit, and a third control signal is generated to the third switch module to control the conduction mode of the third switch module so as to change the first voltage output by the switch unit and received by the comparison module; the comparison module receives a first voltage of a first node group of a target switch unit and a second voltage of a second node when the target switch unit is in a conducting state, and outputs a level signal according to the first voltage and the second voltage. A serial-parallel combined reading mode is adopted, and the reading power consumption is flexibly designed according to the number of electric fuses included in an actual circuit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits and related technical fields, and in particular, to an electric fuse state reading circuit, an electronic device, and an electronic chip. Background Art

[0002] Electrical fuses or electrically programmable fuses (efuse) are widely used in the adjustment of integrated circuit functions and electrical characteristics. For example, after the chip is manufactured and packaged, it is tested. Due to circuit imbalance or process deviation, some parameters may deviate from the design range. At this time, the key parameters of the chip can be adjusted by the electrical fuse to reach the target value. Or after the packaging is completed, some functions need to be enabled or disabled according to the actual situation. The electrical fuse can also be used for regulation. The electrical fuse can greatly improve the parameter accuracy and design flexibility of the chip. When the key parameters of the chip are adjusted by the electrical fuse, the instantaneous large current source will pass through the fuse resistor and generate heat to melt it. Generally, the resistance value before the fuse is blown is very low, and the resistance value after the fuse is blown is very high. When the chip is powered on, the state of the fuse will be read, that is, the resistance value of the fuse will be detected. The low resistance state before the fuse is blown is used as logic 0, and the high resistance state after the fuse is blown is used as logic 1, so as to achieve the purpose of adjustment.

[0003] However, in the prior art, the electric fuse status reading circuit generally adopts two reading methods, one is to read the status of each electric fuse bit by bit, and the other is to read the status of all electric fuses at the same time. Among them, in the method of reading the status of each electric fuse bit by bit: the requirements for the timing control circuit are relatively high, and the timing control circuit is usually more complicated. In addition, since the process of reading the status of each electric fuse is performed serially, one bit must be read before the next bit can be read. The time required for the entire reading process is the sum of the time required to read the status of each electric fuse, especially when the number of fuse bits is large, so the entire electric fuse status reading process takes a long time, which will affect the startup speed of the circuit. In the method of reading the status of all electric fuses at the same time: all fuse branches start to work, and the working current of the reading circuit module is the sum of the currents of all branches, and the more fuse bits, the greater the current, and the power supply VDD of the fuse status reading circuit requires a low-voltage power supply. When the fuse status is read at the same time when power is turned on, the larger reading current will pull the power supply voltage VDD to a very low level, thereby causing errors in other modules of the circuit. Summary of the invention

[0004] The embodiments described herein provide an electric fuse status reading circuit, an electronic device, and an electronic chip, which adopt a serial-parallel combined reading method and can flexibly design the reading time and reading power consumption according to the number of electric fuses included in the actual circuit.

[0005] In a first aspect, according to the present disclosure, there is provided an electric fuse state reading circuit, comprising:

[0006] N groups of electric fuse arrays;

[0007] a first switch module, wherein the first switch module comprises N groups of switch units and a main control switch, wherein the Nth group of switch units is arranged correspondingly to the Nth group of electric fuse arrays, the Nth group of switch units and the Nth group of electric fuse arrays are connected in series between the power supply voltage node and the Nth group of first node groups, and the number of first nodes included in each group of first node groups is the same as the number of electric fuses included in each group of electric fuse arrays;

[0008] a second switch module, wherein a first end of the second switch module is electrically connected to first node groups of different groups respectively, and a second end of the second switch module is electrically connected to a first end of the first resistor unit;

[0009] a resistance module, the resistance module comprising a first resistance unit, a second resistance and a third resistance, the second end of the first resistance unit being electrically connected to a ground node, the second resistance being connected in series between the second node and the ground node, the third resistance and the main control switch being connected in series between a power supply voltage node and a second node, the first resistance unit comprising a first resistance and a second resistance having the same resistance value, and the third resistance having a resistance value between the resistance before the electric fuse is blown and the resistance after the electric fuse is blown;

[0010] a main control module, configured to generate a first control signal to the first switch module according to a clock signal to control the conduction timing of each switch unit included in the first switch module, and generate a second control signal to the second switch module to control the conduction mode of the second switch module, thereby changing the switch unit electrically connected to the first resistor unit, and generate a third control signal to the third switch module to control the conduction mode of the third switch module, thereby changing the first voltage output by the switch unit received by the comparison module;

[0011] The comparison module is configured to receive a first voltage of a first node group of the target switch unit and a second voltage of a second node when the target switch unit is in an on state, and output a level signal according to the first voltage and the second voltage.

[0012] In some embodiments of the present disclosure, the resistance values ​​of the first resistor and the second resistor are greater than the resistance value of the third resistor.

[0013] In some embodiments of the present disclosure, each group of the electric fuse array includes M electric fuses, each group of the switch units includes M first switches, the second switch module includes M second switches, the third switch module includes M third switches, the first resistor unit includes M first resistors, the first end of the electric fuse is electrically connected to the power supply voltage node, the second end of the electric fuse is electrically connected to the first end of the first switch, the second end of the first switch is electrically connected to the first node, the first end of the second switch is electrically connected to the first node, the second end of the second switch is electrically connected to the first end of the first resistor, the second end of the first resistor is electrically connected to the ground node, the first end of the third switch is electrically connected to the first node, and the second end of the third switch is electrically connected to the comparison module.

[0014] In some embodiments of the present disclosure, the comparison module includes M comparison units, the first end of the first comparison unit receives the first voltage of the first node connected to the first first switch included in the target switch unit, and the second end of each comparison unit receives the second voltage of the second node.

[0015] In some embodiments of the present disclosure, a latch module is also included;

[0016] The latch module is configured to receive the level signal output by the comparison module and store the level signal output by the connected comparison module.

[0017] In some embodiments of the present disclosure, the latch module includes M latch units.

[0018] In some embodiments of the present disclosure, a fourth switch module is further included;

[0019] The main control module is further configured to generate a fourth control signal to the fourth switch module according to the clock signal, so as to control the conduction state of the fourth switch module;

[0020] The fourth switch module is configured to determine a conduction state according to a received fourth control signal.

[0021] In some embodiments of the present disclosure, a turn-on time of the fourth switch module is after a turn-on time of the target switch unit, and a turn-off time of the fourth switch module is before a turn-off time of the target switch unit.

[0022] In a second aspect, according to the content of the present disclosure, an electronic device is provided, comprising the electric fuse state reading circuit as described in any one of the first aspect.

[0023] In a second aspect, according to the contents of the present disclosure, an electronic chip is provided, comprising the electronic device described in the second aspect.

[0024] In the electric fuse state reading circuit, electronic device and electronic chip provided by the embodiments of the present disclosure, in the process of reading the electric fuse state, the main control module generates a first control signal to the first switch module according to the clock signal, so that each group of switch units included in the first switch module is turned on according to the clock signal, and generates a second control signal to the second switch module according to the clock signal, so that in different clock signal cycles, the second switch module is turned on in different ways, thereby realizing that in different clock signal cycles, each switch unit is sequentially connected to the first resistor unit, and generates a third control signal to the third switch module according to the clock signal, so that in different clock signal cycles, the second switch module is turned on in different ways. cycle, the third switch module is turned on in different ways, so that in different clock signal cycles, the comparison module receives the first voltage of the first node group corresponding to different electric fuse arrays in sequence, and then determines the state of the electric fuses included in each group of electric fuse arrays by comparing the first voltage of the first node group corresponding to different electric fuse arrays with the second voltage of the second node. Compared with the prior art of reading the state of each electric fuse bit by bit or reading the state of all electric fuses at the same time, the electric fuse state reading circuit provided in the present application adopts a serial-parallel combination reading method, which can flexibly design the reading time and reading power consumption according to the number of electric fuses included in the actual circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0026] Figure 1 is a structural schematic diagram of an electric fuse state reading circuit provided by an embodiment of the present disclosure;

[0027] Figure 2 is a structural schematic diagram of another electric fuse state reading circuit provided by an embodiment of the present disclosure;

[0028] Figure 3 It is a structural schematic diagram of another electric fuse state reading circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0031] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0032] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0033] Based on the problems existing in the prior art, the present disclosure provides an electric fuse state reading circuit. Figure 1 is a schematic diagram of the structure of an electric fuse state reading circuit provided by an embodiment of the present disclosure, such as Figure 1As shown, the electric fuse state reading circuit includes: N groups of electric fuse arrays 10; a first switch module 20, the first switch module 20 includes N groups of switch units (21, ..., 2N) and a main control switch 22, the Nth group of switch units 2N is correspondingly arranged with the Nth group of electric fuse arrays 1N, the Nth group of switch units 2N and the Nth group of electric fuse arrays 1N are connected in series between the power supply voltage node and the Nth group of first node groups (AN1, ..., ANM), and the number of first nodes included in each group of first node groups is the same as the number of electric fuses included in each group of electric fuse arrays; a second switch module 30, the first end of the second switch module 30 is electrically connected to the first node groups of different groups respectively, and the second end of the second switch module 30 is electrically connected to the first end of the first resistor unit; a resistor module 40, the resistor module 40 includes a first resistor unit 41, a second resistor R2 and a third resistor R3, the second end of the first resistor unit 41 is electrically connected to the ground node, the second resistor R3 is connected in series between the second node A2 and the ground node, and the third resistor R4 is connected in series between the second node A2 and the ground node. The resistor and the main control switch 200 are connected in series between the power supply voltage node and the second node A2, the first resistor R1 and the second resistor R2 have the same resistance value, and the resistance value of the third resistor R3 is between the resistance before the electric fuse is blown and the resistance after the fuse is blown; the main control module 50 is configured to generate a first control signal to the first switch module 20 according to the clock signal to control the conduction timing of each switch unit included in the first switch module 20, and generate a second control signal to the second switch module 30 to control the conduction mode of the second switch module 30, thereby changing the switch unit electrically connected to the first resistor unit 41, and generate a third control signal to the third switch module 60 to control the conduction mode of the third switch module 60, thereby changing the first voltage output by the switch unit received by the comparison module 70; the comparison module 70 is configured to receive the first voltage of the first node group of the target switch unit when the target switch unit is in the on state, and receive the second voltage of the second node, and output a level signal according to the first voltage and the second voltage.

[0034] Specific, combined Figure 1In the embodiment of the present disclosure, the electric fuse array is divided into N groups of electric fuse arrays, and one group of electric fuse arrays corresponds to a group of switch units. For example, the electric fuse array includes a first group of electric fuse arrays 11, a second group of electric fuse arrays 12, ..., and an Nth group of electric fuse arrays 1N. The first switch module 20 includes a first group of switch units 21, a second group of switch units 22, ..., an Nth group of switch units 2N and a main control switch 200. The first group of electric fuse arrays 11 and the first group of switch units 21 are connected in series between the power supply voltage node and the first node of the first group. The first end of the main control switch 200 is connected to the third resistor R3, and the second end of the main control switch 200 is electrically connected to the second resistor R2 and the second node A2, respectively.

[0035] It should be noted that the number of first nodes included in each first node group is the same as the number of electrical fuses included in each electrical fuse array.

[0036] The main control module 50 receives the clock signal, and at the first rising edge of the clock signal, generates a first control signal to the first group of switch units 21 to control the first group of switch units 21 to be turned on, generates a second control signal to the second switch module 30 to control the second switch module 30 to be turned on in a first manner, so that the first resistor unit 41 is electrically connected to the first group of switch units 21 through the second switch module 30 (that is, the first resistor unit 41 is electrically connected to the first group of first node groups (A11, ..., A1M) through the second switch module 30), generates a third control signal to the third switch module 60 to control the third switch module 60 to be turned on in a first manner, so that the comparison module 70 receives the first voltage output by the first group of first node groups (A11, ..., A1M), generates a first control signal to the second group of switch units 22 to control the second group of switch units 22 to be turned on, generates a second control signal to the second switch module 30 to control the second switch module 30 to be turned on in a second manner, so that the first resistor unit 41 is electrically connected to the second group of switch units 22 through the second switch module 30. The first resistor unit 41 is electrically connected to the second group of first node groups (A21, ..., A2M) through the second switch module 30), generates a third control signal to the third switch module 60, controls the third switch module 60 to be turned on in the second mode, so that the comparison module 70 receives the first voltage output by the second group of first node groups (A21, ..., A2M), ..., generates a first control signal to the Nth group of switch units 2N at the Nth rising edge of the clock signal, controls the Nth group of switch units 2N to be turned on, and generates a second control signal To the second switch module 30, control the second switch module 30 to be turned on in the Nth manner, so that the first resistance unit 41 is electrically connected to the Nth group of switch units 2N through the second switch module 30 (that is, the first resistance unit 41 is electrically connected to the Nth group of first node groups (AN1, ..., ANM) through the second switch module 30), generate a third control signal to the third switch module 60, control the third switch module 60 to be turned on in the Nth manner, so that the comparison module 70 receives the first voltage output by the Nth group of first node groups (AN1, ..., ANM).

[0037] The comparison module receives the first voltage of the Nth group of first nodes when the Nth group of switch units is turned on, and receives the second voltage of the second node, and outputs a level signal by comparing the first voltage of the Nth group of first nodes with the second voltage of the second node.

[0038] It should be noted that in the above embodiment, after receiving the clock signal, the main control module controls the main control switch to be in the on state all the time.

[0039] also, Figure 1exemplarily indicates that the second switch module is electrically connected to the first node group of the first group, and the second switch module is electrically connected to the second node group of the second group, that is, at the first rising edge of the clock signal, the specific connection mode of the electric fuse state reading circuit, Figure 2 It is exemplified that the second switch module is electrically connected to the first node group of the Nth group, and the second switch module is electrically connected to the first node group of the Nth group, that is, at the Nth rising edge of the clock signal, the specific connection method of the electric fuse state reading circuit is not specifically illustrated in the embodiments of the present disclosure.

[0040] In the electric fuse state reading circuit provided by the embodiment of the present disclosure, during the process of reading the electric fuse state, the main control module generates a first control signal to the first switch module according to the clock signal, so that each group of switch units included in the first switch module is turned on according to the clock signal, and generates a second control signal to the second switch module according to the clock signal, so that in different clock signal cycles, the second switch module is turned on in different ways, thereby realizing that in different clock signal cycles, each switch unit is sequentially connected to the first resistor unit, and generates a third control signal to the third switch module according to the clock signal, so that in different clock signal cycles, the third switch module is turned on in different ways. The switch module is turned on in different ways, so that in different clock signal cycles, the comparison module receives the first voltage of the first node group corresponding to different electric fuse arrays in turn, and then determines the state of the electric fuses included in each group of electric fuse arrays by comparing the first voltage of the first node group corresponding to different electric fuse arrays with the second voltage of the second node. Compared with the prior art of reading the state of each electric fuse bit by bit or reading the state of all electric fuses at the same time, the electric fuse state reading circuit provided in the present application adopts a serial-parallel combination reading method, which can flexibly design the reading time and reading power consumption according to the number of electric fuses included in the actual circuit.

[0041] On the basis of the above embodiments, a specific implementation method is provided, where each group of electric fuse arrays includes M electric fuses, each group of switch units includes M first switches, the second switch module includes M second switches, the third switch module includes M third switches, the first resistor unit includes M first resistors, the first end of the electric fuse is electrically connected to the power supply voltage node, the second end of the electric fuse is electrically connected to the first end of the first switch, the second end of the first switch is electrically connected to the first node, the first end of the second switch is electrically connected to the first node, the second end of the second switch is electrically connected to the first end of the first resistor, the second end of the first resistor is electrically connected to the ground node, the first end of the third switch is electrically connected to the first node, and the second end of the third switch is electrically connected to the comparison module.

[0042] The comparison module includes M comparison units, a first end of a first comparison unit receives a first voltage of a first node connected to a first first switch included in the target switch unit, and a second end of each comparison unit receives a second voltage of a second node.

[0043] Combination Figure 1 , each group of electric fuse arrays includes M electric fuses, each group of switch units includes M first switches, the comparison module includes M comparison units, the second switch module includes M second switches, the third switch module includes M third switches, the main control module generates a first control signal to the first switch module at the first rising edge of the clock signal, the first group of switch units included in the first switch module is turned on, that is, the M first switches of the first group of switch units are turned on, the first group of electric fuse arrays is electrically connected to the first group of first node groups through the first group of switch units, specifically, the first electric fuse of the first group of electric fuse arrays is electrically connected to the first first node of the first group of first node groups through the first first switch of the first group of switch units, ..., the Mth electric fuse of the first group of electric fuse arrays is electrically connected to the Mth first node of the first group of first node groups through the Mth first switch of the first group of switch units; the main control module generates a second control signal to the second switch module block, the M second switches included in the second switch module are turned on in the first manner, that is, the first resistor unit is electrically connected to the first group of first node groups through the M second switches included in the second switch module, specifically, the first first resistor is electrically connected to the first first node of the first group of first node groups through the first second switch, ..., the Mth first resistor is electrically connected to the Mth first node of the first group of first node groups through the Mth second switch; the main control module generates a third control signal to the third switch module, and the M third switches included in the third switch module are turned on in the first manner, that is, the comparison unit is electrically connected to the first group of first node groups through the M third switches included in the third switch module, specifically, the first comparison unit is electrically connected to the first first node of the first group of first node groups through the first third switch, ..., the Mth comparison unit is electrically connected to the Mth first node of the first group of first node groups through the Mth third switch.

[0044] By analogy, the main control module generates a first control signal to the first switch module at the Nth rising edge of the clock signal, and the Nth group of switch units included in the first switch module is turned on, that is, the M first switches of the Nth group of switch units are turned on, and the Nth group of electric fuse arrays are electrically connected to the Nth group of first node groups through the Nth group of switch units. Specifically, the first electric fuse of the Nth group of electric fuse arrays is electrically connected to the first first node of the Nth group of first node groups through the first first switch of the Nth group of switch units, ..., the Mth electric fuse of the Nth group of electric fuse arrays is electrically connected to the Mth first node of the Nth group of first node groups through the Mth first switch of the Nth group of switch units; the main control module generates a second control signal to the second switch module, and the M second switches included in the second switch module are turned on in the Nth way, that is, the first resistor unit is turned on. The comparison unit is electrically connected to the Nth group of first nodes through the M second switches included in the second switch module. Specifically, the first first resistor is electrically connected to the first first node of the Nth group of first nodes through the first second switch, ..., the Mth first resistor is electrically connected to the Mth first node of the Nth group of first nodes through the Mth second switch; the main control module generates a third control signal to the third switch module, and the M third switches included in the third switch module are turned on in the Nth way, that is, the comparison unit is electrically connected to the Nth group of first nodes through the M third switches included in the third switch module. Specifically, the first comparison unit is electrically connected to the first first node of the Nth group of first nodes through the first third switch, ..., the Mth comparison unit is electrically connected to the Mth first node of the Nth group of first nodes through the Mth third switch.

[0045] In a specific exemplary embodiment, at the first rising edge of the clock signal, the first electric fuse of the first group of electric fuse arrays is electrically connected to the first first node of the first group of first node groups through the first first switch of the first group of switch units, ..., the Mth electric fuse of the first group of electric fuse arrays is electrically connected to the Mth first node of the first group of first node groups through the Mth first switch of the first group of switch units, the first first resistor is electrically connected to the first first node of the first group of first node groups through the first second switch, ..., the Mth first resistor is electrically connected to the Mth first node of the first group of first node groups through the Mth second switch, the first comparison unit is electrically connected to the first first node of the first group of first node groups through the first third switch, ..., the Mth comparison unit is electrically connected to the Mth first node of the first group of first node groups through the Mth third switch. The first comparison unit receives a first voltage of a first first node and a second voltage of a second node of a first group of electric fuse arrays, the second comparison unit receives a first voltage of a second first node and a second voltage of a second node of the first group of electric fuse arrays, ..., the Mth comparison unit receives a first voltage of an Mth first node and a second voltage of a second node of the first group of electric fuse arrays, and each comparison unit determines the state of the electric fuse by comparing the first voltage and the second voltage.

[0046] Based on the above embodiments, continue to refer to Figure 1 The electric fuse state reading circuit also includes a latch module, which is configured to receive the level signal output by the comparison module and store the level signal output by the connected comparison module.

[0047] The latch module includes M latch units.

[0048] In addition, the electric fuse state reading circuit is also provided to include a latch module, which latches the level signals output by the comparison module in the clock cycles corresponding to different clock signals, and then determines the state of each group of electric fuse arrays according to the level signals output by the comparison module in the clock cycles corresponding to the different clock signals latched by the latch module.

[0049] Specifically, taking the first voltage of the first first node of the first group of first node groups received by the first comparison unit as an example, the first voltage of the first first node of the first group of first node groups received by the first comparison unit satisfies:

[0050]

[0051] The second voltage of the second node received by the first comparison unit satisfies:

[0052]

[0053] Since the first resistor and the second resistor have the same resistance value, the difference between the first voltage and the second voltage satisfies:

[0054]

[0055] If the electric fuse is not blown, the resistance of the electric fuse r11 is small, r11<R3, then V1>V2, so the first comparison unit outputs a low level. If the electric fuse is blown, the resistance of the electric fuse r11 is large, r11>R2, then V1<V2, and the first comparison unit outputs a high level.

[0056] In a specific implementation, the resistance value of the first resistor and the resistance value of the second resistor are much greater than the resistance value of the third resistor.

[0057] By setting the resistance of the first resistor and the resistance of the second resistor to be much greater than the resistance of the third resistor, the first voltage output to the comparison module changes greatly before and after the electric fuse is blown.

[0058] In a specific embodiment, the resistance of the electric fuse before it is blown is generally 100 ohms, and the resistance of the electric fuse after it is blown is generally 10 kilo-ohms. The resistance of the third resistor is between the resistance before the melting point of the electric fuse and the resistance after the melting point. The resistance of the third resistor is generally set to 3 kilo-ohms. When the power supply voltage is 5V, the current flowing through the branch where the second resistor and the third resistor are located is generally 100 mA. At this time, the resistance of the second resistor is 47 kilo-ohms, that is, the second resistor is much larger than the resistance of the third resistor. In order to realize the judgment of the state of the electric fuse, it can be known from the above formula that when the resistance of the first resistor and the second resistor are set to be the same, the state of the electric fuse can be determined only by comparing the resistance of the third resistor and the electric fuse. Therefore, the resistance of the first resistor is the same as the resistance of the second resistor, and the resistance of the first resistor and the resistance of the second resistor are much larger than the resistance of the third resistor.

[0059] The electric fuse state reading circuit provided by the embodiment of the present disclosure can realize the judgment of the electric fuse state without using a current mirror circuit to provide bias current for each electric fuse branch, that is, by setting the appropriate resistance values ​​of the first resistor, the second resistor and the third resistor, the comparison module determines the state of the electric fuse by comparing the first voltage of the first node and the second voltage of the second node. Compared with the current mirror circuit used in the prior art, when the transistor of the current mirror circuit has a low precision of the current flowing into the comparison module due to non-ideal factors such as process deviation, substrate bias effect or transistor working in the linear region, it will affect the accuracy of the comparison module in judging the state of the electric fuse. In addition, when the resistance of the electric fuse after the fuse is particularly close to the reference resistance (that is, the third resistance), it may output an erroneous result, especially when the power supply voltage is low during reading, and the current of each branch will also be very small, which will make this problem more serious.

[0060] The electric fuse state reading circuit provided by the embodiment of the present disclosure includes a first resistance unit, a second resistor and a third resistor by setting a resistance module, and a comparison module compares a first voltage output by a first node and a second voltage output by a second node, wherein the first voltage of the first node is related to the resistance value of the electric fuse, and the second voltage of the second node is related to the resistance value of the third resistor. Since the voltage compared by the comparison module is a voltage division of a high-precision resistor, it is less affected by process deviation and MOS working area. Moreover, as can be seen from the formula, the output of the comparison module mainly depends on the size relationship between the third resistor and the resistance value of the electric fuse, and the resistance value of the third resistor can be configured according to the resistance value of the electric fuse. Usually, the difference between the resistance value of the configured third resistor and the resistance before and after the electric fuse is blown is more obvious, so that the comparison result of this circuit has higher reliability.

[0061] Based on the above embodiments, Figure 3 is a structural diagram of another electric fuse state reading circuit provided by an embodiment of the present disclosure, such as Figure 3 As shown, the electric fuse state reading circuit also includes a fourth switch module 90, and the main control module 50 is also configured to generate a fourth control signal to the fourth switch module according to the clock signal to control the conduction state of the fourth switch module; the fourth switch module 90 is configured to determine the conduction state according to the received fourth control signal.

[0062] The turn-on time of the fourth switch module is after the turn-on time of the target switch unit, and the turn-off time of the fourth switch module is before the turn-off time of the target switch unit.

[0063] Specifically, by setting the turn-on time of the fourth switch module to be after the turn-on time of the target switch unit, and the turn-off time of the fourth switch module to be before the turn-off time of the target switch unit, that is, delaying a certain time after the first switch module, the second switch module and the third switch module are turned on, and then controlling the fourth switch module to be turned on, after the fourth switch module is turned on, the latch module starts to read the level signal output by the comparison module, and after the latch module finishes reading the level signal output by the comparison module, it delays for a period of time before turning off the first switch module, the second switch module and the third switch module, thereby improving the reliability of the latch module reading.

[0064] The embodiment of the present disclosure further provides an electronic chip, which includes the current comparison circuit for off-chip resistance identification provided by the embodiment of the present disclosure.

[0065] The embodiments of the present disclosure also provide an electronic device. The electronic device includes an electronic chip according to the embodiments of the present disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer, a smart phone, etc.

[0066] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0067] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0068] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0069] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An electric fuse state reading circuit, characterized in that: include: N groups of electric fuse arrays; a first switch module, wherein the first switch module comprises N groups of switch units and a main control switch, wherein the Nth group of switch units is arranged correspondingly to the Nth group of electric fuse arrays, the Nth group of switch units and the Nth group of electric fuse arrays are connected in series between the power supply voltage node and the Nth group of first node groups, and the number of first nodes included in each group of first node groups is the same as the number of electric fuses included in each group of electric fuse arrays; a second switch module, wherein a first end of the second switch module is electrically connected to first node groups of different groups respectively, and a second end of the second switch module is electrically connected to a first end of the first resistor unit; a resistance module, the resistance module comprising a first resistance unit, a second resistance and a third resistance, the second end of the first resistance unit being electrically connected to a ground node, the second resistance being connected in series between the second node and the ground node, the third resistance and the main control switch being connected in series between a power supply voltage node and a second node, the first resistance unit comprising a first resistance and a second resistance having the same resistance value, and the third resistance having a resistance value between the resistance before the electric fuse is blown and the resistance after the electric fuse is blown; a main control module, configured to generate a first control signal to the first switch module according to a clock signal to control the conduction timing of each switch unit included in the first switch module, and generate a second control signal to the second switch module to control the conduction mode of the second switch module, thereby changing the switch unit electrically connected to the first resistor unit, and generate a third control signal to the third switch module to control the conduction mode of the third switch module, thereby changing the first voltage output by the switch unit received by the comparison module; The comparison module is configured to receive a first voltage of a first node group of the target switch unit and a second voltage of a second node when the target switch unit is in an on state, and output a level signal according to the first voltage and the second voltage.

2. The circuit according to claim 1, characterized in that The resistance values ​​of the first resistor and the second resistor are greater than the resistance value of the third resistor.

3. The circuit according to claim 1, characterized in that Each group of the electric fuse array includes M electric fuses, each group of the switch units includes M first switches, the second switch module includes M second switches, the third switch module includes M third switches, the first resistor unit includes M first resistors, the first end of the electric fuse is electrically connected to the power supply voltage node, the second end of the electric fuse is electrically connected to the first end of the first switch, the second end of the first switch is electrically connected to the first node, the first end of the second switch is electrically connected to the first node, the second end of the second switch is electrically connected to the first end of the first resistor, the second end of the first resistor is electrically connected to the ground node, the first end of the third switch is electrically connected to the first node, and the second end of the third switch is electrically connected to the comparison module.

4. The circuit according to claim 3, characterized in that The comparison module includes M comparison units, a first end of the first comparison unit receives a first voltage of a first node connected to a first first switch included in the target switch unit, and a second end of each comparison unit receives a second voltage of a second node.

5. The circuit according to claim 1, characterized in that Also includes a latch module; The latch module is configured to receive the level signal output by the comparison module and store the level signal output by the connected comparison module.

6. The circuit according to claim 5, characterized in that The latch module includes M latch units.

7. The circuit according to claim 5, characterized in that Also includes a fourth switch module; The main control module is further configured to generate a fourth control signal to the fourth switch module according to the clock signal, so as to control the conduction state of the fourth switch module; The fourth switch module is configured to determine a conduction state according to a received fourth control signal.

8. The circuit according to claim 7, characterized in that The turn-on time of the fourth switch module is after the turn-on time of the target switch unit, and the turn-off time of the fourth switch module is before the turn-off time of the target switch unit.

9. An electronic device, characterized in that: The invention comprises the electric fuse state reading circuit as claimed in any one of claims 1 to 8.

10. An electronic chip, characterized in that: An electronic device comprising the electronic device described in claim 9.

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