Drive device

Abstract

Provided is a drive device for a power semiconductor, the drive device being provided with: a first circuit; a second circuit; a state signal generation unit that generates a first state signal indicating the state of the first circuit using a digital quantity of a plurality of bits; and a communication control unit that controls an output period during which the first circuit outputs the first state signal on the basis of a load state signal indicating a transition timing of ON / OFF of the power semiconductor.

Description

Technical Field

[0001] The invention relates to a driving device. Background Art

[0002] Conventionally, there is known a configuration in which a driving device that drives a target device such as a power semiconductor outputs a state of the driving device such as the temperature of the driving device (for example, see Patent Documents 1 to 3).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-93903 Patent Document 2: Japanese Patent Application Publication No. 2009-258016 Patent Document 3: U.S. Patent No. 5,210,846 Summary of the invention

[0004] Technical issues It is preferable to perform communication between circuits in the driving device with high accuracy.

[0005] Technical Solution In order to solve the above-mentioned problems, a first embodiment of the present invention provides a driving device for a power semiconductor. The driving device may include a first circuit. Any of the driving devices may include a second circuit. Any of the driving devices may include a state signal generating unit that generates a first state signal that indicates the state of the first circuit using a digital quantity of multiple bits. Any of the driving devices may include a communication control unit that controls the output period of the first circuit outputting the first state signal based on a load state signal indicating the transition moment of the on-off of the power semiconductor.

[0006] In any of the above-described drive devices, the communication control unit may allow output of the first state signal after a predetermined stop period has elapsed from a time when the power semiconductor is switched from on to off.

[0007] In any of the above drive devices, the first circuit may output the first state signal in response to a clock signal input from the second circuit. In any of the above drive devices, the communication control unit may control an input period of the clock signal from the second circuit to the first circuit based on the load state signal.

[0008] In any of the above-described drive devices, the communication control unit may control the stop period in accordance with characteristics of the power semiconductor.

[0009] In any of the above-described drive devices, the communication control unit may control the stop period in accordance with a magnitude of a power supply voltage applied to the power semiconductor.

[0010] In any of the above-described drive devices, the communication control unit may control the stop period in accordance with a capacity of a load connected to the power semiconductor.

[0011] In any of the above-mentioned driving devices, the second circuit may control a cycle of the clock signal in accordance with a length of the output period.

[0012] In any of the above-mentioned driving devices, the first circuit may be a low-side circuit that operates according to a first reference voltage. In any of the above-mentioned driving devices, the second circuit may be a high-side circuit that operates according to a second reference voltage higher than the first reference voltage. Any of the above-mentioned driving devices may include a transmission unit that converts the reference voltage of the first state signal corresponding to the first reference voltage and transmits the first state signal obtained by converting the reference voltage to the low-side circuit.

[0013] In any of the above-mentioned driving devices, the transmission unit may include a capacitor provided between the high-side circuit and the low-side circuit.

[0014] In a second aspect of the present invention, a driving device for a power semiconductor is provided. The driving device may include a low-side circuit that operates according to a first reference voltage. Any of the driving devices may include a high-side circuit that operates according to a second reference voltage that is higher than the first reference voltage. Any of the driving devices may include a status signal generating unit that generates a high-side status signal that uses a digital quantity of multiple bits to represent the status of the high-side circuit. Any of the driving devices may include a transmission unit that converts the reference voltage of the high-side status signal to correspond to the first reference voltage, and transmits the high-side status signal obtained by converting the reference voltage to the low-side circuit.

[0015] In any of the above-mentioned driving devices, the low-side circuit may include a transmission unit that transmits the high-side state signal to the outside.

[0016] In any of the above driving devices, the low-side circuit may generate a low-side state signal indicating a state of the low-side circuit using a digital quantity. In any of the above driving devices, the transmitting unit may output the high-side state signal and the low-side state signal from a common terminal.

[0017] In any of the above driving devices, the transmission unit may include an insulating element that transmits the high-side state signal in a state where the high-side circuit and the low-side circuit are electrically insulated.

[0018] In any of the above-mentioned driving devices, the transmission unit may include a level conversion circuit that converts a signal level of the high-side state signal in accordance with the first reference voltage.

[0019] In any of the above-mentioned driving devices, the high-side state signal may have a plurality of bit times corresponding to the plurality of bits of the digital quantity, and the signal level in each bit time represents a value corresponding to the value of each bit of the digital quantity. It should be noted that the bit time is the time occupied by 1 bit of information in the digital signal.

[0020] In any of the above-mentioned driving devices, the state signal generating unit may include a pulse generating unit that generates a start pulse indicating the start time of each of the bit times and an end pulse indicating the end time of each of the bit times. In any of the above-mentioned driving devices, the state signal generating unit may include a signal synthesizing unit that generates the high-side state signal including the start pulse and the end pulse and making the signal level during the period between the start pulse and the end pulse a level corresponding to the digital amount.

[0021] In any of the above driving devices, the polarities of the start pulse and the end pulse may be inverted.

[0022] In any of the above-mentioned driving devices, the low-side circuit can extract the start time or the end time of each bit time in the high-side status signal received from the transmission part, and detect the signal level of the high-side status signal at a detection time pre-set based on the start time or the end time.

[0023] Any of the above-described drive devices may further include a communication control unit configured to control a period during which the high-side circuit outputs the high-side state signal based on a load state signal indicating a timing of transition between on and off of the power semiconductor.

[0024] In any of the above-described drive devices, the communication control unit may allow output of the high-side state signal after a predetermined period has elapsed from a time when the power semiconductor is switched from on to off.

[0025] In any of the above-mentioned driving devices, the high-side circuit may output the high-side state signal corresponding to the clock signal input from the low-side circuit. In any of the above-mentioned driving devices, the communication control unit may control the period of inputting the clock signal from the low-side circuit to the high-side circuit based on the load state signal.

[0026] The above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1This is a diagram showing an example of a power supply device 300 according to an embodiment of the present invention.

[0028] Figure 2 1 is a diagram showing an example of the insulating element 32 .

[0029] Figure 3 2 is a block diagram showing a configuration example of the high-side circuit 10 .

[0030] Figure 4 2 is a block diagram showing a configuration example of the low-side circuit 50 .

[0031] Figure 5 2 is a block diagram showing a configuration example of the state signal generating unit 20 and the input circuit 62 .

[0032] Figure 6 Yes Description Figure 5 The timing chart of the operation example of the status signal generating unit 20 shown in FIG.

[0033] Figure 7 Yes Description Figure 5 The timing chart of the operation example of the input circuit 62 shown in FIG.

[0034] Figure 8 2 is a state machine showing the state transition of the state signal generating unit 20 .

[0035] Fig. 9 is a state machine showing the state transition of the input circuit 62 .

[0036] Fig.10 2 is a diagram showing another example of the transmission unit 30 .

[0037] Fig.11 2 is a diagram showing a configuration example of the level conversion circuit 34 .

[0038] Fig.12 1 is a diagram showing another example of the driving device 100 .

[0039] Fig.13 : is a diagram showing an example of the signal waveforms of the control signal DRVIN, the clock signal CLK, and the output voltage VOUT.

[0040] Fig.14 It is shown Fig.12 2 is a block diagram of a configuration example of the high-side circuit 10 shown.

[0041] Fig.15 It is shown Fig.12 2 is a block diagram of a configuration example of the low-side circuit 50 shown.

[0042] Fig.16 It is shown Figures 12 to 151 is a block diagram of a configuration example of the state signal generating unit 20 and the input circuit 62 in the driving device 100 shown.

[0043] Fig.17 1 is a diagram showing an example of the high withstand voltage element 33 .

[0044] Fig.18 It is a diagram showing an example of the output unit 74 .

[0045] Fig.19 is a diagram showing an example of the input circuit 72 .

[0046] Fig. 20 1 is a diagram showing an example of the time waveform of each signal of the driving device 100 .

[0047] Fig.21 It is shown Figures 12 to 15 1 is a block diagram of another configuration example of the state signal generating unit 20 and the input circuit 62 in the driving device 100 shown.

[0048] Fig. 22 1 is a diagram showing an example of the input-output circuit 93 .

[0049] Explanation of symbols 10···High-side circuit, 11···High-side circuit unit, 12···Drive circuit, 14···Voltage detection circuit, 16···Current detection circuit, 18···Temperature detection circuit, 20···State signal generation unit, 21···Selection circuit, 22···Signal synthesis unit, 23···Output circuit, 24···Pulse generation unit, 25···Oscillation circuit, 26···Digital signal generation unit, 27···Light emitting element, 29···Light receiving element, 30···Transmission ···unit, 31···capacitor, 32···insulating element, 33···high withstand voltage element, 34···level conversion circuit, 35···transistor, 36···resistor, 37···diode, 50···low-side circuit, 52···drive circuit, 54···voltage detection circuit, 56···current detection circuit, 58···temperature detection circuit, 60···transmitting unit, 61···terminal, 62···input circuit, 63···input unit, 64···edge detection circuit 、65···Latch circuit、66···Data holding circuit、67···Timer circuit、68···Control circuit、70···Communication control unit、71···High-side communication circuit、72···Input circuit、73···Low-side communication circuit、74···Output unit、81···Buffer、82···Inverter、83、84、85、86···Diode、87、88···Pull-up resistor、89、90···Pull-down resistor、91···Differential circuit、93 ···Input / output circuit, 94···Input / output unit, 100···Drive device, 101, 102···Diode, 103, 104···Pull-down resistor, 105, 106···Pull-up resistor, 107···Buffer, 108···Inverter, 109···Differential circuit, 110···Edge, 111, 112···Input / output terminal, 200···Output device, 202, 204···Power semiconductor, 300···Power supply device DETAILED DESCRIPTION

[0050] The present invention is described below by the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of the features described in the embodiments are not necessarily all necessary for the technical solution of the invention. It should be noted that in this specification and the drawings, for elements with substantially the same function and structure, repeated descriptions are omitted by marking the same symbols, or illustrations of elements that are not directly related to the present invention are omitted. In addition, in a drawing, elements with the same function and structure are representatively marked with symbols, and sometimes symbols are omitted for elements other than those used as representatives.

[0051] In the present specification, when described as “same” or “equal”, this may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0052] Figure 1 1 is a diagram showing an example of a power supply device 300 according to an embodiment of the present invention. The power supply device 300 supplies power to a load. The load is, for example, a circuit installed in a vehicle or an industrial robot, but is not limited thereto. The power supply device 300 includes a drive device 100 and an output device 200.

[0053] The output device 200 supplies power to the load. The output device 200 includes a power semiconductor 202 and a power semiconductor 204. The power semiconductor 202 and the power semiconductor 204 may be, for example, IGBTs or MOSFETs, or other devices. The power semiconductor 202 and the power semiconductor 204 in this example are arranged in series between the high voltage wiring VDD and the ground potential GND.

[0054] The power semiconductor 202 in this example is a high-side MOSFET whose drain terminal is connected to the high voltage wiring VDD and whose source terminal is connected to the load. The power semiconductor 204 is a low-side MOSFET whose drain terminal is connected to the load and whose source terminal is connected to the ground potential GND. The output device 200 may also have a plurality of sets of power semiconductors 202 and power semiconductors 204. For example, the output device 200 may be a three-phase circuit having three sets of power semiconductors 202 and power semiconductors 204.

[0055] The drive device 100 drives the power semiconductor 202 and the power semiconductor 204. The drive device 100 of this example controls the switching operation of the power semiconductor 202 and the power semiconductor 204. The drive device 100 includes a high-side circuit unit 11, a transmission unit 30, and a low-side circuit 50.

[0056] The high-side circuit unit 11 controls the switching operation of the power semiconductor 202 based on the input control signal. The second power supply voltage VH_U and the second reference voltage VS_U are applied to the high-side circuit unit 11. The high-side circuit unit 11 operates based on the second power supply voltage VH_U and the second reference voltage VS_U. The second reference voltage VS_U is a voltage higher than the first reference voltage GND of the low-side circuit 50. The second reference voltage VS_U in this example is the voltage of the source terminal of the power semiconductor 202.

[0057] The control signal input to the high-side circuit unit 11 is a signal for controlling the timing of switching the power semiconductor 202. For example, the control signal is a signal that becomes a high level (H level) during a period when the power semiconductor 202 should be in an on state, and becomes a low level (L level) during a period when the power semiconductor 202 should be in an off state.

[0058] The high-side circuit unit 11 applies a drive signal having a waveform corresponding to the control signal to the power semiconductor 202. The drive signal may be input to the gate terminal of the power semiconductor 202. The drive signal may have the same logic value pattern as the control signal. The high-side circuit unit 11 may output a drive signal of a level corresponding to the second power supply voltage VH_U during a period when the power semiconductor 202 should be turned on, and may output a drive signal of a level corresponding to the second reference voltage VS_U during a period when the power semiconductor 202 should be turned off.

[0059] The high-side circuit unit 11 has one or more high-side circuits 10 corresponding to the number of power semiconductors 202 to be controlled. The high-side circuit unit 11 of this example has three high-side circuits 10-U, 10-V, and 10-W. Each high-side circuit 10 outputs a drive signal for the corresponding power semiconductor 202. Each high-side circuit 10 can be connected to each power supply. Each second power supply voltage VH_U, VH_V, and VH_W are applied to each high-side circuit 10. Each second reference voltage VS_U, VS_V, and VS_W are applied to each high-side circuit 10.

[0060] The low-side circuit 50 controls the switching action of the power semiconductor 204 based on the input control signal. The first power supply voltage VH_L and the first reference voltage GND are applied to the low-side circuit 50. The low-side circuit 50 operates based on the first power supply voltage VH_L and the first reference voltage GND. The first power supply voltage VH_L is lower than the second power supply voltage VH_U. The first reference voltage GND is lower than the second reference voltage VS. The first reference voltage GND can be a ground voltage.

[0061] The control signal input to the low-side circuit 50 is a signal for controlling the timing of switching the power semiconductor 204. For example, the control signal is a signal that becomes an H level when the power semiconductor 204 should be turned on and becomes an L level when the power semiconductor 204 should be turned off.

[0062] The low-side circuit 50 applies a drive signal having a waveform corresponding to the control signal to the power semiconductor 204. The drive signal may be input to the gate terminal of the power semiconductor 204. The drive signal may have the same logic value pattern as the control signal. The low-side circuit 50 may output a drive signal of a level corresponding to the first power supply voltage VH_L during the period when the power semiconductor 204 should be turned on, and output a drive signal of a level corresponding to the first reference voltage GND during the period when the power semiconductor 204 should be turned off. The low-side circuit 50 outputs one or more drive signals corresponding to the number of power semiconductors 204 to be controlled.

[0063] The low-side circuit 50 outputs a state signal SCL indicating the state of the drive device 100. The state signal SCL is a digital signal. The state signal SCL can be output to a control device that controls the drive device 100. The control device can control the drive device 100 based on the state signal SCL. For example, the control device can stop the operation of the drive device 100 when an abnormality occurs in the drive device 100.

[0064] The state signal SCL includes information indicating the state of the high-side circuit 10. The state signal SCL may also include information indicating the state of the low-side circuit 50. The low-side circuit 50 of this example outputs a state signal SCL, which includes both the state of the high-side circuit 10 and the state of the low-side circuit 50. The state signal SCL may include information indicating at least any one of the temperature at a predetermined location of each circuit, the current flowing in the predetermined location, and the voltage applied to the predetermined location. The state signal SCL may also include information indicating whether at least any one of the temperature, current, and voltage of each circuit is within a predetermined allowable range.

[0065] Each high-side circuit 10 generates a high-side state signal HSD_U that uses a digital value of multiple bits to indicate the state of the high-side circuit 10. The high-side state signal HSD_U in this example is a signal that becomes a voltage corresponding to the second power supply voltage VH_U during the H logic period and becomes a voltage corresponding to the second reference voltage VS during the L logic period. In this specification, a logic value of 1 is sometimes referred to as H logic, and a logic value of 0 is sometimes referred to as L logic.

[0066] exist Figure 1 In the example, the high-side circuits 10-U, 10-V, 10-W generate high-side status signals HSD_UU, HSD_UV, HSD_UW. Each high-side status signal HSD_U includes information indicating at least one of the temperature, current and voltage at the corresponding high-side circuit 10 and whether these values ​​are within the allowable range.

[0067] The transmission unit 30 generates a high-side state signal HSD_L obtained by converting the second reference voltage VS of the high-side state signal HSD_U into the first reference voltage GND. The transmission unit 30 of this example converts the high-side state signals HSD_UU, HSD_UV, and HSD_UW into high-side state signals HSD_LU, HSD_LV, and HSD_LW. The high-side state signals HSD_LU, HSD_LV, and HSD_LW can be signals having the same logic value pattern as the high-side state signals HSD_UU, HSD_UV, and HSD_UW and having the same bit time. The bit time is the time occupied by 1 bit of information in the signal.

[0068] The high-side state signal HSD_L in this example is a signal that becomes a voltage corresponding to the second reference voltage VS during the L logic period. The high-side state signal HSD_L may become a voltage corresponding to the first power supply voltage VH_L during the H logic period, or may become another voltage.

[0069] The transmission section 30 transmits the high-side state signal HSD_L to the low-side circuit 50. The low-side circuit 50 outputs a state signal SCL including information included in the high-side state signal HSD_L.

[0070] The second reference voltage VS of the high-side circuit 10 changes correspondingly to the operating state of the power semiconductor 202 and the power semiconductor 204. Therefore, the reference voltage of the high-side state signal HSD_U also changes. According to this example, the transmission unit 30 converts the reference voltage of the high-side state signal HSD into a reference voltage suitable for processing by the low-side circuit 50. Therefore, the low-side circuit 50 can easily process the high-side state signal HSD. In addition, the low-side circuit 50 can generate a state signal SCL including both the state of the low-side circuit 50 and the state of the high-side circuit 10. Therefore, the state of the high-side circuit 10 can be notified to the outside with a simple structure.

[0071] The transmission unit 30 of this example includes one or more insulating elements 32 corresponding to one or more high-side circuits 10. The insulating element 32 converts and transmits the reference voltage of the high-side state signal HSD while electrically insulating the high-side circuit 10 and the low-side circuit 50.

[0072] Figure 2 : is a diagram showing an example of an insulating element 32. The insulating element 32 of this example is a photocoupler having a light emitting element 27 and a light receiving element 29. The light emitting element 27 emits light according to the high-side state signal HSD_U. The light emitting element 27 is, for example, a light emitting diode. A second reference voltage VS is applied to a cathode terminal of the light emitting element 27. A high-side state signal HSD_U is applied to an anode terminal of the light emitting element 27.

[0073] The light receiving element 29 receives the light emission signal from the light emitting element 27 and generates a high-side state signal HSD_L. The light receiving element 29 is, for example, a phototransistor. A first reference voltage GND is applied to the emitter terminal of the light receiving element 29. The voltage of the collector terminal of the light receiving element 29 is output as the high-side state signal HSD_L. The light receiving element 29 can generate a high-side state signal HSD_L, which becomes a predetermined high voltage during a period when light with a predetermined intensity or above is being received, and becomes the first reference voltage GND during a period when light with a predetermined intensity or above is not being received. The high voltage of the high-side state signal HSD_L may be the same as or different from the first power supply voltage VH_L.

[0074] Figure 3 1 is a block diagram showing a configuration example of a high-side circuit 10. The high-side circuit 10 of this example includes a drive circuit 12, a voltage detection circuit 14, a current detection circuit 16, a temperature detection circuit 18, and a state signal generation unit 20. The drive circuit 12 outputs a drive signal for controlling the power semiconductor 202 based on a control signal input from an external control device or the like.

[0075] The voltage detection circuit 14 detects the voltage of a predetermined part of the high-side circuit 10. For example, the voltage detection circuit 14 can detect the second power supply voltage VH_U at a part to which the second power supply voltage VH_U is applied. The voltage detection circuit 14 can determine whether the difference between the detected voltage and the reference value is within an allowable range. The voltage detection circuit 14 can notify the drive circuit 12 of the determination result. When the difference between the voltage detected by the voltage detection circuit 14 and the reference value is not within the allowable range, the drive circuit 12 can control the power semiconductor 202 to be in an off state.

[0076] The current detection circuit 16 detects the current flowing in a predetermined portion of the high-side circuit 10. For example, the current detection circuit 16 can detect the current flowing from the drive circuit 12 to the power semiconductor 202. The current detection circuit 16 can determine whether the difference between the detected current and the reference value is within an allowable range. The current detection circuit 16 can notify the drive circuit 12 of the determination result. When the difference between the current detected by the current detection circuit 16 and the reference value is not within the allowable range, the drive circuit 12 can control the power semiconductor 202 to be in an off state.

[0077] The temperature detection circuit 18 detects the temperature of a predetermined portion of the high-side circuit 10. For example, the temperature detection circuit 18 can detect the temperature of the drive circuit 12. The temperature detection circuit 18 can determine whether the difference between the detected temperature and the reference value is within an allowable range. The temperature detection circuit 18 can notify the drive circuit 12 of the determination result. When the difference between the temperature detected by the temperature detection circuit 18 and the reference value is not within the allowable range, the drive circuit 12 can control the power semiconductor 202 to be in an off state.

[0078] The voltage detection circuit 14, the current detection circuit 16 and the temperature detection circuit 18 can also detect the voltage, current and temperature of the output device 200. The voltage detection circuit 14, the current detection circuit 16 and the temperature detection circuit 18 can detect the voltage, current and temperature of the power semiconductor 202.

[0079] The status signal generating unit 20 generates a high-side status signal HSD_U indicating the status of the high-side circuit 10 based on at least one of the voltage detected by the voltage detection circuit 14, the current detected by the current detection circuit 16, and the temperature detected by the temperature detection circuit 18. The high-side status signal HSD_U may include at least any one of the values ​​(V, A, °C) of the voltage, current, and temperature, and may also include the determination result of at least one of the voltage detection circuit 14, the current detection circuit 16, and the temperature detection circuit 18. The high-side status signal HSD_U may also include information indicating other statuses of the high-side circuit 10. The high-side status signal HSD_U may include information related to the frequency of the voltage or current of the high-side circuit 10, may include information related to the accumulated operating time, and may also include other information. The high-side status signal HSD_U may include information indicating the current status of the high-side circuit 10, and may also include information indicating the past status of the high-side circuit 10.

[0080] Figure 4 is a block diagram showing a configuration example of the low-side circuit 50. The low-side circuit 50 of this example includes a drive circuit 52, a voltage detection circuit 54, a current detection circuit 56, a temperature detection circuit 58, a transmission unit 60, and an input circuit 62. The drive circuit 52 outputs a drive signal for controlling the power semiconductor 204 based on a control signal input from an external control device or the like.

[0081] The voltage detection circuit 54 detects the voltage of a predetermined part of the low-side circuit 50. For example, the voltage detection circuit 54 can detect the first power supply voltage VH_L at a part to which the first power supply voltage VH_L is applied. The voltage detection circuit 54 can determine whether the difference between the detected voltage and the reference value is within an allowable range. The voltage detection circuit 54 can notify the drive circuit 52 of the determination result. When the difference between the voltage detected by the voltage detection circuit 54 and the reference value is not within the allowable range, the drive circuit 52 can control the power semiconductor 204 to be in an off state.

[0082] The current detection circuit 56 detects the current flowing in a predetermined portion of the low-side circuit 50. For example, the current detection circuit 56 can detect the current flowing from the drive circuit 52 to the power semiconductor 204. The current detection circuit 56 can determine whether the difference between the detected current and the reference value is within the allowable range. The current detection circuit 56 can notify the drive circuit 52 of the determination result. When the difference between the current detected by the current detection circuit 56 and the reference value is not within the allowable range, the drive circuit 52 can control the power semiconductor 204 to be in the off state.

[0083] The temperature detection circuit 58 detects the temperature of a predetermined portion of the low-side circuit 50. For example, the temperature detection circuit 58 can detect the temperature of the drive circuit 52. The temperature detection circuit 58 can determine whether the difference between the detected temperature and the reference value is within the allowable range. The temperature detection circuit 58 can notify the drive circuit 52 of the determination result. When the difference between the temperature detected by the temperature detection circuit 58 and the reference value is not within the allowable range, the drive circuit 52 can control the power semiconductor 204 to be in the off state.

[0084] The voltage detection circuit 54, the current detection circuit 56, and the temperature detection circuit 58 can also detect the voltage, current, and temperature of the output device 200. The voltage detection circuit 54, the current detection circuit 56, and the temperature detection circuit 58 can detect the voltage, current, and temperature of the power semiconductor 204.

[0085] The transmitting unit 60 generates a low-side state signal indicating the state of the low-side circuit 50 in a digital quantity based on at least one of the voltage detected by the voltage detection circuit 54, the current detected by the current detection circuit 56, and the temperature detected by the temperature detection circuit 58. Regarding the low-side circuit 50, the low-side state signal may include the same information as the high-side state signal.

[0086] One or more high-side state signals HSD_L are input from the transmission unit 30 to the input circuit 62. In this example, high-side state signals HSD_LU, HSD_LV, and HSD_LW are input to the input circuit 62. The input circuit 62 outputs digital signals DOUT_U, DOUT_V, and DOUT_W that represent information included in the high-side state signals HSD_LU, HSD_LV, and HSD_LW using a digital quantity of multiple bits.

[0087] The sending unit 60 sends a status signal SCL to an external device, and the status signal SCL includes a digital signal DOUT of a high-side status signal HSD_L. The sending unit 60 of this example outputs a digital signal DOUT of a high-side status signal and a digital signal of a low-side status signal from a common terminal 61. The status signal SCL and the status signal SDA may include information of both the digital signal DOUT of the high-side status signal and the digital signal of the low-side status signal. The status signal SCL may include the digital signal DOUT of the high-side status signal and the digital signal of the low-side status signal in a time-sharing manner. The sending unit 60 may output the status signal SCL to a display device that displays the status of the driving device 100, or may output the status signal SCL to a recording device that records the status of the driving device 100.

[0088] Figure 5 1 is a block diagram showing a configuration example of the state signal generating unit 20 and the input circuit 62. The state signal generating unit 20 of this example includes a digital signal generating unit 26, a selecting circuit 21, a signal synthesizing unit 22, an output circuit 23, a pulse generating unit 24, and an oscillating circuit 25. The input circuit 62 of this example includes an input unit 63, an edge detecting circuit 64, a latch circuit 65, a data holding circuit 66, a timer circuit 67, and a control circuit 68.

[0089] Figure 6 Yes Description Figure 5 1 is a timing diagram of an operation example of the state signal generating unit 20 shown in FIG. The oscillator circuit 25 generates a clock signal T having a predetermined period. Each component of the state signal generating unit 20 can be input with the clock signal T, and can operate according to the period of the clock signal T. In addition, an enable signal DEN indicating the start of the operation can be input to the state signal generating unit 20. In this example, the operation of the state signal generating unit 20 starts at the moment when the enable signal DEN changes from the L level to the H level.

[0090] The digital signal generation unit 26 receives the detection results of one or more state detection circuits such as the voltage detection circuit 14, the current detection circuit 16, and the temperature detection circuit 18. The digital signal generation unit 26 generates a digital signal D representing the input detection result. The digital signal in this example is an 8-bit signal, but the number of bits of the digital signal is not limited to this.

[0091] The digital signal D may include at least one value (V, A, ° C.) of the voltage, current and temperature of the high-side circuit 10 , and may also include the determination result of at least one of the voltage detection circuit 14 , the current detection circuit 16 and the temperature detection circuit 18 . Figure 6 The digital signal generation unit 26 in the example generates a digital signal D having a logic value pattern of 0110_0101. This logic value pattern is information indicating the state of the high-side circuit 10. Figure 6 In FIG. 1 , an example in which a digital signal D has this logic value pattern is described.

[0092] The pulse generator 24 generates a count signal DS, the value of which increases at every predetermined period. The pulse generator 24 of this example counts the number of bit times by taking four cycles of the clock signal T as one bit time, and generates a count signal DS indicating the count value. The count value of the count signal DS increases by 1 from an initial value (e.g., 0), and when the count value reaches a predetermined upper limit value (e.g., 9), the next count value returns to the initial value (e.g., 0).

[0093] The number of count values ​​from the initial value to the upper limit value of the count signal DS is greater than the number of bits of the digital signal D. Since the digital signal D in this example is 8 bits, the number of count values ​​from the initial value to the upper limit value of the count signal DS is 9 or more. Figure 6 In the example of , the number of count values ​​of the count signal DS is 10 integers from 0 to 9.

[0094] The selection circuit 21 outputs a binary digital signal S based on the digital signal D and the count signal DS. The digital signal S is a binary digital signal having a waveform corresponding to the logic value pattern of the digital signal D. The digital signal S in this example is a signal that changes the signal level in each bit time to either an H level corresponding to a logic value 1 or an L level corresponding to a logic value 0. The bit time is the time occupied by 1 bit of information in the digital signal S. Figure 6 In the example, the bit time is 4 times the length of the period of the clock signal T.

[0095] The selection circuit 21 of this example reads the logic value of the bit corresponding to the count value of the count signal DS among the bits of the digital signal D, and generates a digital signal S in accordance with the read logic value. For example, the initial value of the count value corresponds to the most significant bit of the digital signal D, and the upper limit value of the count value corresponds to the least significant bit of the digital signal D.

[0096] exist Figure 6In the example, since the logic value of the most significant bit of the digital signal D is 0, the signal level of the digital signal S is L level during the bit time when the count value of the count signal DS indicates the initial value 0. Similarly, the logic values ​​of the digital signal D corresponding to the count values ​​1, 2, ... 7 of the count signal DS are 1, 1, 0, 0, 1, 0, 1. Therefore, the signal level of the digital signal S at each bit time sequentially changes to H, H, L, L, H, L, H.

[0097] The period when the count value of the count signal DS is 8 and 9 is the blanking period. After the blanking period, the next digital value of the digital signal D is started (in Figure 6 In this example, the signal level of the digital signal S during the blanking period is L level.

[0098] The pulse generating unit 24 generates a start pulse T1 indicating the start time of each bit time and an end pulse T2 indicating the end time of each bit time. The start pulse T1 in this example is a pulse train configured at the start time of each bit time. As an example, the timing of the leading edge of the start pulse T1 coincides with the start time of the bit time. The end pulse T2 in this example is a pulse train configured at the end time of each bit time. As an example, the timing of the trailing edge of the end pulse T2 coincides with the end time of the bit time. The pulse width of each pulse of the start pulse T1 and the end pulse T2 is less than half of 1 bit time. The pulse width in this example is 1 / 4 of 1 bit time (i.e., 1 cycle of the clock signal T).

[0099] The pulse generating unit 24 can output a blanking signal BK. The blanking signal BK in this example is a signal that becomes an H level during a blanking period and becomes an L level during other periods.

[0100] Figure 6 The state signal HS_STATE in is a signal indicating the operation state of the state signal generating unit 20. The enable signal DEN of the state HIDLE is at an L level, indicating an idle state. The enable signal DEN of the state HSERPAR is at an H level, indicating a state in which the digital signal D is being processed. It should be noted that in the state HSERPAR, the blanking signal BK is at an L level. The state HBK indicates a blanking state in which the enable signal DEN is at an H level and the blanking signal BK is at an H level. In the standby state, if the enable signal DEN changes to an H level, the processing of the next digital quantity of the digital signal D begins.

[0101] The signal synthesizer 22 generates a high-side state signal SS based on the digital signal S. The high-side state signal SS has a plurality of bit times corresponding to a plurality of bits of the digital quantity of the digital signal D. Figure 6In the example of FIG. 1 , DATA0 or DATA1 is used to represent each bit time of the high-side state signal SS.

[0102] The signal level of the high-side state signal SS in each bit time represents the value corresponding to each bit of the digital quantity of the digital signal D. Figure 6 In the example, DATA0 is the bit time with a logic value of 0, and DATA1 is the bit time with a logic value of 1.

[0103] The signal synthesizer 22 of this example generates a high-side state signal SS, which includes a start pulse T1 and an end pulse T2, and sets the signal level in the period between the start pulse T1 and the end pulse T2 to a level corresponding to the digital amount of the digital signal D. In this example, the signal level in the period between the start pulse T1 and the end pulse T2 is the same as the signal level of the digital signal S. The signal synthesizer 22 can insert the start pulse T1 and the end pulse T2 into the signal waveform of the digital signal S, thereby generating the high-side state signal SS. The high-side state signal SS is a signal having the same waveform pattern as the above-mentioned high-side state signal HSD_U. According to this example, the start time and the end time of each bit time can be clearly indicated. Therefore, in the subsequent circuits such as the input circuit 62, the digital amount of the high-side state signal can be detected with high precision.

[0104] The polarity of the start pulse T1 and the end pulse T2 can be inverted. The polarity of the pulse is determined by whether the leading edge of the two edges is the rising edge or the falling edge. Figure 6 In the example, the start pulse T1 is a pulse with a falling edge. The end pulse T2 is a pulse with a rising edge. The signal synthesizer 22 configures the start pulse T1 and the end pulse T2 in such a way that the trailing edge of the end pulse T2 of the previous bit time and the leading edge of the start pulse T1 of the bit time become a common edge. By making the polarity of the start pulse T1 and the end pulse T2 different, the edge can always be configured at the boundary of each bit time. Figure 6 In the example of , in the high-side state signal SS, a falling edge is always configured at the boundary time of each bit time. In addition, in the high-side state signal SS, no falling edge is configured except at the boundary time of each bit time.

[0105] The high-side state signal SS in this example changes to a signal level corresponding to the digital quantity after the pulse time of the start pulse T1 (for example, one cycle of the clock signal T) has passed since the falling edge. During DATA0, after the pulse time of the start pulse T1 has passed, the signal level of the high-side state signal SS is also maintained at the L level. However, at the moment of the leading edge of the end pulse T2, the signal level of the high-side state signal SS changes to the H level. In addition, during DATA1, if the pulse time of the start pulse T1 has passed, the signal level of the high-side state signal SS changes to the H level. The signal level of the high-side state signal SS is maintained at the H level until the start moment of the next bit time.

[0106] In this example, during the blanking period when the blanking signal BK is at the H level, the high-side state signal SS is maintained at the H level. That is, the signal level of the high-side state signal SS during the blanking period is the same as the signal level just before the leading edge of the start pulse T1. Thus, in the subsequent processing of the digital quantity of the digital signal D, the leading edge of the start pulse T1 can be configured at the start time of the first bit time.

[0107] The output circuit 23 outputs the high-side state signal HSD_U based on the high-side state signal SS. The high-side state signal HSD_U has the same waveform pattern as the high-side state signal SS. The high-side state signal HSD_U may have a predetermined delay time relative to the high-side state signal SS. The output circuit 23 of this example latches the value of the high-side state signal SS according to the cycle of the clock signal T, and sequentially outputs it as the high-side state signal HSD_U. In this case, the high-side state signal HSD_U is delayed by one cycle of the clock signal T relative to the high-side state signal SS.

[0108] Figure 7 Yes Description Figure 5 The input circuit 62 can be operated in accordance with the timing diagram of the input circuit 62. Figure 6 The operation is performed in the same cycle as the clock signal T shown, but the operation may be performed in other cycles.

[0109] An enable signal LDEN indicating the start of an operation may be input to the input circuit 62. In this example, at the time when the enable signal LDEN changes from the L level to the H level, the signal processing of the high-side state signal HSD_L is started.

[0110] The input unit 63 generates an input signal DI based on the high-side state signal HSD_U. The input signal DI may have the same waveform pattern as the high-side state signal HSD_U. The input unit 63 may generate the input signal DI by sampling the high-side state signal HSD_U according to a predetermined period. That is, the input signal DI is a signal equivalent to the high-side state signal HSD_U. In this specification, the input signal DI is sometimes treated as the high-side state signal HSD_U.

[0111] The input signal DI may be a binary digital signal in which the first reference voltage GND is set to an L level and the first power supply voltage VH_L is set to an H level. Figure 6 The high-side state signal HSD_U shown in the figure has a plurality of bit times DATA0 and DATA1. In addition, each bit time of the input signal DI includes a start pulse T1 and an end pulse T2, similarly to the high-side state signal HSD_U.

[0112] The edge detection circuit 64 detects the edge configured at the boundary of each bit time of the input signal DI. Thus, the start time or end time of each bit time of the high-side state signal HSD_L (in this example, the input signal DI) received from the transmission unit 30 can be extracted. The edge detection circuit 64 generates an edge detection signal DE corresponding to the detected edge. The edge detection signal DE is a signal indicating the start time or end time of each bit time of the input signal DI.

[0113] The edge detection circuit 64 of this example detects the falling edge of the input signal DI. The edge detection circuit 64 generates an edge detection signal DE having an edge at the moment of the falling edge. The edge detection signal DE of this example has a rising edge at the moment of the falling edge of the input signal DI. After the rising edge, the edge detection signal DE of this example maintains an H level during a maintenance period shorter than 1 bit time. After the maintenance period, the edge detection signal DE changes to an L level. Then, it changes to an H level at the beginning of the next bit time. Thus, a rising edge can be configured in the edge detection signal DE in synchronization with the beginning of each bit time in the input signal DI. During the blanking period after each bit time, the signal level of the edge detection signal DE of this example is maintained at an L level.

[0114] The timer circuit 67 generates a strobe signal SLT based on the edge detection signal DE. The strobe signal SLT is a signal configured with an edge in a manner having a predetermined delay time relative to the rising edge of the edge detection signal DE. The strobe signal SLT in this example has a rising edge in a manner having a predetermined delay time relative to the rising edge of the edge detection signal DE. The strobe signal SLT has a pulse that maintains an H level only for a predetermined pulse width from the rising edge. The pulse width is shorter than the bit time. The pulse width may be the same as the pulse width of the start pulse T1 or the end pulse T2.

[0115] The delay time is greater than the pulse width of the start pulse T1. In addition, the delay time is shorter than the time from the start of the bit time to the leading edge of the end pulse. That is, the rising edge of the selection signal SLT in this example is arranged in the period representing the signal level corresponding to the logical value in each bit time. The rising edge of the selection signal SLT can be arranged in the center of each bit time.

[0116] The latch circuit 65 detects the signal level of the input signal DI at a detection time set based on the start time or end time of each bit time of the input signal DI. The latch circuit 65 of this example latches the signal level of the input signal DI at the time of the rising edge of the selection signal SLT. Thus, the latch circuit 65 can detect the signal level corresponding to the logical value of each bit time of the input signal DI. The latch circuit 65 generates a digital signal DL of multiple bits based on the signal level detected in each bit time. The number of bits of the digital signal DL is the same as the number of bits of the digital signal D (8 bits in this example).

[0117] The latch circuit 65 of this example sequentially inserts the logic value detected corresponding to the rising edge of the selection signal SLT into the least significant bit of the digital signal DL. Before inserting the logic value into the least significant bit of the digital signal DL, the latch circuit 65 shifts the logic value of each bit of the digital signal DL by 1 bit toward the upper bit side. By such processing, a digital signal DL corresponding to the logic value pattern of the input signal DI can be generated.

[0118] The control circuit 68 can generate a count signal DCNT obtained by counting predetermined edges in the edge detection signal DE. The count signal DCNT is a signal whose count value increases by 1 every time a bit time passes. The initial value of the count signal DCNT in this example is 0.

[0119] The control circuit 68 outputs an output control signal PLT, which has a pulse at a moment when a predetermined time has passed since the count value of the count signal DCNT reached the upper limit value. The upper limit value of the count value of the count signal DCNT corresponds to the number of bits of the digital signal DL. The upper limit value in this example is 7. The predetermined time can be measured by the timer circuit 67. The predetermined time can be longer than 1 bit time. Thus, a pulse of the output control signal PLT can be generated after the processing of the final bit of the digital signal DL is completed. The control circuit 68 can output a pulse of the output control signal PLT when the predetermined time has passed and the edge detection signal DE is at the L level.

[0120] The data holding circuit 66 imports the digital quantity of the digital signal DL in response to the pulse of the output control signal PLT. Thus, the data holding circuit 66 can import the digital signal DL after the logic values ​​of all bits (8 bits in this example) of the digital quantity are inserted. The data holding circuit 66 holds the digital quantity of the imported digital signal DL in a register or the like. The data holding circuit 66 outputs the held digital quantity as a digital signal DOUT.

[0121] The control circuit 68 can set the count value of the count signal DCNT to an initial value at the timing of outputting a pulse of the control signal PLT, thereby making it possible to use the count signal DCNT of the initial value in the subsequent digital quantity processing.

[0122] The latch circuit 65 can set the logic value of each bit of the digital signal DL to an initial value (eg, 0) at the timing of outputting a pulse of the control signal PLT. Thus, the digital signal DL of the initial value can be used in the subsequent processing of digital quantities.

[0123] Figure 7 The state signal LS_STATE in is a signal indicating the operation state of the input circuit 62. The enable signal LDEN of the state LIDLE is at an L level, indicating an idle state. The enable signal LDEN of the state LSERPAR is at an H level, indicating a state in which the high-side state signal HSD_L is processed. The state LBK indicates a blanking state in which the enable signal LDEN is at an H level and the count signal DCNT is at an upper limit value.

[0124] Figure 8 2 is a conceptual diagram of a state machine showing state transitions of the state signal generating unit 20 . Figure 8 The states of the state machine HIDLE, HSERPAR, HBK and Figure 6 The states are the same as those described in the state signal HS_STATE.

[0125] During the period when the enable signal DEN indicates 0, the state signal generating unit 20 is in the standby state HIDLE. If the enable signal DEN changes from 0 to 1, the state signal generating unit 20 changes to the processing state HSERPAR. In the processing state HSERPAR, Figure 6 As described in , the state signal generating unit 20 performs processing on the digital signal D.

[0126] When the count value of the count signal DS reaches a value corresponding to the last bit of the digital signal D (DS=7 in this example) and the end pulse T2 is generated, the process ends until the last bit of the digital signal D. In this case, the state signal generating unit 20 changes to the blanking state HBK.

[0127] The blanking state HBK continues until the count value of the count signal DS reaches the upper limit value (DS=9 in this example) and the end pulse T2 is generated. At the moment when the blanking state HBK ends, when the enable signal DEN is at the L level (DEN=0), the state signal generating unit 20 changes to the standby state HIDLE. At the moment when the blanking state HBK ends, when the enable signal DEN is at the H level (DEN=1), the state signal generating unit 20 changes to the processing state HSERPAR and performs the next digital quantity processing for the digital signal D.

[0128] Fig. 9 is a conceptual diagram of a state machine showing state transitions of the input circuit 62 . Fig. 9 The states of the state machine LIDLE, LSERPAR, LBK and Figure 7 The states are the same as those described in the state signal LS_STATE.

[0129] During the period when the enable signal LDEN indicates 0, the input circuit 62 is in the standby state LIDLE. If the enable signal LDEN changes from 0 to 1, the input circuit 62 changes to the processing state LSERPAR. In the processing state LSERPAR, Figure 7 As described in , the input circuit 62 performs processing on the high-side state signal HSD_U.

[0130] In the processing state LSERPAR, when the count value of the count signal DCNT is a value just before the upper limit value (DNCT=6) and the input signal DI generates a falling edge, the input circuit 62 starts processing the last bit of the input signal DI. After starting processing the last bit, the input circuit 62 changes to the blanking state HBK and maintains the count value of the count signal DCNT at the upper limit value.

[0131] The blanking state HBK continues until a pulse of the output control signal PLT is generated (PLT=1). If a pulse of the output control signal PLT is generated, the input circuit 62 changes to the idle state LIDLE. In the idle state LIDLE, if the enable signal DEN becomes H level (DEN=1), the input circuit 62 processes the next digital quantity of the high-side state signal HSD_L.

[0132] Fig.10 30 is a diagram showing another example of the transmission unit 30. The transmission unit 30 of this example has a level conversion circuit 34 instead of Figure 1 The insulating element 32 described in the above description is used. The configuration other than the transmission unit 30 is the same as any of the embodiments described in this specification.

[0133] The level conversion circuit 34 generates a high-side state signal HSD_L obtained by shifting the signal level of the high-side state signal HSD_U in accordance with the first reference voltage GND. The level conversion circuit 34 of this example generates a high-side state signal HSD_L obtained by converting the second reference voltage VS of the high-side state signal HSD_U into the first reference voltage GND. The level conversion circuit 34 does not electrically insulate the state signal generating unit 20 and the input circuit 62.

[0134] Fig.11 3 is a diagram showing a configuration example of a level conversion circuit 34. The level conversion circuit 34 of this example includes a transistor 35, a resistor 36, and a diode 37. The transistor 35 is provided between a node to which the second power supply voltage VH_U is applied and the first reference voltage GND, and a high-side state signal HSD_U is input to a gate terminal of the transistor 35. The transistor 35 of this example is a p-channel MOSFET. The transistor 35 is turned off during a period when the high-side state signal HSD_U is at an H level, and is turned on during a period when the high-side state signal HSD_U is at an L level.

[0135] The resistor 36 is provided between the node of the first reference voltage GND and the transistor 35. In addition, the diode 37 is provided in parallel with the resistor 36 between the node of the first reference voltage GND and the transistor 35. The first reference voltage GND is applied to the anode terminal of the diode 37. The level conversion circuit 34 of this example outputs the voltage of the cathode terminal of the diode 37 as the high-side state signal HSD_L.

[0136] During the period when the high-side state signal HSD_U is at the H level, the transistor 35 is in the off state. In this case, the diode 37 does not conduct in the reverse direction, and the voltage of the anode terminal becomes a predetermined voltage. The cathode terminal of the diode 37 may be applied with the first power supply voltage VH_L or may be applied with another voltage. The H level of the high-side state signal HSD_L may be the same as or different from the first power supply voltage VH_L.

[0137] During the period when the high-side state signal HSD_U is at the L level, the transistor 35 is turned on. The second power supply voltage VH_U is applied to the cathode terminal of the diode 37. The diode 37 is reversely conducted, and the voltage of the cathode terminal becomes the first reference voltage GND. As a result, the L level of the high-side state signal HSD_L is the first reference voltage GND. According to the level conversion circuit 34 of this example, the high-side state signal HSD_U can be level-converted into the high-side state signal HSD_L with a simple structure.

[0138] Fig.12 1 is a diagram showing another example of the drive device 100. The drive device 100 of the present invention includes a communication control unit 70. The other structures and functions are the same as any example described in this specification. When the first state signal is output from the first circuit in the drive device 100 to the second circuit in the drive device 100, the drive device 100 of this example controls the output period during which the first circuit can output the first state signal. The first state signal is a signal that indicates the state of the first circuit using a digital quantity of multiple bits.

[0139] exist Fig.12 In the example, the high-side circuit unit 11 or each high-side circuit 10 is the first circuit, and the low-side circuit 50 is the second circuit. The high-side state signal HSD_U output by the high-side circuit 10 is an example of a first state signal. However, the first circuit and the second circuit are not limited to these. For example, the first circuit can be a sensor circuit that detects the temperature or current of the output device 200 and outputs a first state signal corresponding to the detection result. The second circuit can be a circuit that controls the drive device 100 or the output device 200 corresponding to the detection result of the first circuit.

[0140] The communication control unit 70 controls the output period based on a load state signal indicating the on / off transition timing of at least one of the power semiconductor 202 and the power semiconductor 204. In this specification, the power semiconductor 202 and the power semiconductor 204 are sometimes collectively referred to as the output device 200.

[0141] The load state signal is, for example, a control signal input to the drive device 100, but is not limited thereto. Any signal that indicates the transition time of the output device 200 can be used as the load state signal. For example, a gate signal input to the gate terminal of the output device 200 can also be used as the load state signal. In this example, the control signal is sometimes referred to as DRVIN.

[0142] At the moment of the on-off state transition of the output device 200, the voltage and current of a predetermined node of the output device 200 vary greatly. The variation of the voltage and current of the output device 200 may affect the signal transmission of the driving device 100. For example, when a common power supply voltage or reference voltage is applied to the output device 200 and the driving device 100, the power supply voltage or reference voltage of the driving device 100 may vary due to the variation of the voltage and current of the output device 200. In addition, when the power supply voltage or reference voltage is not common, there is a case where the radiation noise caused by the variation of the voltage and current of the output device 200 affects the signal transmission of the driving device 100.

[0143] The communication control unit 70 of this example stops outputting the high-side state signal HSD_U from the high-side circuit 10 from the moment when the on-off of the output device 200 is switched to the moment when the preset stop period has passed. The communication control unit 70 allows the output of the high-side state signal HSD_U from the high-side circuit 10 after the stop period has passed. As a result, the influence of the switch of the output device 200 is reduced, and the high-side state signal HSD_U can be transmitted from the high-side circuit 10 to the low-side circuit 50 with high accuracy. The stop period can be preset by the manufacturer or user of the drive device 100. The stop period can be longer than the period from the start of the switch of the output device 200 to the stabilization of the voltage or current of the output device 200.

[0144] The high-side circuit 10 of this example outputs a high-side state signal HSD_U in response to the clock signal CLK_U input from the low-side circuit 50. The high-side circuit 10 outputs the high-side state signal HSD_U when the clock signal CLK_U is input, and does not output the high-side state signal HSD_U when the clock signal CLK_U is not input.

[0145] The communication control unit 70 of this example controls the input period of the clock signal CLK_U from the low-side circuit 50 to the high-side circuit 10 based on the control signal DRVIN. The communication control unit 70 can control the input of the clock signal CLK_U to the high-side circuit 10 by controlling the output of the clock signal CLK_L from the low-side circuit 50. In this way, it is possible to control whether the high-side state signal HSD_U from the high-side circuit 10 is output.

[0146] The transmission unit 30 of this example has Figures 1 to 11 In addition to the functions described above, the transmission unit 30 has a function of transmitting the clock signal CLK. The transmission unit 30 includes one or more high withstand voltage elements 33 provided corresponding to each high-side circuit 10 .

[0147] like Figures 1 to 11As described in , each high-voltage element 33 converts the reference voltage of the high-side state signal HSD_U from the high-side circuit 10 into the first reference voltage GND of the low-side circuit 50. The high-voltage element 33 transmits the high-side state signal HSD_L obtained by converting the reference voltage to the low-side circuit 50. In addition, each high-voltage element 33 converts the reference voltage of the clock signal CLK_L from the low-side circuit 50 into the second reference voltage VS of the high-side circuit 10. The high-voltage element 33 transmits the clock signal CLK_U obtained by converting the reference voltage to the high-side circuit 10. The high-voltage element 33 can be Figures 1 to 11 The insulating element 32 in the example may be the same element as that of the insulating element 32 or may be an element of other structure.

[0148] Fig.13 : is a diagram showing an example of signal waveforms of the control signal DRVIN, the clock signal CLK, and the output voltage VOUT. The clock signal CLK is the clock signal CLK_L output by the low-side circuit 50 or the clock signal CLK_U input to the high-side circuit 10. The clock signal CLK_L and the clock signal CLK_U have time waveforms synchronized with each other. The output voltage VOUT is the voltage output by the output device 200 to the load.

[0149] As the logic value of the control signal DRVIN changes, the output device 200 switches. As the output device 200 switches, the output voltage VOUT of the output device 200 changes between the H level and the L level. As described above, the variation of the output voltage VOUT may affect the signal transmission of the driving device 100.

[0150] The communication control unit 70 of this example stops the input of the clock signal to the high-side circuit 10 from the transition moment of the control signal DRVIN until the predetermined stop period P1 has passed. As a result, the output of the high-side state signal HSD_U from the high-side circuit 10 during the stop period P1 can be stopped. The communication control unit 70 allows the input of the clock signal to the high-side circuit 10 during the output period P2 from the moment when the stop period P1 has passed until the next transition moment of the control signal DRVIN. Through such control, the influence of the switch of the output device 200 is reduced, and the high-side state signal HSD_U can be transmitted with high accuracy.

[0151] The communication control unit 70 may control the length of the stop period P1 according to the characteristics of the output device 200 (ie, the power semiconductors 202 and 204). The characteristics of the output device 200 may affect the length of the transition period P3 from the time when the control signal DRVIN changes to when the output voltage VOUT stabilizes.

[0152] The communication control unit 70 can make the stop period P1 longer than the transition period P3. As a result, the high-side state signal HSD_U can be transmitted with higher accuracy. On the other hand, if the stop period P1 is too long, the period during which the high-side state signal HSD_U can be transmitted will be shortened. The stop period P1 can be less than twice the transition period P3. The communication control unit 70 can control the stop period P1 based on the length of the transition period P3.

[0153] The communication control unit 70 can control the length of the stop period P1 in accordance with the slope of the edge 110 of the output voltage VOUT (i.e., the time differential value dV / dt of the voltage). The edge 110 can be a rising edge or a falling edge. The edge 110 can be the one with a smaller slope between the rising edge and the falling edge. The smaller the slope of the edge 110, the longer the transition period P3. The smaller the slope of the edge 110, the longer the communication control unit 70 can make the stop period P1.

[0154] The communication control unit 70 can control the length of the stop period P1 according to the power supply voltage VDD of the output device 200. The larger the power supply voltage VDD is, the longer the transition period P3 is. The larger the power supply voltage VDD is, the longer the communication control unit 70 can make the stop period P1.

[0155] The communication control unit 70 can control the length of the stop period P1 in accordance with the capacity of the load connected to the output device 200. The larger the capacity of the load, the longer the transition period P3. The larger the capacity of the load, the longer the communication control unit 70 can make the stop period P1.

[0156] The low-side circuit 50 can control the cycle of the clock signal CLK_L in accordance with the length of the output period P2. The length of the output period P2 can be the length of the output period P2 when the control signal DRVIN presents an H logic, the length of the output period P2 when the control signal DRVIN presents an L logic, or the shorter of these lengths.

[0157] By setting the stop period P1, the output period P2 becomes shorter, and the number of pulses of the clock signal CLK included in the output period P2 becomes less. The high-side circuit 10 outputs the high-side state signal HSD_U corresponding to the pulses of the clock signal CLK. Therefore, if the number of pulses of the clock signal CLK included in the output period P2 becomes less, the number of bits that can be transmitted during one output period P2 will decrease. The shorter the output period P2, the shorter the period of the clock signal CLK_L can be made by the low-side circuit 50. The low-side circuit 50 can control the period of the clock signal CLK_L in such a way that one output period P2 includes pulses of the clock signal CLK_L greater than the set value. Thus, the high-side state signal HSD_U of the set number of bits can be transmitted during one output period P2.

[0158] The high-side circuit 10 can control the content of the data included in the high-side state signal HSD_U corresponding to the length of the output period P2. The shorter the output period P2, the less data the high-side circuit 10 can include in the high-side state signal HSD_U. For example, the high-side circuit 10 can select the content of the data included in the high-side state signal HSD_U corresponding to the length of the output period P2. Figure 3 The number of detection results included in the high-side state signal HSD_U among the voltage detection results, current detection results and temperature detection results described in .

[0159] Fig.14 It is shown Fig.12 The high-side circuit 10 of this example has a block diagram of a configuration example. Figure 3 The high-side circuit 10 shown in FIG. 1 is similar in structure to the high-side circuit 10 shown in FIG. However, the clock signal CLK_U from the low-side circuit 50 is input to the state signal generating unit 20 of this example. The state signal generating unit 20 outputs the high-side state signal HSD_U in response to the pulse of the clock signal CLK_U. Therefore, by controlling the clock signal CLK_U, it is possible to control whether the high-side state signal USD_U is output.

[0160] Fig.15 It is shown Fig.12 The low-side circuit 50 of this example has a block diagram of a configuration example. Figure 4 The input circuit 62 of this example is an input-output circuit that receives the high-side state signal HSD_L and outputs the clock signal CLK_L. The communication control unit 70 controls whether to output the clock signal CLK_L of the input circuit 62. As described above, by controlling the clock signal CLK_L, it is possible to control whether to output the high-side state signal USD_U.

[0161] The communication control unit 70 of this example is provided outside the low-side circuit 50. In other examples, the communication control unit 70 may be provided inside the low-side circuit 50. The input circuit 62 may also function as the communication control unit 70. The communication control unit 70 may operate according to the reference voltage of the low-side circuit 50.

[0162] Fig.16 It is shown Figures 12 to 15 FIG. 1 is a block diagram of a configuration example of the state signal generating unit 20 and the input circuit 62 in the driving device 100 shown in FIG. Figure 5 The state signal generating unit 20 shown in FIG. 1 further includes an input circuit 72. Fig.16 In Figure 5The selection circuit 21, the signal synthesizing unit 22, the pulse generating unit 24, and the oscillation circuit 25 shown are collectively referred to as the high-side communication circuit 71. The high-side communication circuit 71 may further include other configurations.

[0163] The input circuit 72 receives the clock signal CLK_U and outputs the internal clock signal CKU. The internal clock signal CKU may have the same pulse pattern as the clock signal CLK_U. Each component of the high-side communication circuit 71 may operate in accordance with the pulse of the internal clock signal CKU. Thus, the high-side communication circuit 71 outputs the high-side state signal SS during the input of the clock signal CLK_U, and stops generating and outputting the high-side state signal SS if the input of the clock signal CLK_U stops.

[0164] Relative to Figure 5 The input circuit 62 shown in FIG. 1 further includes an output unit 74. Fig.16 In Figure 5 The edge detection circuit 64, latch circuit 65, timer circuit 67 and control circuit 68 shown are collectively referred to as a low-side communication circuit 73. The low-side communication circuit 73 of this example further has a configuration for outputting an internal clock CKL to an output unit 74.

[0165] The communication control section 70 controls whether the internal clock CKL is output from the low-side communication circuit 73 to the output section 74. The communication control section 70 may be provided in the low-side communication circuit 73.

[0166] The output unit 74 outputs a clock signal CLK_L in response to the internal clock CKL. The clock signal CLK_L may have the same pulse pattern as the internal clock CKL. With such a configuration, the period during which the high-side communication circuit 71 outputs the high-side state signal SS can be controlled using the clock signal CLK_L.

[0167] Fig.17 1 is a diagram showing an example of a high-voltage element 33. The high-voltage element 33 of this example has a capacitor 31 provided between the high-side circuit 10 and the low-side circuit 50. The high-voltage element 33 has a capacitor 31 for each signal to be transmitted. The high-voltage element 33 of this example has a capacitor 31 for each clock signal CLK and the high-side state signal HSD. Fig.17 In the example of , the clock signal CLK and the high-side state signal HSD are differential signals. In this case, two capacitors 31 are provided for each clock signal CLK and high-side state signal HSD. The capacity of each capacitor 31 may be smaller than 1 pF. The capacity of the capacitor 31 may be larger than 0.05 pF.

[0168] By using the capacitor 31 in the transmission unit 30, the circuit cost can be reduced. On the other hand, by using the capacitor 31, the transmission unit 30 becomes easily affected by the operation of the output device 200. In this example, since the transmission of the high-side state signal HSD is stopped corresponding to the transition timing of the output device 200, the high-side state signal HSD and the clock signal CLK can be transmitted with high accuracy using a low-cost transmission unit 30.

[0169] Fig.18 is a diagram showing an example of the output unit 74. The output unit 74 of this example has a buffer 81, an inverter 82, a diode 83, and a diode 84. The buffer 81 outputs the internal clock CKL as a clock signal CLK_LP. The inverter 82 inverts the logic value of the internal clock CKL and outputs it as a clock signal CLK_LN. The diode 83 clamps the voltage at the output end of the buffer 81 below a certain voltage. The diode 84 clamps the voltage at the output end of the inverter 82 below a certain voltage. With such a configuration, the output unit 74 outputs differential clock signals CLK_LP and CLK_LN. It should be noted that the output circuit 23 may also have the same configuration as the output unit 74. In the output circuit 23, the high-side state signal SS is input to the buffer 81 and the inverter 82, and the differential high-side state signals HSD_UP and HSD_UN are output.

[0170] Fig.19 1 is a diagram showing an example of input circuit 72. Input circuit 72 generates internal clock signal CKU from differential clock signals CLK_UP and CLK_UN. Input circuit 72 of this example includes differential circuit 91, pull-up resistor 87, pull-up resistor 88, diode 85, diode 86, pull-down resistor 89, and pull-down resistor 90.

[0171] The differential circuit 91 outputs the internal clock signal CKU corresponding to the difference between the clock signals CLK_UP and CLK_UN. Thus, the common mode noise can be removed. The pull-up resistor 87 connects the transmission path of the clock signal CLK_UP to the high potential VDDU. The pull-down resistor 89 connects the transmission path to the reference potential GNDU. The diode 85 clamps the voltage of the transmission path to a certain voltage or less. The pull-up resistor 88 connects the transmission path of the clock signal CLK_UN to the high potential VDDU. The pull-down resistor 90 connects the transmission path to the reference potential GNDU. The diode 86 clamps the voltage of the transmission path to a certain voltage or less. It should be noted that the input unit 63 can also have the same structure as the input circuit 72. In the input unit 63, the high-side state signal HSD_L is input instead of the clock signal CLK_U, and the input signal DI is output instead of the internal clock signal CKU. In addition, in the input section 63 , the high potential VDDL and the reference potential GNDL of the low-side circuit 50 are applied instead of the high potential VDDU and the reference potential GNDU of the high-side circuit 10 .

[0172] Fig. 20 is a diagram showing an example of a time waveform of each signal of the driving device 100. Fig. 20 In FIG. 1 , only the waveform of one side of the differential signal (N side) is shown. As described above, the communication control unit 70 stops outputting the internal clock CKL of the low-side communication circuit 73 from the transition moment of the control signal DRVIN until the stop period P1 has passed. Therefore, during the stop period P1, the clock signal CLK_LN and the clock signal CLK_UN have no pulses. Fig. 20 In the embodiment, the waveform of the clock signal CLK_UN is blunted by the capacitor 31.

[0173] The internal clock signal CKU of the high-side circuit 10 has the same pulse pattern as the clock signal CLK_UN. However, the waveform of the internal clock signal CKU is shaped by the input circuit 72 .

[0174] The high-side communication circuit 71 outputs a high-side state signal SS in response to the pulse of the internal clock signal CKU. The high-side state signal SS in this example is a signal whose pulse width is modulated in response to the value of the information to be transmitted. The high-side state signal SS has no pulse during the stop period P1. Similarly, the high-side state signals HSD_UN and LN also have no pulse during the stop period P1. Fig. 20 In the embodiment, the waveform of the high-side state signal HSD_LN is blunted by the capacitor 31 .

[0175] The input unit 63 outputs the input signal DI obtained by shaping the waveform of the high-side state signal HSD_LN. The low-side communication circuit 73 converts the input signal DI into a digital signal DL and outputs it. The low-side communication circuit 73 can also output the digital signal DL during the stop period P1. The data holding circuit 66 outputs a digital signal DOUT corresponding to the digital signal DL.

[0176] Fig.21 It is shown Figures 12 to 15 1 is a block diagram of another configuration example of the state signal generating unit 20 and the input circuit 62 in the driving device 100 shown in FIG. The state signal generating unit 20 of this example has an input-output circuit 93 instead of the output circuit 23. The input circuit 62 of this example has an input-output unit 94 instead of the input unit 63. Figures 12 to 20 The same as any of the examples described in .

[0177] The input / output circuit 93 and the input / output unit 94 of this example transmit signals bidirectionally to each other. Figures 12 to 20 Similarly to the example of , the high-side state signal HSD_U is outputted in correspondence with the high-side state signal SS. In addition, the low-side signal LSD_U from the low-side circuit 50 is inputted to the input-output circuit 93 of this example. The input-output circuit 93 generates an input signal SDU in correspondence with the low-side signal LSD_U and inputs it to the high-side communication circuit 71. The low-side signal LSD_U can be a signal for controlling the operation of the high-side circuit 10.

[0178] The input / output circuit 93 may receive an output control signal DOEU for switching between outputting a high-side state signal HSD_U corresponding to the high-side state signal SS and outputting an input signal SDU corresponding to the low-side signal LSD. The output control signal DOEU may be generated by the high-side communication circuit 71 .

[0179] The input / output unit 94 and Figures 12 to 20 Similarly to the example of , the input signal DI is outputted in accordance with the high-side state signal HSD_L. In addition, the input / output unit 94 of this example outputs the low-side signal LSD_L in accordance with the low-side signal DOUTL.

[0180] A control signal DOEL can be input to and output from the input / output unit 94. This output control signal DOEL switches whether to output a low-side signal LSD_L corresponding to the low-side signal DOUTL or an input signal DI corresponding to the high-side status signal HSD_L. The low-side signal LSD_L and the output control signal DOEL can be generated by the low-side communication circuit 73. The communication control unit 70 can stop the output of the low-side signal LSD_L by setting the logical value of the output control signal DOEL to the L logic during the stop period P1. Alternatively, the communication control unit 70 can also stop the output of the low-side signal DOUTL from the low-side communication circuit 73 during the stop period P1.

[0181] Fig. 22 FIG. is an example diagram showing the input / output circuit 93. The input / output circuit 93 in this example includes a buffer 107, an inverter 108, diodes 101, 102, pull-up resistors 105, 106, pull-down resistors 103, 104, a differential circuit 109, input / output terminals 111, and input / output terminals 112.

[0182] The pull-up resistor 105 connects the input / output terminal 111 to the high potential VDDU. The pull-down resistor 103 connects the input / output terminal 111 to the reference potential GNDU. The diode 101 clamps the voltage of the input / output terminal 111 to a certain voltage or below. The pull-up resistor 106 connects the input / output terminal 112 to the high potential VDDU. The pull-down resistor 104 connects the input / output terminal 112 to the reference potential GNDU. The diode 102 clamps the voltage of the input / output terminal 112 to a certain voltage or below.

[0183] The buffer 107 outputs a high-side status signal SS. The inverter 108 outputs a signal obtained by inverting the high-side status signal SS. Here, the output control signal DOEU is input to the power supply terminals of the buffer 107 and the inverter 108. When the output control signal DOEU shows the L logic (reference potential), the buffer 107 and the inverter 108 output a high impedance regardless of the logical value of the high-side status signal SS.

[0184] When the output control signal DOEU shows the H logic, the buffer 107 outputs a high-side status signal HSD_UP corresponding to the high-side status signal SS to the input / output terminal 111. When the output control signal DOEU shows the H logic, the inverter 108 outputs a high-side status signal HSD_UN obtained by inverting the high-side status signal SS to the input / output terminal 112. In this case, the differential circuit 109 can output an input signal SDU corresponding to the difference between the high-side status signal SS and the inverted signal of the high-side status signal SS.

[0185] When the output control signal DOEU shows L logic, the low-side signal LSD_UP and the low-side signal LSD_UN are input to the differential circuit 109 via the input / output terminal 111 and the input / output terminal 112. In this case, the differential circuit 109 outputs an input signal SDU corresponding to the difference between the low-side signal LSD_UP and the low-side signal LSD_UN.

[0186] The input / output unit 94 may also have the same configuration as Fig. 22 the input / output circuit 93. In the input / output unit 94, the low-side signal DOUTL and the output control signal DOEL are input instead of the high-side state signal SS and the output control signal DOEU, and the input signal DI is output instead of the input signal SDU. In addition, the input / output terminal 111 is input with the high-side state signal HSD_LP and outputs the low-side signal LSD_LP. The input / output terminal 112 is input with the high-side state signal HSD_LN and outputs the low-side signal LSD_LN.

[0187] As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious that various changes or improvements can be made to the above embodiments by those skilled in the art. It can be clearly understood from the claims that the embodiments to which such changes or improvements are applied can also be included in the technical scope of the present invention.

Claims

1. A driving device, characterized in that: It is a driver for power semiconductors and has: First Circuit; Second Circuit; a state signal generating unit that generates a first state signal indicating a state of the first circuit using a digital value of a plurality of bits; and A communication control unit controls an output period of the first circuit outputting the first state signal based on a load state signal indicating a transition timing between on and off of the power semiconductor.

2. The driving device according to claim 1, characterized in that: The communication control unit allows output of the first state signal after a predetermined stop period has elapsed from a time when the power semiconductor is switched from on to off.

3. The driving device according to claim 1, characterized in that: The first circuit outputs the first state signal in response to a clock signal input from the second circuit, The communication control unit controls an input period of the clock signal from the second circuit to the first circuit based on the load state signal.

4. The driving device according to claim 2, characterized in that: The communication control unit controls the stop period according to the characteristics of the power semiconductor.

5. The driving device according to claim 2, characterized in that: The communication control unit controls the stop period according to the magnitude of a power supply voltage applied to the power semiconductor.

6. The driving device according to claim 2, characterized in that: The communication control unit controls the stop period according to the capacity of a load connected to the power semiconductor.

7. The driving device according to claim 3, characterized in that: The second circuit controls a cycle of the clock signal in accordance with a length of the output period.

8. The driving device according to any one of claims 1 to 7, characterized in that: The first circuit is a low-side circuit that operates according to a first reference voltage. The second circuit is a high-side circuit that operates according to a second reference voltage higher than the first reference voltage. The driving device further includes a transmission unit that converts a reference voltage of the first state signal in accordance with the first reference voltage and transmits the first state signal obtained by converting the reference voltage to the low-side circuit.

9. The driving device according to claim 8, characterized in that: The transmission section has a capacitor provided between the high-side circuit and the low-side circuit.

10. A driving device, characterized in that: It is a driver for power semiconductors and has: a low-side circuit that operates according to a first reference voltage; a high-side circuit operating according to a second reference voltage higher than the first reference voltage; a state signal generating unit for generating a high-side state signal representing a state of the high-side circuit using a digital value of a plurality of bits; as well as A transmission unit converts a reference voltage of the high-side state signal corresponding to the first reference voltage, and transmits the high-side state signal obtained by converting the reference voltage to the low-side circuit.

11. The driving device according to claim 10, characterized in that: The low-side circuit includes a transmission unit that transmits the high-side state signal to the outside.

12. The driving device according to claim 11, characterized in that: The low-side circuit generates a low-side state signal indicating a state of the low-side circuit using a digital quantity, The transmitting section outputs the high-side state signal and the low-side state signal from a common terminal.

13. The driving device according to any one of claims 10 to 12, characterized in that: The transmission section includes an insulating element that transmits the high-side state signal in a state where the high-side circuit and the low-side circuit are electrically insulated.

14. The driving device according to any one of claims 10 to 12, characterized in that: The transmission unit includes a level conversion circuit that converts a signal level of the high-side state signal in accordance with the first reference voltage.

15. The driving device according to any one of claims 10 to 12, characterized in that: The high-side state signal has a plurality of bit times corresponding to the plurality of bits of the digital quantity, and a signal level in each bit time indicates a value corresponding to a value of each bit of the digital quantity.

16. The driving device according to claim 15, characterized in that: The state signal generating unit comprises: a pulse generating unit for generating a start pulse indicating a start time of each of the bit times and an end pulse indicating an end time of each of the bit times; as well as A signal synthesizing unit generates the high-side state signal including the start pulse and the end pulse and causing a signal level in a period between the start pulse and the end pulse to be a level corresponding to the digital amount.

17. The driving device according to claim 16, characterized in that: The polarities of the start pulse and the end pulse are inverted.

18. The driving device according to claim 16, characterized in that: The low-side circuit extracts the start time or the end time of each bit time in the high-side state signal received from the transmission unit, and detects the signal level of the high-side state signal at a detection time preset based on the start time or the end time.

19. The driving device according to any one of claims 10 to 12, characterized in that: The drive device further includes a communication control unit configured to control a period during which the high-side circuit outputs the high-side state signal based on a load state signal indicating a timing of transition between on and off of the power semiconductor.

20. The driving device according to claim 19, characterized in that The communication control unit allows output of the high-side state signal after a predetermined period has elapsed from a time when the power semiconductor is switched between on and off.

21. The driving device according to claim 19, characterized in that The high-side circuit outputs the high-side state signal corresponding to the clock signal input from the low-side circuit, The communication control unit controls a period during which the clock signal is input from the low-side circuit to the high-side circuit based on the load state signal.

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