Decision path randomization system and method applied to split SAR ADC (Synthetic Aperture Radar Analog to Digital Converter)

Abstract

The invention relates to a decision path randomization system and method applied to a split type SAR ADC, the system comprises an SAR logic module, a capacitor array, a pseudo-random number generator and a segment distribution logic module, the input end of the SAR logic module is connected with the capacitor array, the output end of the SAR logic module is connected with the input end of the segment distribution logic module, and the input end of the segment distribution logic module is connected with the pseudo-random number generator. The output end of the pseudo-random number generator is connected with the input end of a segment distribution logic module, the generated pointer number Dpoint is output to the segment distribution logic module, the output end of the segment distribution logic module is connected with a capacitor array, the segment distribution logic module processes the Dpoint to generate a high-segment digital code value dM and a low-segment digital code value dL, the high-segment digital code value dM and the low-segment digital code value dL are input into the capacitor array, and the capacitor array is connected with the high-segment digital code value dM and the low-segment digital code value dL. And controlling the on-off state of the capacitor array. Under the condition that the total area of the capacitor array and the complexity of circuit design are kept unchanged, the number of switches and calibration parameters are reduced exponentially, the required calculation amount and storage space are reduced, the hardware overhead is reduced, and the power consumption in a digital calibration module is reduced.

Description

Technical Field

[0001] The present invention relates to a decision path randomization system and method applied to a split-type SAR ADC, belonging to the technical field of analog integrated circuits. Background Art

[0002] Analog-to-Digital Converter (ADC) can realize the conversion of analog signals to digital signals. Designing a data converter with excellent performance has become a key issue in circuit design. ADC converts analog signals with continuous time and amplitude into corresponding discrete digital signals, which is convenient for subsequent information processing, storage and transmission. Realizing low power consumption, high speed and high precision ADC has become the main trend of current design.

[0003] The core unit of capacitive SAR ADC is the digital-to-analog converter (DAC), which uses the charge distribution principle to implement binary search of voltage. However, due to the influence of the process, capacitor mismatch will reduce the accuracy of SAR ADC. Therefore, a specific calibration method should be used to calibrate the capacitor mismatch to reduce the influence of the process on the accuracy of SAR ADC. Digital calibration is the mainstream of current calibration technology, among which split SAR ADC calibration is very common.

[0004] In order to ensure effective calibration when the input is a DC signal, split SAR ADC usually adopts a decision path randomization method based on the segmented capacitor array. However, in the traditional split SAR ADC decision path randomization method, using the same unit capacitor in each segment of the capacitor array will cause the number of switches and calibration parameters to increase exponentially with the increase of the number of binary bits. The corresponding required calculation amount and storage space also increase exponentially with the increase of the number of binary bits, and the power consumption of the digital calibration module is also greatly increased.

[0005] By changing the size of the unit capacitor corresponding to the high-order code value in the sub-capacitor array, the number of switches and calibration parameters can be reduced exponentially while the total area of ​​the capacitor array and the complexity of the circuit design remain unchanged, and the required amount of calculation and storage space can be reduced, thereby reducing hardware overhead and reducing power consumption in the digital calibration module. Unused capacitors are added to each segment of the sub-capacitor array. For any given conversion cycle, the diversity of capacitor segment allocation selection, that is, the diversity of SARADC decision paths, can be ensured to increase the non-singularity of the coefficient matrix and effectively extract calibration information. The number of decision paths in each segment of the sub-capacitor array can also be adjusted by changing the number of unused low-order capacitors in each segment of the sub-capacitor array. Summary of the invention

[0006] The object of the present invention is to overcome the shortcomings and deficiencies of the prior art and to provide a decision path randomization system and method for a split-type SAR ADC, which can reduce the number of switches and calibration parameters by multiples while keeping the total area of ​​the capacitor array and the complexity of circuit design unchanged, thereby reducing the required amount of calculation and storage space, thereby reducing hardware overhead and reducing power consumption in a digital calibration module.

[0007] By adding unused capacitors to the sub-capacitor array, for any given conversion cycle, the diversity of capacitor segment allocation selection, that is, the diversity of SAR ADC decision paths, can be ensured, the non-singularity of the coefficient matrix can be increased, and the calibration information can be effectively extracted. In addition, the number of decision paths of each sub-capacitor array can be adjusted by changing the number of unused low-order capacitors in each sub-capacitor array, thereby effectively calibrating the influence of non-ideal factors such as capacitor mismatch, parasitic capacitance, temperature drift, aging, etc. in the actual circuit, thereby improving the accuracy of the circuit.

[0008] The technical solution of the present invention is as follows:

[0009] A decision path randomization system for a split SAR ADC includes: a SAR logic module, a capacitor array, a pseudo-random number generator, and a segment allocation logic module, wherein:

[0010] The input end of the SAR logic module is connected to a capacitor array, the output end of the SAR logic module is connected to the input end of the segment allocation logic module, the comparator result Di (1≤i≤4) is output to the segment allocation logic module, the output end of the pseudo-random number generator is connected to the input end of the segment allocation logic module, the generated pointer number Dpoint is output to the segment allocation logic module, the output end of the segment allocation logic module is connected to a capacitor array, and the segment allocation logic module generates a high-segment digital code value d after processing Dpoint M And the low-order digital code value d L , and input it into the DAC switch network in the capacitor array to control the switching state of the capacitor array.

[0011] The segment allocation logic module allocates the segment to the logical code value d Mi (0≤i≤2),d Li (0≤i≤3) is output to the DAC switch network, which is used to control the unit capacitance C Mi (0≤i≤2), C Li (0≤i≤3) switching state.

[0012] Preferably according to the present invention, the capacitor array includes an upper array and a lower array. The lower array includes a DAC switch network, a sampling capacitor, a redundant capacitor, and a comparator. 16-bit sampling capacitors are provided, and 1 redundant capacitor is provided in parallel for every 3 sampling capacitors. Every 3 sampling capacitors and 1 redundant capacitor form 1 sub-array. The 4 sampling capacitors of the highest bit form a sub-array alone without a redundant capacitor. Except for the 2 sub-arrays of the highest bit, the remaining adjacent sub-arrays are connected by bridging capacitors. The sampling capacitors and the redundant capacitors are both connected to the DAC switch network. The sub-arrays of the highest bit and the second highest bit are output terminals and are connected to the negative input terminal of the comparator, and the voltage of its upper plate is V TP ; during sampling, the lower plates of all capacitors are connected to Vin, and after sampling is completed, they are disconnected and connected to +Vref or -Vref according to the result after the bit conversion of the analog-to-digital converter.

[0013] The structure and connection method of the upper array are the same as those of the lower array, and the upper array is connected to the positive input terminal of the comparator.

[0014] Preferably according to the present invention, the highest-bit sampling capacitor in the sub-array is composed of 2 unit capacitors C Mi ; the second highest-bit sampling capacitor is composed of 1 unit capacitor C Mi ; the third-bit sampling capacitor is composed of 2 unit capacitors C Li ; the lowest-bit sampling capacitor is composed of 1 unit capacitor C Li ; the sub-array also includes 1 unused unit capacitor C Li .

[0015] Further preferably according to the present invention, C Mi and C Li satisfy: C Mi = 4C Li .

[0016] The randomization method of the above decision path randomization system applied to the split-type SAR ADC is as follows:

[0017] (1) The pseudo-random number generator randomly generates a value within the range of 0-11 as the pointer number Dpoint. The pointer number Dpoint is respectively converted into the high-bit pointer Point_M and the low-bit pointer Point_L through the segment allocation logic module. The high-bit pointer Point_M is converted into a 3-bit high-segment digital code value d M0 、d M1 、d M2 , and the low-bit pointer Point_L is converted into a 4-bit low-segment digital code value d L0 、d L1 、d L2 、d L3 ;

[0018] (2) The 3-bit high-segment digital code value dM0 d M1 d M2 Used to convert the D 1 , D 2 The code value is assigned to the DAC switch network to control the upper 3-bit unit capacitor C M0 , C M1 , C M2 The switch status, 4-bit low-order digital code value d L0 d L1 d L2 d L3 Used to convert the D 3 , D 4 The code value is assigned to the DAC switch network to control the lower 4-bit unit capacitance C L0 , C L1 , C L2 , C L3 ,The required number of switches and calibration parameters for each sub-array is 7.

[0019] In each sub-array, 7 switches correspond to C M0 , C M1 , C M2 , C L0 , C L1 , C L2 , C L3 , the calibration parameter refers to the unit capacitance C to be calibrated Mi (0≤i≤2), C Li (0≤i≤3), so the number of switches and calibration parameters required in each sub-array is 7.

[0020] When all capacitors are calibrated as independent parameters, the number of switches and calibration parameters required for the total capacitor array of a sub-ADC is 35, and the coefficient matrix dA / dB has 35 bits. For the split-type SAR ADC, the number of switches and calibration parameters required is 70 in total, and the coefficient matrix dA and dB has 70 bits.

[0021] According to a preferred embodiment of the present invention, in step (1), when an unused low-bit capacitor is added to each segment sub-array, the segment allocation logic module generates the decoding of the pointer number Dpoint in the following manner:

[0022] Point_M=D_point mod 3(0≤Point_M≤2)

[0023] Point_L=D_point mod 4(0≤Point_L≤3)

[0024] d Mi=(i+3-Point_M)mod 3(0≤i≤2)

[0025] d L i =(i+4-Point_L)mod 4(0≤i≤3)

[0026] Where mod represents the remainder operation, i+3-Point_M, i+4-Point_L prevents negative numbers.

[0027] According to the preferred embodiment of the present invention, in step (2), the D of the SAR logic module 1 , D 2 , D 3 , D 4 Code value d for the segment allocation logic module Mi d Li The allocation is as follows:

[0028]

[0029] In the traditional split-type SAR ADC decision path randomization method, using the same unit capacitor in each sub-capacitor array will cause the number of switches and calibration parameters to increase exponentially with the increase of the number of binary bits. The corresponding required calculation amount and storage space also increase exponentially with the increase of binary bits, and the power consumption of the digital calibration module is also greatly increased.

[0030] By changing the size of the unit capacitor corresponding to the high-order code value in the sub-capacitor array, the number of switches and calibration parameters can be reduced while the total area of ​​the capacitor array and the complexity of the circuit design remain unchanged, thereby reducing the required calculation amount and storage space, and reducing the power consumption in the digital calibration module and reducing hardware overhead.

[0031] Unused capacitors are added to each segment of the capacitor array. For any given conversion cycle, the diversity of capacitor segment allocation selection, that is, the diversity of SAR ADC decision paths, can be ensured to increase the non-singularity of the coefficient matrix dA, dB and effectively extract the calibration information.

[0032] The number of decision paths of each sub-capacitor array can be adjusted by changing the number of unused low-order capacitors in each sub-capacitor array. When one unused low-order capacitor is added to each sub-capacitor array, there are 12 decision paths for each sub-capacitor array, and the calibration parameters are 7. If two unused low-order capacitors are added to each sub-capacitor array, the number of decision paths for each sub-capacitor array is increased to 15, and the calibration parameters are 8. In this way, the number of decision paths is proportionally increased without increasing the area and calibration parameters, and the non-singularity of the coefficient matrices dA and dB is increased.

[0033] Compared with the prior art, the present invention has the following advantages and effects:

[0034] 1. The present invention can reduce the number of switches required for the DAC switch network by multiples, thereby reducing hardware overhead.

[0035] 2. The present invention can reduce calibration parameters exponentially, thereby reducing the required amount of calculation and storage space and reducing power consumption in the digital calibration module.

[0036] 3. The present invention can improve the calibration parameter update frequency of the split SAR ADC digital calibration. Since the present invention reduces the number of calibration parameters, a calibration parameter update can be performed with a smaller number of conversion intervals, thereby improving the calibration parameter update frequency.

[0037] 4. The circuit design of the present invention is highly flexible and can adjust the number of decision paths of each sub-capacitor array by changing the number of unused low-order capacitors in each sub-capacitor array, thereby proportionally increasing the number of decision paths with almost no increase in area and calibration parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the control logic of the segment allocation logic module for decoding the pointer number Dpoint and the code value Di generated by the SAR logic module for the unit capacitance in the highest segment sub-array of the present invention.

[0039] Figure 2 It is a partial structural schematic diagram of the capacitor array of the present invention.

[0040] Figure 3 Schematic diagram of the sub-array structure of the present invention and its corresponding unit capacitance. DETAILED DESCRIPTION

[0041] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

[0042] Example

[0043] like Figure 1 As shown, this embodiment provides a decision path randomization system applied to a split SAR ADC, including: a SAR logic module, a capacitor array, a pseudo-random number generator and a segment allocation logic module, wherein:

[0044] The input end of the SAR logic module is connected to a capacitor array, the output end of the SAR logic module is connected to the input end of the segment allocation logic module, the comparator result Di (1≤i≤4) is output to the segment allocation logic module, the output end of the pseudo-random number generator is connected to the input end of the segment allocation logic module, the generated pointer number Dpoint is output to the segment allocation logic module, the output end of the segment allocation logic module is connected to a capacitor array, and the segment allocation logic module generates a high-segment digital code value d after processing Dpoint M And the low-order digital code value d L , and input it into the DAC switch network in the capacitor array to control the switching state of the capacitor array.

[0045] The segment allocation logic module allocates the segment to the logical code value d Mi (0≤i≤2),d Li (0≤i≤3) is output to the DAC switch network, which is used to control the unit capacitance C Mi (0≤i≤2), C Li (0≤i≤3) switching state.

[0046] The capacitor array includes an upper array and a lower array. The lower array includes a DAC switch network, a sampling capacitor, a redundant capacitor and a comparator. A 16-bit sampling capacitor is set. Every 3 sampling capacitors are connected in parallel with a redundant capacitor. Every 3 sampling capacitors and a redundant capacitor form a sub-array. The highest 4 sampling capacitors are separately composed of a sub-array without redundant capacitors. Except for the highest 2-segment sub-array, the other adjacent sub-arrays are connected by bridge capacitors. The sampling capacitors and redundant capacitors are connected to the DAC switch network. The highest and second highest sub-arrays are output terminals, connected to the negative input terminal of the comparator, and their upper plate voltage is V TP ; During sampling, the lower plates of all capacitors are connected to Vin, and after sampling, they are disconnected and connected to +Vref or -Vref according to the result after the analog-to-digital converter bit conversion.

[0047] The structure and connection method of the upper array are the same as those of the lower array, and the upper array is connected to the positive input terminal of the comparator.

[0048] The array structure is shown below: Figure 2 As shown, the sampling capacitor is C bi (1≤i≤16), the redundant capacitor is C b4R , C b7R , C b10R , C b13R , the bridge capacitance is C bri (1≤i≤3).

[0049] The highest bit sampling capacitor in the subarray consists of two unit capacitors C Mi The second highest sampling capacitor consists of 1 unit capacitor C MiThe third sampling capacitor consists of 2 unit capacitors C Li The lowest sampling capacitor consists of 1 unit capacitor C Li The subarray also includes an unused unit capacitor C Li .

[0050] Taking the highest segment array as an example, the highest bit sampling capacitor C b1 The two unit capacitors C Mi Composition, the second highest sampling capacitor C b2 By a unit capacitor C Mi The third sampling capacitor C b3 The two unit capacitors C Li The lowest sampling capacitor C b4 By a unit capacitor C Li Composition, the highest segment subarray C Li is 500pF, and the C Li It is 63pF.

[0051] C Mi and C Li Satisfaction: C Mi =4C Li .

[0052] The randomization method of the decision path randomization system applied to the split SAR ADC described above has the following steps:

[0053] (1) The pseudo-random number generator randomly generates a value in the range of 0-11 as the pointer number Dpoint. The pointer number Dpoint is converted into a high-order pointer Point_M and a low-order pointer Point_L through the segment allocation logic module. The high-order pointer Point_M is converted into a 3-bit high-segment digital code value d M0 d M1 d M2 , the low-order pointer Point_L is converted to the 4-bit low-order digital code value d L0 d L1 d L2 d L3 ;

[0054] (2) 3-digit high-order digital code value d M0 d M1 d M2 Used to convert the D 1 , D 2 The code value is assigned to the DAC switch network to control the upper 3-bit unit capacitor C M0 , C M1 , C M2 The switch status, 4-bit low-order digital code value dL0 d L1 d L2 d L3 Used to convert the D 3 , D 4 The code value is assigned to the DAC switch network to control the lower 4-bit unit capacitance C L0 , C L1 , C L2 , C L3 ,The required number of switches and calibration parameters for each sub-array is 7.

[0055] In each sub-array, 7 switches correspond to C M0 , C M1 , C M2 , C L0 , C L1 , C L2 , C L3 , the calibration parameter refers to the unit capacitance C to be calibrated Mi (0≤i≤2), C Li (0≤i≤3), so the number of switches and calibration parameters required in each sub-array is 7.

[0056] When all capacitors are calibrated as independent parameters, the number of switches and calibration parameters required for the total capacitor array of a sub-ADC is 35, and the coefficient matrix dA / dB has 35 bits. For the split-type SAR ADC, the number of switches and calibration parameters required is 70 in total, and the coefficient matrix dA and dB has 70 bits.

[0057] In step (1), when an unused low-bit capacitor is added to each segment sub-array, the segment allocation logic module generates the decoding of the pointer number Dpoint in the following manner:

[0058] Point_M=D_point mod 3(0≤Point_M≤2)

[0059] Point_L=D_point mod 4(0≤Point_L≤3)

[0060] d Mi =(i+3-Point_M)mod 3(0≤i≤2)

[0061] d L i =(i+4-Point_L)mod 4(0≤i≤3)

[0062] Where mod represents the remainder operation, i+3-Point_M, i+4-Point_L prevents negative numbers.

[0063] In step (2), the D of the SAR logic module 1 , D 2 , D 3 , D 4 Code value d for the segment allocation logic module Mi d Li The allocation is as follows:

[0064]

[0065] The following table shows the pointer numbers Dpoint, Point_M, Point_L and the thermometer code value d in this embodiment. M d L Table 1 shows the corresponding relationship between the high-order capacitor C pointed to by the high-order pointer Point_M when an unused low-order unit capacitor is added to each sub-array. M The digital code value d M is 0, and the other high-position capacitors C M The digital code value d M The next ones are 1, 2, and the high-order capacitor C with a digital code value of 0 or 1 M The combination is the highest capacitor C b1 , and the digital code value is then assigned to D 1 , the high-order capacitor C with a digital code value of 2 M The second highest capacitance C b2 , and the digital code value is then assigned to D 2 The low-order capacitor C pointed to by the low-order pointer Point_L L The digital code value d L is 0, and the other low-position capacitors C L The digital code value d L The following are 1, 2, 3, and the low-order capacitor C with a digital code value of 0 or 1 L The combination is the third capacitor C b3 , and the digital code value is then assigned to D 3 , the low-order capacitor C with a digital code value of 2 L The lowest capacitance C b4 , and the digital code value is then assigned to D 4 , the low-order capacitor C with a digital code value of 3 L is a capacitor not used in this conversion, and the digital code value is subsequently assigned to 0. When an unused low-order unit capacitor is added to each segment, there are 12 decision paths for each segment, which is sufficient to ensure that the coefficient matrices dA and dB are non-singular matrices for DC signals, thereby achieving effective calibration.

[0066] Table 2 shows the pointer numbers Dpoint, Point_M, Point_L and the thermometer code value d M dL According to the corresponding relationship table, when two unused low-order unit capacitors are added to each sub-array, the number of decision paths is proportionally increased without increasing the capacitor array area and calibration parameters. The number of decision paths for each segment is increased to 15, which further improves the randomness of the decision path and the non-singularity of the coefficient matrices dA and dB, thereby achieving effective calibration.

[0067] Table 1: Correspondence table of pointer numbers Dpoint, Point_M, Point_L and thermometer code values ​​dM, dL

[0068] Dpoint Point_M Point_L dM dL 0 0 0 [0 1 2] [0 1 2 3] 1 1 1 [2 0 1] [3 0 1 2] 2 2 2 [1 2 0] [2 3 0 1] 3 0 3 [0 1 2] [1 2 3 0] 4 1 0 [2 0 1] [0 1 2 3] 5 2 1 [1 2 0] [3 0 1 2] 6 0 2 [0 1 2] [2 3 0 1] 7 1 3 [2 0 1] [1 2 3 0] 8 2 0 [1 2 0] [0 1 2 3] 9 0 1 [0 1 2] [3 0 1 2] 10 1 2 [2 0 1] [2 3 0 1] 11 2 3 [1 2 0] [1 2 3 0]

[0069] Table 2: Correspondence between pointer numbers Dpoint, Point_M, Point_L and thermometer code values ​​dM, dL

[0070]

[0071]

[0072] The comparison between the randomization method of this embodiment and the randomization method of the traditional ADC decision path is shown in Table 3 and Table 4. Table 3 is a comparison table of the calibration of the three-segment capacitor array as a whole, and Table 4 is a comparison table of the calibration of all capacitors as independent parameters. According to the comparison, whether the three-segment capacitor array is calibrated as a whole or all capacitors are calibrated as independent parameters, this embodiment can reduce the number of switches and calibration parameters by multiples, and reduce the size of the coefficient matrix dA and dB by multiples, thereby reducing the required calculation amount and storage space and reducing the power consumption in the digital calibration module. Because this embodiment reduces the calibration parameters, it is possible to select a calibration parameter to be updated once per fewer conversion times under the same circumstances, thereby increasing the update frequency of the calibration parameters.

[0073] Table 3: Comparison of the calibration of the three low-range capacitor arrays as a whole

[0074]

[0075] Table 4: Comparison of all capacitors calibrated as independent parameters

[0076]

[0077] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A decision path randomization system for a split SAR ADC, characterized in that: include: SAR logic module, capacitor array, pseudo-random number generator and segment allocation logic module, where: The input end of the SAR logic module is connected to a capacitor array, the output end of the SAR logic module is connected to the input end of the segment allocation logic module, the output end of the pseudo-random number generator is connected to the input end of the segment allocation logic module, and the generated pointer number Dpoint is output to the segment allocation logic module. The output end of the segment allocation logic module is connected to a capacitor array. After processing Dpoint, the segment allocation logic module generates a high-segment digital code value d M And the low-order digital code value d L , and input it into the capacitor array to control the switching state of the capacitor array.

2. The decision path randomization system for split-type SAR ADC according to claim 1, wherein: The capacitor array includes an upper array and a lower array. The lower array includes a DAC switch network, a sampling capacitor, a redundant capacitor and a comparator. A 16-bit sampling capacitor is set. Every 3 sampling capacitors are connected in parallel with a redundant capacitor. Every 3 sampling capacitors and a redundant capacitor form a sub-array. The highest 4 sampling capacitors are separately composed of a sub-array without redundant capacitors. Except for the highest 2-segment sub-array, the other adjacent sub-arrays are connected by bridge capacitors. The sampling capacitors and redundant capacitors are connected to the DAC switch network. The highest and second highest sub-arrays are output terminals, connected to the negative input terminal of the comparator, and their upper plate voltage is V TP ; The structure and connection method of the upper array are the same as those of the lower array, and the upper array is connected to the positive input terminal of the comparator.

3. The decision path randomization system for split-type SAR ADC according to claim 2, characterized in that: The highest bit sampling capacitor in the subarray consists of two unit capacitors C Mi The second highest sampling capacitor consists of 1 unit capacitor C Mi The third sampling capacitor consists of 2 unit capacitors C Li The lowest sampling capacitor consists of 1 unit capacitor C Li The subarray also includes an unused unit capacitor C Li .

4. The decision path randomization system for split-type SAR ADC according to claim 3, characterized in that: C Mi and C Li Satisfaction: C Mi =4C Li .

5. The randomization method of the decision path randomization system applied to the split SAR ADC according to claim 4, characterized in that: Here are the steps: (1) The pseudo-random number generator randomly generates a value in the range of 0-11 as the pointer number Dpoint. The pointer number Dpoint is converted into a high-order pointer Point_M and a low-order pointer Point_L through the segment allocation logic module. The high-order pointer Point_M is converted into a 3-bit high-segment digital code value d M0 ,d M1 ,d M2 , the low-order pointer Point_L is converted to the 4-bit low-order digital code value d L0 ,d L1 ,d L2 ,d L3 ; (2) 3-digit high-order digital code value d M0 ,d M1 ,d M2 It is used to assign the D1 and D2 code values ​​of the SAR logic module to the DAC switch network, respectively controlling the switch state of the upper 3-bit unit capacitor and the lower 4-bit digital code value d L0 ,d L1 ,d L2 ,d L3 It is used to assign the D3 and D4 code values ​​of the SAR logic module to the DAC switch network, respectively controlling the lower 4-bit unit capacitance. The required number of switches and calibration parameters for each sub-array is 7.

6. The randomization method of the decision path randomization system applied to the split SAR ADC according to claim 5, characterized in that: In step (1), when an unused low-bit capacitor is added to each segment sub-array, the segment allocation logic module generates the decoding of the pointer number Dpoint in the following manner: Point_M=D_point mod 3(0≤Point_M≤2) Point_L=D_point mod 4(0≤Point_L≤3) d Mi =(i+3-Point_M)mod 3(0≤i≤2) d Li =(i+4-Point_L)mod 4(0≤i≤3) Where mod represents the remainder operation, i+3-Point_M, i+4-Point_L prevents negative numbers.

7. The randomization method of the decision path randomization system applied to the split SAR ADC according to claim 5, characterized in that: In step (2), the code values ​​of D1, D2, D3, and D4 of the SAR logic module correspond to the code value d of the segment allocation logic module. Mi ,d Li The allocation is as follows:

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