ATE-based high-speed converter clock synchronization method and test system

Abstract

The invention provides a clock synchronization method and a test system of a high-speed converter based on an automatic test equipment (ATE), and relates to the technical field of integrated circuit test. The ATE generates a reference clock signal and sends the reference clock signal to a frequency synthesizer; the frequency synthesizer generates a sampling clock signal and sends the sampling clock signal to the high-speed converter, and additionally generates a re-check clock signal and sends the re-check clock signal back to the ATE; the ATE judges whether the re-check clock signal is normal or not, if the re-check clock signal is normal, synchronization is initiated, and an SYNC pin of the high-speed converter is pulled down; and the ATE collects output data of the high-speed converter, then compares the output data of the high-speed converter in a clock scanning mode until matching of the feature characters is completed, records a time difference between a reference clock signal output by the ATE and the feature characters, and records the difference value into subsequent data collection, so that clock data recovery is completed, and synchronization is realized. According to the invention, synchronization of the sampling clock of the high-speed converter and the ATE can be realized quickly and efficiently, and the test efficiency and stability are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a clock synchronization method and a testing system for a high-speed converter based on ATE. Background Art

[0002] The performance of high-speed analog-to-digital / digital-to-analog converters (HSCs) is generally affected by external circuits such as the power supply, reference voltage, and clock source. The clock source has the greatest impact. The following formula shows that the magnitude of clock jitter directly determines the conversion accuracy of a high-speed converter.

[0003]

[0004] In the above formula, SNR is the signal-to-noise ratio, f is the analog signal frequency, and tj is the clock jitter.

[0005] In addition, the data port of a high-speed converter often outputs a read / write clock, which generally has a certain phase relationship with the sampling clock. The synchronization of the data clock and the sampling clock is required to ensure the validity of the collected / input data.

[0006] After decades of development, automatic test equipment (ATE) has become extremely comprehensive. Its testing features are highly integrated, programmable, and data standardized, resulting in optimal development and testing efficiency in mass production testing of integrated circuits. Therefore, high-speed converter chip measurement still primarily relies on ATE equipment. However, nearly all ATE equipment currently available on the market cannot provide high-performance femtosecond clocks, making it difficult to test high-speed converters.

[0007] Neither the digital nor the analog sources built into ATE can meet the clock testing requirements of high-speed converters. Currently, the highest-end ATE, such as Teradyne's ULTRA FLEX and Advantest's 93k, can output clock signals up to 800MHz, with clock signal jitter typically in the picosecond range. A 14-bit, 250Msps ADC (such as the ADS4449) requires clock jitter of ≤190fs. For high-speed converters operating in the GHz range, clock jitter requirements reach tens of fs, making conventional ATE unable to meet these testing requirements. While Advantest currently offers high-performance clock boards, their signal frequency bands are very narrow (10kHz to 200MHz) and they fail to achieve fs-level performance, making them unsuitable for testing current GHz-level high-speed converters.

[0008] Because the machine clock source cannot meet the test requirements of high-speed converters, external instruments can only be used to provide the clock. However, this cannot guarantee the synchronization of the data clock and the sampling clock, which leads to errors in reading and writing data.

[0009] For example, a 12-bit 6Gsps ADC has a 6GHz sampling clock. When tested using imported Teradyne ULTRAFLEX ATE, the ATE can only provide a maximum clock of 800MHz, and the typical jitter performance is 5ps. According to Formula 1, the SNR is only 24dB, which cannot meet the test requirements.

[0010] Figure 1 This example shows an existing system architecture that adds a high-performance RF signal source external to the ATE to provide a clock for testing. The ATE sends a 100MHz clock to synchronize the signal source. The host computer then sets the signal source's output frequency and amplitude and controls the output via a communication interface (USB, Ethernet, GPIB, etc.). The RF signal source outputs are all single-ended, so a single-ended-to-differential conversion circuit with impedance matching to the ADC must be designed on the test board.

[0011] Using an external high-performance signal source in ATE requires designing a suitable single-ended-to-differential clock matching circuit. External cabling is also more complex, requiring not only connection to the ATE's synchronous clock but also connection of the signal source output to the ATE test platform, which presents a challenge for testing and debugging. Furthermore, each test requires interaction between the ATE and the signal source (to set output frequency, power, etc.). ATE itself is a highly integrated system, requiring a host computer to connect the ATE and signal source. Each test requires the ATE to issue commands to the host computer, which then sets the signal according to preset specifications. Once the signal source outputs, the host computer notifies the ATE to proceed with the test. This communication process is cumbersome and inefficient. Furthermore, high-performance RF signal sources are inherently precision equipment and are expensive, typically costing over one million yuan. Frequent disassembly and assembly of the test platform can easily cause wear and tear on the RF signal source.

[0012] The article "High-Speed, High-Resolution ADC Dynamic Parameter Testing Based on 93000 ATE" (Microelectronics Journal, June 2011) proposes adding a crystal oscillator to the test board (referred to as the loadboard) as the sampling clock for the high-speed ADC. Because the ATE master clock and the crystal oscillator are not synchronized, repeated sampling is used to ensure accurate sampling within the test time window. For testing high-speed ADC dynamic parameters, the number of collected samples is limited; typically, a few thousand data points are sufficient for calculation. This method is effective, but requires more data to be collected for judgment. However, when testing static parameters (such as DNL and INL), the sample size is very large, and this method cannot guarantee error-free acquisition. Because the ATE master clock and the crystal oscillator are not synchronized, it is difficult to guarantee that even a few erroneous data points will be present among the hundreds of thousands of collected data points.

[0013] Moreover, for ultra-high-speed ADCs with sampling rates reaching the GHz level, the data interface is basically a high-speed SERDES interface. The above method is no longer applicable to the current ultra-high-speed AD / DA converters with increasingly faster speeds.

[0014] In addition, there are also some existing technologies such as patent CN201210359789.0 "A method for testing and acquiring data of ADC chips based on non-cognate clocks", which proposes to acquire the output data signal of the ADC chip under test and the sampling clock signal of the ADC chip under test at the same time, increase the acquisition speed to N times of the sampling clock, determine the positions of the rising and falling edges of the sampling clock signal according to the change positions from 0 to 1 and from 1 to 0 in the acquired clock signal, and determine the corresponding test output data of the ADC chip under test in each sampling clock cycle, which can avoid the data acquisition error caused by the accumulation of phase deviations due to different sources of the sampling clock and the ADC output data acquisition clock. However, this patent is based on testing of non-cognate clocks and does not adopt a solution that synchronizes ATE and sampling clocks. Summary of the Invention

[0015] In view of the above problems, the purpose of the present invention is to provide a clock synchronization method and test system for a high-speed converter based on ATE, which can quickly and efficiently synchronize the sampling clock of the high-speed converter with the ATE, thereby improving test efficiency and stability.

[0016] The technical solution adopted by the present invention to achieve its invention object is a clock synchronization method for a high-speed converter based on ATE, comprising the following steps:

[0017] S1. Select a suitable frequency synthesizer based on the clock frequency required by the high-speed converter under test, and configure the frequency synthesizer's multiplication and division coefficients, output signal format, and amplitude through the digital channel module of the automatic test equipment (ATE).

[0018] S2, the digital channel module of the automatic test equipment ATE generates a reference clock signal and sends it to the frequency synthesizer;

[0019] S3. The frequency synthesizer generates the sampling clock signal required for high-speed converter testing and sends it to the high-speed converter. It also generates an output clock as a check signal and sends it back to the digital channel module of the automatic test equipment (ATE) to monitor the status of the output clock.

[0020] S4, the digital channel module of the automatic test equipment ATE determines whether the detected return signal is normal as a standard for determining the normal output of the frequency synthesizer. If it is normal, the process goes to step S5; if it is abnormal, the process goes to step S1 to configure the frequency synthesizer;

[0021] S5. The digital channel module of the automatic test equipment ATE initiates synchronization, that is, pulls the SYNC pin of the high-speed converter low.

[0022] S6, high-speed converter outputs characteristic characters;

[0023] S7. The high-speed serial signal module of the automatic test equipment ATE collects the output data of the high-speed converter, and then compares the output data of the high-speed converter through a clock scanning method until the characteristic character is matched. The time difference between the reference clock signal output by the automatic test equipment ATE and the characteristic character is recorded, and this difference is included in the subsequent data collection to complete the clock data recovery and achieve synchronization.

[0024] Furthermore, the characteristic character is the group synchronization character 0xBC.

[0025] The present invention also provides a test system for a high-speed converter based on ATE, comprising automatic test equipment ATE and a test board, wherein:

[0026] The automatic test equipment ATE includes:

[0027] A digital channel module, configured to configure the frequency synthesizer's multiplication and division coefficients, output signal format, and amplitude, to generate a reference clock signal and send it to the frequency synthesizer, to initiate synchronization by pulling the SYNC pin of the high-speed converter under test low, and to determine whether the detected return clock signal is normal to determine the state of the frequency synthesizer's output clock;

[0028] A high-speed serial signal module is used to collect the output data of the high-speed converter, compare the output data of the high-speed converter through clock scanning until the characteristic character is matched, record the time difference between the reference clock signal output by the automatic test equipment ATE and the characteristic character, and incorporate this difference into subsequent data collection to complete clock data recovery;

[0029] The test board includes,

[0030] A high-speed converter under test mounted thereon;

[0031] The frequency synthesizer is used to generate a sampling clock signal required for high-speed converter testing based on the pre-configured information and reference clock signal sent by the digital channel module of the automatic test equipment ATE and send it to the high-speed converter. It also generates an output clock as a feedback signal and sends it back to the digital channel module of the automatic test equipment ATE to monitor the output clock status of the frequency synthesizer.

[0032] Furthermore, the output data of the high-speed converter is output through a high-speed SERDES interface.

[0033] The beneficial effects of the present invention are:

[0034] (1) The synchronization performance of the sampling clock and ATE can meet the requirements of all high-speed AD / DA converters. The converter sampling rate is not limited by ATE. Only the appropriate frequency synthesizer needs to be selected.

[0035] (2) The test platform has strong integrity and simple structure. The present invention only requires ATE, a test board and a fixture, which is consistent with the test of general integrated circuits. The test platform has a simple structure and better test stability.

[0036] (3) High test efficiency: The present invention adds a frequency synthesizer to the test board and directly configures it through the digital channel of ATE, which greatly simplifies the operation and greatly improves the efficiency.

[0037] (4) Low cost. Frequency synthesizers are relatively cheap, generally costing only a few dozen to a hundred yuan.

[0038] (V) High stability of the test platform. Since the present invention has a simple structure, and only has a test board except for the ATE, without other peripherals, the control of the entire test platform is relatively simple, thus ensuring the stability of the platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of an existing system architecture for adding an external signal source to provide a clock for testing;

[0040] Figure 2 This is a block diagram of the overall implementation of the clock synchronization method according to embodiment 1 of the present invention;

[0041] Figure 3 This is a flowchart of a clock synchronization method according to embodiment 1 of the present invention;

[0042] Figure 4 This is a schematic diagram of the test system structure of Example 2 of the present invention;

[0043] Figure 5 The figure is a flow chart of clock synchronization performed by the test system according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] Example 1

[0046] Figures 2-3 A specific implementation of the clock synchronization method of a high-speed converter based on ATE of the present invention is shown, comprising the following steps:

[0047] S1. Select a suitable frequency synthesizer based on the clock frequency required by the high-speed converter under test, and configure the frequency synthesizer's multiplication and division coefficients, output signal format, and amplitude through the digital channel module of the automatic test equipment (ATE).

[0048] S2, the digital channel module of the automatic test equipment ATE generates a reference clock signal and sends it to the frequency synthesizer;

[0049] S3. The frequency synthesizer generates the sampling clock signal required for high-speed converter testing and sends it to the high-speed converter. It also generates an output clock as a check signal and sends it back to the digital channel module of the automatic test equipment (ATE) to monitor the output clock status.

[0050] S4, the digital channel module of the automatic test equipment ATE determines whether the detected return signal is normal. If it is normal, the process goes to step S5; if it is not normal, the process goes to step S1 to configure the frequency synthesizer;

[0051] S5. The digital channel module of the automatic test equipment ATE initiates synchronization, that is, pulls the SYNC pin of the high-speed converter low.

[0052] S6. The high-speed converter outputs a characteristic character, which is a group synchronization character 0xB.

[0053] S7. The high-speed serial signal module of the automatic test equipment ATE collects the output data of the high-speed converter, and then compares the output data of the high-speed converter through a clock scanning method until the group synchronization character 0xB is matched. The time difference between the reference clock signal output by the automatic test equipment ATE and the group synchronization character 0xB is recorded, and this difference is included in the subsequent data collection to complete clock data recovery and achieve synchronization.

[0054] Example 2

[0055] Figure 4 A specific embodiment of the ATE-based high-speed converter test system of the present invention is shown, which includes automatic test equipment ATE and a test board, wherein:

[0056] The automatic test equipment ATE adopts American Teradyne ULTRA FLEX, including:

[0057] The digital channel module UP1600 is used to configure the frequency synthesizer's multiplication and division coefficients, output signal format, and amplitude. It is used to generate a reference clock signal and send it to the frequency synthesizer. It is used to initiate synchronization, pull low the SYNC pin of the high-speed converter under test, and determine whether the detected return clock signal is normal.

[0058] A high-speed serial signal module is used to collect the output data of the high-speed converter, compare the output data of the high-speed converter through clock scanning until the characteristic character is matched, record the time difference between the reference clock signal output by the automatic test equipment ATE and the characteristic character, and incorporate this difference into subsequent data collection to complete clock data recovery;

[0059] The test board includes,

[0060] A high-speed converter under test mounted thereon, wherein the high-speed converter is a high-speed ADC, and output data thereof is output through a high-speed SERDES interface;

[0061] The frequency synthesizer uses LMX2592, which is used to generate the sampling clock signal required for high-speed converter testing based on the pre-configured information and reference clock signal issued by the automatic test equipment ATE digital channel module and send it to the high-speed converter. It also generates an output clock as a feedback signal and sends it back to the digital channel module of the automatic test equipment ATE to monitor the output clock status of the frequency synthesizer.

[0062] This embodiment uses the LMX2592 frequency synthesizer to provide an ultra-low jitter clock for a high-speed ADC. The LMX2592 has an output frequency range of 20MHz to 9800MHz, with a typical clock jitter of 49fs. When the analog input is 4GHz, the theoretical SNR can reach 58dBc.

[0063] The ULTRA FLEX UP1600 digital channel module provides a 100MHz reference clock for the LMX2592 frequency synthesizer for clock synchronization, ensuring phase correlation between the high-speed ADC sampling clock and the ATE. The LMX2592 outputs a 6GHz sampling clock to the high-speed ADC, providing a high-speed clock. A 500MHz feedback signal is fed back to the digital channel module of the automated test equipment (ATE) to monitor the LMX2592's output.

[0064] After the ATE detects the 500MHz check signal and determines that the frequency synthesizer LMX2592 is outputting normally, the digital channel module pulls the SYNC pin of the high-speed ADC low and compares the ADC output data using clock scanning until the group synchronization character 0xBC is matched. The module then records the time difference between the output reference clock and the group synchronization character and incorporates this difference into subsequent data acquisition, completing clock data recovery (CDR) and achieving synchronous acquisition.

[0065] The specific process of clock synchronization using the above test system is as follows: Figure 5 shown.

Claims

1. A clock synchronization method for a high-speed converter based on ATE, characterized in that: The steps include: S1. Select a suitable frequency synthesizer according to the clock frequency required by the high-speed converter under test, and configure the frequency multiplication and division coefficients, output signal format and amplitude of the frequency synthesizer through the digital channel module of the automatic test equipment ATE; S2, the digital channel module of the automatic test equipment ATE generates a reference clock signal and sends it to the frequency synthesizer; S3, the frequency synthesizer generates the sampling clock signal required for the high-speed converter test and sends it to the high-speed converter, and also generates an output clock as a check clock signal and sends it back to the digital channel module of the automatic test equipment ATE; S4, the digital channel module of the automatic test equipment ATE determines whether the detected checkback clock signal is normal, if it is normal, it turns to step S5, if it is not normal, it turns to the configuration of the frequency synthesizer in step S1; S5, the digital channel module of the automatic test equipment ATE initiates synchronization, that is, the SYNC pin of the high-speed converter is pulled low; S6, high-speed converter outputs characteristic characters; S7. The high-speed serial signal module of the automatic test equipment ATE collects the output data of the high-speed converter, and then compares the output data of the high-speed converter by clock scanning until the characteristic character is matched, records the time difference between the reference clock signal output by the automatic test equipment ATE and the characteristic character, and includes this difference in subsequent data collection, completes clock data recovery, and realizes synchronization.

2. The clock synchronization method of a high-speed converter based on ATE according to claim 1, characterized in that: The characteristic character is the group synchronization character 0xBC.

3. A high-speed converter test system based on ATE, characterized in that: Including automatic test equipment ATE, test board, including: The automatic test equipment ATE comprises: A digital channel module, used to configure the frequency multiplication and division coefficients, output signal format and amplitude of the frequency synthesizer, to generate a reference clock signal and send it to the frequency synthesizer, to initiate synchronization, to pull down the SYNC pin of the high-speed converter under test, and to determine whether the detected return clock signal is normal; A high-speed serial signal module is used to collect the output data of the high-speed converter, compare the output data of the high-speed converter by clock scanning until the characteristic character is matched, and record the time difference between the reference clock signal output by the automatic test equipment ATE and the characteristic character, and include the difference in subsequent data collection to complete clock data recovery; The test board comprises, A high-speed converter under test mounted thereon; The frequency synthesizer is used to generate a sampling clock signal required for high-speed converter testing and send it to the high-speed converter according to the pre-configuration information and reference clock signal sent by the digital channel module of the automatic test equipment ATE, and also generate an output clock as a check clock signal and send it back to the digital channel module of the automatic test equipment ATE.

4. The ATE-based high-speed converter test system according to claim 3, characterized in that: The output data of the high-speed converter is output through a high-speed SERDES interface.

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