Multi-channel parallel AGC method and device, electronic equipment and storage medium

Abstract

The invention provides a multi-channel parallel AGC method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining an input signal, carrying out the signal sampling of the input signal, and obtaining sampling data; inputting the sampling data into a sliding window structure in parallel, and calculating the maximum amplitude value of the sampling data in the sliding window through the sliding window structure; determining gain control parameters of AGC according to the signal threshold value and the maximum amplitude value of the sampling data; and executing parallel gain control processing on the input signal according to the gain control parameter to obtain multi-path parallel gain output of the input signal. The multi-channel parallel signal AGC processing method has the beneficial effects that the stability in the AGC processing process of the multi-channel parallel signals is improved, and the amplitude jump in the AGC processing process of the parallel signals is reduced.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a multi-channel parallel AGC method, device, electronic equipment and storage medium. Background Art

[0002] When processing the intermediate frequency signal, the instability of the external signal input power (the position of the external radiation signal source changes, the signal of the external radiation source is blocked, or the hardware link is interfered, etc.) will cause the amplitude of the signal obtained by the ADC to differ greatly when sampling. At this time, it is necessary to automatically adjust the amplitude of the signal in the digital domain to keep the amplitude of the signal within a relatively stable range. In addition, when the signal is relayed over long distances, the relay point needs to automatically amplify the signal according to the attenuation of the signal. At this time, an automatic gain adjustment system, namely AGC, is needed to automatically adjust the output gain of the signal to keep the amplitude of the output signal relatively stable.

[0003] In the prior art, the accumulated value of the amplitude value of a fixed number of points is statistically compared with the upper and lower limits of the AGC threshold. When it is higher than the upper limit of the threshold, the gain is reduced, and when it is lower than the lower limit of the threshold, the gain is increased accordingly. In this way, the output amplitude of the signal changes within the threshold range and the amplitude of the output signal is kept relatively stable.

[0004] Referring to the prior art, such as Figure 1 The AGC flow chart shown and Figure 2 In the level value calculation process shown, when the prior art performs automatic gain control, the gain control is not smooth enough, and when the amplitude changes greatly, it is easy to have amplitude jumps. When the sampling rate of the signal is as high as the Ghz level, and the working clock of the FPGA cannot reach Ghz, the amplitude values ​​of continuous sampling points cannot be accumulated and counted using the above solution. And when there are multiple signals that need to be processed simultaneously, but the relative amplitudes of the multiple signals need to be kept stable (that is, the multiple signals use the same gain), the gain control of the multiple signals is difficult to achieve. Summary of the invention

[0005] The main purpose of the embodiments of the present invention is to provide a multi-channel parallel AGC method, device, electronic device and storage medium, which improves the stability of the multi-channel parallel signal AGC processing process and reduces the amplitude jump during the parallel signal AGC processing process.

[0006] One aspect of the present invention provides a multi-channel parallel AGC method, comprising:

[0007] Acquire an input signal, and perform signal sampling on the input signal to obtain sampling data;

[0008] The sampled data are input in parallel into a sliding window structure, and the maximum amplitude value of the sampled data in the sliding window is calculated through the sliding window structure;

[0009] Determine the gain control parameters of AGC according to the signal threshold value and maximum amplitude value of the sampled data;

[0010] According to the gain control parameters, parallel gain control processing is performed on the input signal to obtain multi-channel parallel gain outputs of the input signal.

[0011] According to the multi-channel parallel AGC method, the input signal is sampled to obtain sampled data, including:

[0012] The input signal is sampled and processed by high-speed AD and preset sampling rate to obtain a digital signal;

[0013] According to the frequency of the digital signal and the processing clock frequency, the digital signal is subjected to serial-to-parallel conversion processing to obtain the sampling data for parallel input, wherein the serial-to-parallel conversion processing is used to make the frequency of the digital signal meet the processing clock frequency requirement.

[0014] According to the multi-channel parallel AGC method, the method further comprises:

[0015] The sampling and serial-to-parallel conversion processing of the input signal is performed by FPGA, and the processing clock frequency is the processing clock frequency of FPGA.

[0016] According to the multi-channel parallel AGC method, the maximum amplitude value of the sampled data in the sliding window is calculated by the sliding window structure, including:

[0017] The sampled data is input and output through each sliding window using a FIFO queue, and the amount of data in the sliding window remains fixed;

[0018] The maximum absolute value of the amplitude of the sampled data in each sliding window is calculated in real time to obtain the maximum amplitude value.

[0019] According to the multi-channel parallel AGC method, the sliding window size of the sliding window structure is determined according to the AGC type of the input signal.

[0020] According to the multi-channel parallel AGC method, the gain control parameter of the AGC is determined according to the signal threshold value and the maximum amplitude value of the sampled data, including:

[0021] Determine the threshold value according to the signal strength threshold before performing AGC on the sampled data;

[0022] The gain is calculated based on the threshold value and the maximum amplitude value to obtain the gain control parameter of the AGC.

[0023] According to the multi-channel parallel AGC method, performing parallel gain control processing on the input signal according to the gain control parameter includes:

[0024] FPGA is used to perform truncation processing according to the product of the sampling data and the gain control parameter, so as to adjust the amplitude of the input signal.

[0025] Another aspect of an embodiment of the present invention provides a multi-channel parallel AGC device, comprising:

[0026] The first module is used to obtain an input signal, sample the input signal, and obtain sampled data;

[0027] The second module is used to input the sampled data into a sliding window structure in parallel, and calculate the maximum amplitude value of the sampled data in the sliding window through the sliding window structure;

[0028] The third module is used to determine the gain control parameter of the AGC according to the signal threshold value and the maximum amplitude value of the sampled data;

[0029] The fourth module is used to perform parallel gain control processing on the input signal according to the gain control parameter to obtain multi-channel parallel gain output of the input signal.

[0030] Another aspect of an embodiment of the present invention provides an electronic device, including a processor and a memory;

[0031] The memory is used to store programs;

[0032] The processor executes the program to implement the method described above.

[0033] The embodiment of the present invention also discloses a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device can read the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method described above.

[0034] The beneficial effects of the present invention are as follows: by means of a sliding window, the gain of the signal is adjusted in real time, instead of changing the gain of the signal after a fixed number of sampling points, the response speed of the gain adjustment is increased, and at the same time, the change process of the signal amplitude is made smoother, thereby avoiding the generation of an obvious amplitude jump process; by means of a sliding window of controllable length, the situation where the amplitude period of the signal itself changes slowly and the channel changes drastically can be adapted, and various amplitude jump situations can be well adapted; by using an FPGA in parallel to count the data of the sampling points, the working clock requirement in the processing process can be reduced, and the processing of high sampling rate signals can be realized, and the gain adjustment of multi-channel parallel signals can be realized, so as to facilitate the gain when processing multiple signals at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0036] Figure 1 It is a schematic diagram of the AGC flow chart of the prior art.

[0037] Figure 2 It is a diagram of the level value calculation process of the prior art.

[0038] Figure 3 It is a schematic flow chart of a multi-channel parallel AGC method according to an embodiment of the present invention.

[0039] Figure 4 It is a schematic diagram of the working process of a multi-channel parallel AGC system according to an embodiment of the present invention.

[0040] Figure 5 It is a schematic diagram of the overall architecture workflow of a multi-channel parallel AGC according to an embodiment of the present invention.

[0041] Figure 6 2 is a schematic diagram of a sliding window structure according to an embodiment of the present invention.

[0042] Figure 7 Schematic diagram of high sampling rate signal gain adjustment according to an embodiment of the present invention.

[0043] Figure 8 It is a schematic diagram of AGC adjustment of multi-channel AD sampling in an embodiment of the present invention.

[0044] Fig. 9 It is a schematic diagram of a multi-channel parallel AGC device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In the subsequent description, the use of suffixes such as "module", "component" or "unit" used to represent elements is only for the purpose of facilitating the description of the present invention, and has no specific meaning in itself. Therefore, "module", "component" or "unit" can be used in a mixed manner. "First", "second" and the like are only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the order of the indicated technical features. In this subsequent description, the continuous numbering of the method steps is for the convenience of review and understanding. In combination with the overall technical solution of the present invention and the logical relationship between the various steps, adjusting the implementation order between the steps will not affect the technical effect achieved by the technical solution of the present invention. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0046] Explanation of terms

[0047] FPGA, field programmable gate array.

[0048] AGC, automatic gain control.

[0049] Sampling rate, the sampling accuracy of the time domain signal of AD / ADC, corresponds to the number of sampleable points in 1 second.

[0050] refer to Figure 1 , Figure 1 It is a schematic diagram of the AGC process of the prior art, and its process is as follows:

[0051] (1) The amplitude change of the output signal is counted, and the level value of each 512 sampling points is accumulated to obtain the level value of an update point.

[0052] (2) Compare the level value with the upper limit of the AGC threshold. If it is lower than the upper limit of the threshold, proceed to step 3. Otherwise, jump to step 5 and continue.

[0053] (3) Compare the level value with the lower limit of the AGC threshold. If it is higher than the lower limit, proceed to step 4.

[0054] (4) Increase the gain of the amplifier by one step to amplify the amplitude of the output signal.

[0055] (5) Correspondingly, the gain of the amplifier is reduced, so that the amplitude of the output signal is reduced accordingly.

[0056] (6) Determine whether the gain value is consistent with the currently set gain value. When the gain value is consistent with the current gain value, do not change the gain value. Otherwise, proceed to step 7.

[0057] (7) Change the gain value by setting it to the currently calculated gain value.

[0058] Figure 2 It is a level value calculation process diagram of the prior art, including taking the maximum value plus the minimum value of the IQ two-way signal as the amplitude value, then putting it into the accumulator for accumulation, taking the amplitude value accumulated at every 512 sampling points, obtaining the level value after passing through the comparison table, and finally determining the change of the gain value based on the comparison of the level value.

[0059] refer to Figure 3 , Figure 3 1 is a flow chart of a multi-channel parallel AGC method according to an embodiment of the present invention, which includes but is not limited to steps S100 to S400:

[0060] S100, acquiring an input signal, sampling the input signal, and obtaining sampled data.

[0061] In some embodiments, the input signal is sampled and processed through high-speed AD and a preset sampling rate to obtain a digital signal; the digital signal is serially-to-parallel converted according to the frequency of the digital signal and the processing clock frequency to obtain sampling data for parallel input, wherein the serial-to-parallel conversion is used to make the frequency of the digital signal meet the processing clock frequency requirement.

[0062] In some embodiments, the sampling and serial-to-parallel conversion processing of the input signal is performed by the FPGA, and the processing clock frequency is the processing clock frequency of the FPGA.

[0063] It is understandable that when the sampling rate of the signal is as high as the Ghz level, and the working clock of the FPGA cannot reach Ghz, this embodiment can solve the AGC processing when the working clock of the FPGA cannot reach Ghz by performing serial-to-parallel conversion on the digital signal.

[0064] S200, inputting the sampled data into the sliding window structure in parallel, and calculating the maximum amplitude value of the sampled data in the sliding window through the sliding window structure.

[0065] In some embodiments, the sampled data is input and output through each sliding window using a FIFO queue, and the amount of data in the sliding window is kept at a fixed value; the maximum absolute value of the amplitude of the sampled data in each sliding window is calculated in real time to obtain the maximum amplitude value.

[0066] In some embodiments, the sliding window size of the sliding window structure is determined according to the AGC type of the input signal.

[0067] S300, determining an AGC gain control parameter according to a signal threshold value and a maximum amplitude value of the sampled data.

[0068] In some embodiments, the threshold value is determined according to the signal strength threshold before the AGC is performed on the sampled data; the gain is calculated according to the threshold value and the maximum amplitude value to obtain the gain control parameter of the AGC.

[0069] In some embodiments, the threshold value (Threshold) is the signal strength threshold at which the gain is adjusted for the sampled data. When the input signal is lower than this value, AGC will not be performed. The maximum amplitude value is the maximum output signal amplitude allowed. When this value is exceeded, AGC will reduce the gain to avoid signal distortion.

[0070] S400, performing parallel gain control processing on the input signal according to the gain control parameter to obtain multi-channel parallel gain outputs of the input signal.

[0071] In some implementations, an FPGA is used to perform truncation processing based on the product of the sampled data and the gain control parameter to adjust the amplitude of the input signal.

[0072] In some embodiments, if the input signal is below a threshold value, the gain is maintained at a higher level to enhance the signal; between the threshold value and the maximum amplitude value, the gain is dynamically adjusted according to the amplitude of the input signal to keep the output signal within an allowable range; exceeding the maximum amplitude value, when the input signal exceeds the maximum amplitude value, the AGC should reduce the gain to prevent signal distortion.

[0073] In some embodiments, reference Figure 4 The schematic diagram of the multi-channel parallel AGC system workflow is as follows:

[0074] A part of the signal input is sent to the data sliding window for data comparison calculation, and the maximum amplitude of the signal is counted inside the sliding window. Because digital signals have positive and negative values, the maximum absolute value of the signal is counted here.

[0075] In some embodiments, reference Figure 5 This is a schematic diagram of the overall architecture of multi-channel parallel AGC. It converts and calculates the gain control parameters according to the threshold value of the signal, and then outputs the gain parameters to the gain control unit to control the gain to adjust the output amplitude of the signal to ensure that the output amplitude of the signal is stable within a range. Automatic gain control function is realized.

[0076] A gain control unit is added at the signal output to amplify or reduce the input signal amplitude to adjust the signal output, so that the output signal amplitude remains within a stable range. The gain control unit adjusts the amplitude by multiplying the input signal by the gain control parameter and then truncates it in the FPGA. The FPGA can easily realize streamlined data processing without data blocking.

[0077] refer to Figure 6 The sliding window structure diagram shown in the figure, in which the sliding window module sets a fixed size value each time to ensure that the size of the sliding window data can be adjusted to meet different signal requirements. The working mode of the sliding window is similar to the FIFO queue structure, where the first data in is output first, but the amount of data inside the sliding window needs to be guaranteed to be constant. The maximum value statistics module needs to count the maximum value of the data inside the sliding window, and the maximum value changes in real time with the change of the data inside the sliding window.

[0078] The embodiment of the present invention adopts parameterized configuration to implement a multi-channel parallel structure. When different parameters are configured, the number of channels of the hardware link compiled by the FPGA will be different, so as to realize parallel processing of multi-channel data and facilitate the processing of high sampling rate signals or multi-channel signals.

[0079] refer to Figure 7 High sampling rate signal gain adjustment diagram and Figure 8 Schematic diagram of multi-channel AD sampling AGC adjustment.

[0080] Figure 7 The sampling rate of the high-speed AD is 1.2Ghz. After sampling the analog signal, the sampled data converted to the FPGA is 2-channel 600Mhz digital signals. Because the internal clock of the FPGA cannot reach 600Mhz, the primitive is used inside the FPGA to convert the 2-channel 600Mhz signal into 4-channel 300Mhz signals in series and parallel to meet the clock frequency that the FPGA can process. Then the AGC module of the present application solution is used to adjust the amplitude of the signal in parallel to realize the processing of high sampling rate signals.

[0081] Figure 8 When multiple AD sampling signals are input at the same time, it is necessary to ensure that the relative amplitude values ​​of each AD output signal remain unchanged after the amplitude adjustment, that is, the gain values ​​of the multiple AD sampling signals need to be consistent at the same time. This solution can be used for control, and the amplitudes of multiple AD signals can be adjusted simultaneously and quickly.

[0082] Fig. 9 1 is a diagram of a multi-channel parallel AGC analysis device according to an embodiment of the present invention. The device includes a first module 910 , a second module 920 , a third module 930 and a fourth module 940 .

[0083] Among them, the first module is used to obtain the input signal, sample the input signal, and obtain the sampled data; the second module is used to input the sampled data in parallel to the sliding window structure, and calculate the maximum amplitude value of the sampled data in the sliding window through the sliding window structure; the third module is used to determine the gain control parameters of the AGC according to the signal threshold value and the maximum amplitude value of the sampled data; the fourth module is used to perform parallel gain control processing on the input signal according to the gain control parameters to obtain multi-channel parallel gain outputs of the input signal.

[0084] Exemplarily, with the cooperation of the first module, the second module, the third module and the fourth module in the device, the embodiment device can implement any of the aforementioned multi-channel parallel AGC methods, that is, obtaining an input signal, sampling the input signal to obtain sampled data; inputting the sampled data in parallel to a sliding window structure, and calculating the maximum amplitude value of the sampled data in the sliding window through the sliding window structure; determining the gain control parameters of the AGC according to the signal threshold value and the maximum amplitude value of the sampled data; and performing parallel gain control processing on the input signal according to the gain control parameters to obtain multi-channel parallel gain outputs of the input signal. The beneficial effects of the present invention are as follows: by means of a sliding window, the gain of the signal is adjusted in real time, instead of changing the gain of the signal after a fixed number of sampling points, the response speed of the gain adjustment is increased, and at the same time, the change process of the signal amplitude is made smoother, thereby avoiding the generation of an obvious amplitude jump process; by means of a sliding window of controllable length, the situation where the amplitude period of the signal itself changes slowly and the channel changes drastically can be adapted, and various amplitude jump situations can be well adapted; by using an FPGA in parallel to count the data of the sampling points, the working clock requirement in the processing process can be reduced, and the processing of high sampling rate signals can be realized, and the gain adjustment of multi-channel parallel signals can be realized, so as to facilitate the gain when processing multiple signals at the same time.

[0085] An embodiment of the present invention further provides an electronic device, the electronic device comprising a processor and a memory;

[0086] The memory stores a program;

[0087] The processor executes the program to execute the aforementioned multi-channel parallel AGC method; the electronic device has the function of carrying and running the multi-channel parallel AGC software system provided by the embodiment of the present invention, for example, a personal computer, a minicomputer, a main frame, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or communicates with a charged particle tool or other imaging device, etc.

[0088] An embodiment of the present invention further provides a computer-readable storage medium, wherein the storage medium stores a program, and the program is executed by a processor to implement the multi-channel parallel AGC method as described above.

[0089] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0090] The embodiment of the present invention also discloses a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device can read the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the aforementioned multi-channel parallel AGC method.

[0091] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features described may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0092] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0093] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0094] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0095] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0096] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0097] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0098] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A multi-channel parallel AGC method, characterized in that: include: Acquire an input signal, and perform signal sampling on the input signal to obtain sampling data; The sampled data are input in parallel into a sliding window structure, and the maximum amplitude value of the sampled data in the sliding window is calculated through the sliding window structure; Determine the gain control parameters of AGC according to the signal threshold value and maximum amplitude value of the sampled data; According to the gain control parameters, parallel gain control processing is performed on the input signal to obtain multi-channel parallel gain outputs of the input signal.

2. The multi-channel parallel AGC method according to claim 1, characterized in that: The step of sampling the input signal to obtain sampled data includes: The input signal is sampled and processed by high-speed AD and preset sampling rate to obtain a digital signal; According to the frequency of the digital signal and the processing clock frequency, the digital signal is subjected to serial-to-parallel conversion processing to obtain the sampling data for parallel input, wherein the serial-to-parallel conversion processing is used to make the frequency of the digital signal meet the processing clock frequency requirement.

3. The multi-channel parallel AGC method according to claim 2, characterized in that: The method further comprises: The sampling and serial-to-parallel conversion processing of the input signal is performed by FPGA, and the processing clock frequency is the processing clock frequency of FPGA.

4. The multi-channel parallel AGC method according to claim 1, characterized in that: The calculating the maximum amplitude value of the sampled data in the sliding window by using the sliding window structure includes: The sampled data is input and output through each sliding window using a FIFO queue, and the amount of data in the sliding window remains fixed; The maximum absolute value of the amplitude of the sampled data in each sliding window is calculated in real time to obtain the maximum amplitude value.

5. The multi-channel parallel AGC method according to claim 1, characterized in that: The sliding window size of the sliding window structure is determined according to the AGC type of the input signal.

6. The multi-channel parallel AGC method according to claim 1, characterized in that: Determining the gain control parameter of the AGC according to the signal threshold value and the maximum amplitude value of the sampled data includes: Determine the threshold value according to the signal strength threshold before performing AGC on the sampled data; The gain is calculated based on the threshold value and the maximum amplitude value to obtain the gain control parameter of the AGC.

7. The multi-channel parallel AGC method according to claim 1, characterized in that: The performing parallel gain control processing on the input signal according to the gain control parameter comprises: FPGA is used to perform truncation processing according to the product of the sampling data and the gain control parameter, so as to adjust the amplitude of the input signal.

8. A multi-channel parallel AGC device, characterized in that: include: The first module is used to obtain an input signal, sample the input signal, and obtain sampled data; The second module is used to input the sampled data into a sliding window structure in parallel, and calculate the maximum amplitude value of the sampled data in the sliding window through the sliding window structure; The third module is used to determine the gain control parameter of the AGC according to the signal threshold value and the maximum amplitude value of the sampled data; The fourth module is used to perform parallel gain control processing on the input signal according to the gain control parameter to obtain multi-channel parallel gain output of the input signal.

9. An electronic device, characterized in that: including a processor and a memory; The memory is used to store programs; The processor executes the program to implement the multi-channel parallel AGC method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The storage medium stores a program, and the program is executed by a processor to implement the multi-channel parallel AGC method according to any one of claims 1 to 7.

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