Self-adaptive frame format preprocessing method based on hardware working mode

Abstract

The invention belongs to the technical field of information, and particularly relates to an adaptive frame format preprocessing method based on a hardware working mode, which adaptively selects a PCM frame format preprocessing parameter most suitable for a current application scene based on an AD chip acquisition rate and a PCM transmission rate in PCM transmission, and determines a corresponding AD ping-pong design. And adaptive processing is carried out on the analog quantity position in the PCM frame format in the programming and loading processes of the PCM frame format. According to the method, the real-time performance and reliability of telemetry data acquisition are improved, meanwhile, the problem that the analog quantity position in the PCM frame content is disordered when multiple AD are adopted for ping-pong operation is solved, good adaptability is achieved, and the method can generally adapt to different AD chips and different PCM transmission rates.

Description

Technical Field

[0001] The invention belongs to the field of information technology, and in particular relates to an adaptive frame format preprocessing method based on a hardware working mode. Background Art

[0002] Pulse Code Modulation (PCM) technology is widely used in the field of telemetry data collection and transmission. The telemetry data required to be transmitted will form a frame format according to the order in which it is sent in the PCM frame, and the frame format is stored in the EEPROM storage device. When telemetry data transmission is required, the FPGA will read the frame format stored in the EEPROM and temporarily store it in the FPGA's own BRAM for the PCM framing module in the FPGA to read, so that the PCM framing module can control the specific content and format of the PCM transmission data according to the frame format in the BRAM.

[0003] PCM transmission data contains a variety of data contents such as digital quantity, image data, analog quantity, etc. The transmission position of different data in a PCM frame is determined by the PCM frame format. The working sequence of PCM transmission data is as follows: Figure 1 As shown in the figure, when FPGA is sending telemetry data, it will read the PCM frame format that needs to be transmitted at the current moment from BRAM in sequence, and then select the corresponding data according to the format for PCM framing and sending. Taking PCM transmission of analog quantity as an example, FPGA reads the frame format and determines that the data that needs to be transmitted at the current moment is analog quantity, that is, it will immediately start the analog switch of the analog quantity and start the AD chip conversion. When the AD conversion is completed, the conversion result is sent out through PCM framing, as shown in the figure. Figure 2 shown.

[0004] However, the acquisition and transmission of analog quantities in PCM frames are affected by the current hardware working mode. To ensure that the analog quantities transmitted by PCM are correct, it is necessary to ensure that the AD chip has correctly acquired, converted and transmitted the required analog quantities when PCM sends analog data. When the PCM transmission rate is very fast, but the AD chip acquisition rate is very slow or the communication rate is very slow, the FPGA cannot use PCM to transmit the analog quantities collected in real time according to the current frame format, which poses a hidden danger to the real-time and reliability of the analog data telemetry acquisition. Therefore, in actual design, multiple AD chips are sometimes used for ping-pong operation to ensure the normal operation of the AD chip while meeting the PCM transmission rate. The specific working conditions are as follows: Figure 3 shown.

[0005] Depend on Figure 3It can be seen that when two AD chips are used for analog quantity acquisition in ping-pong operation, the analog quantity of the actual PCM transmission will lag behind the analog quantity in the frame format by two cycles, resulting in the disorder of the analog quantity position in the PCM frame. In addition, in actual application scenarios, due to factors such as accuracy and cost, the working mode of the AD chip in PCM transmission and the PCM transmission rate are different, and the corresponding AD chip uses a different design of ping-pong operation.

[0006] Therefore, it is necessary to propose a reasonable and adaptive frame format preprocessing method for the frame format burning and loading process in different application environments. The analog frame format in the frame format can be preprocessed according to the working mode of the AD chip and the PCM transmission rate in the current situation. Summary of the invention

[0007] 1. Technical issues to be resolved

[0008] The technical problem to be solved by the present invention is how to provide an adaptive frame format preprocessing method based on a hardware working mode to adapt to the transmission of analog quantity acquisition results under different types of AD chips and PCM transmission rates.

[0009] (II) Technical solution

[0010] In order to solve the above technical problems, the present invention proposes an adaptive frame format preprocessing method based on a hardware working mode, the method comprising the following steps:

[0011] Step 1, calculate the PCM frame format preprocessing parameter N according to the current hardware working mode;

[0012] Step 2: According to the EEPROM chip communication interface requirements, the PCM frame format preprocessing parameter N and the PCM frame format are burned into the address range specified in the EEPROM; after the burning is completed, the FPGA is powered off and then powered on again;

[0013] Step 3, load all frame formats in the PCM frame;

[0014] Step 4: Perform PCM frame format preprocessing.

[0015] Further, in step 1, the PCM frame format preprocessing parameter N is calculated as:

[0016]

[0017] Among them, t PCM is the PCM transmission period determined according to the current usage requirements, t AD is the analog acquisition time calculated according to the current AD chip working mode, t AD for:

[0018] t AD =t C +t S +t T ,

[0019] Among them, t C ,t S and t T They are the acquisition time, conversion time and transmission time of analog data respectively.

[0020] Furthermore, step 3 includes:

[0021] Step 3.1, read the PCM frame format from EEPROM;

[0022] Step 3.2, the read frame format content and the read PCM frame position sequence are stored in different BRAMs in the FPGA respectively;

[0023] Step 3.3: Determine whether all frame formats in the PCM frame have been loaded:

[0024] If completed, go to step 3.4;

[0025] If not completed, add 1 to the read length L of the PCM frame format, go to step 3.1, and read the PCM frame format of the next byte;

[0026] Step 3.4: After all PCM frame formats are loaded, read the PCM frame format preprocessing parameter N from the first byte position in the EEPROM, and go to step 4.

[0027] Furthermore, step 4 specifically includes:

[0028] Step 4.1, read the PCM frame format to be judged from the address P of the BRAM storing the frame format inside the FPGA, set the judgment length of the PCM frame format to P, and judge whether the read PCM frame format to be judged is an analog quantity:

[0029] If the PCM frame format to be judged is not analog, go to step 4.2.

[0030] Otherwise, go to step 4.3;

[0031] Step 4.2, the PCM frame format content read out in step 4.1 is used as storage data, and the position sequence in the PCM frame is used as the storage offset address, and is stored in the PCM frame format RAM inside the FPGA;

[0032] If the current frame format is not the last frame format in the PCM frame, then add 1 to P and go to step 4.1 to determine whether the next PCM frame format is analog;

[0033] Otherwise, go to step 4.6;

[0034] Step 4.3: According to the PCM frame format preprocessing parameter N read out in step 3.4, determine whether PCM frame format preprocessing is required:

[0035] If N=1, go to step 4.4;

[0036] Otherwise, go to step 4.5;

[0037] Step 4.4, the PCM frame format content read out in step 4.1 is used as storage data, and the position sequence in the PCM frame is used as the storage offset address, and is stored in the PCM frame format RAM inside the FPGA;

[0038] If the current PCM frame format is not the last frame format in the PCM frame, then P is increased by 1, and the process goes to step 4.1 to determine whether the next PCM frame format is analog;

[0039] Otherwise, go to step 4.6;

[0040] Step 4.5, the analog quantity in the PCM frame format is cyclically moved forward by N analog quantity positions, the PCM frame format content read out in step 4.1 is used as storage data, and the processed analog quantity position is used as the storage offset address and stored in the PCM frame format RAM;

[0041] If the current frame format is not the last frame format in the PCM frame, then add 1 to P and go to step 4.1 to determine whether the next PCM frame format is analog;

[0042] Otherwise, go to step 4.6;

[0043] Step 4.6: Complete all PCM frame format loading preprocessing, and store the preprocessed PCM frame format into the FPGA internal frame format BRAM for controlling PCM transmission.

[0044] (III) Beneficial effects

[0045] Compared with the conventional PCM frame format burning and loading process, the present invention improves the real-time and reliability of telemetry data acquisition, and solves the problem of analog quantity position disorder in the PCM frame content caused by using multiple ADs for ping-pong operation. It has good adaptability and can generally adapt to different AD chips and different PCM transmission rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1This is the working timing diagram of PCM sending data;

[0047] Figure 2 Send analog quantity working timing diagram for PCM;

[0048] Figure 3 This is the working sequence diagram of PCM sending analog quantity under AD ping-pong operation;

[0049] Figure 4 It is a schematic diagram of the frame format preprocessing process that can be configured based on the parameters of the hardware working mode;

[0050] Figure 5 This is a schematic diagram of FPGA internal BRAM storage after the PCM frame format is loaded;

[0051] Figure 6 This is a schematic diagram of FPGA frame format BRAM storage after non-analog frame format processing is completed;

[0052] Figure 7 This is a schematic diagram of FPGA frame format BRAM storage after N=1 analog frame format processing is completed;

[0053] Figure 8 This is a schematic diagram of FPGA frame format BRAM storage after N=2 analog frame format processing is completed;

[0054] Fig. 9 This is a schematic diagram of the frame format before preprocessing;

[0055] Fig.10 This is a schematic diagram of the frame format after N=2 preprocessing. DETAILED DESCRIPTION

[0056] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0057] like Figure 4 As shown, in a specific embodiment of the present invention, the following steps are included:

[0058] Step 1: Explain the parameter-configurable frame format preprocessing process based on the hardware working mode in the proposed mechanism.

[0059] PCM transmission data contains a variety of data content, including digital quantity, image data, analog quantity, etc. The transmission position of different data in a PCM frame is determined by the PCM frame format. The transmission of analog quantity in the PCM frame is affected by the working mode of the AD chip in the current situation. To ensure that the AD chip has correctly collected, converted and transmitted the required analog quantity when PCM transmits analog quantity, it is necessary to pre-process the analog quantity in the frame format according to the working mode of the AD chip and the PCM transmission rate in the current situation.

[0060] First, it is necessary to determine the PCM frame format preprocessing parameter N. The PCM frame format preprocessing parameter N is selected as follows.

[0061]

[0062] Among them, t AD is the analog acquisition time (in ms) calculated according to the current AD chip working mode. The analog acquisition time t AD (Unit: ms) includes the acquisition time t of analog data C (unit: ms), conversion time t S (unit: ms) and transmission time t T (Unit: ms). Acquisition time t C and conversion time t S It is related to the selection of AD chip. The transmission time t T It is related to the communication interface requirements of the AD chip. That is:

[0063] t AD＝ t C +t S +t T ;

[0064] t PCM The PCM transmission period t is determined according to the current usage requirements. PCM (Unit: ms). PCM Represents the time required for PCM to transmit each analog acquisition result.

[0065] The analog acquisition time t calculated according to the current AD chip working mode AD and the current PCM transmission period t PCM The selected PCM frame format preprocessing parameter N represents the relationship between the analog acquisition rate and the PCM transmission rate in the current situation:

[0066] If N=1, it means that the current analog acquisition rate can meet the PCM transmission rate. In this case, only one AD is needed to meet the PCM transmission requirements, and the analog frame format does not need to be preprocessed;

[0067] If N>1, it means that the current analog acquisition rate cannot meet the PCM transmission rate. In this case, N AD chips need to be used for ping-pong operation to meet the PCM transmission requirements. At the same time, the analog frame format needs to be preprocessed and the analog frame format needs to be moved N positions in advance to ensure that the AD chip can start analog acquisition in advance.

[0068] After determining the PCM frame format preprocessing parameter N, go to step 2.

[0069] Step 2: Burn the PCM frame format preprocessing parameter N and the PCM frame format. According to the EEPROM chip communication interface requirements, the PCM frame format preprocessing parameter N and the PCM frame format are burned into the specified address range of the EEPROM. The specific storage effect of the EEPROM is shown in Table 1.

[0070] Table 1 Storage effect in EEPROM

[0071] Storage Location Storage Content 1st byte position Frame format preprocessing parameters (N) Frame format address range PCM frame format

[0072] After the PCM frame format preprocessing parameter N and PCM frame format are burned, the FPGA can be powered off and then powered on again to load the PCM frame format and go to step 3;

[0073] Step 3: Load all frame formats in the PCM frame. After the FPGA is powered on, the PCM frame format will be loaded first.

[0074] Step 3.1, read the PCM frame format from the EEPROM.

[0075] During the PCM frame format loading process, the loaded frame format sequence is preprocessed as needed to ensure that when the AD chip acquisition is slow, analog quantity acquisition can be performed in advance according to the required PCM analog quantity sending sequence. Therefore, during the PCM frame format loading process, the read length of the PCM frame format is set to L, which represents the length of the PCM frame format that has been read out. When reading the frame format for the first time, set L=0, and read the address from the specified PCM frame format address interval to the PCM frame format base address + L, and read the PCM frame format content under this address.

[0076] Step 3.2: Store the read PCM frame format content (C) and the read PCM frame position sequence (S) into different BRAMs in the FPGA. Figure 5 As indicated, go to step 3.3.

[0077] Step 3.3, determine whether all frame formats in the PCM frame have been loaded. If completed, go to step 3.4. If not completed, add 1 to the reading length L of the PCM frame format, go to step 3.1, and read the PCM frame format of the next byte.

[0078] Step 3.4: After all PCM frame formats are loaded, read the frame format preprocessing parameter N from the first byte position in the EEPROM and go to step 4.

[0079] Step 4: Perform PCM frame format preprocessing.

[0080] Step 4.1: Determine whether the PCM frame format is an analog quantity, and make judgments based on the PCM frame format content loaded into the BRAM of the FPGA.

[0081] In the process of PCM frame format processing and judgment, the judgment length of the PCM frame format is set to P, which represents the length of the frame format that has been judged. When the first PCM frame format is judged, P=0 is set, and the PCM frame format content to be judged is read from the address P of the BRAM that stores the PCM frame format inside the FPGA. If the current PCM frame format is not an analog quantity, go to step 4.2, otherwise go to step 4.3.

[0082] Step 4.2: The current PCM frame format is not an analog quantity. The PCM frame format is not affected by the acquisition rate of the AD chip, and no PCM frame format preprocessing is required. Directly use the PCM frame format content (C) read out in step 4.1 as storage data, and the position sequence (S) in the PCM frame as the storage offset address, and store it in the FPGA internal frame format RAM, such as Figure 6 If the current frame format is not the last frame format in the PCM frame, then P is increased by 1, and the process goes to step 4.1 to determine whether the next PCM frame format is analog, otherwise, the process goes to step 4.6.

[0083] Step 4.3: If the current PCM frame format is analog, it is necessary to read the PCM frame format preprocessing parameter N in step 3.4 to determine whether PCM frame format preprocessing is required. If N=1, go to step 4.4, otherwise go to step 4.5.

[0084] Step 4.4, PCM frame format preprocessing parameter N = 1, which means that the analog acquisition rate in the current situation can meet the PCM transmission rate, and the analog related PCM frame format does not need to be preprocessed. The PCM frame format content (C) read out in step 4.1 is directly used as the storage data, and the position sequence (S) in the PCM frame is used as the storage offset address and stored in the FPGA internal frame format RAM, such as Figure 7 If the current frame format is not the last frame format in the PCM frame, then P is increased by 1, and the process goes to step 4.1 to determine whether the next PCM frame format is analog, otherwise, the process goes to step 4.6.

[0085] Step 4.5, PCM frame format preprocessing parameter N>1, which means that in the current situation, multiple ADs need to be used for ping-pong operations to meet the PCM transmission requirements, and the analog quantity-related PCM frame format also needs to be preprocessed. That is, the analog quantity in the PCM frame format is cyclically moved forward by N analog quantity positions. Taking N=2 as an example, all analog quantities are advanced by 2 analog quantity positions, and the third analog quantity appearing in the PCM frame is placed in the position of the first analog quantity. The fourth analog quantity appearing in the PCM frame is placed in the position of the second analog quantity, and so on. The PCM frame format content (C) read out in step 4.1 is used as the storage data, and the processed analog quantity position (S') is used as the storage offset address and stored in the PCM frame format RAM, such as Figure 8 The PCM frame format content before and after preprocessing is shown in the figure. Fig. 9 and Fig.10 If the current frame format is not the last frame format in the PCM frame, then P is increased by 1, and the process goes to step 4.1 to determine whether the next PCM frame format is analog, otherwise, the process goes to step 4.6.

[0086] Step 4.6: Complete all PCM frame format loading preprocessing, and store the preprocessed frame format into the FPGA internal frame format BRAM for controlling PCM transmission.

[0087] The present invention takes into account that the transmission of analog quantities in PCM frames is affected by the working mode of AD chips in the current situation. Based on the AD chip acquisition rate and PCM transmission rate in PCM transmission, the present invention adaptively selects the PCM frame format preprocessing parameters that are most suitable for the current application scenario, determines the corresponding AD ping-pong design, and adaptively processes the analog quantity position in the PCM frame format during the burning and loading process of the PCM frame format.

[0088] Compared with the conventional PCM frame format burning and loading process, the present invention improves the real-time and reliability of telemetry data acquisition, and solves the problem of analog quantity position disorder in the PCM frame content caused by using multiple ADs for ping-pong operation. It has good adaptability and can generally adapt to different AD chips and different PCM transmission rates.

[0089] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An adaptive frame format preprocessing method based on hardware working mode, characterized in that: The steps include: Step 1, calculate the PCM frame format preprocessing parameter N according to the current hardware working mode; Step 2: According to the EEPROM chip communication interface requirements, the PCM frame format preprocessing parameter N and the PCM frame format are burned into the address range specified in the EEPROM; after the burning is completed, the FPGA is powered off and then powered on again; Step 3, load all frame formats in the PCM frame; Step 4: Perform PCM frame format preprocessing.

2. The method for adaptive frame format preprocessing based on hardware working mode according to claim 1, characterized in that: In step 1, the PCM frame format preprocessing parameter N is calculated as: Among them, t PCM is the PCM transmission period determined according to the current usage requirements, t AD is the analog acquisition time calculated according to the current AD chip working mode, t AD for: t AD =t C +t S +t T , Among them, t C ,t S and t T They are the acquisition time, conversion time and transmission time of analog data respectively.

3. The method for adaptive frame format preprocessing based on hardware working mode according to claim 2, characterized in that: Step 3 includes: Step 3.1, read the PCM frame format from EEPROM; Step 3.2, the read frame format content and the read PCM frame position sequence are stored in different BRAMs in the FPGA respectively; Step 3.3, determine whether all frame formats in the PCM frame have been loaded: if completed, go to step 3.4; If not completed, add 1 to the read length L of the PCM frame format, go to step 3.1, and read the PCM frame format of the next byte; Step 3.4: After all PCM frame formats are loaded, read the PCM frame format preprocessing parameter N from the first byte position in the EEPROM, and go to step 4.

4. The method for adaptive frame format preprocessing based on hardware working mode according to claim 3, characterized in that: Step 4 specifically includes: Step 4.1, read the PCM frame format to be judged from the address P of the BRAM storing the frame format inside the FPGA, set the judgment length of the PCM frame format to P, and judge whether the read PCM frame format to be judged is an analog quantity: If the read PCM frame format to be determined is not analog, go to step 4.2, otherwise, go to step 4.3; Step 4.2, the PCM frame format content read out in step 4.1 is used as storage data, and the position sequence in the PCM frame is used as the storage offset address, and is stored in the PCM frame format RAM inside the FPGA; If the current frame format is not the last frame format in the PCM frame, add 1 to P and go to step 4.1 to determine whether the next PCM frame format is analog; Otherwise, go to step 4.6; Step 4.3: According to the PCM frame format preprocessing parameter N read out in step 3.4, determine whether PCM frame format preprocessing is required: If N=1, go to step 4.4; Otherwise, go to step 4.5; Step 4.4, the PCM frame format content read out in step 4.1 is used as storage data, and the position sequence in the PCM frame is used as the storage offset address, and is stored in the PCM frame format RAM inside the FPGA; If the current PCM frame format is not the last frame format in the PCM frame, then P is increased by 1, and the process goes to step 4.1 to determine whether the next PCM frame format is analog; Otherwise, go to step 4.6; Step 4.5, the analog quantity in the PCM frame format is cyclically moved forward by N analog quantity positions, the PCM frame format content read out in step 4.1 is used as storage data, and the processed analog quantity position is used as the storage offset address and stored in the PCM frame format RAM; If the current frame format is not the last frame format in the PCM frame, add 1 to P and go to step 4.1 to determine whether the next PCM frame format is analog; Otherwise, go to step 4.6; Step 4.6: Complete all PCM frame format loading preprocessing, and store the preprocessed PCM frame format into the FPGA internal frame format BRAM for controlling PCM transmission.

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