Method for regulating and controlling performance of SRAM device

Abstract

The invention discloses a method for regulating and controlling the performance of an SRAM (Static Random Access Memory) device, which comprises the following steps: S1, providing a device layout in which a plurality of polycrystalline silicon grids distributed along a first direction, a plurality of active regions distributed along a second direction and a plurality of storage units are formed, and grid cuts are arranged on the polycrystalline silicon grids; wherein the first direction is perpendicular to the second direction; s2, adjusting the distance between the grid cutting part and the adjacent active region, and updating the device layout; s3, manufacturing an SRAM (Static Random Access Memory) device according to the updated device layout; s4, performing a performance test on the SRAM device to obtain a test result; s5, comparing the test result with a preset device performance target; and repeating the steps S1 to S5 until the test result meets the performance target of the device. By means of the scheme, controllable adjustment of the read-write performance of the SRAM device can be achieved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing processes, and in particular to a method for regulating the performance of an SRAM device. Background Art

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously reducing the size of the device to increase its speed. At present, due to the entry into the nanotechnology process node, the preparation and performance of semiconductor devices are restricted by various physical limits.

[0003] For SRAM devices, the performance is mainly regulated by adjusting the ratio between each MOSFET transistor, especially for small nodes, the read and write performance of SRAM devices is mainly adjusted by changing the size of each transistor active area. The ratio of transistors in SRAM generally includes , and ,in , , , and the product of the three is 1. and Reducing it will lead to a decrease in SNM (Static Noise Margin) and a decrease in read performance; Reduction will lead to a decrease in WM (Write Margin) and a decrease in write performance. Currently, the means of adjusting the read and write performance of SRAM devices from the internal structure of the device usually sacrifices chip area. Improving SRAM read and write performance through external auxiliary circuits will also sacrifice chip area. Summary of the invention

[0004] In order to solve the above problems, the present application provides a method for regulating the performance of an SRAM device.

[0005] A method for regulating the performance of an SRAM device provided in an embodiment of the present application includes: S1: providing a device layout, wherein a plurality of polysilicon gates distributed along a first direction, a plurality of active areas distributed along a second direction, and a plurality of storage units are formed in the device layout, and a gate cut is arranged on the polysilicon gate; wherein the first direction is perpendicular to the second direction; S2: adjusting the distance between the gate cut and the active area adjacent thereto, and updating the device layout; S3: manufacturing the SRAM device according to the updated device layout; S4: Performing a performance test on the SRAM device to obtain a test result; S5: comparing the test results with a preset device performance target; Repeat S1 to S5 until the test result meets the device performance target.

[0006] In some embodiments, each of the memory cells comprises a plurality of transistors, the transistors comprising a pull-up transistor, a pull-down transistor and a transmission transistor, the active regions where the transmission transistor and the pull-down transistor are located are adjacent to the active region where the pull-up transistor is located; a polysilicon gate constituting a gate structure of the transmission transistor is adjacent to a polysilicon gate constituting a gate structure of the pull-up transistor and the pull-down transistor; The gate cut is located on a polysilicon gate constituting a gate structure of the pass transistor.

[0007] In some embodiments, adjusting the distance between the gate cut and an active region adjacent thereto comprises: By adjusting the size of the gate cut and / or the position of the gate cut on the polysilicon gate, the distance between the gate cut and the active region adjacent to the gate cut and where the transfer transistor is located is adjusted.

[0008] In some embodiments, the test result includes performance parameters of the SRAM device and performance parameters of at least one selected target memory cell, where the target memory cell is any one of all the memory cells.

[0009] In some embodiments, the performance parameters of the target memory cell include but are not limited to the threshold voltage and saturation current of each transistor.

[0010] In some embodiments, the closer the distance between the gate cut and the active region adjacent thereto where the pass transistor is located, the worse the performance of the pass transistor.

[0011] The technical solution of this application has at least the following advantages: By adjusting the distance between the gate cut and the active area adjacent to it, the speed of the transmission transistor is changed, while the pull-up transistor and the pull-down transistor remain unchanged, achieving the purpose of regulating the cell ratio of the SRAM device and realizing controllable adjustment of the read and write performance of the SRAM device; By adjusting the gate cutting during the design stage of the device layout, the process complexity is not increased, and there is no need to increase additional costs or sacrifice device area. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 is a flow chart of a method for regulating the performance of an SRAM device provided by an exemplary embodiment of the present application; Figure 2 It is a schematic diagram of a device layout provided by an exemplary embodiment of the present application.

[0014] Description of reference numerals: 101, first polysilicon gate; 102, second polysilicon gate; 201, first active region; 202, second active region; 203, third active region; 204, fourth active region; 30, memory cell. DETAILED DESCRIPTION

[0015] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0016] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0017] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0018] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0019] The present application provides a method for regulating the performance of an SRAM device, referring to Figure 1 , the method comprises the following steps: S1: A device layout is provided, in which a plurality of polysilicon gates distributed along a first direction, a plurality of active areas distributed along a second direction, and a plurality of storage units are formed, and a gate cut is arranged on the polysilicon gate, wherein the first direction is perpendicular to the second direction.

[0020] For example, the device layout can be obtained by drawing with layout software. Figure 2 As shown, a number of polysilicon gates are spaced apart along a first direction in the device layout, and the polysilicon gates extend along a second direction, a number of active regions are spaced apart along the second direction, and the active regions extend along the first direction, the first direction is perpendicular to the second direction, and a number of symmetrically repeated storage cells 30 are also formed in the device layout. A gate cut is provided on the polysilicon gate, and in the SRAM device, the gate cut is mainly used to cut off the gate between the transfer transistor and the pull-up transistor.

[0021] Furthermore, each memory cell includes a plurality of transistors, the transistors include a pull-up transistor, a pull-down transistor, and a transmission transistor, and the active regions where the transmission transistor and the pull-down transistor are located are adjacent to the active region where the pull-up transistor is located. The polysilicon gate constituting the gate structure of the transmission transistor is adjacent to the polysilicon gate constituting the gate structure of the pull-up transistor and the pull-down transistor. Figure 2 The storage unit 30 in FIG. 1 is taken as an example to illustrate that the storage unit 30 includes a first pull-up transistor PU1, a first pull-down transistor PD1, a first transmission transistor PG1, a second pull-up transistor PU2, a second pull-down transistor PD2, and a second transmission transistor PG2. Figure 2As shown. Among them, the first pull-up transistor PU1 is located in the first active area 201, the first transfer transistor PG1 and the first pull-down transistor PD1 are both located in the second active area 202, the gate structure of the first transfer transistor PG1 is composed of the first polysilicon gate 101, and the gate structure of the first pull-up transistor PU1 and the gate structure of the first pull-down transistor PD1 are both composed of the second polysilicon gate 102. A first gate cut POC1 is provided on the first polysilicon gate 101, and the first gate cut POC1 is located between the first active area 201 and the second active area 202. The second pull-up transistor PU2 is located in the third active area 203, the second transfer transistor PG2 and the first pull-down transistor PD2 are both located in the fourth active area 204, the gate structure of the second transfer transistor PG2 is composed of the second polysilicon gate 102, and the gate structure of the second pull-up transistor PU2 and the gate structure of the second pull-down transistor PD2 are both composed of the first polysilicon gate 101. A first gate cut POC2 is disposed on the second polysilicon gate 102 , and the second gate cut POC2 is located between the third active region 203 and the fourth active region 204 .

[0022] S2: Adjust the distance between the gate cut and the active area adjacent to it, and update the device layout.

[0023] Exemplarily, in the layout software, the distance between each gate cut and the active area adjacent to the gate cut in the device layout is adjusted, and after the adjustment is completed, the device layout is updated and saved.

[0024] Further, for any gate cut, the distance between the gate cut and the active area adjacent to it where the transfer transistor is located can be adjusted by adjusting its size in the second direction, or the distance between the gate cut and the active area adjacent to it where the transfer transistor is located can be adjusted by adjusting its position on the polysilicon gate, or the distance between the gate cut and the active area adjacent to it where the transfer transistor is located can be adjusted by adjusting the size and position of the gate cut at the same time, and the specific adjustment method and adjustment amount can be set according to specific needs. After the adjustment is completed, the device layout is updated and saved.

[0025] Furthermore, for any gate cut, the adjustment target is consistent, that is, for each gate cut, after the adjustment is completed, the distance between it and the active area where the adjacent transfer transistor is located is consistent. Figure 2 As shown, after the adjustment is completed, the distance between the first gate cut POC1 and the second active region 202 is equal to the distance between the second gate cut POC2 and the fourth active region 204 .

[0026] Further, when adjusting the distance between the gate cut and the adjacent active region, the closer the distance between the gate cut and the active region where the transmission transistor is located and adjacent to it, the worse the performance of the transmission transistor. Taking Figure 2 as an example, on the first polysilicon gate 101, due to the existence of the first gate cut POC1, after the subsequent gate line end etching process, dielectric materials such as silicon oxide and silicon nitride filling the trench apply stress to the channel, affecting the threshold voltage, saturation current, etc. of each transistor. For the first transmission transistor PG1, the closer the first gate cut POC1 on the first polysilicon gate 101 is to it, the greater the compressive stress on the channel in the first transmission transistor PG1, and the worse the performance of the first transmission transistor PG1. For the first pull-up transistor PU1 and the first pull-down transistor PD1, since the second gate cut POC2 on the second polysilicon gate 102 where they are located is farther away, the performance is weakly affected. Therefore, for any gate cut, it mainly affects the performance of the transmission transistor on the polysilicon gate where it is located, while having a weak impact on the performance of the pull-up transistor and the pull-down transistor on the polysilicon gate where it is located, thus achieving the technical effect of changing the speed of the transmission transistor while keeping the pull-up transistor and the pull-down transistor unchanged, achieving the purpose of regulating the cell ratio of the SRAM device, and realizing the controllable adjustment of the read and write performance of the SRAM device.

[0027] S3: Manufacture the SRAM device according to the updated device layout.

[0028] Exemplarily, manufacture the SRAM device according to the updated device layout and the current standard manufacturing process.

[0029] S4: Perform performance testing on the SRAM device to obtain test results.

[0030] Exemplarily, the WAT performance testing can be performed on the SRAM device to obtain test results.

[0031] Further, the test results include the performance parameters of the SRAM device and the performance parameters of at least one selected target storage cell, and the target storage cell is any one of all storage cells. For example, a storage cell can be pre-selected as the target storage cell to be tested. When performing the WAT performance testing, by testing the target storage cell, the threshold voltage and saturation current of each transistor, such as the pull-up transistor, the pull-down transistor, and the transmission transistor, can be obtained.

[0032] S5: Compare the test results with the preset device performance target.

[0033] Exemplarily, compare the obtained test results with the preset device performance target.

[0034] When the obtained test results meet the preset device performance target, the above process can be ended and mass production can be carried out with the current device layout. Otherwise, S1 to S5 in the above are repeated until the test results meet the device performance target.

[0035] The method for regulating the performance of an SRAM device provided in an embodiment of the present application achieves the technical effect of changing the speed of the transmission transistor by adjusting the distance between the gate cut and the active area adjacent thereto, while keeping the pull-up transistor and the pull-down transistor unchanged, thereby achieving the purpose of regulating the cell ratio of the SRAM device and realizing controllable regulation of the read and write performance of the SRAM device. At the same time, the method mainly adjusts the gate cut in the design stage of the device layout, without increasing the process complexity, and without requiring additional cost or sacrificing device area.

[0036] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for regulating the performance of an SRAM device, characterized in that: include: S1: providing a device layout, wherein a plurality of polysilicon gates distributed along a first direction, a plurality of active areas distributed along a second direction, and a plurality of storage units are formed in the device layout, and a gate cut is arranged on the polysilicon gate; wherein the first direction is perpendicular to the second direction; S2: adjusting the distance between the gate cut and the active area adjacent thereto, and updating the device layout; S3: manufacturing the SRAM device according to the updated device layout; S4: Performing a performance test on the SRAM device to obtain a test result; S5: comparing the test results with a preset device performance target; Repeat S1 to S5 until the test result meets the device performance target.

2. The method for regulating the performance of an SRAM device according to claim 1, characterized in that: Each of the memory cells comprises a plurality of transistors, the transistors comprising a pull-up transistor, a pull-down transistor and a transmission transistor, the active regions where the transmission transistor and the pull-down transistor are located are adjacent to the active region where the pull-up transistor is located; a polysilicon gate constituting a gate structure of the transmission transistor is adjacent to a polysilicon gate constituting a gate structure of the pull-up transistor and the pull-down transistor; The gate cut is located on a polysilicon gate constituting a gate structure of the pass transistor.

3. The method for regulating the performance of an SRAM device according to claim 2, characterized in that: The step of adjusting the distance between the gate cut and an active area adjacent thereto comprises: By adjusting the size of the gate cut and / or the position of the gate cut on the polysilicon gate, the distance between the gate cut and the active region adjacent to the gate cut and where the transfer transistor is located is adjusted.

4. The method for regulating the performance of an SRAM device according to claim 1, characterized in that: The test result includes the performance parameter of the SRAM device and the performance parameter of at least one selected target memory cell, where the target memory cell is any one of all the memory cells.

5. The method for regulating the performance of an SRAM device according to claim 4, characterized in that: The performance parameters of the target storage unit include but are not limited to the threshold voltage and saturation current of each transistor.

6. The method for regulating the performance of an SRAM device according to claim 2, characterized in that: The closer the distance between the gate cut and the active region adjacent thereto where the transfer transistor is located, the worse the performance of the transfer transistor.

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