Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a substrate; discrete laminated devices are formed on the substrate, each laminated device comprises a first device structure and a second device structure which are sequentially arranged in the normal direction of the surface of the substrate, the first device structure comprises a first transistor, the second device structure comprises a second transistor and a third transistor, and the third transistor comprises a third transistor and a fourth transistor. The second transistor and the third transistor share a second channel layer, and the second channel layer is formed in an epitaxial mode. By adopting the technical scheme, the storage density of the semiconductor structure can be improved, and the data read-write speed is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Static Random Access Memory (SRAM) has the characteristics of low power consumption, high-speed access and high integration, and is widely used in various chips.

[0003] In order to improve the performance of the chip, higher requirements are put forward for the static random access memory, for example, the static random access memory needs to have a higher storage density. However, due to the limitation of the process node, the storage density of the static random access memory cannot be further increased, and the refinement requirements of the process machine are high, which reduces the performance of the static random access memory. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor structure and a method for forming the same, which can improve the storage density of the semiconductor structure and increase the data reading and writing speed.

[0005] The present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming discrete stacked devices on the substrate, each stacked device comprising a first device structure and a second device structure arranged in sequence along a normal direction of the substrate surface, wherein the first device structure comprises a first transistor, the second device structure comprises a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, and the second channel layer is formed by epitaxy.

[0006] Accordingly, the present invention provides a semiconductor structure, comprising: a substrate; discrete stacked devices located on the substrate, each stacked device comprising a first device structure and a second device structure sequentially arranged along a normal direction of a surface of the substrate; The first device structure includes a first transistor, the second device structure includes a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, and the second channel layer is formed by epitaxy.

[0007] Compared with the prior art, the technical solution of the present invention has the following advantages: In the method for forming a semiconductor structure provided by the present invention, by making each stacked device be arranged along the surface direction of the substrate normal line, and the second transistor and the third transistor share the second channel layer, the volume of each stacked device is reduced, and the integration of the stacked device is improved, thereby improving the storage density; and, by forming the second channel layer by epitaxial method, the size of the second channel layer can be reduced, and it is not limited by the lithography machine, and the second channel layer formed by epitaxial growth has better doping density and uniformity, reducing the influence of the short channel effect, thereby improving the storage density of the semiconductor structure and improving the data reading and writing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of a top view of a semiconductor structure in a first embodiment of the present invention; Figures 2 to 14 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention; Fig.15 for Figure 1 A schematic diagram of the structure of the electrical connection relationship of the stacked device is included; Fig.16 for Fig.15 A schematic diagram of an equivalent circuit of the semiconductor structure shown; Fig.17 It is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention; Fig.18 Schematic diagram of structures corresponding to each step in the third embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0009] As can be seen from the background technology, due to the limitation of process nodes, the size of static random access memory cannot be further reduced. This is because: when the process node continues to decrease, a photolithography machine adapted to the process node is required to perform the patterning process. Due to the limitation of the process machine (such as a photolithography machine), the size of the conductive channel cannot meet the process requirements, and the storage density of the static random access memory cannot be further increased.

[0010] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming discrete stacked devices on the substrate, each stacked device comprising a first device structure and a second device structure arranged in sequence along a normal direction of the substrate surface, wherein the first device structure comprises a first transistor, the second device structure comprises a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, and the second channel layer is formed by epitaxy.

[0011] By adopting the method for forming a semiconductor structure provided by the present invention, by arranging each stacked device along the surface direction of the substrate normal, and sharing the second channel layer between the second transistor and the third transistor, the volume of each stacked device is reduced, and the integration degree of the stacked devices is improved, so that the storage density can be improved; moreover, by forming the second channel layer by epitaxy, the size of the second channel layer can be reduced, without being limited by a lithography machine, and the formed second channel layer has better doping density and uniformity through epitaxial growth, reducing the influence of the short channel effect. Therefore, the storage density of the semiconductor structure can be improved, and the data reading and writing speed can be increased.

[0012] To make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be illustrated below with reference to the accompanying drawings.

[0013] Figure 1 It is a top view structural schematic diagram of the semiconductor structure in the first embodiment of the present invention, Figures 2 to 14 It is a structural schematic diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention, Figures 2 to 13 It is Figure 1 a cross-sectional view along the A-A1 direction in Fig.14 It is Figure 1 a cross-sectional view along the B-B1 direction in Fig.15 It is Figure 1 a schematic diagram of the electrical connection relationship of the stacked devices included in Fig.16 It is Fig.15 an equivalent circuit schematic diagram of the semiconductor structure shown.

[0014] It should be noted that, first, for the convenience of understanding and explaining the present application, Figure 1 the dimensions are not exactly corresponding to those of other drawings, but this does not limit the present application; second, in Figure 1 the top view structural schematic diagram shown, for the convenience of explanation, the first transistors Q4 and Q3 are also schematically shown, but in the actual top view, Q4 and Q3 cannot be shown; third, in order to show the relative position relationship between the first transistor Q3 and the second transistor Q1, and the relative position between the first transistor Q4 and the second transistor Q2, Figure 1 only a part of the second transistors Q1 and Q2 is shown; fourth, it should be noted that Figures 2 to 18 it is a schematic diagram and does not show all the structures of the substrate 100.

[0015] Refer to Figures 1 to 15 , and provide the substrate 100.

[0016] The substrate 100 can provide a process operation basis for the formation process of the semiconductor structure.

[0017] The semiconductor structure may include a memory cell, such as a static random access memory SRAM. In some other embodiments, the semiconductor structure may also include other types of memory cells.

[0018] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0019] The semiconductor substrate may also be a silicon-on-insulator structure, such as silicon-on-insulator (SOI), or a germanium-on-insulator structure, such as germanium-on-insulator; the semiconductor substrate may also include an alloy semiconductor structure, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof; the semiconductor substrate may also be a lightly doped substrate or a substrate on which an epitaxial layer is grown.

[0020] A discrete stacked device (as a non-limiting example, Figure 1 A separate first stacked device 200 and a second stacked device 300 are shown, each stacked device comprising a first device structure (not shown) and a second device structure (not shown) sequentially arranged along the normal direction of the surface of the substrate 100 .

[0021] In this embodiment, by forming a first device structure and a second device structure having a stacking relationship, the integration of the stacked device is improved, so that more first device structures and second device structures can be formed to increase the storage density.

[0022] In this embodiment, the first device structure may include a first transistor, and the second device structure may include a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, and the second channel layer is formed by epitaxy.

[0023] Forming the second channel layer by epitaxy can reduce the size of the second channel layer and reduce the limitation of the photolithography machine. The second channel layer formed by epitaxial growth has better doping density and uniformity, which reduces the influence of the short channel effect and improves the reading and writing speed.

[0024] Furthermore, by making the second transistor and the third transistor share the second channel layer, the integration level of the stacked device can be further improved.

[0025] In a specific embodiment, the first stacked device 200 may include a first transistor Q4 , a second transistor Q2 located on the first transistor Q4 , and a third transistor T2 sharing a second channel layer with the second transistor Q2 .

[0026] Accordingly, the second stacked device 300 may include a first transistor Q3 , a second transistor Q1 located on the first transistor Q3 , and a third transistor T1 sharing a second channel layer with the second transistor Q1 .

[0027] It should be noted that, first, when the semiconductor structure is an SRAM, the first stacked device 200 and the second stacked device 300 constitute an SRAM bit cell.

[0028] Specifically, the first transistor Q4 in the first stacked device 200 can be used as a first pull-up transistor, the second transistor Q2 can be used as a first pull-down transistor, the third transistor T2 can be used as a first control transistor, and the first transistor Q4 and the second transistor Q2 constitute a first inverter.

[0029] The first transistor Q3 in the second stacked device 300 can be used as a second pull-up transistor, the second transistor Q1 can be used as a second pull-down transistor, the third transistor T1 can be used as a second control transistor, and the first transistor Q3 and the second transistor Q1 constitute a second inverter.

[0030] Second, the "discrete stacked device" mentioned in the present invention refers to a device stacked vertically along the surface of the substrate 100, each layer has a specific function, and together they achieve overall performance.

[0031] In this embodiment, the steps of forming each stacked device may be the same.

[0032] For ease of understanding and description, the formation process of the first stacked device 200 is exemplarily described.

[0033] Specifically, the steps of forming a stacked device (eg, the first stacked device 200 ) may include: See also Figures 1 to 8 , forming a first number (in a non-limiting example, the first number may be greater than or equal to 3) of first epitaxial layers on the substrate 100, at least one of the epitaxial layers serving as a first channel layer of the first transistor, wherein each of the first epitaxial layers has its own doping type and doping concentration; forming a first gate structure 210, wherein the first gate structure 210 at least contacts the sidewall of the first channel layer.

[0034] In this embodiment, the first channel layer of the first transistor is formed by epitaxy; and the first gate structure 210 is in contact with at least the sidewall of the first channel layer to achieve control over the first channel layer.

[0035] More specifically, each first epitaxial layer is formed by an epitaxial process, and a doping treatment is performed during the epitaxial growth process.

[0036] In other words, when forming any first epitaxial layer, the doping operation is performed while the epitaxial process is being performed. On the one hand, the process parameters of the epitaxial process are controllable, and the first epitaxial layers with different thicknesses can be formed, thereby reducing the thickness of part or all of the first epitaxial layers and forming a first channel layer with a smaller size; on the other hand, the epitaxial process and the doping operation are performed simultaneously, and the first epitaxial layer formed by epitaxial growth has better doping density and uniformity, and the uniformity of doping concentration at different positions of the same epitaxial layer is improved, which is conducive to reducing the short channel effect.

[0037] In this embodiment, the epitaxial process may include an atomic layer deposition process or a molecular beam epitaxy process.

[0038] In this embodiment, for any first epitaxial layer, the formation step may include: forming multiple sub-first epitaxial layers in sequence, and performing doping treatment in the step of forming any sub-first epitaxial layer, wherein in the step of forming each sub-first epitaxial layer, the doping type and doping concentration are the same to further improve the doping uniformity of the first epitaxial layer.

[0039] In this embodiment, by making each first epitaxial layer have its own doping type, the doping type between adjacent first epitaxial layers can be controlled. Among the three continuous first epitaxial layers, the doping type of the middle epitaxial layer is different from the doping type of the upper and lower first epitaxial layers. In this way, an epitaxial structure with a conductive channel and source and drain doping regions can be formed by the three epitaxial layers with the above-mentioned doping characteristics, so as to enhance the control capability of the gate structure.

[0040] In this embodiment, the doping concentration of the first epitaxial layer directly affects parameters such as the conductivity and carrier mobility of the semiconductor structure. Therefore, the doping concentration of each first epitaxial layer can be set based on actual needs so that each first epitaxial layer has its own doping concentration, that is, different first epitaxial layers have the same or different doping concentrations.

[0041] See also Figures 6 to 12, forming a second number of second epitaxial layers on the first gate structure 210, at least one second epitaxial layer serving as the second channel layer, wherein each second epitaxial layer has its own doping type and doping concentration; forming a second gate structure 230 and a third gate structure 232, wherein the second gate structure 230 and the third gate structure 232 are in contact with at least the sidewalls of the second channel layer.

[0042] In this embodiment, after forming the first gate structure 210 , a second channel layer is formed by epitaxy, and a second gate structure 230 and a third gate structure 232 contacting two sidewalls of the second channel layer are formed.

[0043] More specifically, each second epitaxial layer is formed by an epitaxial process, and a doping treatment is performed during the epitaxial growth process.

[0044] In other words, when forming any second epitaxial layer, the doping operation is performed while the epitaxial process is performed. On the one hand, the process parameters of the epitaxial process are controllable, and the second epitaxial layer with different thicknesses can be formed, so that the thickness of part or all of the second epitaxial layer can be reduced to form a second channel layer of smaller size; on the other hand, the epitaxial process and the doping operation are performed simultaneously, and the second epitaxial layer formed by epitaxial growth has better doping density and uniformity, and the uniformity of doping concentration at different positions of the same epitaxial layer is improved, which is conducive to reducing the short channel effect.

[0045] In this embodiment, the epitaxial process may include an atomic layer deposition process or a molecular beam epitaxy process.

[0046] In this embodiment, for any second epitaxial layer, the formation step may include: forming multiple sub-second epitaxial layers in sequence, and performing doping treatment in the step of forming any sub-second epitaxial layer, wherein in the step of forming each sub-second epitaxial layer, the doping type and doping concentration are the same to further improve the doping uniformity of the second epitaxial layer.

[0047] In this embodiment, by making each second epitaxial layer have its own doping type, the doping type between adjacent epitaxial layers can be controlled. Among the three consecutive second epitaxial layers, the doping type of the middle epitaxial layer is different from the doping type of the upper and lower second epitaxial layers. In this way, an epitaxial structure with a conductive channel and source and drain doping regions can be formed through the three epitaxial layers with the above-mentioned doping characteristics to enhance the control capability of the gate structure.

[0048] In this embodiment, the doping concentration of the second epitaxial layer directly affects parameters such as the conductivity and carrier mobility of the semiconductor structure. Therefore, the doping concentration of each second epitaxial layer can be set based on actual needs so that each second epitaxial layer has its own doping concentration, that is, different second epitaxial layers have the same or different doping concentrations.

[0049] In actual applications, the inventors further discovered that, under the influence of temperature, there is diffusion between adjacent first epitaxial layers, and there is diffusion between adjacent second epitaxial layers, and the higher the temperature, the more serious the diffusion phenomenon. This causes the doping ions between adjacent epitaxial layers to transfer, which will change the characteristics of some or all epitaxial layers, significantly reduce the performance of the semiconductor structure, or the semiconductor structure cannot play its intended role.

[0050] As an example, if the doping concentrations of adjacent first epitaxial layers are different, the diffusion phenomenon may cause the doping concentration of the first epitaxial layer with a high doping concentration to become lower, while the doping concentration of the first epitaxial layer with a low doping concentration to increase; if the doping concentrations of adjacent second epitaxial layers are different, the diffusion phenomenon may cause the doping concentration of the second epitaxial layer with a high doping concentration to become lower, while the doping concentration of the second epitaxial layer with a low doping concentration to increase.

[0051] As another example, if the doping types of adjacent first epitaxial layers are different, the diffusion phenomenon may make the doping types of the two first epitaxial layers consistent, and the semiconductor structure may fail; if the doping types of adjacent second epitaxial layers are different, the diffusion phenomenon may make the doping types of the two second epitaxial layers consistent, and the semiconductor structure may fail.

[0052] In this embodiment, each first epitaxial layer and each second epitaxial layer are formed in a relatively low temperature environment.

[0053] In some embodiments, the formation temperature of each first epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius, for example, 650 degrees Celsius, 700 degrees Celsius, and 750 degrees Celsius.

[0054] That is, the formation temperature of any first epitaxial layer is not higher than 800 degrees Celsius, so that when forming the second layer and subsequent first epitaxial layers, the diffusion phenomenon is reduced or avoided, so that each first epitaxial layer maintains its own characteristics and improves the performance of the semiconductor structure.

[0055] In this embodiment, the formation parameters of each first epitaxial layer may also include: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and at least one of an epitaxial rate of 200 angstroms / minute to 300 angstroms / minute.

[0056] In other words, by changing the formation temperature of the first epitaxial layer, at least one of the aforementioned parameters is adaptively adjusted, so that the silicon source gas used in the epitaxial process is adapted to the current temperature, and by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, and the formation quality of the epitaxial layer can be improved. That is, when the formation temperature is reduced, the epitaxial rate is also reduced.

[0057] In some embodiments, the formation temperature of each second epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius, for example, 650 degrees Celsius, 700 degrees Celsius, and 750 degrees Celsius.

[0058] That is, the formation temperature of any second epitaxial layer is not higher than 800 degrees Celsius, so that when forming the second layer and subsequent second epitaxial layers, the diffusion phenomenon is reduced or avoided, so that each second epitaxial layer maintains its own characteristics and improves the performance of the semiconductor structure.

[0059] In this embodiment, the formation parameters of each second epitaxial layer may also include: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and at least one of an epitaxial rate of 200 angstroms / minute to 300 angstroms / minute.

[0060] In other words, by changing the formation temperature of the second epitaxial layer, at least one of the aforementioned parameters is adaptively adjusted, so that the silicon source gas used in the epitaxial process is adapted to the current temperature, and by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, and the formation quality of the epitaxial layer can be improved. That is, when the generation temperature is reduced, the epitaxial rate is also reduced.

[0061] It should be noted that in order to further reduce the impact of temperature, the epitaxial layer, gate structure, and film layers related to the gate structure in this solution are all formed using a process not exceeding 800 degrees Celsius.

[0062] In this embodiment, the first number is greater than or equal to 3, that is, the number of first epitaxial layers is at least 3. By making the number of first epitaxial layers greater than or equal to 3, at least a source, a drain, and a channel layer located between the source and the drain can be formed to realize the function of current flow.

[0063] When the first number is greater than or equal to 3, the method for forming the semiconductor structure in this solution can satisfy: A first first epitaxial layer, wherein the first first epitaxial layer is used to form a first source-drain doped layer.

[0064] The first source-drain doped layer can be used as a source or a drain of the first transistor Q3. When the first transistor Q3 is working, the first source-drain doped layer can be used to provide a carrier source.

[0065] In this embodiment, when the first transistor is an NMOS transistor, the first first epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the first first epitaxial layer may be Si or SiC, or other materials compatible with the substrate material; when the first transistor Q3 is a PMOS transistor, the first first epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the first first epitaxial layer may be Si or SiGe, or other materials compatible with the substrate material.

[0066] In a specific embodiment, the material of the first epitaxial layer may be Si.

[0067] A second first epitaxial layer, wherein the second first epitaxial layer is used to form a first channel layer.

[0068] The first channel layer is used to provide a flow region for a carrier source.

[0069] In this embodiment, when the first transistor is an NMOS transistor, the second first epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the second first epitaxial layer may be Si or SiGe, or other materials compatible with the substrate material; when the first transistor is an NMOS transistor, the second first epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the second first epitaxial layer is Si or SiC, or other materials compatible with the substrate material.

[0070] In a specific embodiment, the material of the second first epitaxial layer may be Si.

[0071] The third first epitaxial layer is used to form a second source-drain doped layer.

[0072] The second source-drain doped layer can be used as a source or a drain of the first transistor Q3. When the first transistor Q3 is working, the second source-drain doped layer can be used to provide a carrier source.

[0073] In this embodiment, when the first transistor Q3 is an NMOS transistor, the third first epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the third first epitaxial layer may be Si or SiC, or other materials compatible with the substrate material; when the first transistor Q3 is a PMOS transistor, the third epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the third first epitaxial layer is Si or SiGe, or other materials compatible with the substrate material.

[0074] In a specific embodiment, the material of the third first epitaxial layer may be Si.

[0075] It should be pointed out that, first, when the number of epitaxial layers is larger (for example, greater than 3), there are adjacent first epitaxial layers used as layers with the same function, for example, two consecutive first epitaxial layers are used as source and drain doping layers; second, the functions of the first first epitaxial layer, the second first epitaxial layer and the third first epitaxial layer listed in the above example are only for schematic illustration, which is used to indicate that there are three consecutive first epitaxial layers that can be used as the source, the drain, and the channel layer between the source and the drain in the semiconductor structure, and it should not be understood as a limitation on the present invention.

[0076] In this embodiment, the first source-drain doped layer is one of the source and the drain, and the second source-drain doped layer is the other of the source and the drain.

[0077] In other words, one of the first source-drain doped layer and the second source-drain doped layer serves as a source, and the other serves as a drain.

[0078] In this embodiment, the doping type of the first source-drain doping layer is different from the doping type of the channel layer.

[0079] In a specific embodiment, the doping type of the first source-drain doping layer is N-type, and the doping type of the first channel layer is P-type.

[0080] In a specific embodiment, the doping type of the first source-drain doping layer is P-type, and the doping type of the first channel layer is N-type.

[0081] In this embodiment, the doping type of the second source-drain doping layer is different from the doping type of the first channel layer.

[0082] In a specific embodiment, the doping type of the second source-drain doping layer is N-type, and the doping type of the first channel layer is P-type.

[0083] In a specific embodiment, the doping type of the second source-drain doping layer is P-type, and the doping type of the first channel layer is N-type.

[0084] It should be pointed out that, first, this scheme does not limit the doping types of the first source-drain doping layer, the second source-drain doping layer and the first channel layer, as long as the doping types of the first source-drain doping layer and the first channel layer are different, and the doping types of the second source-drain doping layer and the first channel layer are different; second, in this scheme, when the doping type is N-type, the doping ions may include: P, As or Sb; when the doping type is P-type, the doping ions may include: B, Ga or In.

[0085] In this embodiment, the first source-drain doped layer and the second source-drain doped layer have the same doping type, and are different from the channel layer, so that when a voltage is applied to the gate structure, the carrier (electron or hole) concentration in the channel layer region will increase significantly, so that the region adjacent to the channel layer and the gate structure is inverted to form a conductive channel. When a voltage is applied between the first source-drain doped layer and the second source-drain doped layer, the carriers begin to move along the conductive channel under the action of the electric field to form a current.

[0086] In this embodiment, the doping concentration of the first source-drain doping layer is greater than the doping concentration of the first channel layer. Under the same electric field strength, the first source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction capability.

[0087] In some embodiments, the doping concentration of the first source-drain doping layer is 10 to 100 times the doping concentration of the channel layer.

[0088] By making the doping concentration of the first source-drain doping layer 10 to 100 times the doping concentration of the channel layer, the selection range of the doping concentration of the first source-drain doping layer is broadened, and based on the doping concentration of the first channel layer, a first source-drain doping layer adapted to the doping concentration of the first channel layer can be formed.

[0089] In a specific embodiment, the doping concentration of the first source-drain doping layer can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the first channel layer can be 1E 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0090] In this embodiment, the doping concentration of the second source-drain doping layer is greater than the doping concentration of the first channel layer. Under the same electric field strength, the second source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction capability.

[0091] In some embodiments, the doping concentration of the second source-drain doping layer is 10 to 100 times the doping concentration of the first channel layer.

[0092] By making the doping concentration of the second source-drain doping layer 10 to 100 times the doping concentration of the channel layer, for example, 10 times, 50 times, 80 times, etc., this broadens the selection range of the doping concentration of the second source-drain doping layer, and can form a second source-drain doping layer that is compatible with the doping concentration of the channel layer based on the doping concentration of the channel layer.

[0093] In a specific embodiment, the doping concentration of the second source-drain doping layer can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the first channel layer can be 1E 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0094] In this embodiment, the thickness of the channel layer will directly affect the conductivity, current driving capability and switching speed of the semiconductor structure. For example, when the thickness of the channel layer is thin, the migration time of carriers in the channel layer can be reduced, thereby improving the conductivity.

[0095] In this solution, the first channel layer is in direct contact with the first source-drain doping layer and the second source-drain doping layer, the short channel effect is not obvious, and the thickness range of the channel layer spans a large range, so it can be set based on process requirements to cope with different process nodes.

[0096] In a specific embodiment, the thickness of the first channel layer is 10 nm to 50 nm, for example, 14 nm, 28 nm, 40 nm, etc., so that a process machine with a large technology node can be used to produce a channel layer equivalent to a smaller technology node, thereby reducing the requirements for the process machine.

[0097] It should be noted that the thickness of the channel layer described in the above example is only an example. In the actual manufacturing process, the thickness of the channel layer can be appropriately reduced or increased.

[0098] In other words, the present solution adopts an epitaxial process, and the thickness of the first channel layer is controllable. The thickness of the first channel layer can be made to meet the process requirements by setting the parameters of the epitaxial process according to the requirements of the semiconductor structure to be manufactured.

[0099] In this embodiment, the first source-drain doping layer or the second source-drain doping layer plays a role in providing carriers, and its impact on the performance of the semiconductor structure is smaller than the impact of the channel layer on the performance of the semiconductor structure. The thickness of the first source-drain doping layer or the second source-drain doping layer can be greater than the thickness of the channel layer.

[0100] In addition, a thicker first source-drain doped layer or a thicker second source-drain doped layer can generally reduce the contact resistance between the first source-drain doped layer and the channel layer, thereby increasing the carrier injection efficiency and improving the conductivity of the device.

[0101] In a specific embodiment, the thickness of the first source-drain doping layer may be 500 angstroms to 1000 angstroms.

[0102] In a specific embodiment, the thickness of the second source-drain doping layer may be 500 angstroms to 1000 angstroms.

[0103] In this embodiment, the second number is greater than or equal to 3, that is, the number of second epitaxial layers is at least 3. By making the number of second epitaxial layers greater than or equal to 3, at least a source, a drain, and a channel layer located between the source and the drain can be formed to realize the function of current flow.

[0104] When the second number is greater than or equal to 3, the method for forming the semiconductor structure in this solution may satisfy: A first second epitaxial layer, wherein the first second epitaxial layer is used to form a third source-drain doped layer.

[0105] A second second epitaxial layer, wherein the second second epitaxial layer is used to form the second channel layer.

[0106] A third second epitaxial layer is formed, wherein the third second epitaxial layer forms a fourth source-drain doped layer.

[0107] The third source-drain doped layer is one of the source and the drain, and the fourth source-drain doped layer is the other of the source and the drain.

[0108] In this embodiment, the doping concentration of the third source-drain doping layer can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the second channel layer can be 1E 12 atom / cm 3 To 1E 13 atom / cm 3 , the doping concentration of the fourth source-drain doping layer can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 .

[0109] It should be noted that for the detailed description of the second epitaxial layer, reference can be made to the description of the first epitaxial layer, which will not be elaborated here.

[0110] In this embodiment, in different application scenarios, the order of forming the first gate structure and the first number of first epitaxial layers may be different, and the order of forming the second gate structure, the third gate structure and the second number of second epitaxial layers may be different, which are respectively explained by examples below.

[0111] In this embodiment, during the process of forming the first number (wherein the first number may be 3) of first epitaxial layers, the first gate structure 210 is formed, wherein the top first epitaxial layer 212 is located above the first gate structure 210 .

[0112] Accordingly, see Figures 2 to 7 , the forming method may include: See also Figures 2 to 4 , forming a third number of first epitaxial layers.

[0113] In this embodiment, the third number of first epitaxial layers may include a first epitaxial layer for forming a first channel layer.

[0114] In a specific embodiment, the second first epitaxial layer 206 may serve as a first channel layer.

[0115] For more details about the first epitaxial layer, please refer to the aforementioned examples.

[0116] In this embodiment, the third number is smaller than the first number.

[0117] In a specific embodiment, the first number may be 3, and the third number may be 2. That is, the first first epitaxial layer 202 and the second first epitaxial layer 206 are first formed on the substrate 100 , and then the third first epitaxial layer 212 is formed after the first gate structure 210 is formed.

[0118] More specifically, see Figure 2 , a first epitaxial layer 202 is formed on the substrate 100 .

[0119] The first epitaxial layer 202 may be used as a source region or a drain region.

[0120] See also Figure 3 and Figure 4 , a second first epitaxial layer 206 is formed on the first first epitaxial layer 202 .

[0121] The second first epitaxial layer 206 may serve as a first channel layer.

[0122] See also Figure 5 , forming a first trench G1 penetrating at least part or all of the first epitaxial layer, wherein the first trench exposes a sidewall of the penetrated first epitaxial layer.

[0123] The first trench G1 provides a location space for forming the first gate structure 210 .

[0124] In this embodiment, the first trench G1 can penetrate the second first epitaxial layer 206 and part or all of the thickness of the first first epitaxial layer 202 and expose all side walls of the second first epitaxial layer 206 and part or all of the side walls of the first first epitaxial layer 202 .

[0125] In short, the first trench G1 may penetrate the already formed first epitaxial layer, and needs to expose the sidewall of the first epitaxial layer serving as the first channel layer.

[0126] In this embodiment, a patterning process is adopted to form the first trench G1 in the second first epitaxial layer 206 .

[0127] See also Figure 6 , forming the first gate structure 210 in the first trench G1, the first gate structure 210 at least adjacent to the first channel layer (ie Figure 6 The second layer (illustrated as the first epitaxial layer 206) is in contact with the sidewalls thereof.

[0128] When the semiconductor device is working, the first gate structure 210 is used to control the opening and closing of the first channel layer.

[0129] In this embodiment, the first gate structure 210 is a polysilicon gate structure or an amorphous silicon gate structure.

[0130] In this embodiment, the step of forming the first gate structure 210 includes: forming a first gate material layer (not shown) on the second first epitaxial layer 206 (i.e., the non-top first epitaxial layer), the first gate material layer also filling the first trench G1; removing the first gate material layer above the top of the first trench G1 through a planarization process (e.g., chemical mechanical polishing CMP), and retaining the first gate material layer in the first trench G1 as the first gate structure 210.

[0131] In this embodiment, the material of the gate material layer includes polysilicon.

[0132] In this embodiment, a chemical vapor deposition process is used to form the gate material layer. The film layer formed by the chemical vapor deposition method is thin and uniform, and has a dense structure, which is beneficial to improving the formation quality of the first gate structure 210 .

[0133] In a specific embodiment, the chemical vapor deposition process may be low pressure chemical vapor deposition (LPCVD).

[0134] It should be noted that during the process of forming the first gate structure 210 , the process temperature should not exceed 800 degrees Celsius.

[0135] See next Figure 5and Figure 6 The step of forming the first gate structure 210 may further include: forming a first gate oxide layer 208 on the sidewall and bottom of the first trench G1.

[0136] In this embodiment, the first gate oxide layer 208 may be formed by a furnace process.

[0137] Compared with conventional high-temperature thermal oxidation, the above method can grow a high-quality first gate oxide layer 208 at a lower temperature, has better thickness control and uniformity, and is compatible with the growth temperature of the first epitaxial layer.

[0138] In this embodiment, the first gate structure 210 may also cover the sidewall and bottom of the first gate oxide layer 208 .

[0139] In this embodiment, the first gate structure 210 contacts the sidewall of the first channel layer (ie, the second first epitaxial layer 206 ).

[0140] In this way, when the second first epitaxial layer 206 is used as the first channel layer, the first gate structure 210 is in contact with the second first epitaxial layer 206. When a driving voltage is applied to the first gate structure 210, the first channel layer can be turned on, so that the second first epitaxial layer 206 and the third first epitaxial layer 212 (see Figure 7 ) form a conductive channel between them.

[0141] In other words, in the present invention, the first gate structure 210 only needs to be in contact with the first epitaxial layer serving as the first channel layer. In other words, the first epitaxial layer in contact with the first gate structure 210 includes the first epitaxial layer serving as the first channel layer.

[0142] Accordingly, see Figure 3 and Figure 4 Before forming the first channel layer (ie, the second first epitaxial layer 206), the forming method may further include: forming a first insulating structure (eg, Figure 3 A first insulating structure 204 is formed in the first epitaxial layer 202 (shown in the figure), wherein the first portion of the first epitaxial layer is located below a first channel layer (ie, the second epitaxial layer 206) to be formed subsequently.

[0143] In this embodiment, the step of forming the first insulating structure 204 may include: forming a groove (not shown in the figure) in the first epitaxial layer 202, wherein the groove exposes all or part of the side walls of the first epitaxial layer 202; forming a first insulating material layer filling the groove on the first epitaxial layer 202; and using a planarization process to remove the first insulating material layer above the top of the groove, with the remaining part of the first insulating material layer serving as the first insulating structure 204.

[0144] The first insulating material layer may be formed by using a chemical vapor deposition process; the first insulating material layer is an insulating material, wherein the insulating material may include one or more of silicon oxide and silicon nitride.

[0145] In this embodiment, when the first insulating structure 204 is formed, see Figure 5 , the first trench G1 only penetrates the second first epitaxial layer 206 ; the first trench G1 is also located above the first insulating structure 204 and exposes the surface of the first insulating structure 204 .

[0146] See also Figure 7 , forming a remaining number of first epitaxial layers on the first gate structure.

[0147] In this embodiment, the remaining number of first epitaxial layers may refer to a third first epitaxial layer 212 , and the third first epitaxial layer 212 may serve as the other of a source region or a drain region.

[0148] See next Figure 7 After forming the first gate structure 210 , the formation method further includes: forming a second insulating structure 214 in the first epitaxial layer (eg, the third first epitaxial layer 212 ) above the first channel layer, wherein the second insulating structure 214 contacts the surface of the first gate structure 210 .

[0149] For the description of the second insulating structure 214 , please refer to the aforementioned example.

[0150] In this embodiment, during the process of forming the second number of second epitaxial layers, the second gate structure 230 and the third gate structure 232 are formed, wherein the top second epitaxial layer (eg Fig.12 The schematically illustrated third second epitaxial layer 234 is located above the second gate structure 230 and the third gate structure 232 .

[0151] Accordingly, see Figures 8 to 12 , the forming method may include: See also Figures 8 to 10 , forming a fourth number of second epitaxial layers.

[0152] In this embodiment, the fourth number of second epitaxial layers may include a second epitaxial layer for forming a second channel layer.

[0153] In a specific embodiment, the second second epitaxial layer 224 may serve as a second channel layer.

[0154] For more details about the second epitaxial layer, please refer to the aforementioned examples.

[0155] In this embodiment, the fourth number is smaller than the second number.

[0156] In a specific embodiment, the second number may be 3, and the fourth number may be 2, that is, the first second epitaxial layer 218 and the second first epitaxial layer 224 are first formed on the top first epitaxial layer, and after the second gate structure 230 and the third gate structure 232 are formed, the third second epitaxial layer 234 is formed.

[0157] More specifically, see Figure 8 , a first second epitaxial layer 218 is formed on the top first epitaxial layer (eg, the third first epitaxial layer 212 ).

[0158] The first second epitaxial layer 218 may be used as a source region or a drain region.

[0159] See also Fig. 9 and Fig.10 , a second second epitaxial layer 224 is formed on the first second epitaxial layer 218 .

[0160] The second second epitaxial layer 224 may serve as a second channel layer.

[0161] See next Fig.10 , forming a third trench G3 and a fourth trench G4 that penetrate at least a portion of the second epitaxial layer, and separate trenches G3 and G4, wherein the third trench G3 and the fourth trench G4 both expose the sidewalls of the penetrated second epitaxial layer.

[0162] The third trench G3 provides a location space for forming the second gate structure 230 , and the fourth trench G4 provides a location space for forming the third gate structure 232 .

[0163] In this embodiment, the third trench G3 can penetrate the second second epitaxial layer 224 and part or all of the thickness of the first second epitaxial layer 218 and expose all side walls of the second second epitaxial layer 224 and part or all of the side walls of the first second epitaxial layer 218.

[0164] The fourth trench G4 may penetrate the second second epitaxial layer 224 and part or all of the thickness of the first second epitaxial layer 218 , and expose all sidewalls of the second second epitaxial layer 224 and part or all of the sidewalls of the first second epitaxial layer 218 .

[0165] In this embodiment, the third trench G3 and the fourth trench G4 only penetrate the second second epitaxial layer 224 and expose the sidewall of the second second epitaxial layer 224 and the surface of the first second epitaxial layer 218 .

[0166] In short, the third trench G3 and the fourth trench G4 need to expose the sidewalls of the first epitaxial layer serving as the first channel layer.

[0167] The formation process of the third trench G3 and the fourth trench G4 may refer to the description of the first trench G1 .

[0168] See also Fig.11 , the second gate structure 230 is formed in the third trench G3 , and the second gate structure 230 at least contacts the sidewall of the second channel layer (eg, the second second epitaxial layer 224 ).

[0169] The formation process, material composition, and other related contents of the second gate structure 230 may refer to the aforementioned description of the first gate structure 210 .

[0170] In some embodiments, see Fig.10 and Fig.11 Before forming the second gate structure 230 , the forming method further includes: forming a second gate oxide layer 226 on the sidewall and the bottom of the third trench G3 .

[0171] The formation process, material composition, and other related contents of the second gate oxide layer 226 may refer to the aforementioned description of the first gate oxide layer 208 .

[0172] The third gate structure 232 is formed in the fourth trench G4 , and the third gate structure 232 at least contacts the sidewall of the second channel layer (eg, the second second epitaxial layer 224 ).

[0173] The formation process, material composition, and other related contents of the third gate structure 232 may refer to the aforementioned description of the first gate structure 210 .

[0174] In some embodiments, see Fig.10 and Fig.11 Before forming the third gate structure 232 , the forming method further includes: forming a third gate oxide layer 228 on the sidewall and bottom of the fourth trench G4 .

[0175] The formation process, material composition, and other related contents of the third gate oxide layer 228 may refer to the aforementioned description of the first gate oxide layer 208 .

[0176] It should be pointed out that, first, in the present scheme, the third trench G3 and the fourth trench G4 can be formed in the same step, or they can be formed in steps, and the present scheme does not impose any restrictions; second, in the present scheme, after the third trench G3 and the fourth trench G4 are formed, the second gate structure 230 and the third gate structure 232 can be formed in the same step, or they can be formed in steps, and the present scheme does not impose any restrictions.

[0177] In this embodiment, the second gate structure 230 is in contact with a sidewall on one side of the second channel layer, and the third gate structure 232 is in contact with a sidewall on the other side of the second channel layer.

[0178] In other words, the second gate structure 230 and the third gate structure 232 are distributed on both sides of the same second channel layer.

[0179] Correspondingly, before forming the second epitaxial layer serving as the second channel layer, the formation method further includes: forming a third insulating structure 220 in the second epitaxial layer of the third part (the first second epitaxial layer 218), wherein the second epitaxial layer of the third part is located below the subsequently formed second channel layer (i.e., the second second epitaxial layer 224).

[0180] The formation method, material composition, and other related contents of the third insulating structure 220 may refer to the aforementioned description of the first insulating structure 204 .

[0181] In this embodiment, when the third insulating structure 220 is formed, see Fig.10 , the third trench G3 only penetrates the second second epitaxial layer 224 ; the third trench G3 is also located above the third insulating structure 220 and exposes the surface of the third insulating structure 220 .

[0182] Correspondingly, before forming the second epitaxial layer serving as the second channel layer, the formation method further includes: forming a fourth insulating structure 222 in the second epitaxial layer of the third part, wherein the second epitaxial layer of the third part is located below the subsequently formed second channel layer (ie, the second second epitaxial layer 224).

[0183] The formation method, material composition, and other related contents of the fourth insulating structure 222 may refer to the aforementioned description of the first insulating structure 204 .

[0184] In this embodiment, when the fourth insulating structure 222 is formed, see Fig.10 , the fourth trench G4 only penetrates the second second epitaxial layer 224 ; the fourth trench G4 is also located above the fourth insulating structure 222 and exposes the surface of the fourth insulating structure 222 .

[0185] In this embodiment, see Fig.12 The projection of the second gate structure 230 on the substrate 100 covers at least a portion of the first gate structure 210, so that the second gate structure 230 and the first gate structure 210 have a gap D along the surface parallel to the substrate 100, which is conducive to reducing the difficulty of forming a conductive structure in contact with the first gate structure 210.

[0186] More specifically, see Fig.12, a projection of the second gate structure 230 on the first gate structure 210 has a spacing D between it and the distal end of the first gate structure 210 , and the distal end of the first gate structure 210 is an end that does not overlap with the second gate structure 230 .

[0187] See also Fig.12 , forming a remaining number of second epitaxial layers on the second gate structure 230 and the third gate structure 232 .

[0188] In this embodiment, the remaining number of second epitaxial layers may refer to a third second epitaxial layer 234 , and the third second epitaxial layer 234 may serve as the other of a source region or a drain region.

[0189] See also Figure 8 In the step of forming a discrete stacked device on the substrate 100, a first isolation structure 216 is also formed. The first isolation structure 216 is located between the first device structure and the second device structure to achieve insulation between the first device structure and the second device structure.

[0190] More specifically, the first isolation structure 216 is located between the top first epitaxial layer and the bottom second epitaxial layer.

[0191] In this embodiment, after the second device structure is formed, a conductive structure may be further formed to lead out corresponding film layers in the first device structure and the second device structure.

[0192] More specifically, see Fig.13 The method for forming a semiconductor structure further includes: forming a first conductive structure CT11 , wherein the first conductive structure CT11 is electrically connected to the first gate structure 210 .

[0193] In this embodiment, the steps of forming the first conductive structure CT11 may include: forming an interlayer dielectric layer 236 on the second device structure, i.e., the third second epitaxial layer 234; removing a portion of the interlayer dielectric layer 236, and all of the second epitaxial layer below the portion of the interlayer dielectric layer 236, and a portion of the first epitaxial layer to form a first opening (not shown) exposing the first gate structure 210; forming a first spacer layer IS1 on the sidewalls of the first opening; and forming a first conductive plug P1 at least in the remaining space of the first opening.

[0194] The step of forming the first spacer layer IS1 on the sidewall of the first opening includes: forming a first spacer material layer in the first opening; removing the first spacer material layer at the bottom of the first opening, and using the remaining first spacer material layer as the first spacer layer IS1. For example, an etch-back process is used to remove the insulating material layer at the bottom of the first opening.

[0195] The material of the first spacer layer IS1 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride.

[0196] The material of the first conductive plug P1 includes materials with good conductive properties such as cobalt, copper, aluminum or tungsten.

[0197] A second conductive structure CT12 is formed, and the second conductive structure CT12 is electrically connected to the second gate structure 230 .

[0198] The second conductive structure CT12 includes: a second isolation layer IS2 and a second conductive plug P2 covering the sidewall of the second isolation layer IS2.

[0199] The method of forming the second conductive structure CT12 can refer to the description of the first conductive structure CT1 , except that, in the process of forming the second conductive structure CT12 , the second opening exposes the surface of the second gate structure 230 .

[0200] A third conductive structure CT13 is formed, and the third conductive structure CT13 is electrically connected to the third gate structure 232 .

[0201] The third conductive structure CT13 includes: a third isolation layer IS3 and a third conductive plug P3 covering the sidewall of the third isolation layer IS3.

[0202] The manner of forming the third conductive structure CT13 may refer to the description of the first conductive structure CT1 , except that, in the process of forming the third conductive structure CT13 , the third opening exposes the surface of the third gate structure 232 .

[0203] In this embodiment, for each first epitaxial layer in part or all of the first epitaxial layers, at least one fourth conductive structure is formed, and each fourth conductive structure is electrically connected to the corresponding first epitaxial layer.

[0204] In this embodiment, along the normal direction of the substrate surface, multiple layers of first epitaxial layers and first epitaxial layers and second epitaxial layers are stacked and arranged, and when the fourth conductive structure is formed, the fourth conductive structure is electrically connected to the two epitaxial layers.

[0205] In this case, during the process of forming the first conductive structure, electrical insulation is required at least between the epitaxial layers that are not electrically connected, so as to avoid a short circuit problem caused by the electrical connection between the first conductive structure and at least two epitaxial layers.

[0206] More specifically, the step of forming at least one fourth conductive structure may include: A seventh trench (not shown) is formed, wherein the seventh trench at least exposes a portion of the side wall of the first epitaxial layer electrically connected to the fourth conductive structure; a first insulating layer is formed on the side wall of the seventh trench; and a fourth conductive plug is formed at least in the remaining space of the seventh trench, wherein the fourth conductive plug is electrically connected to the first epitaxial layer, and the fourth conductive plug and the first insulating layer serve as the fourth conductive structure.

[0207] As a specific example, combining Figures 1 to 13 , see Fig.14 When the number of the first epitaxial layer is three, the number of the fourth conductive structures may be three.

[0208] More specifically, the fourth conductive structure CT14 may include a first insulating layer IS4, and a fourth conductive plug P4 covering the side walls of the first isolation structure IS4 and electrically connected to the third first epitaxial layer 212; the fourth conductive structure CT15 may include a first insulating layer IS5, and a fourth conductive plug P5 covering the side walls of the first isolation structure IS5 and electrically connected to the first first epitaxial layer 202; the fourth conductive structure CT16 may include a first insulating layer IS6, and a fourth conductive plug P6 covering the side walls of the first isolation structure IS6 and electrically connected to the second first epitaxial layer 206.

[0209] It should be noted that, in the case of forming the first insulating structure, the first conductive structure and the fourth conductive structure also penetrate the first isolation structure.

[0210] In this embodiment, for each second epitaxial layer in part or all of the second epitaxial layers, at least one fifth conductive structure is formed, and each fifth conductive structure is electrically connected to the corresponding second epitaxial layer.

[0211] In this embodiment, along the normal direction of the substrate surface, between the multiple second epitaxial layers, when the fifth conductive structure is formed, there is a situation where the fifth conductive structure is electrically connected to the two epitaxial layers.

[0212] In this case, during the formation process, at least the epitaxial layers that are not electrically connected need to be electrically insulated to avoid short circuit problems caused by the fifth conductive structure being electrically connected to at least two epitaxial layers.

[0213] More specifically, the step of forming at least one fifth conductive structure may include: An eighth trench is formed, wherein the eighth trench at least exposes a portion of the side wall of the second epitaxial layer electrically connected to the second conductive structure; a second insulating layer is formed on the side wall of the eighth trench; and a fifth conductive plug is formed at least in the remaining space of the eighth trench, wherein the fifth conductive plug is electrically connected to the second epitaxial layer, and the fifth conductive plug and the second insulating layer serve as the fifth conductive structure.

[0214] As a specific example, combining Figures 1 to 14 When the number of the second epitaxial layer is three, the number of the fifth conductive structures may be three.

[0215] More specifically, the fifth conductive structure CT17 may be electrically connected to the first second epitaxial layer 218 ; the fifth conductive structure CT18 may be electrically connected to the second second epitaxial layer 224 ; and the fifth conductive structure CT19 may be electrically connected to the third second epitaxial layer 234 .

[0216] For more description about the fifth conductive structure, please refer to the aforementioned examples.

[0217] also, Figure 1 A fifth conductive structure CT20 electrically connected to the third second epitaxial layer 234 of the third transistor T2 is also illustrated.

[0218] In this embodiment, when the second epitaxial layer is the topmost epitaxial layer, a fifth conductive plug may be directly formed to serve as a fifth conductive structure. For example, the fifth conductive structure CT20 contacts the sidewall of the third second epitaxial layer 234 .

[0219] In this embodiment, when the second epitaxial layer is the topmost epitaxial layer, two fifth conductive structures may be formed on the top second epitaxial layer.

[0220] It should be noted that, firstly, the formation process of the first conductive structure to the fifth conductive structure in the above examples is only an example and cannot be understood as a limitation of the present invention; secondly, Figure 1 In the illustrated structure, some fifth conductive structures overlap with the fourth conductive structures along one direction.

[0221] In a specific application, for example, one of the conductive structures may be formed first, and then the other conductive structures may be formed; for another example, the steps of forming an opening / groove and an insulating layer may be performed first, and then a conductive plug may be formed simultaneously or in steps; for another example, the step of forming a groove may be performed first, and then the step of forming an insulating layer may be performed, and finally a conductive plug may be formed simultaneously or in steps.

[0222] In one embodiment, the steps of forming the opening / trench and the insulating layer are performed in stages, and then the conductive plug is formed simultaneously.

[0223] It should be noted that in the scheme of forming the openings / grooves in steps, when forming the first opening / groove, only the area for forming the first groove is exposed, while other areas are covered.

[0224] It should also be noted that the formation process of the second stacked device 300 can refer to the description of the first stacked device 200. Figure 1In the structure shown, the second stacked device 300 also forms the first to fifth conductive structures accordingly, wherein the first conductive structure is CT21, the second conductive structure is CT22, the third conductive structure is CT23, the fourth conductive structure is CT24, CT25 and CT26, and the fifth conductive structure is CT27, CT28 and CT29.

[0225] also, Figure 1 A fifth conductive structure CT30 electrically connected to the third second epitaxial layer 234 of the third transistor T1 is also illustrated.

[0226] It should be noted that in this solution, the reason for leading out the epitaxial layer as the channel layer through the conductive structure is that, on the one hand, when the epitaxial layer is used as the channel layer, it does not contact the substrate, so the substrate cannot serve as a discharge channel for the channel layer; on the other hand, the distance between the conductive structures used to lead out the three epitaxial layers is relatively close, and there is a problem of charge accumulation in the channel layer. In summary, by providing a conductive structure electrically connected to the channel layer, the charge in the channel layer can be extracted and the leakage current can be reduced.

[0227] In addition, the conductive structure connected to the channel layer can be used as a ground terminal to provide a reference value for the entire semiconductor structure.

[0228] Then combine Figure 1 , see Fig.15 and Fig.16 After forming the first conductive structure to the fifth conductive structure, the forming method further includes: A first metal lead ML1 is formed, and the first metal lead ML1 is electrically connected to the first conductive structure and the second conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device respectively.

[0229] As a specific embodiment, the first metal lead ML1 may be electrically connected to the first conductive structure CT11 and the second conductive structure CT12 of the first stacked device 200 , and the fourth conductive structure CT24 and the fifth conductive structure CT27 of the second stacked device 300 .

[0230] A second metal lead ML2 is formed, and the second metal lead ML2 is electrically connected to the first conductive structure and the second conductive structure of another stacked device, and to the fourth conductive structure and the fifth conductive structure of the current stacked device.

[0231] As a specific embodiment, the second metal lead ML2 may be electrically connected to the first conductive structure CT21 and the second conductive structure CT22 of another stacked device 300 , and the fourth conductive structure CT14 and the fifth conductive structure CT17 of the current stacked device 200 .

[0232] In this embodiment, when the semiconductor structure is an SRAM, the first metal lead ML1 and the second metal lead ML2 realize electrical connection between the first transistor Q4 and the second transistor Q2 , and between the first transistor Q3 and the second transistor Q1 .

[0233] A third metal lead ML3 is formed, and the third metal lead is electrically connected to the fourth conductive structure and the fifth conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device, respectively.

[0234] As a specific embodiment, the third metal lead ML3 may be electrically connected to the fourth conductive structure CT15 and the fifth conductive structure CT18 of the first stacked device 200 , and the fourth conductive structure CT25 and the fifth conductive structure CT28 of the second stacked device 300 .

[0235] In this embodiment, when the semiconductor structure is a SRAM, a third metal lead ML3 is formed to connect to VCC.

[0236] A fourth metal lead ML4 is formed, and the fourth metal lead ML4 is electrically connected to the fourth conductive structure and the fifth conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device, respectively.

[0237] As a specific embodiment, the fourth metal lead ML4 may be electrically connected to the fourth conductive structure CT16 and the fifth conductive structure CT19 of the first stacked device 200 , and the fourth conductive structure CT26 and the fifth conductive structure CT29 of the second stacked device 300 .

[0238] In this embodiment, when the semiconductor structure is an SRAM, the fourth metal lead ML4 is used as a ground terminal and connected to VSS.

[0239] A fifth metal lead ML5 is formed, and the fifth metal lead ML5 is electrically connected to the current stacked device and the third conductive structure of another stacked device, respectively.

[0240] As a specific embodiment, the fifth metal lead ML5 may be electrically connected to the third conductive structure CT13 of the first stacked device 200 and the third conductive structure CT23 of the second stacked device 300 .

[0241] In this embodiment, when the semiconductor structure is an SRAM, the fifth metal lead ML5 serves as a word line WL.

[0242] A sixth metal lead ML6 is formed, and the sixth metal lead ML6 is electrically connected to the fifth conductive structure CT20 of the current stacked device.

[0243] In this embodiment, when the semiconductor structure is an SRAM, the sixth metal lead ML6 serves as an inverted bit line ( ).

[0244] A seventh metal lead ML7 is formed, and the seventh metal lead ML7 is electrically connected to the fifth conductive structure CT30 of another stacked device.

[0245] In this embodiment, when the semiconductor structure is a SRAM, the seventh metal lead ML7 serves as a bit line (BL).

[0246] It should be noted that see Fig.16 In actual wiring, the third transistor T1 is also electrically connected to the second transistor Q1 and the first transistor Q3 at the same time.

[0247] Similarly, the third transistor T2 is also electrically connected to the second transistor Q2 and the first transistor Q4.

[0248] In this embodiment, in the step of forming discrete stacked devices on the substrate, a second isolation structure is also formed, and the second isolation structure is located between adjacent stacked devices to achieve isolation between the stacked devices.

[0249] See also Fig.17 The schematic diagram of the structure corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention is shown. The same parts as the above-mentioned embodiments are not described again. The difference is that: In this embodiment, see Fig.17 After forming the first number of first epitaxial layers (eg, a first first epitaxial layer 202 , a second first epitaxial layer 206 , and a third first epitaxial layer 212 ), the first gate structure 210 is formed.

[0250] In other words, the first number of first epitaxial layers are formed, and a second trench (not shown) is formed that penetrates at least a portion of the first epitaxial layer, and the second trench exposes the side walls of the penetrated first epitaxial layer (in this embodiment, the second trench exposes the side walls of the second first epitaxial layer 206 and the third first epitaxial layer 212); the first gate structure 210 is formed in the second trench, and the first gate structure 210 is in contact with at least the side walls of the first channel layer (i.e., the second first epitaxial layer 206).

[0251] See also Fig.18 The schematic diagram of the structure corresponding to each step in the third embodiment of the method for forming a semiconductor structure of the present invention is shown. The same parts as the above-mentioned embodiments are not described again. The difference is that: In this embodiment, see Fig.18After forming the second number of second epitaxial layers (eg, the first second epitaxial layer 218 , the second second epitaxial layer 224 , and the third second epitaxial layer 234 ), the second gate structure 230 is formed.

[0252] In other words, the second number of second epitaxial layers is formed; a fifth trench (not marked in the figure) and a sixth trench (not marked in the figure) are formed to penetrate at least a portion of the second epitaxial layer, and are separate, the fifth trench and the sixth trench exposing the side walls of the penetrated second epitaxial layer (in the present embodiment, the fifth trench and the sixth trench both expose the side walls of the second second epitaxial layer 224 and the third second epitaxial layer 234); the second gate structure 230 is formed in the fifth trench, the second gate structure 230 is in contact with the side wall of at least one side of the second channel layer; the third gate structure 232 is formed in the sixth trench, the third gate structure 232 is in contact with at least the other side wall of the second channel layer.

[0253] The present invention also provides a semiconductor structure. Figure 1 and Fig.13 , the semiconductor structure includes: a substrate 100; a discrete stacked device (as a non-limiting example, Figure 1 The diagram shows a discrete first stacked device 200 and a second stacked device 300 located on the substrate 100, each stacked device comprising a first device structure (not shown) and a second device structure (not shown) sequentially arranged along the normal direction of the substrate surface.

[0254] The substrate 100 may provide a process operation basis for a formation process of a semiconductor structure.

[0255] The semiconductor structure may include a memory cell, such as a static random access memory SRAM. In some other embodiments, the semiconductor structure may also include other types of memory cells.

[0256] In a specific embodiment, the first stacked device 200 may include a first transistor Q4 , a second transistor Q2 located on the first transistor Q4 , and a third transistor T2 sharing a second channel layer with the second transistor Q2 .

[0257] Accordingly, the second stacked device 300 may include a first transistor Q3 , a second transistor Q1 located on the first transistor Q3 , and a third transistor T1 sharing a second channel layer with the second transistor Q1 .

[0258] It should be noted that, first, when the semiconductor structure is an SRAM, the first stacked device 200 and the second stacked device 300 constitute an SRAM bit cell.

[0259] Specifically, the first transistor Q4 in the first stacked device 200 can be used as a first pull-up transistor, the second transistor Q2 can be used as a first pull-down transistor, the third transistor T2 can be used as a first control transistor, and the first transistor Q4 and the second transistor Q2 constitute a first inverter.

[0260] The first transistor Q3 in the second stacked device 300 can be used as a second pull-up transistor, the second transistor Q1 can be used as a second pull-down transistor, the third transistor T1 can be used as a second control transistor, and the first transistor Q3 and the second transistor Q1 constitute a second inverter.

[0261] In this embodiment, the first transistor includes: a plurality of first epitaxial layers arranged in sequence along the surface of the substrate 100 (as a non-limiting example, the plurality of first epitaxial layers include a first first epitaxial layer 202, a second first epitaxial layer 206, and a third first epitaxial layer 212), at least one epitaxial layer serving as a first channel layer of the first transistor, wherein each first epitaxial layer has its own doping type and doping concentration; a first gate structure 210, contacting at least the sidewall of the first channel layer.

[0262] Each first epitaxial layer has its own doping concentration and doping type. For more description of the first epitaxial layer, please refer to the above examples.

[0263] In this embodiment, the plurality of first epitaxial layers satisfy at least one or more of the following: The first first epitaxial layer 202 is used as a first source-drain doped layer.

[0264] For more description of the first epitaxial layer 202 , please refer to the aforementioned examples.

[0265] The second first epitaxial layer 206 is used as the first channel layer.

[0266] For more description of the second first epitaxial layer 206 , please refer to the aforementioned examples.

[0267] The third first epitaxial layer 212 is used as a second source-drain doped layer.

[0268] For more description of the third first epitaxial layer 212 , please refer to the aforementioned examples.

[0269] In this embodiment, the first source-drain doped layer is one of the source and the drain, and the second source-drain doped layer is the other of the source and the drain.

[0270] More specifically, the first first epitaxial layer 202 serves as a source, and the third first epitaxial layer 212 serves as a drain.

[0271] When the semiconductor device is working, the first gate structure 210 is used to control the opening and closing of the first channel layer.

[0272] In this embodiment, the first gate structure 210 is a polysilicon gate structure or an amorphous silicon gate structure.

[0273] In this embodiment, the first gate structure 210 is in contact with the sidewall of the first channel layer (ie, the second first epitaxial layer 206 ), and the semiconductor structure further includes: The first insulating structure 204 penetrates through the first epitaxial layer below the first channel layer and contacts the sidewall of the first channel layer and the bottom of the first gate structure 210 .

[0274] For more description about the first insulating structure 204 , please refer to the aforementioned examples.

[0275] The second insulating structure 214 penetrates the first epitaxial layer above the first channel layer and contacts the sidewall of the first epitaxial layer and the surface of the first gate structure.

[0276] For more description about the second insulating structure 214 , please refer to the aforementioned examples.

[0277] It should be noted that when the first gate structure 210 is still in contact with the sidewalls of other first epitaxial layers, the second insulating structure 214 (eg Fig.17 ).

[0278] In this embodiment, the semiconductor structure may further include: a first gate oxide layer 208 , wherein the first gate oxide layer 208 covers the sidewall of the first gate structure 210 and is located between the first gate structure 210 and the first first epitaxial layer 202 .

[0279] The second transistor Q2 may include: a plurality of second epitaxial layers arranged in sequence along the surface of the substrate 100 (as a non-limiting example, the plurality of second epitaxial layers include a first second epitaxial layer 218, a second second epitaxial layer 224, and a third second epitaxial layer 234), at least one second epitaxial layer serving as a second channel layer of the second transistor Q2, wherein each second epitaxial layer has its own doping type and doping concentration; a second gate structure 230, at least in contact with the sidewall of the first channel layer; wherein the bottom second epitaxial layer is located on the top first epitaxial layer.

[0280] When the semiconductor device is working, the second gate structure 230 is used to control the opening and closing of the second channel layer.

[0281] In this embodiment, the second gate structure 230 is a polysilicon gate structure or an amorphous silicon gate structure.

[0282] In this embodiment, the third transistor T2 includes: a plurality of second epitaxial layers shared with the second transistor Q2, the second channel layer of the second transistor Q2 also serving as the second channel layer of the third transistor T2; and a third gate structure 232 contacting at least the sidewall of the second channel layer.

[0283] In other words, the third transistor T2 has a plurality of second epitaxial layers sequentially arranged along the surface of the substrate 100 (as a non-limiting example, the plurality of second epitaxial layers include a first second epitaxial layer 218, a second second epitaxial layer 224, and a third second epitaxial layer 234), and at least one second epitaxial layer serves as a second channel layer of the third transistor T2, wherein each second epitaxial layer has its own doping type and doping concentration.

[0284] When the semiconductor device is working, the third gate structure 232 is used to control the opening and closing of the second channel layer.

[0285] In this embodiment, the third gate structure 232 is a polysilicon gate structure or an amorphous silicon gate structure.

[0286] In this embodiment, the second gate structure 230 is in contact with the sidewall of one side of the second channel layer, and the third gate structure 232 is in contact with the sidewall of the other side of the second channel layer. The semiconductor structure further includes: The third insulating structure 220 penetrates the second epitaxial layer below the second channel layer and contacts the sidewall of the second epitaxial layer and the bottom of the second gate structure.

[0287] For example, the third insulating structure 220 contacts the sidewall of the second second epitaxial layer, and the third insulating structure 220 is located in the first second epitaxial layer 218 .

[0288] The fourth insulating structure 222 penetrates the second epitaxial layer below the second channel layer and contacts the sidewall of the second epitaxial layer and the surface of the third gate structure.

[0289] Similarly, the fourth insulating structure 222 is located in the first second epitaxial layer 218 .

[0290] For more descriptions about the third insulating structure 220 and the fourth insulating structure 222 , please refer to the aforementioned examples.

[0291] It should be noted that when the first gate structure 210 is still in contact with the sidewalls of other second epitaxial layers, the fourth insulating structure 222 (eg Fig.18 ).

[0292] In this embodiment, the semiconductor structure may further include: a second gate oxide layer 226 , wherein the second gate oxide layer 226 covers the sidewall of the second gate structure 230 and is located between the second gate structure 230 and the first second epitaxial layer 218 .

[0293] The third gate oxide layer 228 covers the sidewall of the third gate structure 232 and is located between the third gate structure 232 and the first second epitaxial layer 218 .

[0294] In this embodiment, in order to facilitate the introduction of the corresponding film layers in the first device structure and the second device structure, Figure 1 , Fig.13 and Fig.14 , the semiconductor structure may further include: The first conductive structure CT11 is electrically connected to the first gate structure 210 .

[0295] In this embodiment, the first conductive structure CT11 may include: a first spacer layer IS1 that contacts the side walls of the entire second epitaxial layer and a portion of the side walls of the first epitaxial layer (for example, the third first epitaxial layer 212); and a first conductive plug P1 that covers the side walls of the first spacer layer IS1 and is electrically connected to the first gate structure 210.

[0296] The second conductive structure CT12 is electrically connected to the second gate structure 230 .

[0297] In this embodiment, the second conductive structure CT12 may include: a second spacer IS2 contacting the sidewall of a portion of the second epitaxial layer (eg, the third second epitaxial layer 234 ); and a second conductive plug P2 covering the sidewall of the second spacer IS2 and electrically connected to the second gate structure 230 .

[0298] The third conductive structure CT13 is electrically connected to the third gate structure 232 .

[0299] In this embodiment, the third conductive structure CT13 may include: a third spacer IS3 contacting the sidewall of a portion of the second epitaxial layer (for example, the third second epitaxial layer 234 ); and a third conductive plug P3 covering the sidewall of the third spacer IS3 and electrically connected to the third gate structure 232 .

[0300] At least one fourth conductive structure is electrically connected to the corresponding first epitaxial layer.

[0301] In this embodiment, there are three fourth conductive structures CT14, CT15 and CT16, wherein the fourth conductive structure CT14 is electrically connected to the third first epitaxial layer 212; the fourth conductive structure CT15 is electrically connected to the first first epitaxial layer 202; and the fourth conductive structure CT16 is electrically connected to the second first epitaxial layer 206.

[0302] The fourth conductive structure includes: a first insulating layer, and a conductive plug covering the sidewall of the first insulating layer and electrically connected to the corresponding first epitaxial layer.

[0303] The relative position relationship between the first insulating layer and other film layers can be found in the above examples.

[0304] At least one fifth conductive structure is electrically connected to the corresponding second epitaxial layer.

[0305] In this embodiment, there are three fifth conductive structures CT17, CT18 and CT19, wherein the fifth conductive structure CT17 can be electrically connected to the first second epitaxial layer 218; the fifth conductive structure CT18 can be electrically connected to the second second epitaxial layer 224; and the fifth conductive structure CT19 can be electrically connected to the third second epitaxial layer 234.

[0306] also, Figure 1 and Fig.13 A fifth conductive structure CT20 is also illustrated, which is electrically connected to the third second channel layer 234 of the third transistor T2.

[0307] The fifth conductive structure includes: a second insulating layer, and a conductive plug covering the sidewall of the second insulating layer and electrically connected to the corresponding second epitaxial layer.

[0308] The relative position relationship between the second insulating layer and other film layers can be found in the above examples.

[0309] In this embodiment, combined with Figure 1 , see Fig.13 and Fig.15 , the semiconductor structure may further include: A first metal lead ML1 is electrically connected to a first conductive structure and a second conductive structure of a current stacked device, and a fourth conductive structure and a fifth conductive structure of another stacked device, respectively.

[0310] The second metal lead ML2 is electrically connected to the first conductive structure and the second conductive structure of another stacked device, and to the fourth conductive structure and the fifth conductive structure of the current stacked device.

[0311] The third metal lead ML3 is electrically connected to the fourth conductive structure and the fifth conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device respectively.

[0312] The fourth metal lead ML4 is electrically connected to the fourth conductive structure and the fifth conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device respectively.

[0313] A fifth metal lead ML5 is electrically connected to the current stacked device and the third conductive structure of another stacked device respectively.

[0314] As a specific embodiment, the fifth metal lead ML5 may be electrically connected to the third conductive structure CT13 of the first stacked device 200 and the third conductive structure CT23 of the second stacked device 300 .

[0315] In this embodiment, when the semiconductor structure is an SRAM, the fifth metal lead ML5 serves as a word line WL.

[0316] The sixth metal lead ML6 is electrically connected to the fifth conductive structure CT20 of the current stacked device.

[0317] In this embodiment, when the semiconductor structure is an SRAM, the sixth metal lead ML6 serves as an inverted bit line ( ).

[0318] The seventh metal lead ML7 is electrically connected to the fifth conductive structure CT30 of another stacked device.

[0319] For detailed description of the first to seventh metal leads ML1 to ML7 , reference may be made to the aforementioned examples.

[0320] In this embodiment, the semiconductor structure may further include: a first isolation structure 216, wherein the first isolation structure 216 is located between the first device structure and the second device structure to achieve insulation between the first device structure and the second device structure.

[0321] Specifically, the first isolation structure 216 is located between the third first epitaxial layer 212 and the first second epitaxial layer 218 .

[0322] In this embodiment, in the step of forming discrete stacked devices on the substrate, a second isolation structure is also formed, and the second isolation structure is located between adjacent stacked devices to achieve isolation between the stacked devices.

[0323] In this embodiment, the semiconductor structure may further include: an interlayer dielectric layer 236 located on the topmost epitaxial layer and covering the side walls of the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure and the fifth conductive structure.

[0324] In this embodiment, the material of the interlayer dielectric layer 236 is an insulating material, for example, the material of the interlayer dielectric layer 236 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0325] It should be noted that the semiconductor structure described in this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0326] Although the present specification is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Discrete stacked devices are formed on the substrate, each stacked device comprising a first device structure and a second device structure sequentially arranged along the normal direction of the substrate surface, wherein the first device structure comprises a first transistor, the second device structure comprises a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, and the second channel layer is formed by epitaxy.

2. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming each stacked device include: forming a first number of first epitaxial layers on the substrate, at least one of the epitaxial layers being used as a first channel layer of the first transistor, wherein each of the first epitaxial layers has its own doping type and doping concentration; forming a first gate structure, wherein the first gate structure at least contacts a sidewall of the first channel layer; forming a second number of second epitaxial layers on the first gate structure, at least one second epitaxial layer serving as the second channel layer, wherein each second epitaxial layer has its own doping type and doping concentration; A second gate structure and a third gate structure are formed, wherein the second gate structure and the third gate structure are in contact with at least a sidewall of the second channel layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: Each first epitaxial layer and / or each second epitaxial layer is formed by an epitaxial process, and a doping process is performed during the epitaxial growth process.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: The formation temperature of each first epitaxial layer and / or each second epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius.

5. The method for forming a semiconductor structure according to claim 4, wherein: The formation parameters of each first epitaxial layer and / or the formation parameters of each second epitaxial layer also include: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and at least one of an epitaxial rate of 200 angstroms / minute to 300 angstroms / minute.

6. The method for forming a semiconductor structure according to claim 2, wherein: The first number is greater than or equal to 3, and the first number of first epitaxial layers satisfies at least one or more of the following: a first layer of first epitaxial layer, the first layer of first epitaxial layer is used to form a first source-drain doped layer; a second layer of first epitaxial layer, the second layer of first epitaxial layer is used to form the first channel layer; a third layer of first epitaxial layer, the third layer of first epitaxial layer is used to form a second source-drain doped layer; the first source-drain doped layer is one of the source or the drain, and the second source-drain doped layer is the other of the source or the drain; The second number is greater than or equal to 3, and the second number of second epitaxial layers satisfies at least one or more of the following: a first layer of second epitaxial layer, the first layer of second epitaxial layer is used to form a third source-drain doped layer; a second layer of second epitaxial layer, the second layer of second epitaxial layer is used to form the second channel layer; a third layer of second epitaxial layer, the third layer of second epitaxial layer is used to form a fourth source-drain doped layer; the third source-drain doped layer is one of the source or the drain, and the fourth source-drain doped layer is the other of the source or the drain.

7. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming the first gate structure satisfies at least one or more of the following: In the process of forming the first number of first epitaxial layers, forming the first gate structure, the top first epitaxial layer being located above the first gate structure; After forming the first number of first epitaxial layers, the first gate structure is formed.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: In the process of forming the first number of first epitaxial layers, when forming the first gate structure, the forming method includes: forming a third number of first epitaxial layers, the third number of first epitaxial layers including a first epitaxial layer for forming a first channel layer, and the third number is less than the first number; Forming a first trench penetrating at least a portion or all of the first epitaxial layer, wherein the first trench exposes a sidewall of the penetrated first epitaxial layer; forming the first gate structure in the first trench, wherein the first gate structure at least contacts a sidewall of the first channel layer; A remaining number of first epitaxial layers are formed on the first gate structure.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The first gate structure is in contact with a sidewall of the first channel layer; Before forming the first channel layer, the forming method further includes: forming a first insulating structure in the first portion of the first epitaxial layer; wherein the first trench is located above the first insulating structure and exposes the surface of the first insulating structure, and the first portion of the first epitaxial layer is located below the first channel layer to be formed subsequently; After forming the first gate structure, the forming method further includes: forming a second insulating structure in the first epitaxial layer of the second portion, the second insulating structure is in contact with the surface of the first gate structure, and the first epitaxial layer of the second portion is located above the formed first channel layer.

10. The method for forming a semiconductor structure according to claim 7, wherein: After forming the multiple first epitaxial layers, when forming the first gate structure, the forming method includes: forming the first number of first epitaxial layers; forming a second trench penetrating at least a portion of the first epitaxial layer, wherein the second trench exposes a sidewall of the penetrated first epitaxial layer; The first gate structure is formed in the second trench, and the first gate structure at least contacts with a sidewall of the first channel layer.

11. The method for forming a semiconductor structure according to claim 2, wherein: The steps of forming the second gate structure and the third gate structure satisfy at least one or more of the following: In the process of forming the second number of second epitaxial layers, forming the second gate structure and the third gate structure, the top second epitaxial layer being located above the second gate structure and the third gate structure; After forming the second number of second epitaxial layers, the second gate structure and the third gate structure are formed.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: In the process of forming the second number of second epitaxial layers, when forming the second gate structure and the third gate structure, the forming method includes: forming a fourth number of second epitaxial layers, the fourth number of second epitaxial layers including a second epitaxial layer for forming a second channel layer, and the fourth number is less than the second number; Forming a third trench and a fourth trench that penetrate at least a portion of the second epitaxial layer and are separate, wherein the third trench and the fourth trench both expose side walls of the penetrated second epitaxial layer; forming the second gate structure in the third trench, wherein the second gate structure is in contact with at least one sidewall of the second channel layer; forming the third gate structure in the fourth trench, wherein the third gate structure at least contacts the sidewall of the other side of the second channel layer; A remaining number of second epitaxial layers are formed on the second gate structure and the third gate structure.

13. The method for forming a semiconductor structure according to claim 12, wherein: The second gate structure and the third gate structure are in contact with a sidewall of the second channel layer; Before forming the second epitaxial layer as the second channel layer, the forming method further includes: forming a third insulating structure in the third portion of the second epitaxial layer; wherein the third trench is located above the third insulating structure and exposes the surface of the third insulating structure, and the third portion of the second epitaxial layer is located below the second channel layer formed subsequently; Before forming the second epitaxial layer as the second channel layer, the forming method further includes: forming a fourth insulating structure in the second epitaxial layer of the third portion; the fourth trench is located above the fourth insulating structure and exposes a surface of the fourth insulating structure.

14. The method for forming a semiconductor structure according to claim 11, wherein: After forming the second number of second epitaxial layers, when forming the second gate structure and the third gate structure, the forming method includes: forming said second number of second epitaxial layers; forming a fifth trench and a sixth trench which penetrate at least a portion of the second epitaxial layer and are separate, wherein the fifth trench and the sixth trench expose the sidewall of the penetrated second epitaxial layer; forming the second gate structure in the fifth trench, wherein the second gate structure is in contact with at least one sidewall of the second channel layer; The third gate structure is formed in the sixth trench, and the third gate structure at least contacts the other sidewall of the second channel layer.

15. The method for forming a semiconductor structure according to claim 2, wherein: In the step of forming a discrete stacked device on the substrate, a first isolation structure is also formed, and the first isolation structure is located between the first device structure and the second device structure.

16. The method for forming a semiconductor structure according to claim 2, wherein: Also meets at least one or more of the following: forming a first conductive structure, wherein the first conductive structure is electrically connected to the first gate structure; forming a second conductive structure, wherein the second conductive structure is electrically connected to the second gate structure; A third conductive structure is formed, wherein the third conductive structure is electrically connected to the third gate structure. For each first epitaxial layer in part or all of the first epitaxial layers, at least one fourth conductive structure is formed, and each fourth conductive structure is electrically connected to the corresponding first epitaxial layer; For each second epitaxial layer in part or all of the second epitaxial layers, at least one fifth conductive structure is formed, and each fifth conductive structure is electrically connected to the corresponding second epitaxial layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: The step of forming at least one fourth conductive structure comprises: forming a seventh trench, wherein the seventh trench at least exposes a portion of the sidewall of the first epitaxial layer electrically connected to the fourth conductive structure; forming a first insulating layer on the sidewall of the seventh trench; forming a fourth conductive plug at least in the remaining space of the seventh trench, wherein the fourth conductive plug is electrically connected to the first epitaxial layer, and the fourth conductive plug and the first insulating layer serve as the fourth conductive structure; The step of forming at least one fifth conductive structure includes: forming an eighth trench, wherein the eighth trench at least exposes a portion of the side wall of the second epitaxial layer electrically connected to the second conductive structure; forming a second insulating layer on the side wall of the eighth trench; and forming a fifth conductive plug at least in the remaining space of the eighth trench, wherein the fifth conductive plug is electrically connected to the second epitaxial layer, and the fifth conductive plug and the second insulating layer serve as the fifth conductive structure.

18. The method for forming a semiconductor structure according to claim 16, wherein: Satisfy at least one or more of the following: Forming a first metal lead, wherein the first metal lead is electrically connected to the first conductive structure and the second conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device respectively; forming a second metal lead, wherein the second metal lead is electrically connected to the first conductive structure and the second conductive structure of another stacked device, and to the fourth conductive structure and the fifth conductive structure of the current stacked device; Forming a third metal lead, wherein the third metal lead is electrically connected to the fourth conductive structure and the fifth conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device respectively; Forming a fourth metal lead, wherein the fourth metal lead is electrically connected to the fourth conductive structure and the fifth conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device respectively; forming a fifth metal lead, wherein the fifth metal lead is electrically connected to the current stacked device and the third conductive structure of another stacked device respectively; forming a sixth metal lead, wherein the sixth metal lead is electrically connected to the fifth conductive structure of the current stacked device; A seventh metal lead is formed, wherein the seventh metal lead is electrically connected to a fifth conductive structure of another stacked device.

19. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming discrete stacked devices on the substrate, a second isolation structure is also formed, and the second isolation structure is located between adjacent stacked devices.

20. A semiconductor structure, characterized in that: include: substrate; Discrete stacked devices are located on the substrate, each stacked device comprising a first device structure and a second device structure sequentially arranged along a normal direction of the substrate surface; The first device structure includes a first transistor, the second device structure includes a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, and the second channel layer is formed by epitaxy.

21. The semiconductor structure according to claim 20, characterized in that The first transistor comprises: a first number of first epitaxial layers sequentially arranged along the surface of the substrate, at least one epitaxial layer serving as a first channel layer of the first transistor, wherein each first epitaxial layer has its own doping type and doping concentration; a first gate structure at least in contact with a sidewall of the first channel layer; The second transistor comprises: a plurality of second epitaxial layers sequentially arranged along the surface of the substrate, at least one first epitaxial layer serving as a second channel layer of the second transistor, wherein each second epitaxial layer has its own doping type and doping concentration; a second gate structure at least in contact with a sidewall of the first channel layer; wherein the bottom second epitaxial layer is located on the top first epitaxial layer; The third transistor includes: a plurality of second epitaxial layers shared with the second transistor, the second channel layer of the second transistor also serving as the second channel layer of the third transistor; and a third gate structure at least in contact with a side wall of the second channel layer.

22. The semiconductor structure according to claim 21, characterized in that The first gate structure is in contact with a sidewall of the first channel layer, and the semiconductor structure further includes: A first insulating structure passes through the first epitaxial layer below the first channel layer and contacts the sidewall of the first channel layer and the bottom of the first gate structure; a second insulating structure, penetrating the first epitaxial layer above the first channel layer, and contacting the sidewall of the first epitaxial layer and the surface of the first gate structure; The second gate structure is in contact with a sidewall on one side of the second channel layer, the third gate structure is in contact with a sidewall on the other side of the second channel layer, and the semiconductor structure further includes: a third insulating structure, penetrating through the second epitaxial layer below the second channel layer, and contacting a sidewall of the second epitaxial layer and a bottom of the second gate structure; The fourth insulating structure penetrates the second epitaxial layer below the second channel layer and contacts the sidewall of the second epitaxial layer and the surface of the third gate structure.

23. The semiconductor structure according to claim 21, characterized in that Also includes: a first conductive structure electrically connected to the first gate structure; a second conductive structure electrically connected to the second gate structure; A third conductive structure electrically connected to the third gate structure at least one fourth conductive structure electrically connected to the corresponding first epitaxial layer; At least one fifth conductive structure is electrically connected to the corresponding second epitaxial layer.

24. The semiconductor structure according to claim 23, characterized in that Also includes: A first metal lead, wherein the first metal lead is electrically connected to a first conductive structure and a second conductive structure of a current stacked device, and a fourth conductive structure and a fifth conductive structure of another stacked device; forming a second metal lead, wherein the second metal lead is electrically connected to the first conductive structure and the second conductive structure of another stacked device, and to the fourth conductive structure and the fifth conductive structure of the current stacked device; Forming a third metal lead, wherein the third metal lead is electrically connected to the fourth conductive structure and the fifth conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device respectively; Forming a fourth metal lead, wherein the fourth metal lead is electrically connected to the fourth conductive structure and the fifth conductive structure of the current stacked device, and the fourth conductive structure and the fifth conductive structure of another stacked device respectively; forming a fifth metal lead, wherein the fifth metal lead is electrically connected to the current stacked device and the third conductive structure of another stacked device respectively; forming a sixth metal lead, wherein the sixth metal lead is electrically connected to the fifth conductive structure of the current stacked device; A seventh metal lead is formed, wherein the seventh metal lead is electrically connected to a fifth conductive structure of another stacked device.

25. The semiconductor structure according to claim 21, characterized in that The plurality of first epitaxial layers satisfy at least one or more of the following conditions: a first layer of first epitaxial layers, the first layer of first epitaxial layers being used as a first source-drain doped layer; a second layer of first epitaxial layers, the second layer of first epitaxial layers being used as the first channel layer; a third layer of first epitaxial layers, the third layer of first epitaxial layers being used as a second source-drain doped layer; the first source-drain doped layer being one of a source or a drain, the second source-drain doped layer being the other of a source or a drain; The multiple second epitaxial layers satisfy at least one or more of the following: a first layer of second epitaxial layer, the first layer of second epitaxial layer serves as a third source-drain doped layer; a second layer of second epitaxial layer, the second layer of second epitaxial layer serves as the second channel layer; a third layer of second epitaxial layer, the third layer of second epitaxial layer serves as a fourth source-drain doped layer; the third source-drain doped layer is one of the source or the drain, and the fourth source-drain doped layer is the other of the source or the drain.

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