Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof, and the forming method comprises the following steps: providing a substrate; forming discrete stacked devices on the substrate, each stacked device comprising a first device structure and a second device structure arranged in sequence along a normal direction of a surface of the substrate, wherein the first device structure comprises a first transistor, the second device structure comprises a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer formed by an epitaxial method. By using the above technical scheme, the storage density of the semiconductor structure can be improved, and the data read / write speed can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Static Random Access Memory (SRAM) is widely used in various chips due to its low power consumption, high-speed access, and high integration.

[0003] To improve chip performance, higher requirements are placed on static random access memory (SRAM), such as the need for higher storage density. However, due to process node limitations, the storage density of SRAM cannot be further increased, and the high precision requirements of the manufacturing process equipment reduce the performance of SRAM. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor structure and a method for forming the same, which can improve the storage density of the semiconductor structure and increase the data read and write speed.

[0005] The present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming discrete stacked devices on the substrate, each stacked device including a first device structure and a second device structure arranged sequentially along the normal direction of the substrate surface, wherein the first device structure includes a first transistor, the second device structure includes a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, the second channel layer being formed by epitaxy.

[0006] Accordingly, the present invention provides a semiconductor structure, comprising: a substrate; discrete stacked devices located on the substrate, each stacked device comprising a first device structure and a second device structure sequentially arranged along the normal direction of the substrate surface;

[0007] The first device structure includes a first transistor, the second device structure includes a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, which is formed by epitaxy.

[0008] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0009] In the semiconductor structure formation method provided by the present invention, by arranging each stacked device along the normal surface direction of the substrate, and by having the second transistor and the third transistor share the second channel layer, the volume of each stacked device is reduced, the integration density of the stacked devices is improved, and thus the storage density can be increased. Furthermore, by forming the second channel layer epitaxially, the size of the second channel layer can be reduced, which is not limited by the photolithography machine. Moreover, the epitaxial growth makes the formed second channel layer have better doping density and uniformity, reducing the influence of short-channel effect, thereby improving the storage density of the semiconductor structure and increasing the data read and write speed. Attached Figure Description

[0010] Figure 1 This is a top view of the semiconductor structure in the first embodiment of the present invention;

[0011] Figures 2 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention;

[0012] Figure 15 for Figure 1 A schematic diagram of the electrical connections of the stacked devices;

[0013] Figure 16 for Figure 15 A schematic diagram of the equivalent circuit of the semiconductor structure shown.

[0014] Figure 17 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention;

[0015] Figure 18 This is a schematic diagram of the structure corresponding to each step in the third embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0016] As is known from the background art, the size of Static Random Access Memory (SRAM) cannot be further reduced due to limitations in process nodes. This is because as process nodes continue to shrink, lithography machines adapted to the process nodes are required to perform patterning processes. Due to limitations in the process equipment (such as lithography machines), the size of the conductive channels cannot meet the process requirements, thus preventing further increases in the storage density of SRAM.

[0017] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming discrete stacked devices on the substrate, each stacked device including a first device structure and a second device structure sequentially disposed along the normal direction of the substrate surface, wherein the first device structure includes a first transistor, the second device structure includes a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, the second channel layer being formed by epitaxy.

[0018] The semiconductor structure formation method provided by this invention reduces the volume of each stacked device and increases the integration density of the stacked devices by arranging each stacked device along the normal surface direction of the substrate, and by having the second transistor and the third transistor share the second channel layer. This improves the storage density. Furthermore, forming the second channel layer epitaxially reduces the size of the second channel layer, eliminating the limitations of the photolithography machine. The epitaxial growth also results in better doping density and uniformity in the formed second channel layer, reducing the impact of the short-channel effect. This further improves the storage density of the semiconductor structure and increases the data read / write speed.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be described by way of example below with reference to the accompanying drawings.

[0020] Figure 1 This is a top view of the semiconductor structure in the first embodiment of the present invention. Figures 2 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention. Figures 2 to 13 for Figure 1 A sectional view along the A-A1 direction. Figure 14 for Figure 1 The cross-sectional view along the B-B1 direction in the image. Figure 15 for Figure 1 A schematic diagram showing the electrical connections of the stacked devices is provided. Figure 16 for Figure 15 The diagram shows the equivalent circuit of the semiconductor structure.

[0021] It should be noted that, firstly, for the purpose of facilitating understanding and explanation of this application, Figure 1 The dimensions in the accompanying drawings do not correspond exactly to those in other drawings, but this does not limit the scope of this application; secondly, in Figure 1 The schematic top view of the structure is shown for clarity, but Q4 and Q3 are not shown in the actual top view. Third, to show the relative positions of the first transistor Q3 and the second transistor Q1, and the relative positions of the first transistor Q4 and the second transistor Q2, Figure 1Only a portion of the second transistors Q1 and Q2 are shown; fourth, it should be noted that, Figures 2 to 18 For illustrative purposes only, the full structure of base 100 is not shown.

[0022] See Figures 1 to 15 Provides a base of 100.

[0023] The substrate 100 can provide the basis for the process operation of semiconductor structure formation.

[0024] The semiconductor structure may include memory cells, such as static random access memory (SRAM). In some other embodiments, the semiconductor structure may also include other types of memory cells.

[0025] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0026] The semiconductor substrate may also be a silicon-on-insulator (SOI) structure, or a germanium-on-insulator (SOI) structure; the semiconductor substrate may also include an alloy semiconductor structure, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; the semiconductor substrate may also be a lightly doped substrate or a substrate with an epitaxial layer grown on it.

[0027] Discrete stacked devices are formed on the substrate 100 (as a non-limiting example, Figure 1 The diagram illustrates a discrete first stacked device 200 and a second stacked device 300. Each stacked device includes a first device structure (not shown) and a second device structure (not shown) arranged sequentially along the normal direction of the surface of the substrate 100.

[0028] In this embodiment, by forming a first device structure and a second device structure with a stacked relationship, the integration of the stacked device is improved, thereby enabling the formation of more first device structures and second device structures to increase storage density.

[0029] In this embodiment, the first device structure may include a first transistor, the second device structure may include a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, which is formed by epitaxy.

[0030] By forming the second channel layer through epitaxy, the size of the second channel layer can be reduced, the limitations of the lithography machine can be reduced, and the second channel layer formed by epitaxial growth has better doping density and uniformity, reducing the impact of short channel effect and improving read and write speed.

[0031] Furthermore, by having the second and third transistors share the same second channel layer, the integration density of the stacked device can be further improved.

[0032] In one specific embodiment, the first stacked device 200 may include a first transistor Q4, a second transistor Q2 located on the first transistor Q4, and a third transistor T2 sharing a second channel layer with the second transistor Q2.

[0033] Correspondingly, the second stacked device 300 may include a first transistor Q3, a second transistor Q1 located on the first transistor Q3, and a third transistor T1 sharing a second channel layer with the second transistor Q1.

[0034] It should be noted that, firstly, when the semiconductor structure is SRAM, the first stacked device 200 and the second stacked device 300 constitute an SRAM bit cell.

[0035] Specifically, in the first stacked device 200, the first transistor Q4 can be used as the first pull-up transistor, the second transistor Q2 can be used as the first pull-down transistor, the third transistor T2 can be used as the first control transistor, and the first transistor Q4 and the second transistor Q2 constitute the first inverter.

[0036] In the second stacked device 300, the first transistor Q3 can be used as the second pull-up transistor, the second transistor Q1 can be used as the second pull-down transistor, the third transistor T1 can be used as the second control transistor, and the first transistor Q3 and the second transistor Q1 constitute the second inverter.

[0037] Second, the "discrete stacked device" mentioned in this invention refers to a device that is vertically stacked along the surface direction of the substrate 100, with each layer having a specific function, and together achieving the overall performance.

[0038] In this embodiment, the steps for forming each stacked device can be the same.

[0039] For ease of understanding and illustration, the formation process of the first stacked device 200 will be used as an example for explanation.

[0040] Specifically, the steps of forming a stacked device (e.g., a first stacked device 200) may include:

[0041] See Figures 1 to 8A first epitaxial layer of a first number (in a non-limiting example, the first number may be greater than or equal to 3) is formed on the substrate 100, at least one epitaxial layer serving as the first channel layer of the first transistor, wherein each first epitaxial layer has its own doping type and doping concentration; a first gate structure 210 is formed, the first gate structure 210 being in contact with at least the sidewall of the first channel layer.

[0042] In this embodiment, the first channel layer of the first transistor is formed by epitaxy; and the first gate structure 210 is in contact with at least the sidewall of the first channel layer to achieve control of the first channel layer.

[0043] More specifically, the first epitaxial layer of each layer is formed using an epitaxial process, and doping is performed during the epitaxial growth process.

[0044] In other words, when forming any first epitaxial layer, doping is performed simultaneously with the epitaxial process. On the one hand, the process parameters of the epitaxial process are controllable, enabling the formation of first epitaxial layers with different thicknesses, thereby reducing the thickness of part or all of the first epitaxial layer and forming a first channel layer with a smaller size. On the other hand, by performing the epitaxial process and doping simultaneously, the first epitaxial layer formed by epitaxial growth has better doping density and uniformity, improving the uniformity of doping concentration at different locations within the same epitaxial layer, which helps to reduce the short-channel effect.

[0045] In this embodiment, the epitaxial process may include atomic layer deposition or molecular beam epitaxy.

[0046] In this embodiment, for any first epitaxial layer, the forming steps may include: sequentially forming multiple sub-first epitaxial layers, and performing doping treatment in the step of forming any sub-first epitaxial layer, wherein the doping type and doping concentration are the same in each sub-first epitaxial layer step, so as to further improve the doping uniformity of the first epitaxial layer.

[0047] In this embodiment, by giving each first epitaxial layer its own doping type, the doping type between adjacent first epitaxial layers can be controlled. In three consecutive first epitaxial layers, the doping type of the middle epitaxial layer is different from the doping type of the upper and lower first epitaxial layers. In this way, an epitaxial structure with conductive channels and source / drain doped regions can be formed through three epitaxial layers with the above doping characteristics, thereby enhancing the control capability of the gate structure.

[0048] In this embodiment, the doping concentration of the first epitaxial layer directly affects parameters such as conductivity and carrier mobility of the semiconductor structure. Therefore, the doping concentration of each first epitaxial layer can be set according to actual needs, so that each first epitaxial layer has its own doping concentration, that is, different first epitaxial layers have the same or different doping concentrations.

[0049] See Figures 6 to 12 A second number of second epitaxial layers are formed on the first gate structure 210, with at least one second epitaxial layer serving as the second channel layer, wherein each second epitaxial layer has its own doping type and doping concentration; a second gate structure 230 and a third gate structure 232 are formed, wherein the second gate structure 230 and the third gate structure 232 are at least in contact with the sidewall of the second channel layer.

[0050] In this embodiment, after the first gate structure 210 is formed, a second channel layer is formed by epitaxy, and a second gate structure 230 and a third gate structure 232 that are in contact with the two sidewalls of the second channel layer are formed.

[0051] More specifically, an epitaxial process is used to form the second epitaxial layer in each layer, and doping is performed during the epitaxial growth process.

[0052] In other words, when forming any second epitaxial layer, doping is performed simultaneously with the epitaxial process. On the one hand, the process parameters of the epitaxial process are controllable, enabling the formation of second epitaxial layers with different thicknesses. This allows for the reduction of some or all of the thickness of the second epitaxial layer, resulting in a smaller second channel layer. On the other hand, simultaneous epitaxial processing and doping results in a second epitaxial layer with better doping density and uniformity, improving the uniformity of doping concentration at different locations within the same epitaxial layer. This helps to reduce the short-channel effect.

[0053] In this embodiment, the epitaxial process may include atomic layer deposition or molecular beam epitaxy.

[0054] In this embodiment, for any second epitaxial layer, the forming step may include: sequentially forming multiple sub-second epitaxial layers, and performing doping treatment in the step of forming any sub-second epitaxial layer, wherein the doping type and doping concentration are the same in each sub-second epitaxial layer step, so as to further improve the doping uniformity of the second epitaxial layer.

[0055] In this embodiment, by giving each second epitaxial layer its own doping type, the doping type between adjacent epitaxial layers can be controlled. In three consecutive second epitaxial layers, the doping type of the middle epitaxial layer is different from the doping type of the upper and lower second epitaxial layers. In this way, an epitaxial structure with conductive channels and source / drain doped regions can be formed by three epitaxial layers with the above doping characteristics, thereby enhancing the control capability of the gate structure.

[0056] In this embodiment, the doping concentration of the second epitaxial layer directly affects parameters such as conductivity and carrier mobility of the semiconductor structure. Therefore, the doping concentration of each second epitaxial layer can be set according to actual needs, so that each second epitaxial layer has its own doping concentration, that is, different second epitaxial layers have the same or different doping concentrations.

[0057] In practical applications, the inventors further discovered that diffusion occurs between adjacent first epitaxial layers and adjacent second epitaxial layers under the influence of temperature, and the diffusion becomes more severe at higher temperatures. This causes dopant ions to transfer between adjacent epitaxial layers, altering the properties of some or all of the epitaxial layers, significantly reducing the performance of the semiconductor structure, or rendering the semiconductor structure unable to perform its intended function.

[0058] As an example, if the doping concentrations of adjacent first epitaxial layers are different, the diffusion phenomenon may cause the doping concentration of the first epitaxial layer with a higher doping concentration to decrease, while the doping concentration of the first epitaxial layer with a lower doping concentration to increase; if the doping concentrations of adjacent second epitaxial layers are different, the diffusion phenomenon may cause the doping concentration of the second epitaxial layer with a higher doping concentration to decrease, while the doping concentration of the second epitaxial layer with a lower doping concentration to increase.

[0059] As another example, if the doping types of adjacent first epitaxial layers are different, the diffusion phenomenon may cause the doping types of these two first epitaxial layers to be the same, resulting in semiconductor structure failure; if the doping types of adjacent second epitaxial layers are different, the diffusion phenomenon may cause the doping types of these two second epitaxial layers to be the same, resulting in semiconductor structure failure.

[0060] In this embodiment, each first epitaxial layer and each second epitaxial layer are formed in a low-temperature environment.

[0061] In some embodiments, the formation temperature of each first epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius. For example, 650 degrees Celsius, 700 degrees Celsius, and 750 degrees Celsius, etc.

[0062] That is, the formation temperature of any first epitaxial layer is no higher than 800 degrees Celsius, so that diffusion phenomena are reduced or avoided when forming the second layer and subsequent first epitaxial layers, allowing each first epitaxial layer to maintain its own characteristics and improving the performance of the semiconductor structure.

[0063] In this embodiment, the formation parameters of each first epitaxial layer may further include at least one of the following: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and an epitaxial rate of 200 Å / min to 300 Å / min.

[0064] In other words, by changing the formation temperature of the first epitaxial layer, at least one of the aforementioned parameters is adaptively adjusted, making the silicon source gas used in the epitaxial process compatible with the current temperature. Furthermore, by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, thereby enhancing the formation quality of the epitaxial layer. That is, while reducing the formation temperature, the epitaxial rate is also reduced.

[0065] In some embodiments, the formation temperature of each second epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius. For example, 650 degrees Celsius, 700 degrees Celsius, and 750 degrees Celsius, etc.

[0066] That is, the formation temperature of any second epitaxial layer is no higher than 800 degrees Celsius, so that diffusion phenomena are reduced or avoided when forming the second layer and subsequent second epitaxial layers, allowing each second epitaxial layer to maintain its own characteristics and improving the performance of the semiconductor structure.

[0067] In this embodiment, the formation parameters of each second epitaxial layer may further include at least one of the following: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and an epitaxial rate of 200 Å / min to 300 Å / min.

[0068] In other words, by changing the formation temperature of the second epitaxial layer, at least one of the aforementioned parameters is adaptively adjusted, making the silicon source gas used in the epitaxial process compatible with the current temperature. Furthermore, by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, thereby enhancing the formation quality of the epitaxial layer. That is, while reducing the formation temperature, the epitaxial rate also decreases accordingly.

[0069] It should be noted that, in order to further reduce the impact of temperature, the epitaxial layer, gate structure, and related film layers in this scheme are all formed using a process with a temperature not exceeding 800 degrees Celsius.

[0070] In this embodiment, the first quantity is greater than or equal to 3, that is, the number of the first epitaxial layer is at least 3. By making the number of the first epitaxial layer greater than or equal to 3, at least the source, drain, and channel layer located between the source and drain can be formed to achieve the function of current flow.

[0071] When the first quantity is greater than or equal to 3, the method for forming the semiconductor structure in this scheme can satisfy:

[0072] The first epitaxial layer is used to form the first source / drain doped layer.

[0073] The first source / drain doped layer can be used as the source or drain of the first transistor Q3. When the first transistor Q3 is working, the first source / drain doped layer can be used to provide a source of charge carriers.

[0074] In this embodiment, when the first transistor is an NMOS transistor, the first epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the first epitaxial layer may be Si or SiC, or other materials compatible with the substrate material; when the first transistor Q3 is a PMOS transistor, the first epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the first epitaxial layer may be Si or SiGe, or other materials compatible with the substrate material.

[0075] In one specific embodiment, the material of the first epitaxial layer can be Si.

[0076] The second epitaxial layer is used to form the first channel layer.

[0077] The first channel layer is used to provide the flow region for the carrier source.

[0078] In this embodiment, when the first transistor is an NMOS transistor, the second first epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the second first epitaxial layer may be Si or SiGe, or other materials compatible with the substrate material; when the first transistor is an NMOS transistor, the second first epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the second first epitaxial layer may be Si or SiC, or other materials compatible with the substrate material.

[0079] In one specific embodiment, the material of the second first epitaxial layer can be Si.

[0080] The third epitaxial layer is used to form the second source / drain doped layer.

[0081] The second source / drain doped layer can be used as the source or drain of the first transistor Q3. When the first transistor Q3 is working, the second source / drain doped layer can be used to provide a source of charge carriers.

[0082] In this embodiment, when the first transistor Q3 is an NMOS transistor, the third epitaxial layer may include an epitaxial layer doped with N-type ions, and the material of the third epitaxial layer may be Si or SiC, or other materials compatible with the substrate material; when the first transistor Q3 is a PMOS transistor, the third epitaxial layer may include an epitaxial layer doped with P-type ions, and the material of the third epitaxial layer may be Si or SiGe, or other materials compatible with the substrate material.

[0083] In one specific embodiment, the material of the third first epitaxial layer can be Si.

[0084] It should be noted that, firstly, when there are more than three epitaxial layers, adjacent first epitaxial layers can be used as layers with the same function, for example, two consecutive first epitaxial layers can be used as source and drain doped layers; secondly, the functions of the first, second, and third first epitaxial layers listed in the above examples are only illustrative and are used to indicate that there are three consecutive first epitaxial layers that can serve as the source, drain, and channel layer between the source and drain in a semiconductor structure, and should not be construed as limiting the present invention.

[0085] In this embodiment, the first source / drain doped layer is either the source or the drain, and the second source / drain doped layer is either the source or the drain.

[0086] In other words, one of the first and second source / drain doped layers serves as the source, and the other serves as the drain.

[0087] In this embodiment, the doping type of the first source / drain doped layer is different from the doping type of the channel layer.

[0088] In one specific embodiment, the first source / drain doped layer is N-type and the first channel layer is P-type.

[0089] In one specific embodiment, the first source / drain doped layer is P-type and the first channel layer is N-type.

[0090] In this embodiment, the doping type of the second source / drain doped layer is different from the doping type of the first channel layer.

[0091] In one specific embodiment, the second source / drain doped layer is N-type and the first channel layer is P-type.

[0092] In one specific embodiment, the second source / drain doped layer is P-type and the first channel layer is N-type.

[0093] It should be noted that, firstly, this scheme does not limit the doping types of the first source / drain doped layer, the second source / drain doped layer, and the first channel layer, as long as the doping types of the first source / drain doped layer and the first channel layer are different, and the doping types of the second source / drain doped layer and the first channel layer are different; secondly, in this scheme, when the doping type is N-type, the doping ions can include: P, As, or Sb; when the doping type is P-type, the doping ions can include: B, Ga, or In.

[0094] In this embodiment, the first and second source / drain doped layers have the same doping type, and both are different from the channel layer. When a voltage is applied to the gate structure, the carrier (electron or hole) concentration in the channel layer region increases significantly, causing inversion of the region adjacent to the gate structure and forming a conductive channel. When a voltage is applied between the first and second source / drain doped layers, carriers begin to move along the conductive channel under the influence of the electric field, forming a current.

[0095] In this embodiment, the doping concentration of the first source / drain doped layer is greater than that of the first channel layer. Under the same electric field strength, the first source / drain doped layer with a higher doping concentration can provide more charge carriers, resulting in stronger current conduction capability.

[0096] In some implementations, the doping concentration of the first source / drain doped layer is 10 to 100 times that of the channel layer.

[0097] By making the doping concentration of the first source / drain doped layer 10 to 100 times that of the channel layer, the range of doping concentration selection for the first source / drain doped layer is broadened, and a first source / drain doped layer adapted to the doping concentration of the first channel layer can be formed based on the doping concentration of the first channel layer.

[0098] In one specific embodiment, the doping concentration of the first source / drain doped layer can be 1E. 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the first channel layer can be 1E. 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0099] In this embodiment, the doping concentration of the second source / drain doped layer is greater than that of the first channel layer. Under the same electric field strength, the second source / drain doped layer with a higher doping concentration can provide more charge carriers, resulting in stronger current conduction capability.

[0100] In some implementations, the doping concentration of the second source / drain doped layer is 10 to 100 times that of the first channel layer.

[0101] By making the doping concentration of the second source / drain doped layer 10 to 100 times that of the channel layer, for example, 10 times, 50 times, 80 times, etc., this broadens the selection range of the doping concentration of the second source / drain doped layer, and enables the formation of a second source / drain doped layer that matches the doping concentration of the channel layer based on the doping concentration of the channel layer.

[0102] In one specific embodiment, the doping concentration of the second source / drain doped layer can be 1E. 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the first channel layer can be 1E. 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0103] In this embodiment, the thickness of the channel layer directly affects the conductivity, current driving capability, and switching speed of the semiconductor structure. For example, a thinner channel layer can reduce the migration time of charge carriers in the channel layer and improve conductivity.

[0104] Furthermore, in this scheme, the first channel layer is in direct contact with the first source / drain doped layer and the second source / drain doped layer, the short channel effect is not obvious, and the thickness range of the channel layer is large, so it can be set according to process requirements to cope with different process nodes.

[0105] In one specific embodiment, the thickness of the first channel layer is 10 nm to 50 nm, for example, 14 nm, 28 nm, 40 nm, etc. This allows the use of process equipment with large technology nodes to produce channel layers equivalent to smaller technology nodes, reducing the requirements for process equipment.

[0106] It should be noted that the thickness of the channel layer described in the above example is for illustrative purposes only. In actual manufacturing, the thickness of the channel layer can be appropriately reduced or increased.

[0107] In other words, this solution uses epitaxial technology, and the thickness of the first channel layer is controllable. The thickness of the first channel layer can be made to meet the process requirements by setting the parameters of the epitaxial process according to the requirements of the semiconductor structure to be manufactured.

[0108] In this embodiment, the first source / drain doped layer or the second source / drain doped layer serves to provide charge carriers, and its impact on the performance of the semiconductor structure is less than that of the channel layer. The thickness of the first source / drain doped layer or the second source / drain doped layer can be greater than the thickness of the channel layer.

[0109] In addition, a thicker first or second source / drain doped layer can typically reduce the contact resistance between the layer and the channel layer, thereby improving carrier injection efficiency and device conductivity.

[0110] In one specific embodiment, the thickness of the first source / drain doped layer can be from 500 angstroms to 1000 angstroms.

[0111] In one specific embodiment, the thickness of the second source / drain doped layer can be from 500 angstroms to 1000 angstroms.

[0112] In this embodiment, the second quantity is greater than or equal to 3, that is, the number of the second epitaxial layer is at least 3. By making the number of the second epitaxial layer greater than or equal to 3, at least the source, drain, and channel layer located between the source and drain can be formed to achieve the function of current flow.

[0113] When the second quantity is greater than or equal to 3, the method for forming the semiconductor structure in this scheme can satisfy:

[0114] The first and second epitaxial layers are used to form the third source / drain doped layer.

[0115] The second epitaxial layer is used to form the second channel layer.

[0116] The third epitaxial layer forms the fourth source / drain doped layer.

[0117] The third source / drain doped layer is either the source or the drain, and the fourth source / drain doped layer is either the source or the drain.

[0118] In this embodiment, the doping concentration of the third source / drain doped layer can be 1E. 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the second channel layer can be 1E. 12 atom / cm 3 To 1E 13atom / cm 3 The doping concentration of the fourth source / drain doped layer can be 1E. 14 atom / cm 3 To 1E 15 atom / cm 3 .

[0119] It should be noted that for a detailed description of the second epitaxial layer, please refer to the description of the first epitaxial layer, which will not be elaborated here.

[0120] In this embodiment, the formation order of the first gate structure and the first number of first epitaxial layers may be different in different application scenarios, and the formation order of the second gate structure, the third gate structure and the second number of second epitaxial layers may be different. These will be explained by examples below.

[0121] In this embodiment, the first gate structure 210 is formed during the formation of the first epitaxial layer of the first number (wherein the first number can be 3), wherein the top first epitaxial layer 212 is located above the first gate structure 210.

[0122] Accordingly, see Figures 2 to 7 The formation method may include:

[0123] See Figures 2 to 4 This forms the third number of the first epitaxial layer.

[0124] In this embodiment, the third number of first epitaxial layers may include a first epitaxial layer for forming a first channel layer.

[0125] In one specific embodiment, the second first epitaxial layer 206 can serve as the first channel layer.

[0126] For further details regarding the first epitaxial layer, please refer to the aforementioned example.

[0127] In this embodiment, the third quantity is less than the first quantity.

[0128] In one specific embodiment, the first quantity can be 3, and the third quantity can be 2. That is, after forming the first epitaxial layer 202 and the second epitaxial layer 206 on the substrate 100 to form the first gate structure 210, the third epitaxial layer 212 is then formed.

[0129] More specifically, see Figure 2 A first epitaxial layer 202 is formed on the substrate 100.

[0130] The first epitaxial layer 202 can be either a source region or a drain region.

[0131] See Figure 3 and Figure 4 A second first epitaxial layer 206 is formed on the first first epitaxial layer 202.

[0132] The second epitaxial layer 206 can serve as the first channel layer.

[0133] See Figure 5 A first trench G1 is formed that penetrates at least part or all of the first epitaxial layer, and the first trench exposes the sidewall of the first epitaxial layer that is penetrated.

[0134] The first trench G1 provides location space for forming the first gate structure 210.

[0135] In this embodiment, the first trench G1 can penetrate the second first epitaxial layer 206 and the first first epitaxial layer 202 with a partial or complete thickness, and expose all the sidewalls of the second first epitaxial layer 206 and part or all the sidewalls of the first first epitaxial layer 202.

[0136] In short, the first trench G1 can penetrate the already formed first epitaxial layer and needs to expose the sidewall of the first epitaxial layer, which serves as the first trench layer.

[0137] In this embodiment, a patterning process is used to form a first trench G1 in the second epitaxial layer 206.

[0138] See Figure 6 The first gate structure 210 is formed within the first trench G1, and the first gate structure 210 is at least connected to the first channel layer (i.e., Figure 6 The sidewalls of the schematic second layer (first extension layer 206) are in contact.

[0139] When the semiconductor device is in operation, the first gate structure 210 is used to control the opening and closing of the first channel layer.

[0140] In this embodiment, the first gate structure 210 is a polycrystalline silicon gate structure or an amorphous silicon gate structure.

[0141] In this embodiment, the step of forming the first gate structure 210 includes: forming a first gate material layer (not shown) on the second first epitaxial layer 206 (i.e., the non-top first epitaxial layer), the first gate material layer also filling the first trench G1; removing the first gate material layer above the top of the first trench G1 by a planarization process (e.g., chemical mechanical polishing CMP), and retaining the first gate material layer in the first trench G1 as the first gate structure 210.

[0142] In this embodiment, the material of the gate material layer includes polycrystalline silicon.

[0143] In this embodiment, a chemical vapor deposition process is used to form the gate material layer. The film layer formed by chemical vapor deposition is thin, uniform, and has a dense structure, which is beneficial to improving the formation quality of the first gate structure 210.

[0144] In one specific embodiment, the chemical vapor deposition process can be low-pressure chemical vapor deposition (LPCVD).

[0145] It should be noted that the process temperature should not exceed 800 degrees Celsius during the formation of the first gate structure 210.

[0146] See next Figure 5 and Figure 6 The step of forming the first gate structure 210 may further include forming a first gate oxide layer 208 on the sidewall and bottom of the first trench G1.

[0147] In this embodiment, the first gate oxide layer 208 can be formed using a furnace tube process.

[0148] Compared to traditional high-temperature thermal oxidation, the above method can grow a high-quality first gate oxide layer 208 at a lower temperature, and has better thickness control and uniformity, while being compatible with the growth temperature of the first epitaxial layer.

[0149] In this embodiment, the first gate structure 210 may also cover the sidewalls and bottom of the first gate oxide layer 208.

[0150] In this embodiment, the first gate structure 210 is in contact with the sidewall of the first channel layer (i.e., the second epitaxial layer 206).

[0151] Thus, when the second first epitaxial layer 206 is used as the first channel layer, the first gate structure 210 is in contact with the second first epitaxial layer 206. When a driving voltage is applied to the first gate structure 210, the first channel layer can be turned on, making the second first epitaxial layer 206 and the third first epitaxial layer 212 (see...) Figure 7 Conductive channels are formed between them.

[0152] In other words, in this invention, the first gate structure 210 only needs to be in contact with the first epitaxial layer that serves as the first channel layer. Alternatively, the first epitaxial layer in contact with the first gate structure 210 includes the first epitaxial layer that serves as the first channel layer.

[0153] Accordingly, see below. Figure 3 and Figure 4 Before forming the first channel layer (i.e., the second epitaxial layer 206), the forming method may further include: forming a first insulating structure (e.g., within the first epitaxial layer of the first portion) Figure 3 A first insulating structure 204 is formed within the first epitaxial layer 202 (illustrated), wherein the first portion of the first epitaxial layer is located below the subsequently formed first channel layer (i.e., the second first epitaxial layer 206).

[0154] In this embodiment, the step of forming the first insulating structure 204 may include: forming a groove (not shown in the figure) in the first epitaxial layer 202, the groove exposing all or part of the sidewalls of the first epitaxial layer 202; forming a first insulating material layer that fills the groove on the first epitaxial layer 202; and using a planarization process to remove the first insulating material layer above the top of the groove, with the remaining portion of the first insulating material layer serving as the first insulating structure 204.

[0155] The process can be chemical vapor deposition to form a first insulating material layer; the first insulating material layer is an insulating material, which may include one or more of silicon oxide and silicon nitride.

[0156] In this embodiment, with the first insulating structure 204 formed, see [reference needed]. Figure 5 The first trench G1 only penetrates the second layer of the first epitaxial layer 206; the first trench G1 is also located above the first insulating structure 204 and exposes the surface of the first insulating structure 204.

[0157] See Figure 7 The remaining number of first epitaxial layers are formed on the first gate structure.

[0158] In this embodiment, the remaining number of first epitaxial layers can refer to the third first epitaxial layer 212, which can be either the source region or the drain region.

[0159] See next Figure 7 After forming the first gate structure 210, the forming method further includes: forming a second insulating structure 214 in a first epitaxial layer (e.g., a third first epitaxial layer 212) above the first channel layer, wherein the second insulating structure 214 is in contact with the surface of the first gate structure 210.

[0160] For a description of the second insulating structure 214, please refer to the aforementioned example.

[0161] In this embodiment, during the formation of the second number of second epitaxial layers, the second gate structure 230 and the third gate structure 232 are formed, wherein the top second epitaxial layer (e.g., Figure 12 The schematic third epitaxial layer 234 is located above the second gate structure 230 and the third gate structure 232.

[0162] Accordingly, see Figures 8 to 12 The formation method may include:

[0163] See Figures 8 to 10 This forms the fourth number of second epitaxial layers.

[0164] In this embodiment, the fourth number of second epitaxial layers may include a second epitaxial layer for forming a second channel layer.

[0165] In one specific embodiment, the second epitaxial layer 224 can serve as the second channel layer.

[0166] For further details regarding the second epitaxial layer, please refer to the aforementioned example.

[0167] In this embodiment, the fourth quantity is less than the second quantity.

[0168] In one specific embodiment, the second quantity can be 3 and the fourth quantity can be 2. That is, after forming the first second epitaxial layer 218 and the second first epitaxial layer 224 on the top first epitaxial layer, forming the second gate structure 230 and the third gate structure 232, the third second epitaxial layer 234 is then formed.

[0169] More specifically, see Figure 8 A first second epitaxial layer 218 is formed on the top first epitaxial layer (e.g., the third first epitaxial layer 212).

[0170] The first and second epitaxial layers 218 can be used as either a source region or a drain region.

[0171] See Figure 9 and Figure 10 A second epitaxial layer 224 is formed on the first second epitaxial layer 218.

[0172] The second epitaxial layer 224 can serve as the second channel layer.

[0173] See next Figure 10 The third trench G3 and the fourth trench G4 are formed, which at least penetrate a portion of the second epitaxial layer and are separate, with both the third trench G3 and the fourth trench G4 exposing the sidewall of the penetrated second epitaxial layer.

[0174] The third trench G3 provides location space for forming the second gate structure 230, and the fourth trench G4 provides location space for forming the third gate structure 232.

[0175] In this embodiment, the third trench G3 can penetrate the second epitaxial layer 224 and the first epitaxial layer 218 with a partial or complete thickness, and expose all the sidewalls of the second epitaxial layer 224 and part or all the sidewalls of the first epitaxial layer 218.

[0176] The fourth trench G4 can penetrate the second epitaxial layer 224 and the first epitaxial layer 218 of part or all of its thickness, and expose all the sidewalls of the second epitaxial layer 224 and part or all of the sidewalls of the first epitaxial layer 218.

[0177] In this embodiment, the third trench G3 and the fourth trench G4 only penetrate the second epitaxial layer 224 and expose the sidewall of the second epitaxial layer 224 and the surface of the first epitaxial layer 218.

[0178] In short, the third trench G3 and the fourth trench G4 need to expose the sidewalls of the first epitaxial layer, which serves as the first trench layer.

[0179] The formation process of the third trench G3 and the fourth trench G4 can be found in the description of the first trench G1.

[0180] See Figure 11 The second gate structure 230 is formed in the third trench G3, and the second gate structure 230 is in contact with at least the sidewall of the second channel layer (e.g., the second epitaxial layer 224).

[0181] The formation process, material composition, and other related details of the second gate structure 230 can be found in the aforementioned description of the first gate structure 210.

[0182] In some embodiments, see Figure 10 and Figure 11 Before forming the second gate structure 230, the formation method further includes forming a second gate oxide layer 226 on the sidewalls and bottom of the third trench G3.

[0183] The formation process, material composition, and other related details of the second gate oxide layer 226 can be found in the aforementioned description of the first gate oxide layer 208.

[0184] The third gate structure 232 is formed in the fourth trench G4, and the third gate structure 232 is in contact with at least the sidewall of the second channel layer (e.g., the second epitaxial layer 224).

[0185] The formation process, material composition, and other related details of the third gate structure 232 can be found in the aforementioned description of the first gate structure 210.

[0186] In some embodiments, see Figure 10 and Figure 11 Before forming the third gate structure 232, the formation method further includes forming a third gate oxide layer 228 on the sidewalls and bottom of the fourth trench G4.

[0187] The formation process, material composition, and other related details of the third gate oxide layer 228 can be found in the aforementioned description of the first gate oxide layer 208.

[0188] It should be noted that, firstly, in this scheme, the third trench G3 and the fourth trench G4 can be formed in the same step or in stages, and this scheme does not impose any restrictions; secondly, in this scheme, after the third trench G3 and the fourth trench G4 are formed, the second gate structure 230 and the third gate structure 232 can be formed in the same step or in stages, and this scheme does not impose any restrictions.

[0189] In this embodiment, the second gate structure 230 is in contact with the sidewall of one side of the second channel layer, and the third gate structure 232 is in contact with the sidewall of the other side of the second channel layer.

[0190] In other words, the second gate structure 230 and the third gate structure 232 are distributed on both sides of the same second channel layer.

[0191] Accordingly, before forming the second epitaxial layer as the second channel layer, the forming method further includes forming a third insulating structure 220 within the second epitaxial layer (first second epitaxial layer 218) of the third portion, wherein the second epitaxial layer of the third portion is located below the subsequently formed second channel layer (i.e., second second epitaxial layer 224).

[0192] The method of forming the third insulating structure 220, its material composition, and other related details can be found in the aforementioned description of the first insulating structure 204.

[0193] In this embodiment, when the third insulating structure 220 is formed, see [reference needed]. Figure 10 The third trench G3 only penetrates the second epitaxial layer 224; the third trench G3 is also located above the third insulating structure 220 and exposes the surface of the third insulating structure 220.

[0194] Accordingly, before forming the second epitaxial layer as the second channel layer, the forming method further includes forming a fourth insulating structure 222 within the second epitaxial layer of the third portion, wherein the second epitaxial layer of the third portion is located below the subsequently formed second channel layer (i.e., the second epitaxial layer 224).

[0195] The method of forming the fourth insulating structure 222, its material composition, and other related details can be found in the aforementioned description of the first insulating structure 204.

[0196] In this embodiment, when the fourth insulating structure 222 is formed, see [reference needed]. Figure 10The fourth trench G4 only penetrates the second epitaxial layer 224; the fourth trench G4 is also located above the fourth insulating structure 222 and exposes the surface of the fourth insulating structure 222.

[0197] In this embodiment, see Figure 12 The projection of the second gate structure 230 onto the substrate 100 covers at least a portion of the first gate structure 210, which makes the second gate structure 230 and the first gate structure 210 have a spacing D along a line parallel to the surface of the substrate 100, which helps to reduce the difficulty of forming a conductive structure in contact with the first gate structure 210.

[0198] More specifically, see Figure 12 The projection of the second gate structure 230 onto the first gate structure 210 has a distance D between it and the far end of the first gate structure 210, and the far end of the first gate structure 210 is the end that does not overlap with the second gate structure 230.

[0199] See Figure 12 The remaining number of second epitaxial layers are formed on the second gate structure 230 and the third gate structure 232.

[0200] In this embodiment, the remaining number of second epitaxial layers can refer to the third second epitaxial layer 234, which can serve as either the source region or the drain region.

[0201] See Figure 8 In the step of forming discrete stacked devices on the substrate 100, a first isolation structure 216 is also formed. The first isolation structure 216 is located between the first device structure and the second device structure to achieve insulation between the first device structure and the second device structure.

[0202] More specifically, the first isolation structure 216 is located between the top first epitaxial layer and the bottom second epitaxial layer.

[0203] In this embodiment, after forming the second device structure, a conductive structure can also be formed to bring out the corresponding film layers in the first device structure and the second device structure.

[0204] More specifically, see Figure 13 The method for forming a semiconductor structure further includes: forming a first conductive structure CT11, wherein the first conductive structure CT11 is electrically connected to the first gate structure 210.

[0205] In this embodiment, the step of forming the first conductive structure CT11 may include: forming an interlayer dielectric layer 236 on the second device structure, namely the third layer, the second epitaxial layer 234; removing a portion of the interlayer dielectric layer 236, as well as all the second epitaxial layers below the portion of the interlayer dielectric layer 236, and a portion of the first epitaxial layer, to form a first opening (not shown in the figure) exposing the first gate structure 210; forming a first spacer layer IS1 on the sidewall of the first opening; and forming a first conductive plug P1 in at least the remaining space of the first opening.

[0206] The step of forming the first spacer layer IS1 on the sidewall of the first opening includes: forming a first spacer material layer inside the first opening; removing the first spacer material layer located at the bottom of the first opening, and using the remaining portion of the first spacer material layer as the first spacer layer IS1. For example, an etch-back process can be used to remove the insulating material layer located at the bottom of the first opening.

[0207] The material of the first spacer layer IS1 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride.

[0208] The material of the first conductive plug P1 includes materials with good conductivity such as cobalt, copper, aluminum, or tungsten.

[0209] A second conductive structure CT12 is formed, and the second conductive structure CT12 is electrically connected to the second gate structure 230.

[0210] The second conductive structure CT12 includes: a second spacer layer IS2, and a second conductive plug P2 covering the sidewall of the second spacer layer IS2.

[0211] The method for forming the second conductive structure CT12 can be found in the description of the first conductive structure CT1. The difference is that, in the process of forming the second conductive structure CT12, the second opening exposes the surface of the second gate structure 230.

[0212] A third conductive structure CT13 is formed, and the third conductive structure CT13 is electrically connected to the third gate structure 232.

[0213] The third conductive structure CT13 includes: a third spacer layer IS3, and a third conductive plug P3 covering the sidewall of the third spacer layer IS3.

[0214] The method for forming the third conductive structure CT13 can be found in the description of the first conductive structure CT1. The difference is that, in the process of forming the third conductive structure CT13, the third opening exposes the surface of the third gate structure 232.

[0215] In this embodiment, for each of the first epitaxial layers, either partially or completely, at least one fourth conductive structure is formed, and each fourth conductive structure is electrically connected to the corresponding first epitaxial layer.

[0216] In this embodiment, multiple first epitaxial layers are stacked together along the normal direction of the substrate surface, and between the first epitaxial layer and the second epitaxial layer. When forming the fourth conductive structure, there is a situation where the fourth conductive structure is electrically connected to the two epitaxial layers.

[0217] In this case, during the formation of the first conductive structure, it is necessary to ensure electrical insulation between it and the non-electrically connected epitaxial layers to avoid short circuits caused by the first conductive structure being electrically connected to at least two epitaxial layers.

[0218] More specifically, the step of forming at least one fourth conductive structure may include:

[0219] A seventh trench (not shown) is formed, at least exposing a portion of the sidewall of the first epitaxial layer that is electrically connected to the fourth conductive structure; a first insulating layer is formed on the sidewall of the seventh trench; a fourth conductive plug is formed at least in the remaining space of the seventh trench, the fourth conductive plug being electrically connected to the first epitaxial layer, and the fourth conductive plug and the first insulating layer constituting the fourth conductive structure.

[0220] As a concrete example, combined with Figures 1 to 13 See Figure 14 When the first epitaxial layer has 3 layers, the number of fourth conductive structures can be 3.

[0221] More specifically, the fourth conductive structure CT14 may include a first insulating layer IS4 and a fourth conductive plug P4 covering the sidewall of the first insulating structure IS4 and electrically connected to the third first epitaxial layer 212; the fourth conductive structure CT15 may include a first insulating layer IS5 and a fourth conductive plug P5 covering the sidewall of the first insulating structure IS5 and electrically connected to the first first epitaxial layer 202; the fourth conductive structure CT16 may include a first insulating layer IS6 and a fourth conductive plug P6 covering the sidewall of the first insulating structure IS6 and electrically connected to the second first epitaxial layer 206.

[0222] It should be noted that, in the case of forming the first insulating structure, the first conductive structure and the fourth conductive structure also penetrate the first insulating structure.

[0223] In this embodiment, for each of the second epitaxial layers, either partially or completely, at least one fifth conductive structure is formed, and each fifth conductive structure is electrically connected to the corresponding second epitaxial layer.

[0224] In this embodiment, along the normal direction of the substrate surface, when the fifth conductive structure is formed between the multiple second epitaxial layers, there is a situation where the fifth conductive structure is electrically connected to the two epitaxial layers.

[0225] In this case, during the formation process, electrical insulation is required between the fifth conductive structure and at least two non-electrically connected epitaxial layers to avoid short circuit problems caused by the fifth conductive structure being electrically connected to at least two epitaxial layers.

[0226] More specifically, the step of forming at least one fifth conductive structure may include:

[0227] An eighth trench is formed, at least exposing a portion of the sidewall of the second epitaxial layer that is electrically connected to the second conductive structure; a second insulating layer is formed on the sidewall of the eighth trench; a fifth conductive plug is formed at least in the remaining space of the eighth trench, the fifth conductive plug being electrically connected to the second epitaxial layer, and the fifth conductive plug and the second insulating layer serving as the fifth conductive structure.

[0228] As a concrete example, combined with Figures 1 to 14 When the second epitaxial layer has 3 layers, the number of the fifth conductive structure can be 3.

[0229] More specifically, the fifth conductive structure CT17 can be electrically connected to the first second epitaxial layer 218; the fifth conductive structure CT18 can be electrically connected to the second second epitaxial layer 224; and the fifth conductive structure CT19 can be electrically connected to the third second epitaxial layer 234.

[0230] For a more detailed description of the fifth conductive structure, please refer to the examples above.

[0231] also, Figure 1 The fifth conductive structure CT20, which is electrically connected to the third layer 234 of the second epitaxial layer of the third transistor T2, is also shown.

[0232] In this embodiment, when the second epitaxial layer is the top epitaxial layer, the fifth conductive plug can be directly formed as the fifth conductive structure. For example, the fifth conductive structure CT20 is in contact with the sidewall of the third second epitaxial layer 234.

[0233] In this embodiment, when the second epitaxial layer is the top epitaxial layer, two fifth conductive structures can be formed on the top second epitaxial layer.

[0234] It should be noted that, firstly, the formation processes of the first to fifth conductive structures in the aforementioned examples are merely illustrative and should not be construed as limiting the present invention; secondly, in Figure 1 In the illustrated structure, there are some fifth conductive structures and fourth conductive structures that overlap along one of the directions.

[0235] In practical applications, for example, one conductive structure can be formed first, followed by the formation of other conductive structures; another example is to first perform the steps of forming openings / grooves and insulating layers, and then simultaneously or stepwise form conductive plugs; yet another example is to first perform the step of forming trenches, then perform the step of forming insulating layers, and finally simultaneously or stepwise form conductive plugs.

[0236] In one embodiment, the steps of forming the opening / groove and the insulating layer are performed first, and then the conductive plug is formed simultaneously.

[0237] It should be noted that in the scheme of forming openings / grooves in stages, when forming the first opening / groove, only the area used to form the first groove is exposed, while the other areas are covered.

[0238] It should also be noted that the formation process of the second stacked device 300 can be found in the description of the first stacked device 200. For example, in Figure 1 In the structure shown, the second stacked device 300 also forms the first to fifth conductive structures. The first conductive structure is CT21, the second conductive structure is CT22, the third conductive structure is CT23, the fourth conductive structures are CT24, CT25 and CT26, and the fifth conductive structures are CT27, CT28 and CT29.

[0239] also, Figure 1 The fifth conductive structure CT30, which is electrically connected to the third layer 234 of the second epitaxial layer of the third transistor T1, is also shown.

[0240] It should be noted that the reason for using conductive structures to bring out the epitaxial layers, which serve as the channel layer, in this design is twofold. Firstly, when the epitaxial layers are used as channel layers, they do not contact the substrate, thus preventing the substrate from acting as a discharge channel for the channel layer. Secondly, the close proximity of the conductive structures used to bring out the three epitaxial layers leads to charge accumulation within the channel layer. By incorporating these two points, a conductive structure electrically connected to the channel layer can be used to extract the charge within the channel layer, reducing leakage current.

[0241] In addition, the conductive structure connected to the channel layer can be used as a ground terminal to provide a reference value for the entire semiconductor structure.

[0242] Then combine Figure 1 See Figure 15 and Figure 16 After forming the first to fifth conductive structures, the forming method further includes:

[0243] A first metal lead ML1 is formed, which is electrically connected to the first and second conductive structures of the current stacked device, as well as the fourth and fifth conductive structures of another stacked device.

[0244] As a specific embodiment, the first metal lead ML1 can be electrically connected to the first conductive structure CT11 and the second conductive structure CT12 of the first stacked device 200, as well as the fourth conductive structure CT24 and the fifth conductive structure CT27 of the second stacked device 300.

[0245] A second metal lead ML2 is formed, which is electrically connected to the first and second conductive structures of another stacked device, as well as the fourth and fifth conductive structures of the current stacked device.

[0246] As a specific embodiment, the second metal lead ML2 can be electrically connected to the first conductive structure CT21 and the second conductive structure CT22 of another stacked device 300, as well as the fourth conductive structure CT14 and the fifth conductive structure CT17 of the current stacked device 200.

[0247] In this embodiment, when the semiconductor structure is SRAM, the first metal lead ML1 and the second metal lead ML2 realize the electrical connection between the first transistor Q4, the second transistor Q2, the first transistor Q3, and the second transistor Q1.

[0248] A third metal lead ML3 is formed, which is electrically connected to the fourth and fifth conductive structures of the current stacked device, and the fourth and fifth conductive structures of another stacked device.

[0249] As a specific embodiment, the third metal lead ML3 can be electrically connected to the fourth conductive structure CT15 and the fifth conductive structure CT18 of the first stacked device 200, and the fourth conductive structure CT25 and the fifth conductive structure CT28 of the second stacked device 300.

[0250] In this embodiment, when the semiconductor structure is SRAM, a third metal lead ML3 is formed and connected to VCC.

[0251] A fourth metal lead ML4 is formed, which is electrically connected to the fourth and fifth conductive structures of the current stacked device, and the fourth and fifth conductive structures of another stacked device.

[0252] As a specific embodiment, the fourth metal lead ML4 can be electrically connected to the fourth conductive structure CT16 and the fifth conductive structure CT19 of the first stacked device 200, and the fourth conductive structure CT26 and the fifth conductive structure CT29 of the second stacked device 300.

[0253] In this embodiment, when the semiconductor structure is SRAM, the fourth metal lead ML4 serves as the ground terminal and is connected to VSS.

[0254] A fifth metal lead ML5 is formed, which is electrically connected to the current stacked device and the third conductive structure of another stacked device.

[0255] As a specific embodiment, the fifth metal lead ML5 can be electrically connected to the third conductive structure CT13 of the first stacked device 200 and the third conductive structure CT23 of the second stacked device 300.

[0256] In this embodiment, when the semiconductor structure is SRAM, the fifth metal lead ML5 serves as the word line WL.

[0257] A sixth metal lead ML6 is formed, which is electrically connected to the fifth conductive structure CT20 of the current stacked device.

[0258] In this embodiment, when the semiconductor structure is SRAM, the sixth metal lead ML6 serves as the reverse bit line ( ).

[0259] A seventh metal lead ML7 is formed, which is electrically connected to the fifth conductive structure CT30 of another stacked device.

[0260] In this embodiment, when the semiconductor structure is SRAM, the seventh metal lead ML7 serves as the bit line (BL).

[0261] It should be noted that, see Figure 16 In the actual wiring, the third transistor T1 is also electrically connected to the second transistor Q1 and the first transistor Q3.

[0262] Similarly, the third transistor T2 is also electrically connected to the second transistor Q2 and the first transistor Q4.

[0263] In this embodiment, during the step of forming discrete stacked devices on the substrate, a second isolation structure is also formed. The second isolation structure is located between adjacent stacked devices to achieve isolation between the stacked devices.

[0264] See Figure 17The schematic diagrams of each step in the second embodiment of the method for forming the semiconductor structure of the present invention shown are identical to those in the previous embodiments and will not be described again. The differences are as follows:

[0265] In this embodiment, see Figure 17 After forming the first number of first epitaxial layers (e.g., first epitaxial layer 202, second epitaxial layer 206, and third epitaxial layer 212), the first gate structure 210 is formed.

[0266] In other words, the first number of first epitaxial layers are formed, and a second trench (not shown in the figure) is formed that at least partially penetrates the first epitaxial layer. The second trench exposes the sidewall of the penetrated first epitaxial layer (in this embodiment, the second trench exposes the sidewall of the second first epitaxial layer 206 and the third first epitaxial layer 212). The first gate structure 210 is formed in the second trench, and the first gate structure 210 is in contact with at least the sidewall of the first channel layer (i.e., the second first epitaxial layer 206).

[0267] See Figure 18 The schematic diagrams of each step in the third embodiment of the method for forming the semiconductor structure of the present invention shown are identical to those in the previous embodiments and will not be described again. The differences are as follows:

[0268] In this embodiment, see Figure 18 After forming the second number of second epitaxial layers (e.g., first second epitaxial layer 218, second second epitaxial layer 224 and third second epitaxial layer 234), the second gate structure 230 is formed.

[0269] In other words, the second number of second epitaxial layers are formed; a fifth trench (not shown in the figure) and a sixth trench (not shown in the figure) are formed, each penetrating at least a portion of the second epitaxial layer, and are separate, with the fifth trench and the sixth trench exposing the sidewalls of the penetrating second epitaxial layer (in this embodiment, both the fifth trench and the sixth trench expose the sidewalls of the second epitaxial layer 224 and the third epitaxial layer 234); a second gate structure 230 is formed in the fifth trench, the second gate structure 230 being in contact with at least one sidewall of the second channel layer; and a third gate structure 232 is formed in the sixth trench, the third gate structure 232 being in contact with at least the other sidewall of the second channel layer.

[0270] This invention also provides a semiconductor structure. See [link to related document]. Figure 1 and Figure 13 The semiconductor structure includes: a substrate 100; discrete stacked devices (as a non-limiting example, Figure 1The diagram illustrates a discrete first stacked device 200 and a second stacked device 300 located on the substrate 100. Each stacked device includes a first device structure (not shown) and a second device structure (not shown) arranged sequentially along the normal direction of the substrate surface.

[0271] The substrate 100 can provide the basis for the process operation of semiconductor structure formation.

[0272] The semiconductor structure may include memory cells, such as static random access memory (SRAM). In some other embodiments, the semiconductor structure may also include other types of memory cells.

[0273] In one specific embodiment, the first stacked device 200 may include a first transistor Q4, a second transistor Q2 located on the first transistor Q4, and a third transistor T2 sharing a second channel layer with the second transistor Q2.

[0274] Correspondingly, the second stacked device 300 may include a first transistor Q3, a second transistor Q1 located on the first transistor Q3, and a third transistor T1 sharing a second channel layer with the second transistor Q1.

[0275] It should be noted that, firstly, when the semiconductor structure is SRAM, the first stacked device 200 and the second stacked device 300 constitute an SRAM bit cell.

[0276] Specifically, in the first stacked device 200, the first transistor Q4 can be used as the first pull-up transistor, the second transistor Q2 can be used as the first pull-down transistor, the third transistor T2 can be used as the first control transistor, and the first transistor Q4 and the second transistor Q2 constitute the first inverter.

[0277] In the second stacked device 300, the first transistor Q3 can be used as the second pull-up transistor, the second transistor Q1 can be used as the second pull-down transistor, the third transistor T1 can be used as the second control transistor, and the first transistor Q3 and the second transistor Q1 constitute the second inverter.

[0278] In this embodiment, the first transistor includes: a plurality of first epitaxial layers sequentially disposed along the surface of the substrate 100 (as a non-limiting example, the plurality of first epitaxial layers include a first epitaxial layer 202, a second epitaxial layer 206, and a third epitaxial layer 212), at least one epitaxial layer serving as the first channel layer of the first transistor, wherein each first epitaxial layer has its own doping type and doping concentration; and a first gate structure 210 in contact with at least the sidewall of the first channel layer.

[0279] Each of the first epitaxial layers has its own doping concentration and doping type. For a more detailed description of the first epitaxial layer, please refer to the example above.

[0280] In this embodiment, the plurality of first epitaxial layers satisfy at least one or more of the following:

[0281] The first epitaxial layer 202 serves as the first source / drain doped layer.

[0282] For a more detailed description of the first epitaxial layer 202, please refer to the aforementioned example.

[0283] The second epitaxial layer 206 serves as the first channel layer.

[0284] For a more detailed description of the second layer, the first epitaxial layer 206, please refer to the aforementioned example.

[0285] The third epitaxial layer 212 serves as the second source / drain doped layer.

[0286] For a more detailed description of the third layer, the first epitaxial layer 212, please refer to the aforementioned example.

[0287] In this embodiment, the first source / drain doped layer is either the source or the drain, and the second source / drain doped layer is either the source or the drain.

[0288] More specifically, the first epitaxial layer 202 serves as the source, and the third epitaxial layer 212 serves as the drain.

[0289] When the semiconductor device is in operation, the first gate structure 210 is used to control the opening and closing of the first channel layer.

[0290] In this embodiment, the first gate structure 210 is a polycrystalline silicon gate structure or an amorphous silicon gate structure.

[0291] In this embodiment, the first gate structure 210 is in contact with the sidewall of the first channel layer (i.e., the second epitaxial layer 206), and the semiconductor structure further includes:

[0292] The first insulating structure 204 penetrates the first epitaxial layer below the first channel layer and is in contact with the sidewall of the first channel layer and the bottom of the first gate structure 210.

[0293] For a more detailed description of the first insulating structure 204, please refer to the foregoing example.

[0294] The second insulating structure 214 penetrates the first epitaxial layer above the first channel layer and is in contact with the sidewall of the first epitaxial layer and the surface of the first gate structure.

[0295] For a more detailed description of the second insulating structure 214, please refer to the foregoing example.

[0296] It should be noted that when the first gate structure 210 is still in contact with the sidewalls of other first epitaxial layers, the second insulating structure 214 may not be formed (e.g., Figure 17 ).

[0297] In this embodiment, the semiconductor structure may further include: a first gate oxide layer 208, which covers the sidewall of the first gate structure 210 and is located between the first gate structure 210 and the first epitaxial layer 202.

[0298] The second transistor Q2 may include: a plurality of second epitaxial layers sequentially disposed along the surface of the substrate 100 (as a non-limiting example, the plurality of second epitaxial layers include a first second epitaxial layer 218, a second second epitaxial layer 224, and a third second epitaxial layer 234), at least one outer second epitaxial layer serving as the second channel layer of the second transistor Q2, wherein each second epitaxial layer has its own doping type and doping concentration; a second gate structure 230, which is in contact with at least the sidewall of the first channel layer; wherein the bottom second epitaxial layer is located on the top first epitaxial layer.

[0299] When the semiconductor device is in operation, the second gate structure 230 is used to control the opening and closing of the second channel layer.

[0300] In this embodiment, the second gate structure 230 is a polycrystalline silicon gate structure or an amorphous silicon gate structure.

[0301] In this embodiment, the third transistor T2 includes: a plurality of second epitaxial layers shared with the second transistor Q2, wherein the second channel layer of the second transistor Q2 also serves as the second channel layer of the third transistor T2; and a third gate structure 232 in contact with at least the sidewall of the second channel layer.

[0302] In other words, the third transistor T2 has a plurality of second epitaxial layers sequentially disposed along the surface of the substrate 100 (as a non-limiting example, the plurality of second epitaxial layers include a first second epitaxial layer 218, a second second epitaxial layer 224, and a third second epitaxial layer 234), with at least one second epitaxial layer serving as the second channel layer of the third transistor T2, wherein each second epitaxial layer has its own doping type and doping concentration.

[0303] When the semiconductor device is in operation, the third gate structure 232 is used to control the opening and closing of the second channel layer.

[0304] In this embodiment, the third gate structure 232 is a polycrystalline silicon gate structure or an amorphous silicon gate structure.

[0305] In this embodiment, the second gate structure 230 is in contact with one sidewall of the second channel layer, and the third gate structure 232 is in contact with the other sidewall of the second channel layer. The semiconductor structure further includes:

[0306] The third insulating structure 220 penetrates the second epitaxial layer below the second channel layer and contacts the sidewall of the second epitaxial layer and the bottom of the second gate structure.

[0307] For example, the third insulating structure 220 is in contact with the sidewall of the second epitaxial layer, and the third insulating structure 220 is located within the first second epitaxial layer 218.

[0308] The fourth insulating structure 222 penetrates the second epitaxial layer below the second channel layer and contacts the sidewall of the second epitaxial layer and the surface of the third gate structure.

[0309] Similarly, the fourth insulating structure 222 is located within the first second epitaxial layer 218.

[0310] For further description of the third insulating structure 220 and the fourth insulating structure 222, please refer to the foregoing examples.

[0311] It should be noted that when the first gate structure 210 is still in contact with the sidewalls of other second epitaxial layers, the fourth insulating structure 222 may not be formed (e.g., Figure 18 ).

[0312] In this embodiment, the semiconductor structure may further include a second gate oxide layer 226, which covers the sidewall of the second gate structure 230 and is located between the second gate structure 230 and the first epitaxial layer 218.

[0313] The third gate oxide layer 228 covers the sidewall of the third gate structure 232 and is located between the third gate structure 232 and the first second epitaxial layer 218.

[0314] In this embodiment, to facilitate the introduction of the corresponding film layers in the first and second device structures, please refer to the following section. Figure 1 , Figure 13 and Figure 14 The semiconductor structure may also include:

[0315] The first conductive structure CT11 is electrically connected to the first gate structure 210.

[0316] In this embodiment, the first conductive structure CT11 may include: a first spacer layer IS1 that contacts the sidewalls of all the second epitaxial layers and a portion of the sidewalls of the first epitaxial layer (e.g., the third first epitaxial layer 212); and a first conductive plug P1 that covers the sidewalls of the first spacer layer IS1 and is electrically connected to the first gate structure 210.

[0317] The second conductive structure CT12 is electrically connected to the second gate structure 230.

[0318] In this embodiment, the second conductive structure CT12 may include: a second spacer layer IS2 that contacts the sidewall of a portion of the second epitaxial layer (e.g., the third second epitaxial layer 234); and a second conductive plug P2 that covers the sidewall of the second spacer layer IS2 and is electrically connected to the second gate structure 230.

[0319] The third conductive structure CT13 is electrically connected to the third gate structure 232.

[0320] In this embodiment, the third conductive structure CT13 may include: a third spacer layer IS3 that is in contact with the sidewall of a portion of the second epitaxial layer (e.g., the third second epitaxial layer 234); and a third conductive plug P3 that covers the sidewall of the third spacer layer IS3 and is electrically connected to the third gate structure 232.

[0321] At least one fourth conductive structure is electrically connected to the corresponding first epitaxial layer.

[0322] In this embodiment, there are three fourth conductive structures CT14, CT15 and CT16, wherein the fourth conductive structure CT14 is electrically connected to the third first epitaxial layer 212; the fourth conductive structure CT15 is electrically connected to the first first epitaxial layer 202; and the fourth conductive structure CT16 is electrically connected to the second first epitaxial layer 206.

[0323] The fourth conductive structure includes: a first insulating layer, and a conductive plug that covers the first insulating layer and is electrically connected to the corresponding first epitaxial layer.

[0324] The relative positional relationship between the first insulating layer and the other film layers can be seen in the example above.

[0325] At least one fifth conductive structure is electrically connected to the corresponding second epitaxial layer.

[0326] In this embodiment, there are three fifth conductive structures CT17, CT18 and CT19. The fifth conductive structure CT17 can be electrically connected to the first second epitaxial layer 218; the fifth conductive structure CT18 can be electrically connected to the second second epitaxial layer 224; and the fifth conductive structure CT19 can be electrically connected to the third second epitaxial layer 234.

[0327] also, Figure 1 and Figure 13 The fifth conductive structure CT20 is also illustrated, which is electrically connected to the third second channel layer 234 of the third transistor T2.

[0328] The fifth conductive structure includes: a second insulating layer, and a conductive plug that covers the second insulating layer and is electrically connected to the corresponding second epitaxial layer.

[0329] The relative positional relationship between the second insulating layer and the other films can be seen in the example above.

[0330] In this embodiment, combined with Figure 1 See Figure 13 and Figure 15 The semiconductor structure may also include:

[0331] The first metal lead ML1 is electrically connected to the first and second conductive structures of the current stacked device, as well as the fourth and fifth conductive structures of another stacked device.

[0332] The second metal lead ML2 is electrically connected to the first and second conductive structures of another stacked device, as well as the fourth and fifth conductive structures of the current stacked device.

[0333] The third metal lead ML3 is electrically connected to the fourth and fifth conductive structures of the current stacked device, and the fourth and fifth conductive structures of another stacked device.

[0334] The fourth metal lead ML4 is electrically connected to the fourth and fifth conductive structures of the current stacked device, and the fourth and fifth conductive structures of another stacked device.

[0335] The fifth metal lead ML5 is electrically connected to the current stacked device and the third conductive structure of another stacked device.

[0336] As a specific embodiment, the fifth metal lead ML5 can be electrically connected to the third conductive structure CT13 of the first stacked device 200 and the third conductive structure CT23 of the second stacked device 300.

[0337] In this embodiment, when the semiconductor structure is SRAM, the fifth metal lead ML5 serves as the word line WL.

[0338] The sixth metal lead ML6 is electrically connected to the fifth conductive structure CT20 of the current stacked device.

[0339] In this embodiment, when the semiconductor structure is SRAM, the sixth metal lead ML6 serves as the reverse bit line ( ).

[0340] The seventh metal lead ML7 is electrically connected to the fifth conductive structure CT30 of another stacked device.

[0341] For a detailed description of the first metal lead ML1 to the seventh metal lead ML7, please refer to the foregoing example.

[0342] In this embodiment, the semiconductor structure may further include a first isolation structure 216, which is located between the first device structure and the second device structure to achieve insulation between the first device structure and the second device structure.

[0343] Specifically, the first isolation structure 216 is located between the third first epitaxial layer 212 and the first second epitaxial layer 218.

[0344] In this embodiment, during the step of forming discrete stacked devices on the substrate, a second isolation structure is also formed. The second isolation structure is located between adjacent stacked devices to achieve isolation between the stacked devices.

[0345] In this embodiment, the semiconductor structure may further include: an interlayer dielectric layer 236, located on the topmost epitaxial layer, and covering the sidewalls of the first conductive structure, the second conductive structure, the third conductive structure, the fourth conductive structure, and the fifth conductive structure.

[0346] In this embodiment, the material of the interlayer dielectric layer 236 is an insulating material, for example, silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0347] It should be noted that the semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0348] While this specification discloses the invention as described above, the invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of this invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Discrete stacked devices are formed on the substrate. Each stacked device includes a first device structure and a second device structure arranged sequentially along the normal direction of the substrate surface. The first device structure includes a first transistor, and the second device structure includes a second transistor and a third transistor. The second transistor and the third transistor share a second channel layer, which is formed epitaxially. The first transistor includes a first gate structure, the second transistor includes a second gate structure, and the third transistor includes a third gate structure. The second gate structure and the third gate structure are in contact with at least the sidewalls of the second channel layer. The semiconductor structure includes SRAM. The second transistor serves as a first pull-down transistor, and the first transistor serves as a first pull-up transistor. The projection of the second gate structure on the substrate is located within the projection of the first gate structure on the substrate. The second gate structure and the first gate structure are spaced parallel to the substrate surface. The space refers to the distance between the projection of the second gate structure on the first gate structure and the distal end of the first gate structure. The distal end of the first gate structure is the end that does not overlap with the second gate structure. A first conductive structure is formed, which penetrates the second channel layer, is electrically connected to the first gate structure, and is located at the interval.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The steps for forming each stacked device include: A first number of first epitaxial layers are formed on the substrate, at least one epitaxial layer serving as the first channel layer of the first transistor, wherein each first epitaxial layer has its own doping type and doping concentration; The first gate structure is formed, and the first gate structure is in contact with at least the sidewall of the first channel layer; A second number of second epitaxial layers are formed on the first gate structure, with at least one second epitaxial layer serving as the second channel layer, wherein each second epitaxial layer has its own doping type and doping concentration; The second gate structure and the third gate structure are formed, and the second gate structure and the third gate structure are in contact with at least the sidewall of the second channel layer.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, Each layer of first epitaxial layer and / or each layer of second epitaxial layer is formed using an epitaxial process, and doping is performed during the epitaxial growth process.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The formation temperature of each first epitaxial layer and / or each second epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The formation parameters of each first epitaxial layer and / or each second epitaxial layer further include at least one of the following: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and an epitaxial rate of 200 Å / min to 300 Å / min.

6. The method for forming a semiconductor structure according to claim 2, characterized in that, The first quantity is greater than or equal to 3, and the first epitaxial layer of the first quantity satisfies at least one or more of the following: a first epitaxial layer, the first epitaxial layer being used to form a first source / drain doped layer; a second epitaxial layer, the second epitaxial layer being used to form the first channel layer; a third epitaxial layer, the third epitaxial layer being used to form a second source / drain doped layer; the first source / drain doped layer is one of the source or the drain, and the second source / drain doped layer is the other of the source or the drain; The second quantity is greater than or equal to 3, and the second number of second epitaxial layers satisfies at least one or more of the following: a first second epitaxial layer, which is used to form a third source / drain doped layer; a second second epitaxial layer, which is used to form a second channel layer; a third second epitaxial layer, which is used to form a fourth source / drain doped layer; the third source / drain doped layer is one of the source or the drain, and the fourth source / drain doped layer is the other of the source or the drain.

7. The method for forming a semiconductor structure according to claim 2, characterized in that, The steps for forming the first gate structure satisfy at least one or more of the following: During the formation of the first number of first epitaxial layers, the first gate structure is formed, with the top first epitaxial layer located above the first gate structure; After forming the first number of first epitaxial layers, the first gate structure is formed.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, In the process of forming the first number of first epitaxial layers, the method for forming the first gate structure includes: A third number of first epitaxial layers are formed, the third number of first epitaxial layers including first epitaxial layers for forming a first channel layer, and the third number is less than the first number; A first trench is formed that penetrates at least part or all of the first epitaxial layer, and the first trench exposes the sidewall of the first epitaxial layer that is penetrated. The first gate structure is formed in the first trench, and the first gate structure is in contact with at least the sidewall of the first trench layer; The remaining number of first epitaxial layers are formed on the first gate structure.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, The first gate structure is in contact with the sidewall of the first channel layer; Before forming the first trench layer, the forming method further includes: forming a first insulating structure within a first epitaxial layer of a first portion; wherein the first trench is located above the first insulating structure and exposes the surface of the first insulating structure, and the first epitaxial layer of the first portion is located below the subsequently formed first trench layer; After forming the first gate structure, the forming method further includes: forming a second insulating structure in the first epitaxial layer of the second portion, the second insulating structure being in contact with the surface of the first gate structure, and the first epitaxial layer of the second portion being located above the formed first channel layer.

10. The method for forming a semiconductor structure according to claim 7, characterized in that, After forming multiple first epitaxial layers, the method for forming the first gate structure includes: Forming the first number of first epitaxial layers; A second trench is formed that penetrates at least a portion of the first epitaxial layer, and the second trench exposes the sidewall of the first epitaxial layer that is penetrated. The first gate structure is formed within the second trench, and the first gate structure is in contact with at least the sidewall of the first trench layer.

11. The method for forming a semiconductor structure according to claim 2, characterized in that, The steps of forming the second gate structure and the third gate structure satisfy at least one or more of the following: During the formation of the second number of second epitaxial layers, the second gate structure and the third gate structure are formed, with the top second epitaxial layer located above the second gate structure and the third gate structure; After forming the second number of second epitaxial layers, the second gate structure and the third gate structure are formed.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, In the process of forming the second number of second epitaxial layers, the method for forming the second gate structure and the third gate structure includes: A fourth number of second epitaxial layers are formed, the fourth number of second epitaxial layers including second epitaxial layers for forming second channel layers, and the fourth number is less than the second number; A third trench and a fourth trench are formed, each of which penetrates at least a portion of the second epitaxial layer and is separate, with the third trench and the fourth trench exposing the sidewall of the penetrated second epitaxial layer. The second gate structure is formed in the third trench, and the second gate structure is in contact with at least one sidewall of the second channel layer; The third gate structure is formed in the fourth trench, and the third gate structure is in contact with at least one sidewall on the other side of the second channel layer; The remaining number of second epitaxial layers are formed on the second gate structure and the third gate structure.

13. The method for forming a semiconductor structure according to claim 12, characterized in that, The second gate structure and the third gate structure are in contact with the sidewall of the second channel layer; Before forming the second epitaxial layer as the second channel layer, the forming method further includes: forming a third insulating structure within the third portion of the second epitaxial layer; wherein the third trench is located above the third insulating structure and exposes the surface of the third insulating structure, and the third portion of the second epitaxial layer is located below the subsequently formed second channel layer; Before forming the second epitaxial layer as the second channel layer, the forming method further includes: forming a fourth insulating structure within the second epitaxial layer of the third portion; the fourth trench is located above the fourth insulating structure and exposes the surface of the fourth insulating structure.

14. The method for forming a semiconductor structure according to claim 11, characterized in that, After forming the second number of second epitaxial layers, the method for forming the second gate structure and the third gate structure includes: Form the second number of second epitaxial layers; A fifth trench and a sixth trench are formed that penetrate at least a portion of the second epitaxial layer and are separate, the fifth trench and the sixth trench exposing the sidewall of the penetrated second epitaxial layer; The second gate structure is formed in the fifth trench, and the second gate structure is in contact with at least one sidewall of the second channel layer; The third gate structure is formed within the sixth trench, and the third gate structure is in contact with at least one sidewall of the second channel layer.

15. The method for forming a semiconductor structure according to claim 2, characterized in that, In the step of forming discrete stacked devices on the substrate, a first isolation structure is also formed, the first isolation structure being located between the first device structure and the second device structure.

16. The method for forming a semiconductor structure according to claim 2, characterized in that, It also meets at least one or more of the following conditions: A second conductive structure is formed, and the second conductive structure is electrically connected to the second gate structure; A third conductive structure is formed, and the third conductive structure is electrically connected to the third gate structure. For each of the first epitaxial layers, either partially or completely, at least one fourth conductive structure is formed, and each fourth conductive structure is electrically connected to the corresponding first epitaxial layer. For each of the second epitaxial layers, either partially or completely, at least one fifth conductive structure is formed, and each fifth conductive structure is electrically connected to the corresponding second epitaxial layer.

17. The method for forming a semiconductor structure according to claim 16, characterized in that, The step of forming at least one fourth conductive structure includes: forming a seventh trench, the seventh trench exposing at least a portion of the sidewall of a first epitaxial layer electrically connected to the fourth conductive structure; forming a first insulating layer on the sidewall of the seventh trench; forming a fourth conductive plug at least in the remaining space of the seventh trench, the fourth conductive plug being electrically connected to the first epitaxial layer, the fourth conductive plug and the first insulating layer serving as the fourth conductive structure; The step of forming at least one fifth conductive structure includes: forming an eighth trench, the eighth trench exposing at least a portion of the sidewall of a second epitaxial layer electrically connected to the second conductive structure; forming a second insulating layer on the sidewall of the eighth trench; forming a fifth conductive plug at least in the remaining space of the eighth trench, the fifth conductive plug being electrically connected to the second epitaxial layer, the fifth conductive plug and the second insulating layer serving as the fifth conductive structure.

18. The method for forming a semiconductor structure according to claim 16, characterized in that, Meet at least one or more of the following conditions: A first metal lead is formed, which is electrically connected to the first and second conductive structures of the current stacked device, as well as the fourth and fifth conductive structures of another stacked device. A second metal lead is formed, which is electrically connected to the first and second conductive structures of another stacked device, as well as the fourth and fifth conductive structures of the current stacked device. A third metal lead is formed, which is electrically connected to the fourth and fifth conductive structures of the current stacked device, and the fourth and fifth conductive structures of another stacked device, respectively. A fourth metal lead is formed, which is electrically connected to the fourth and fifth conductive structures of the current stacked device, and the fourth and fifth conductive structures of another stacked device, respectively. A fifth metal lead is formed, which is electrically connected to the current stacked device and the third conductive structure of another stacked device, respectively. A sixth metal lead is formed, which is electrically connected to the fifth conductive structure of the current stacked device; A seventh metal lead is formed, which is electrically connected to the fifth conductive structure of another stacked device.

19. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of forming discrete stacked devices on the substrate, a second isolation structure is also formed, the second isolation structure being located between adjacent stacked devices.

20. A semiconductor structure, characterized in that, include: Base; Discrete stacked devices are located on the substrate, and each stacked device includes a first device structure and a second device structure arranged sequentially along the normal direction of the substrate surface. The first device structure includes a first transistor, the second device structure includes a second transistor and a third transistor, and the second transistor and the third transistor share a second channel layer, which is formed epitaxially. The first transistor includes a first gate structure, the second transistor further includes a second gate structure, and the third transistor further includes a third gate structure. The second gate structure and the third gate structure are in contact with at least the sidewalls of the second channel layer. The semiconductor structure includes SRAM. The second transistor serves as a first pull-down transistor, the first transistor serves as a first pull-up transistor, and the projection of the second gate structure onto the substrate is within the projection of the first gate structure onto the substrate. The second gate structure and the first gate structure are spaced parallel to the substrate surface. This space refers to the distance between the projection of the second gate structure onto the first gate structure and the distal end of the first gate structure, where the distal end of the first gate structure is the end that does not overlap with the second gate structure. A first conductive structure extends through the second channel layer, is electrically connected to the first gate structure, and is located at the interval.

21. The semiconductor structure according to claim 20, characterized in that, The first transistor includes: a first number of first epitaxial layers sequentially disposed along the surface of the substrate, at least one epitaxial layer serving as the first channel layer of the first transistor, wherein each first epitaxial layer has its own doping type and doping concentration; and a first gate structure, which is in contact with at least the sidewall of the first channel layer. The second transistor includes: a plurality of second epitaxial layers sequentially disposed along the surface of the substrate, at least one outer first epitaxial layer serving as the second channel layer of the second transistor, wherein each second epitaxial layer has its own doping type and doping concentration; wherein the bottom second epitaxial layer is located on the top first epitaxial layer; The third transistor includes a plurality of second epitaxial layers shared with the second transistor, wherein the second channel layer of the second transistor also serves as the second channel layer of the third transistor.

22. The semiconductor structure according to claim 21, characterized in that, The first gate structure is in contact with the sidewall of the first channel layer, and the semiconductor structure further includes: The first insulating structure penetrates the first epitaxial layer below the first channel layer and contacts the sidewall of the first channel layer and the bottom of the first gate structure. The second insulating structure penetrates the first epitaxial layer above the first channel layer and contacts the sidewall of the first epitaxial layer and the surface of the first gate structure. The second gate structure is in contact with one sidewall of the second channel layer, and the third gate structure is in contact with the other sidewall of the second channel layer. The semiconductor structure further includes: A third insulating structure penetrates the second epitaxial layer below the second channel layer, and the sidewall of the second epitaxial layer is in contact with the bottom of the second gate structure; The fourth insulating structure penetrates the second epitaxial layer below the second channel layer, and the sidewall of the second epitaxial layer is in contact with the surface of the third gate structure.

23. The semiconductor structure according to claim 21, characterized in that, Also includes: The second conductive structure is electrically connected to the second gate structure; The third conductive structure is electrically connected to the third gate structure. At least one fourth conductive structure is electrically connected to the corresponding first epitaxial layer; At least one fifth conductive structure is electrically connected to the corresponding second epitaxial layer.

24. The semiconductor structure according to claim 23, characterized in that, Also includes: The first metal lead is electrically connected to the first and second conductive structures of the current stacked device, as well as the fourth and fifth conductive structures of another stacked device. A second metal lead is formed, which is electrically connected to the first and second conductive structures of another stacked device, as well as the fourth and fifth conductive structures of the current stacked device. A third metal lead is formed, which is electrically connected to the fourth and fifth conductive structures of the current stacked device, and the fourth and fifth conductive structures of another stacked device, respectively. A fourth metal lead is formed, which is electrically connected to the fourth and fifth conductive structures of the current stacked device, and the fourth and fifth conductive structures of another stacked device, respectively. A fifth metal lead is formed, which is electrically connected to the current stacked device and the third conductive structure of another stacked device, respectively. A sixth metal lead is formed, which is electrically connected to the fifth conductive structure of the current stacked device; A seventh metal lead is formed, which is electrically connected to the fifth conductive structure of another stacked device.

25. The semiconductor structure according to claim 21, characterized in that, The plurality of first epitaxial layers satisfy at least one or more of the following: a first epitaxial layer, wherein the first epitaxial layer serves as a first source / drain doped layer; a second first epitaxial layer, wherein the second first epitaxial layer serves as the first channel layer; a third first epitaxial layer, wherein the third first epitaxial layer serves as a second source / drain doped layer; wherein the first source / drain doped layer is one of the source or the drain, and the second source / drain doped layer is the other of the source or the drain; The plurality of second epitaxial layers satisfy at least one or more of the following: a first second epitaxial layer, wherein the first second epitaxial layer serves as a third source / drain doped layer; a second second epitaxial layer, wherein the second second epitaxial layer serves as a second channel layer; a third second epitaxial layer, wherein the third second epitaxial layer serves as a fourth source / drain doped layer; wherein the third source / drain doped layer is one of the source or the drain, and the fourth source / drain doped layer is the other of the source or the drain.

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