Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate; a capacitor structure including a lower electrode on the substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer; a charge insulating layer on the capacitor structure; and a wiring contact plug extending in the charge insulating layer and electrically connected to the upper electrode, where the upper electrode includes a first upper electrode layer on the capacitor dielectric layer, a second upper electrode layer on the first upper electrode layer, and a third upper electrode layer on the second upper electrode layer, where the first upper electrode layer includes a first semiconductor material, and the second upper electrode layer includes a second semiconductor material. The second upper electrode layer includes a metal group material, and the third upper electrode layer includes a second semiconductor material.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a capacitor structure. Background Art

[0002] With the rapid development of the electronics industry and the increase in user demand, electronic devices are being further miniaturized and becoming more multifunctional. Therefore, semiconductor memory devices used in electronic devices require high integration, and thus the design rules of the elements of semiconductor memory devices have been reduced. Due to this, it may be difficult to ensure the reliability of semiconductor memory devices and the difficulty level of the process is increasing. Summary of the invention

[0003] The inventive concept provides a semiconductor memory device including a capacitor structure in which reliability is ensured and the difficulty level of a process is reduced.

[0004] A semiconductor memory device according to one embodiment includes: a substrate; a capacitor structure including a lower electrode on the substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer; a charge insulating layer on the capacitor structure; and a wiring contact plug extending in the charge insulating layer and electrically connected to the upper electrode, wherein the upper electrode includes a first upper electrode layer on the capacitor dielectric layer, a second upper electrode layer on the first upper electrode layer, and a third upper electrode layer on the second upper electrode layer, and wherein the first upper electrode layer includes a first semiconductor material, the second upper electrode layer includes a metal group material, and the third upper electrode layer includes a second semiconductor material.

[0005] A semiconductor memory device according to one embodiment includes: a substrate including a memory cell area, wherein the memory cell area includes a plurality of active areas; a plurality of word lines extending in a first horizontal direction, wherein the plurality of word lines overlap with the plurality of active areas in a vertical direction; a plurality of bit lines on the plurality of active areas, wherein the plurality of bit lines extend in a second horizontal direction perpendicular to the first horizontal direction; a plurality of buried contacts, wherein each of the plurality of buried contacts contacts a corresponding one of the plurality of active areas and is in a lower portion of a space between adjacent bit lines among the plurality of bit lines; a plurality of landing pads, wherein each of the plurality of landing pads is in an upper portion of the space between the adjacent bit lines among the plurality of bit lines and overlaps with the plurality of bit lines in a vertical direction. The present invention relates to a method for manufacturing a substrate for coating a plurality of bit lines, wherein the plurality of bit lines overlap one of the adjacent bit lines among the plurality of bit lines; a plurality of capacitor structures comprising a plurality of lower electrodes electrically connected to the plurality of landing pads, respectively, a capacitor dielectric layer on the plurality of lower electrodes, and an upper electrode on the capacitor dielectric layer; and a charge insulating layer on the plurality of capacitor structures, wherein a first horizontal direction and a second horizontal direction are parallel to the lower surface of the substrate, wherein a vertical direction is perpendicular to the lower surface of the substrate, wherein the upper electrode comprises a first upper electrode layer on the capacitor dielectric layer, a second upper electrode layer on the first upper electrode layer, and a third upper electrode layer on the second upper electrode layer, wherein the first upper electrode layer comprises a semiconductor material, wherein the second upper electrode layer comprises a metal, and wherein the third upper electrode layer comprises the semiconductor material.

[0006] A semiconductor memory device according to an embodiment includes: a substrate including a memory cell region and a peripheral region, wherein the memory cell region includes a plurality of active regions, and the peripheral region includes at least one logic active region; a gate line on the at least one logic active region; a logic bit line on the gate line; a plurality of word lines extending in a first horizontal direction, wherein the plurality of word lines overlap the plurality of active regions in a vertical direction; a plurality of bit lines on the plurality of active regions, wherein the plurality of bit lines extend in a second horizontal direction perpendicular to the first horizontal direction; a plurality of buried contacts contacting the plurality of active regions, wherein one of the plurality of buried contacts is in a lower portion of a space between adjacent bit lines among the plurality of bit lines; a plurality of landing pads, wherein one of the plurality of landing pads is in an upper portion of the space between the adjacent bit lines among the plurality of bit lines and overlaps one of the adjacent bit lines among the plurality of bit lines in a vertical direction, and wherein at least a portion of each of the plurality of landing pads is at the same height in the vertical direction as the logic bit line. ; a plurality of capacitor structures, comprising a plurality of lower electrodes electrically connected to the plurality of landing pads, respectively, a capacitor dielectric layer on the plurality of lower electrodes, and an upper electrode on the capacitor dielectric layer; a charge insulation layer on the logic bit lines and the plurality of capacitor structures; a plurality of wiring lines on the charge insulation layer; a first wiring contact plug extending in the charge insulation layer, wherein a first wiring line of the plurality of wiring lines is electrically connected to the upper electrode through the first wiring contact plug; and a second wiring contact plug extending in the charge insulation layer, wherein a second wiring line of the plurality of wiring lines is electrically connected to the logic bit line through the second wiring contact plug, wherein the upper electrode comprises a first upper electrode layer on the capacitor dielectric layer, a second upper electrode layer on the first upper electrode layer, and a third upper electrode layer on the second upper electrode layer, wherein the first upper electrode layer comprises polycrystalline silicon germanium, wherein the second upper electrode layer comprises tungsten, wherein the third upper electrode layer comprises polycrystalline silicon germanium, wherein the first horizontal direction and the second horizontal direction are parallel to the lower surface of the substrate, and wherein the vertical direction is perpendicular to the lower surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram illustrating a semiconductor memory device according to an example embodiment;

[0008] Figure 2 is a schematic plan layout showing main elements of a semiconductor memory device according to an example embodiment;

[0009] FIG. 3A to FIG. 3F , 4A to 4F , FIG. 5A to FIG. 5F , 6A to 6F , 7A to 7F , FIG. 8A to FIG. 8F , 9A to 9F , FIG. 10A to FIG. 10F , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13C , FIG. 14A to FIG. 14C as well as FIG. 15A to FIG. 15C is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to example embodiments.

[0010] FIG. 16A to FIG. 16C is a cross-sectional view showing a semiconductor memory device according to an example embodiment;

[0011] FIG. 17A to FIG. 17C is an enlarged cross-sectional view of a semiconductor memory device according to an example embodiment;

[0012] Fig.18 is a cross-sectional view showing a semiconductor memory device according to an example embodiment;

[0013] Fig.19 is a plan layout diagram showing a semiconductor memory device according to an example embodiment, Fig. 20 It is along Fig.19 A cross-sectional view taken along line X1-X1' and line Y1-Y1'; and

[0014] Fig.21 is a plan layout diagram showing a semiconductor memory device according to an example embodiment, Fig. 22 is a perspective view illustrating a semiconductor memory device according to example embodiments. DETAILED DESCRIPTION

[0015] Figure 1 is a block diagram for describing a semiconductor memory device 1 according to an example embodiment.

[0016] Reference Figure 1 , the semiconductor memory device 1 may include a cell region CLR in which memory cells are arranged and a main peripheral region PRR extending around the cell region CLR (e.g., surrounding the cell region CLR in a plan view). According to an embodiment, the cell region CLR may include a sub-peripheral region SPR that divides a cell block SCB. For example, the cell blocks SCB may be spaced apart from each other (in a plan view) by the sub-peripheral regions SPR. A plurality of memory cells may be arranged in the cell block SCB. Here, the cell block SCB may represent an area in which memory cells are uniformly spaced and regularly arranged, and the cell block SCB may be referred to as a sub-cell block.

[0017] A logic unit for inputting an electrical signal to a memory cell or outputting an electrical signal from a memory cell may be provided in the main peripheral region PRR and the sub-peripheral region SPR. In some embodiments, the main peripheral region PRR may include (or may be referred to as) a peripheral circuit region, and the sub-peripheral region SPR may include (or may be referred to as) a core circuit region. The peripheral region PR may include the main peripheral region PRR and the sub-peripheral region SPR. That is, the peripheral region PR may include a peripheral circuit region and a core circuit region. In some embodiments, at least a portion of the sub-peripheral region SPR may be provided only to divide the space of the cell block SCB (without the core circuit region).

[0018] Figure 2 is a schematic plan layout showing main elements of a semiconductor memory device 1 according to an example embodiment.

[0019] Reference Figure 2 , the semiconductor memory device 1 may include a memory cell region CR and a peripheral region PR. The semiconductor memory device 1 may include a plurality of active regions ACT formed in the memory cell region CR and a plurality of logic active regions ACTP formed in the peripheral region PR. The memory cell region CR may be Figure 1 A cell block SCB is shown in which a plurality of memory cells are arranged.

[0020] In some embodiments, the plurality of active regions ACT disposed in the memory cell region CR may be disposed to have a long axis in a diagonal direction relative to a first horizontal direction (e.g., an X direction) and a second horizontal direction (e.g., a Y direction). The first horizontal direction and the second horizontal direction may be parallel to a main surface (e.g., an upper surface or a lower surface) of a substrate 110 to be described later. The first horizontal direction and the second horizontal direction may intersect with each other. For example, the first horizontal direction and the second horizontal direction may be orthogonal to each other.

[0021] A plurality of word lines WL may extend in parallel in a first horizontal direction (e.g., X direction) across the plurality of active regions ACT (overlapping the plurality of active regions ACT in a third direction (e.g., vertical direction or Z direction)) in the memory cell region CR. A plurality of bit lines BL may extend in parallel in a second horizontal direction (e.g., Y direction) on the plurality of word lines WL (overlapping the plurality of word lines WL). The plurality of bit lines BL may be DC-connected (e.g., electrically connected) to the plurality of active regions ACT through a plurality of direct contacts. It will be understood that when an element or layer is referred to as being "coupled to," "connected to," "responsive to," or "on" another element or layer, it may be directly on, directly connected to, or coupled to another element or layer, or one or more intervening elements or layers may exist. Conversely, when an element is referred to as being "directly coupled," "directly connected," "directly responsive to," or "directly on" another element, there is no intervening element. In addition, "electrically connected" conceptually includes physical connection and physical disconnection. As used herein, “element A overlaps element B in direction X” (or similar language) means that there is at least one line that extends in direction X and intersects both elements A and B.

[0022] In some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. In some embodiments, the plurality of buried contacts BC may be arranged in a row (or in a column) in each of a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction).

[0023] A plurality of landing pads LP may be formed on the plurality of buried contacts BC. Each of the plurality of landing pads LP may be disposed to overlap at least a portion of a corresponding buried contact BC among the plurality of buried contacts BC (e.g., overlap in a third direction). In some embodiments, each of the plurality of landing pads LP may extend up to an upper portion of one of two adjacent bit lines BL.

[0024] A plurality of storage nodes SN may be formed on the plurality of landing pads LP. The plurality of storage nodes SN may be formed on the plurality of bit lines BL. The plurality of storage nodes SN may be lower electrodes of a plurality of capacitors, respectively. The storage nodes SN may be connected (eg, electrically connected) to the active region ACT through the landing pad LP and the buried contact BC.

[0025] In the peripheral region PR, a plurality of gate line patterns GLP may be disposed on the logic active region ACTP. Figure 2, the plurality of gate line patterns GLP are shown to extend in parallel in a first horizontal direction (e.g., X direction) on the logic active region ACTP and have a certain width in a second horizontal direction (e.g., Y direction), but the inventive concept is not limited thereto. For example, the plurality of gate line patterns GLP may have various widths or may vary in width, and further, may have a bent portion or may extend in various directions.

[0026] exist Figure 2 In the figure, for the convenience of illustration, other elements except the plurality of logic active regions ACTP and the plurality of gate line patterns GLP are omitted in the peripheral region PR. Figure 2 , it is shown that the plurality of gate line patterns GLP are only disposed on the plurality of logic active regions ACTP, but the present invention is not limited thereto. For example, at least some of the plurality of gate line patterns GLP may extend to the outside of the logic active region ACTP, that is, the logic device isolation layer ( Figure 3E and Figure 3F 115). As used hereinafter, the terms “external / outside / outside configuration,” “external / outside / outside device,” “external / outside / outside power,” “external / outside / outside signal,” or “external” are intended to broadly refer to devices, circuits, blocks, modules, power, and / or signals that reside externally (e.g., outside the functional or physical boundaries) relative to a given circuit, block, module, system, or device.

[0027] The plurality of gate line patterns GLP may be formed at the same level as the plurality of bit lines BL. Here, the horizontal, vertical level or height of an element may refer to the distance from the main surface (e.g., upper surface or lower surface) of the substrate 110 to the element in a third direction (e.g., Z direction). The third direction may be orthogonal to the first horizontal direction and the second horizontal direction. The third direction may be perpendicular to the upper surface (or lower surface) of the substrate 110. For example, if element A is higher than element B, this may mean that element A is disposed farther from the upper surface of the substrate 110 than element B in the Z direction. In some embodiments, the plurality of gate line patterns GLP and the plurality of bit lines BL may include the same material, or at least part of them may include the same material. For example, the process of forming all or some of the plurality of gate line patterns GLP may be the same as the process of forming all or some of the plurality of bit lines BL. In some embodiments, the plurality of gate line patterns GLP and the plurality of bit lines BL may be formed simultaneously by the same process or by a series of processes.

[0028] FIG. 3A to FIG. 3F , 4A to 4F , FIG. 5A to FIG. 5F , 6A to 6F , 7A to 7F , FIG. 8A to FIG. 8F, 9A to 9F , FIG. 10A to FIG. 10F , FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13C , FIG. 14A to FIG. 14C as well as FIG. 15A to FIG. 15C is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an example embodiment, FIG. 16A to FIG. 16C is a cross-sectional view showing a semiconductor memory device according to an example embodiment. Specifically, Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A and Fig.16A is along the line corresponding to Figure 2 A cross-sectional view taken from the line AA′, Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B is along the line corresponding to Figure 2 A cross-sectional view taken at the position of line BB', Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C and Fig. 10C is along the line corresponding to Figure 2 The cross-sectional view is taken from the position of the line CC'. Figure 3D , Figure 4D , Figure 5D , Fig.6D , Fig.7D , Fig.8D , Fig.9D and Fig. 10D is along the line corresponding to Figure 2 A cross-sectional view taken along the line D-D', Figure 3E , Figure 4E , Figure 5E , Fig. 6E , Fig. 7E , Fig. 8E , Fig.9E , Fig. 10E , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16B is along the line corresponding to Figure 2 A cross-sectional view taken along the line EE', Figure 3F , Figure 4F , Fig. 5F , Fig. 6F , Figure 7F , Fig.8F , Fig.9F , Fig.10F , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C , Fig. 15C and Fig. 16C is along the line corresponding to Figure 2 A cross-sectional view taken along line F-F'.

[0029] Reference FIG. 3A to FIG. 3F , a device isolation trench 116T and a logic device isolation trench 115T may be formed in the substrate 110, and a device isolation layer 116 (at least partially) filling the device isolation trench 116T and a logic device isolation layer 115 (at least partially) filling the logic device isolation trench 115T may be formed on (in) the substrate 110.

[0030] In some embodiments, the substrate 110 may include, for example, silicon (Si), such as crystalline Si, polycrystalline Si and / or amorphous Si. In some embodiments, the substrate 110 may include a semiconductor element (such as germanium (Ge)) or a compound semiconductor (such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and indium phosphide (InP)). In some embodiments, the substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may include a buried oxide (BOX) layer. The substrate 110 may include a conductive region, such as an impurity-doped well and / or an impurity-doped structure. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Expressions such as "at least one of..." modify the entire column of elements when following a column of elements, rather than modifying individual elements in the list.

[0031] The device isolation layer 116 and the logic device isolation layer 115 may include, for example, an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The device isolation layer 116 may include a single layer including one insulating layer, a double layer including two insulating layers, or a multilayer including a combination of at least three insulating layers. For example, the device isolation layer 116 may include a double layer or a multilayer including oxide and nitride. However, according to one embodiment, the configuration of the device isolation layer 116 is not limited to the above description. A plurality of active regions 118 may be defined in a memory cell region ( Figure 2 In the substrate 110 in the memory cell region CR), a plurality of logic active regions 117 may be defined in the peripheral region ( Figure 2 In the substrate 110 in the peripheral region PR).

[0032] The device isolation layer 116 may be a portion of the device isolation structure defining a plurality of active regions 118, and the logic device isolation layer 115 may be a portion of the device isolation structure defining a plurality of logic active regions 117. In some embodiments, the device isolation layer 116 and the logic device isolation layer 115 may be formed together and may be referred to as a device isolation structure. The device isolation layer 116 and the logic device isolation layer 115 may not be clearly distinguished from each other in a boundary portion between the memory cell region CR and the peripheral region PR.

[0033] The active region 118 may have a relatively long island shape (in a plan view) in one dimension, which has a short axis and a long axis, such as Figure 2 The logic active region 117 may have a one-dimensional structure such as Figure 2 The logic active region ACTP is shown as a rectangular shape, but is not limited thereto and may have other planar shapes. The active region 118 may be configured (eg, may be) Figure 2 The logic active region 117 may be configured as (eg, may be) Figure 2 The logic active area ACTP in the.

[0034] A plurality of word line trenches 120T may be formed in the substrate 110. The plurality of word line trenches 120T may extend in parallel in a first horizontal direction (e.g., X direction) and may have a line shape, wherein the word line trenches 120T are arranged across the active region 118 (overlapping the active region 118 in a third direction) at equal intervals in a second horizontal direction (e.g., Y direction). In some embodiments, a step height (e.g., a hill shape in a cross-sectional view) may be formed in a lower surface of each of the plurality of word line trenches 120T.

[0035] The resulting material in which the plurality of word line trenches 120T are formed may be cleaned, and then a plurality of gate dielectric layers 122, a plurality of word lines 120, and a plurality of buried insulating layers 124 may be sequentially formed in the plurality of word line trenches 120T. The plurality of word lines 120 may be configured (eg, may be) Figure 2The plurality of word lines WL shown. The plurality of word lines 120 may extend in parallel in a first horizontal direction (e.g., X direction) and may have a linear shape, wherein word line trenches 120T are arranged across the active region 118 at equal intervals in a second horizontal direction (e.g., Y direction) (overlapping the active region 118 in a third direction). The upper surface of each of the plurality of word lines 120 may be disposed at a level lower than the upper surface of the substrate 110. For example, in the third direction, the upper surface of each of the plurality of word lines 120 may be closer to the lower surface of the substrate 110 than the upper surface of the substrate 110. The lower surface of each of the plurality of word lines 120 may have a concave-convex shape, and a saddle-shaped fin field effect transistor (FinFET) may be formed in the plurality of active regions 118. For example, the lower surface of each of the plurality of word lines 120 may include a portion protruding toward the lower surface of the substrate 110.

[0036] Each of the plurality of word lines 120 may have a stacked structure of a lower word line layer 120a and an upper word line layer 120b. For example, the lower word line layer 120a may include, for example, a metal material, a conductive metal nitride, or a combination thereof. In some embodiments, the lower word line layer 120a may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), and / or a combination thereof. For example, the upper word line layer 120b may include doped polysilicon. In some embodiments, the lower word line layer 120a may include a core layer and a barrier layer disposed between the core layer and the gate dielectric layer 122.

[0037] In some embodiments, before or after forming the plurality of word lines 120 , source and drain regions may be formed in the plurality of active regions 118 by implanting impurity ions into portions of the active regions 118 of the substrate 110 on both sides (e.g., opposite sides) of the plurality of word lines 120 .

[0038] The gate dielectric layer 122 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO), and a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film. For example, the gate dielectric layer 122 may have a dielectric constant of (approximately) 10 to (approximately) 25.

[0039] An upper surface of each of the plurality of buried insulating layers 124 may be disposed at substantially the same level as an upper surface of the substrate 110. The buried insulating layer 124 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a combination thereof.

[0040] Reference 4A to 4F, a first insulating layer pattern 112 and a second insulating layer pattern 114 which are sequentially arranged on the device isolation layer 116, the multiple active regions 118, the multiple buried insulating layers 124, the logic device isolation layer 115, and the multiple logic active regions 117 (for example, covering or overlapping them in the third direction) can be formed. For example, the stacked structure of the first insulating layer pattern 112 and the second insulating layer pattern 114 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal family dielectric film, and / or a combination thereof. The stacked structure of the first insulating layer pattern 112 and the second insulating layer pattern 114 may be referred to as an insulating layer pattern. In some embodiments, the insulating layer pattern may be formed by stacking a plurality of insulating layers including a stacked structure of the first insulating layer pattern 112 and the second insulating layer pattern 114. In some embodiments, the first insulating layer pattern 112 may include, for example, silicon oxide, and the second insulating layer pattern 114 may include, for example, silicon oxynitride. In some embodiments, the first insulating layer pattern 112 may include, for example, a non-metallic dielectric film, such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and the second insulating layer pattern 114 may include, for example, a metallic dielectric film. In some embodiments, the second insulating layer pattern 114 may be thicker (in the third direction) than the first insulating layer pattern 112. For example, the first insulating layer pattern 112 may have a thickness of (approximately) to (approximately) The second insulation layer pattern 114 may be thicker than the first insulation layer pattern 112 and may have a thickness (in the third direction) of (approximately) to (approximately) Thickness (in the third direction).

[0041] A conductive semiconductor layer 132P may be formed on the first insulation layer pattern 112 and the second insulation layer pattern 114, and then a direct contact hole 134H extending in the stacked structure of the conductive semiconductor layer 132P, the first insulation layer pattern 112, and the second insulation layer pattern 114 (e.g., passing through the stacked structure) to expose the source region of the active region 118 may be formed, and a direct contact conductive layer 134P that (at least partially) fills the direct contact hole 134H may be formed. In some embodiments, the direct contact hole 134H may extend to the inside of the active region 118, i.e., the source region. The conductive semiconductor layer 132P may include, for example, doped polysilicon. The direct contact conductive layer 134P may include, for example, doped polysilicon. In some embodiments, the direct contact conductive layer 134P may include, for example, an epitaxial silicon layer.

[0042] Reference 4A to 4F and FIG. 5A to FIG. 5F, a metal group conductive layer and an insulating cover layer may be sequentially formed on the conductive semiconductor layer 132P and the direct contact conductive layer 134P (e.g., to cover or overlap them in the third direction) and form a bit line structure 140. In some embodiments, the metal group conductive layer may be a stacked structure of a first metal group conductive layer and a second metal group conductive layer. A plurality of bit lines 147 and a plurality of insulating cover lines 148 may be formed by etching the first metal group conductive layer, the second metal group conductive layer, and the insulating cover layer, each of the plurality of bit lines 147 including a stacked structure of a first metal group conductive pattern 145 and a second metal group conductive pattern 146, each of the first metal group conductive pattern 145 and the second metal group conductive pattern 146 having a line shape, and the plurality of insulating cover lines 148 on the plurality of bit lines 147 (e.g., to cover or overlap the plurality of bit lines 147 in the third direction).

[0043] In some embodiments, the first metal group conductive pattern 145 may include, for example, titanium nitride (TiN) and / or Ti—Si—N (TSN), and the second metal group conductive pattern 146 may include, for example, W and / or tungsten silicide (WSi x ). In some embodiments, the first metal group conductive pattern 145 may perform a function of a diffusion barrier. In some embodiments, the plurality of insulating cover lines 148 may include, for example, silicon nitride.

[0044] One bit line 147 and one insulating cover line 148 on the one bit line 147 (e.g., covering or overlapping the one bit line 147 in the third direction) may configure one bit line structure 140. A plurality of bit line structures 140 (each including a bit line 147 and an insulating cover line 148 on the bit line 147 (e.g., covering or overlapping the bit line 147 in the third direction)) may extend in the second horizontal direction (Y direction). The plurality of bit lines 147 may be configured (e.g., may be) Figure 2 The plurality of bit lines BL are shown. In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132 , which is a portion of the conductive semiconductor layer 132P disposed between the second insulation layer pattern 114 and the first metal group conductive pattern 145 .

[0045] In the etching process of forming the plurality of bit lines 147, a portion of the conductive semiconductor layer 132P and a portion of the direct contact conductive layer 134P may be removed by the etching process to form the plurality of conductive semiconductor patterns 132 and the plurality of direct contact conductive patterns 134, and the portion of the conductive semiconductor layer 132P and the portion of the direct contact conductive layer 134P do not vertically overlap with the bit lines 147 (for example, do not overlap the bit lines 147 in the third direction). In this case, the stacked structure of the first insulating layer pattern 112 and the second insulating layer pattern 114 may function as an etching stop layer in the etching process of forming the plurality of bit lines 147, the plurality of conductive semiconductor patterns 132, and the plurality of direct contact conductive patterns 134. The plurality of direct contact conductive patterns 134 may be configured (for example, may be) Figure 2 The plurality of direct contacts DC as shown. The plurality of bit lines 147 may be electrically connected to the plurality of active regions 118 through the plurality of direct contact conductive patterns 134 .

[0046] Both sidewalls (e.g., opposite sidewalls in the first horizontal direction) of each of the plurality of bit line structures 140 may be covered by an insulating spacer structure 150. For example, the insulating spacer structure 150 may be on opposite sidewalls in the first horizontal direction of each of the plurality of bit line structures 140. Each of the plurality of insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may include a material having a lower dielectric constant than the dielectric constant of the material in the first insulating spacer 152 and / or the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include, for example, a nitride, and the second insulating spacer 154 may include, for example, an oxide. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include, for example, a nitride, and the second insulating spacer 154 may include, for example, a material having an etching selectivity relative to the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 include nitride, the second insulating spacer 154 may include oxide, and in this case, air spacers may be formed by removing the second insulating spacer 154 in a subsequent process.

[0047] Each of the plurality of buried contact holes 170H may be formed between two adjacent bit lines 147 among the plurality of bit lines 147. An inner space of each of the plurality of buried contact holes 170H may be defined by the active region 118 and the insulating spacer structure 150 on a sidewall of each of the two adjacent bit lines 147 between the two adjacent bit lines 147 (e.g., covering or overlapping a sidewall of each of the two adjacent bit lines 147 in a first horizontal direction). For example, each buried contact hole 170H may expose at least a portion of the active region 118 and a portion of the insulating spacer structure 150 between two adjacent bit lines 147 among the plurality of bit lines 147.

[0048] The multiple buried contact holes 170H can be formed by using an insulating spacer structure 150 on two side walls (e.g., opposite side walls in the first horizontal direction) of each of the multiple bit line structures 140 (e.g., covering or overlapping two side walls of each of the multiple bit line structures 140 in the first horizontal direction) as an etching mask to remove a portion of each of the active area 118 and the stacked structure of the first insulation layer pattern 112 and the second insulation layer pattern 114. In some embodiments, an anisotropic etching process can be first performed to remove a portion of the active area 118 and each of the stacked structures of the first insulation layer pattern 112 and the second insulation layer pattern 114 by using the insulating spacer structure 150 on both side walls (e.g., opposite side walls in the first horizontal direction) of each of the multiple bit line structures 140 (e.g., covering or overlapping both side walls of each bit line structure in the first horizontal direction) as an etching mask, and then an isotropic etching process can be performed to further remove another portion of the active area 118, thereby forming the multiple buried contact holes 170H, so that the space defined by the active area 118 is expanded.

[0049] A plurality of gate line structures 140P may be formed in the logic active region 117. In some embodiments, at least one dummy bit line structure 140D may be disposed between the bit line structure 140 and the gate line structure 140P.

[0050] The gate line structure 140P may include a gate line 147P and an insulating cover line 148 on the gate line 147P (e.g., covering or overlapping the gate line 147P in the third direction). The plurality of gate lines 147P included in the plurality of gate line structures 140P may be formed together with the plurality of bit lines 147. That is, the gate line 147P may have a stacked structure of a first metal family conductive pattern 145 and a second metal family conductive pattern 146. The gate insulating layer pattern 142 may be disposed between the gate line 147P and the logic active region 117. In some embodiments, the gate line structure 140P may further include a conductive semiconductor pattern 132 disposed between the gate insulating layer pattern 142 and the first metal family conductive pattern 145. The plurality of gate lines 147P may be configured (e.g., may be) Figure 2 The plurality of gate line patterns GLP are shown.

[0051] The sidewalls of the gate line structure 140P may be covered by the gate insulating spacer 150P. The gate insulating spacer 150P may be on the sidewalls of the gate line structure 140P. The gate insulating spacer 150P may include, for example, nitride. In some embodiments, the gate insulating spacer 150P may include a single layer, but is not limited thereto, and may include a plurality of stacked structures of two or more layers. For example, similar to the insulating spacer structure 150, the gate insulating spacer 150P may include a stacked structure of at least three layers.

[0052] The dummy bit line structure 140D may extend in parallel with the bit line structure 140 in the second horizontal direction (Y direction). The dummy bit line structure 140D may have a structure similar to the bit line structure 140. The dummy bit line structure 140D may include a dummy bit line 147D (including a first metal family conductive pattern 145 and a second metal family conductive pattern 146) and an insulating cover line 148 on the dummy bit line 147D (e.g., covering or overlapping the dummy bit line 147D in the third direction). The sidewall of the dummy bit line structure 140D may be covered by at least one of the insulating spacer structure 150 and the gate insulating spacer 150P.

[0053] In some embodiments, the width of the dummy bit line 147D in the first horizontal direction (e.g., X direction) may have a value greater than the value of the width of the bit line 147 (in the first horizontal direction). In some embodiments, the width of the dummy bit line 147D in the first horizontal direction (e.g., X direction) may have the same value as the value of the width of the bit line 147 (in the first horizontal direction). In some embodiments, the dummy bit line structure 140D may be provided in plurality, the width of the dummy bit line 147D of some of the plurality of dummy bit line structures 140D in the first horizontal direction (e.g., X direction) may have a value greater than the value of the width of the bit line 147 (in the first horizontal direction), and the width of the dummy bit line 147D of other of the plurality of dummy bit line structures 140D in the first horizontal direction (e.g., X direction) may have the same value as the value of the width of the bit line 147 (in the first horizontal direction).

[0054] Reference 6A to 6F , a plurality of buried contacts 170 and a plurality of insulating fences 180 may be formed on every two adjacent sidewalls (e.g., opposite sidewalls in the first horizontal direction) of the plurality of bit line structures 140 (e.g., covering or overlapping every two adjacent sidewalls of the plurality of bit line structures 140 in the first horizontal direction) in the space between the plurality of insulating spacer structures 150 (a pair of insulating spacer structures 150 facing each other). The plurality of buried contacts 170 and the plurality of insulating fences 180 may be alternately arranged in the second horizontal direction (e.g., the Y direction). For example, the plurality of buried contacts 170 may include polysilicon. For example, the plurality of insulating fences 180 may include nitride.

[0055] In some embodiments, the plurality of buried contacts 170 may be arranged in a row in each of a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction). Each of the plurality of buried contacts 170 may extend from the active region 118 in a third direction (e.g., vertical direction or Z direction). The plurality of buried contacts 170 may be configured (e.g., may be) Figure 2 The plurality of buried contacts BC are shown.

[0056] The plurality of buried contacts 170 may be disposed in a space defined by the plurality of insulating spacer structures 150 (e.g., a space between adjacent insulating spacer structures 150 among the plurality of insulating spacer structures 150) on every two adjacent sidewalls (e.g., opposite sidewalls in the first horizontal direction) of the plurality of insulating fences 180 and the plurality of bit line structures 140 (e.g., covering or overlapping the every two adjacent sidewalls in the first horizontal direction). The plurality of buried contacts 170 may (at least) fill a portion of a lower side of the space between the plurality of insulating spacer structures 150 on every two adjacent sidewalls (e.g., opposite sidewalls in the first horizontal direction) of the plurality of bit line structures 140 (e.g., covering or overlapping the every two adjacent sidewalls in the first horizontal direction).

[0057] The level of the upper surface of each of the plurality of buried contacts 170 may be set lower than the level of the upper surface of each of the plurality of insulating cover lines 148. The upper surface of each of the plurality of insulating fences 180 and the upper surface of each of the plurality of insulating cover lines 148 may be set at the same level in a third (or vertical) direction (e.g., Z direction).

[0058] The plurality of landing pad holes 190H may be defined by the plurality of insulating spacer structures 150 and the plurality of insulating fences 180. The plurality of buried contacts 170 may be exposed at (by) lower surfaces of the plurality of landing pad holes 190H. For example, the landing pad holes 190H may be formed to expose upper surfaces of the buried contacts 170, sidewalls of the insulating fences 180, and sidewalls of the insulating spacer structures 150.

[0059] A stacked structure of a first interlayer insulating layer 172 and a second interlayer insulating layer 174 may be formed on a stacked structure of a first insulating layer pattern 112 and a second insulating layer pattern 114 at the periphery of the plurality of gate line structures 140P (or near the plurality of gate line structures 140P). In some embodiments, the first interlayer insulating layer 172 may include, for example, an oxide, and the second interlayer insulating layer 174 may include, for example, a nitride. An upper surface of the second interlayer insulating layer 174 and an upper surface of the gate line structure 140P may have the same level. The stacked structure of the first interlayer insulating layer 172 and the second interlayer insulating layer 174 may be referred to as an interlayer insulating layer.

[0060] In the process of forming the multiple buried contacts 170 and the multiple insulating fences 180, a portion of the upper side of each of the insulating cover line 148, the gate insulating spacer 150P and the insulating spacer structure 150 included in the bit line structure 140, the dummy bit line structure 140D and the gate line structure 140P can be removed, and thus, the level of the upper surface of each of the bit line structure 140, the dummy bit line structure 140D and the gate line structure 140P can be lowered.

[0061] Reference 7A to 7F , a word line contact hole CPHE and a logic active area contact hole CPHF may be formed, each of which extends in (e.g., passes through) the second interlayer insulating layer 174, the first interlayer insulating layer 172, the second insulating layer pattern 114, and the first insulating layer pattern 112. The word line contact hole CPHE and the logic active area contact hole CPHF may be referred to as a plurality of contact holes. The word line contact hole CPHE and the logic active area contact hole CPHF may be referred to as a first contact hole and a second contact hole.

[0062] The word line contact hole CPHE may extend in (e.g., pass through) the second interlayer insulating layer 174, the first interlayer insulating layer 172, the second insulating layer pattern 114, the first insulating layer pattern 112, the buried insulating layer 124, and the upper word line layer 120b, and may extend until the lower word line layer 120a. In some embodiments, the word line contact hole CPHE may extend to the inside of the lower word line layer 120a. For example, the word line contact hole CPHE may extend in a portion (e.g., an upper portion) of the lower word line layer 120a.

[0063] The logic active area contact hole CPHF may extend in (e.g., pass through) the second interlayer insulating layer 174, the first interlayer insulating layer 172, the second insulating layer pattern 114, and the first insulating layer pattern 112, and may extend up to the logic active area 117. In some embodiments, the logic active area contact hole CPHF may extend to the inside of the logic active area 117. For example, the logic active area contact hole CPHF may extend in a portion (e.g., an upper portion) of the logic active area 117.

[0064] Reference FIG. 8A to FIG. 8F , a landing pad material layer 190P can be formed, the landing pad material layer 190P (at least partially) fills the multiple landing pad holes 190H, the word line contact holes CPHE and the logic active area contact holes CPHF and is on the multiple bit line structures 140, the multiple gate line structures 140P and (at least one) dummy bit line structure 140D (for example, covering or overlapping them in a third direction).

[0065] In some embodiments, an interface of the buried contact 170 contacting the landing pad material layer 190P may be higher than a first vertical level LV1 of an upper surface of the second metal group conductive pattern 146 and may be lower than a second vertical level LV2 of an upper surface of the insulating cover line 148 .

[0066] In some embodiments, the landing pad material layer 190P may include a conductive barrier layer and a conductive pad material layer on the conductive barrier layer. For example, the conductive barrier layer may include a metal, a conductive metal nitride, and / or a combination thereof. In some embodiments, the conductive barrier layer may have, for example, a Ti / TiN stacked structure. In some embodiments, the conductive pad material layer may include, for example, tungsten (W).

[0067] In some embodiments, before forming the landing pad material layer 190P, a metal silicide layer may be formed on the plurality of buried contacts 170. The metal silicide layer may be disposed between the landing pad material layer 190P and the plurality of buried contacts 170. The metal silicide layer may include, for example, cobalt silicide (CoSi x ), nickel silicide (NiSi x ) and / or manganese silicide (MnSi x ), but is not limited thereto.

[0068] The unit hard mask pattern HMKC and the logic hard mask pattern HMKP may be formed on the landing pad material layer 190P. In some embodiments, the unit hard mask pattern HMKC and the logic hard mask pattern HMKP may be formed by an extreme ultraviolet (EUV) lithography process, but is not limited thereto. The unit hard mask pattern HMKC and the logic hard mask pattern HMKP may be referred to as a plurality of hard mask patterns.

[0069] Reference 9A to 9F Combined with FIG. 8A to FIG. 8F , a portion of the landing pad material layer 190P may be removed by using the cell hard mask pattern HMKC and the logic hard mask pattern HMKP as an etching mask, and thus, a plurality of landing pads 190, a plurality of logic bit lines BLP, a first contact plug CPE, and a second contact plug CPF may be formed. The plurality of landing pads 190 may fill at least a portion of the plurality of landing pad holes 190H, extend to the plurality of bit line structures 140, and may be separated from each other by the recessed portion 190R. The first contact plug CPE may (at least partially) fill the word line contact hole CPHE, and the second contact plug CPF may (at least partially) fill the logic active area contact hole CPHF.

[0070] The plurality of landing pads 190 may be spaced apart from each other with a recessed portion 190R therebetween. The plurality of landing pads 190 may be disposed on the plurality of buried contacts 170 and may extend to (toward) the plurality of bit line structures 140. In some embodiments, the plurality of landing pads 190 may extend to (toward) the plurality of bit lines 147. The plurality of landing pads 190 may be disposed on the plurality of buried contacts 170 and may be electrically connected to the plurality of buried contacts 170 corresponding to each other. The plurality of landing pads 190 may be connected (e.g., electrically connected) to the active region 118 through the plurality of buried contacts 170. The plurality of landing pads 190 may be configured (e.g., may be) Figure 2 The multiple landing pads LP are shown.

[0071] Each buried contact 170 may be disposed between two adjacent bitline structures 140, and each landing pad 190 may be on one bitline structure 140 (of the two adjacent bitline structures 140) (e.g., may extend to one bitline structure 140) from a region between two bitline structures 140 that are adjacent to each other and have the buried contact 170 therebetween. For example, each landing pad 190 may be on an upper surface of the buried contact 170 between the two adjacent bitline structures 140, a sidewall of one of the two adjacent bitline structures 140, and an upper surface of the one of the two adjacent bitline structures 140.

[0072] The logic bit line BLP may be disposed on the gate line structure 140P. For example, the logic bit line BLP may extend along the insulating cover line 148 of the gate line structure 140P and / or the stacked structure of the first interlayer insulating layer 172 and the second interlayer insulating layer 174. The logic bit line BLP may extend on the gate line 147P. The logic bit line BLP may be a portion of the landing pad material layer 190P that is higher than the second vertical level LV2. At least a portion of each of the plurality of landing pads 190 may be disposed at the same vertical level as the logic bit line BLP.

[0073] Reference FIG. 10A to FIG. 10F , a plurality of lower electrodes 210 and a capacitor dielectric layer 220 may be sequentially formed on the plurality of landing pads 190. Each of the plurality of lower electrodes 210 may be electrically connected to a corresponding landing pad 190 among the plurality of landing pads 190. The capacitor dielectric layer 220 may conformally cover a surface of each of the plurality of lower electrodes 210. For example, the capacitor dielectric layer 220 may be on the sidewall and the upper surface of the lower electrode 210. In some embodiments, the capacitor dielectric layer 220 may be formed in a certain area (e.g., a memory cell area ( Figure 2The capacitor dielectric layer 220 may be provided as a whole (e.g., a one-piece structure) in the memory cell region CR) to cover the plurality of lower electrodes 210. The one-piece structure here may refer to a structure in which there is no visible boundary between two sub-elements. In some other embodiments, the capacitor dielectric layer 220 may be formed to cover the memory cell region CR and the peripheral region ( Figure 2 The plurality of lower electrodes 210 may be configured (for example, may be) Figure 2 The multiple storage nodes SN shown.

[0074] Each of the multiple lower electrodes 210 may have a columnar shape, wherein the interior is filled to include a horizontal cross-sectional surface having a circular shape, but is not limited thereto. In some embodiments, each of the multiple lower electrodes 210 may have a cylindrical shape, wherein the lower portion is closed. In some embodiments, the multiple lower electrodes 210 may be arranged in a honeycomb shape, wherein the multiple lower electrodes 210 are arranged in a zigzag shape in a first horizontal direction (e.g., X direction) and / or a second horizontal direction (e.g., Y direction). In some other embodiments, the multiple lower electrodes 210 may be arranged in a matrix form, wherein the multiple lower electrodes 210 are arranged in a row in each of the first horizontal direction (e.g., X direction) and the second horizontal direction (e.g., Y direction). The multiple lower electrodes 210 may include, for example, impurity-doped silicon, a metal (such as tungsten or copper), or a conductive metal compound (such as titanium nitride). In some embodiments, at least one support pattern contacting the sidewalls of the multiple lower electrodes 210 may be further formed. For example, multiple support patterns contacting the sidewalls of the multiple lower electrodes 210 and arranged at different vertical levels may be further formed.

[0075] The capacitor dielectric layer 220 may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0076] Before forming the plurality of lower electrodes 210, an insulating structure 195 that fills (at least partially) the recessed portion 190R may be formed. In some embodiments, the insulating structure 195 may have a stack structure of oxide and nitride. Fig. 10A and Fig. 10C , it is shown that the upper surface of the insulating structure 195 and the lower surface of the lower electrode 210 are disposed at the same level, but the inventive concept is not limited thereto.

[0077] Before forming the lower electrode 210 and the capacitor dielectric layer 220, a logic cover layer 160 may be formed on the plurality of logic bit lines BLP (e.g., covering or overlapping the plurality of logic bit lines BLP in the first horizontal direction and / or the third direction). The logic cover layer 160 may include, for example, silicon oxide and / or silicon nitride. In some embodiments, the logic cover layer 160 may be formed on the upper surface of each of the plurality of logic bit lines BLP (e.g., to cover or overlap the upper surface of each of the plurality of logic bit lines BLP in the third direction). In some other embodiments, the logic cover layer 160 may be (at least partially) formed to fill the space between every two adjacent logic bit lines BLP among the plurality of logic bit lines BLP and not on the upper surface of each of the plurality of logic bit lines BLP (e.g., not covering the upper surface of each of the plurality of logic bit lines BLP in the third direction).

[0078] Reference FIG. 11A to FIG. 11C , a first upper electrode material layer 232P may be formed on (e.g., covering or overlapping) the capacitor dielectric layer 220 and the logic cover layer 160. The first upper electrode material layer 232P may include, for example, a semiconductor material. In some embodiments, the first upper electrode material layer 232P may include, for example, polycrystalline silicon germanium (SiGe) and / or silicon. For example, the first upper electrode material layer 232P may include doped SiGe and / or doped polycrystalline silicon. The first upper electrode material layer 232P may be formed to fill all spaces between the plurality of lower electrodes 210. For example, the first upper electrode material layer 232P may be formed to have (approximately) 100% carbon dioxide from the uppermost end of the capacitor dielectric layer 220. to (approximately) Thickness.

[0079] The second upper electrode material layer 234P may be formed on the first upper electrode material layer 232P. The second upper electrode material layer 234P may include a metal family material. For example, the second upper electrode material layer 234P may include a metal. In some embodiments, the second upper electrode material layer 234P may include, for example, tungsten. In some embodiments, the second upper electrode material layer 234P may include, for example, a stacked structure of a conductive barrier layer and a metal material layer on (e.g., covering or overlapping) the conductive barrier layer. The conductive barrier layer may include, for example, a metal (such as Ti or Ta) and / or a conductive metal nitride (such as TiN, TaN, or WN). The metal material layer may include, for example, tungsten. For example, the second upper electrode material layer 234P may be formed to have (approximately) to (approximately) In some embodiments, the second upper electrode material layer 234P may include a stacked structure of a metal family material and an interface layer, the interface layer including, for example, a metal oxide, a metal nitride, a metal carbide, and / or a metal silicide. In some embodiments, the interface layer included in the second upper electrode material layer 234P may be formed to have a thickness of (approximately) to (approximately) thickness (e.g., in a third direction).

[0080] The third upper electrode material layer 236P may be formed on the second upper electrode material layer 234P. The third upper electrode material layer 236P may include, for example, a semiconductor material. In some embodiments, the third upper electrode material layer 236P may include, for example, SiGe and / or silicon. For example, the third upper electrode material layer 236P may include doped SiGe and / or doped polysilicon. For example, the third upper electrode material layer 236P may be formed to have (approximately) to (approximately) In some embodiments, the third upper electrode material layer 236P may include the same material as the first upper electrode material layer 232P. For example, the first upper electrode material layer 232P and the third upper electrode material layer 236P may include SiGe.

[0081] Reference FIG. 12A to FIG. 12C Combined with FIG. 11A to FIG. 11C , a unit mask layer may be formed on a portion of the third upper electrode material layer 236P (e.g., covering or overlapping a portion of the third upper electrode material layer 236P in the third direction), and then the third upper electrode layer 236, the second upper electrode layer 234, and the first upper electrode layer 232 may be formed by using the unit mask layer as an etching mask from a portion of each of the third upper electrode material layer 236P, the second upper electrode material layer 234P, and the first upper electrode material layer 232P. The first upper electrode layer 232, the second upper electrode layer 234, and the third upper electrode layer 236 may constitute an upper electrode 230. The plurality of lower electrodes 210, the capacitor dielectric layer 220, and the upper electrode 230 may configure a plurality of capacitor structures 200.

[0082] The unit mask layer may include, for example, a resist material, or may have a stacked structure of a hard mask material and a resist material. The unit mask layer may be formed in the memory cell region ( Figure 2 CR) (e.g., covering or overlapping the memory cell region in the third direction), and may not be in the peripheral region ( Figure 2 The plurality of capacitor structures 200 may be formed, and then the unit mask layer may be removed. The capacitor structure 200 may not be formed in the peripheral region ( Figure 2 PR), and the logic cover layer 160 can be exposed.

[0083] Reference FIG. 13A to FIG. 13C , a buried insulating material layer 262P may be formed on the plurality of capacitor structures 200 and the logic cover layer 160 (e.g., covering or overlapping the plurality of capacitor structures 200 and the logic cover layer 160 in the first horizontal direction and / or the third direction). The buried insulating material layer 262P may include, for example, silicon oxide. The buried insulating material layer 262P may be formed to have a sufficient thickness to cover (or overlap in the first horizontal direction and / or the third direction) all of the plurality of capacitor structures 200. For example, the buried insulating material layer 262P may be formed to include an upper surface at a level higher than the uppermost end of the upper electrode 230.

[0084] Reference FIG. 14A to FIG. 14C Combined with FIG. 13A to FIG. 13C , the buried insulating layer 262 may be formed by removing a portion of the upper side of the buried insulating material layer 262P. The buried insulating layer 262 may be formed by removing a portion of the buried insulating material layer 262P at a level higher than the uppermost end of the upper electrode 230 (e.g., the upper end of the third upper electrode layer 236). For example, by performing a chemical mechanical polishing (CMP) process using the third upper electrode layer 236 as a process stopper, a portion of the upper side of the buried insulating material layer 262P may be removed, and thus the buried insulating layer 262 may be formed. The buried insulating layer 262 may contact the upper electrode 230. For example, a side surface of the buried insulating layer 262 may directly contact each of the first upper electrode layer 232, the second upper electrode layer 234, and the third upper electrode layer 236. The upper surface of the buried insulating layer 262 and the uppermost surface of the upper electrode 230 (i.e., the upper surface of the buried insulating layer 262 and the uppermost surface of the third upper electrode layer 236) may be disposed at the same vertical level to configure a coplanar surface.

[0085] Reference FIG. 15A to FIG. 15C, a covering insulating layer 264 may be formed on the buried insulating layer 262 and the upper electrode 230 (e.g., covering or overlapping the buried insulating layer 262 and the upper electrode 230 in the third direction). The lower surface of the covering insulating layer 264 may directly contact the upper surface of the upper electrode 230 (e.g., the upper surface of the third upper electrode layer 236) and the upper surface of the buried insulating layer 262. The buried insulating layer 262 and the covering insulating layer 264 may configure the charge insulating layer 260. The portion of the charge insulating layer 260 below the uppermost end of the upper electrode 230 (i.e., the uppermost end of the third upper electrode layer 236) may be the buried insulating layer 262, and the portion of the charge insulating layer 260 on the uppermost end of the upper electrode 230 may be the covering insulating layer 264. The covering insulating layer 264 may include, for example, silicon oxide. In some embodiments, the buried insulating layer 262 and the covering insulating layer 264 may include the same material. The buried insulating layer 262 and the capping insulating layer 264 may include, for example, an oxide film and / or an ultra low K (ULK) film. The oxide film may include, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS) and / or a high density plasma (HDP) film. The ULK film may include, for example, a SiOC film and / or a SiCOH film each having a dielectric constant of (approximately) 2.2 to (approximately) 2.4.

[0086] Reference FIG. 16A to FIG. 16C , by removing a portion of the charge insulating layer 260, a plurality of wiring contact holes including a first wiring contact hole MCH1 and a second wiring contact hole MCH2 may be formed. The upper electrode 230 may be exposed at a lower surface of the first wiring contact hole MCH1 (by the lower surface of the first wiring contact hole MCH1). The first wiring contact hole MCH1 may extend in the cover insulating layer 264 (e.g., through the cover insulating layer 264) and may extend in the upper electrode 230 (e.g., extend until the upper electrode 230). In some embodiments, the first wiring contact hole MCH1 may extend to the inside of the upper electrode 230. For example, the first wiring contact hole MCH1 may extend in a portion (e.g., an upper portion) of the upper electrode 230 (e.g., the third upper electrode layer 236). The third upper electrode layer 236 may be exposed at a lower surface of the first wiring contact hole MCH1 (by the lower surface of the first wiring contact hole MCH1). In some embodiments, the first wiring contact hole MCH1 may extend to the inside of the third upper electrode layer 236. For example, the first wiring contact hole MCH1 may pass through the charge insulating layer 260 and may extend to the inside of the third upper electrode layer 236, but may not extend up to the second upper electrode layer 234. The vertical level of the lower surface of the first wiring contact hole MCH1 may be set at a vertical level lower than the uppermost end of the third upper electrode layer 236 and higher than the uppermost end of the second upper electrode layer 234.

[0087] The logic bit line BLP may be exposed at (by) the lower surface of the second wiring contact hole MCH2. The second wiring contact hole MCH2 may extend in (e.g., through) the charge insulation layer 260 and the logic cover layer 160, and may extend in (e.g., until the logic bit line BLP). For example, the second wiring contact hole MCH2 may extend in a portion (e.g., an upper portion) of the logic bit line BLP. In some embodiments, the second wiring contact hole MCH2 may extend to the inside of the logic bit line BLP.

[0088] A plurality of wiring contact plugs including a first wiring contact plug MC1 (at least partially) filling the first wiring contact hole MCH1 and a second wiring contact plug MC2 (at least partially) filling the second wiring contact hole MCH2 may be formed.

[0089] The first wiring contact plug MC1 may contact the third upper electrode layer 236 and may not contact the second upper electrode layer 234. In some embodiments, the first wiring contact plug MC1 may extend to the inside of the upper electrode 230. For example, the first wiring contact plug MC1 may pass through the charge insulation layer 260 and may extend to the inside of the third upper electrode layer 236, but may not extend up to the second upper electrode layer 234. The vertical level of the lower surface of the first wiring contact plug MC1 may be set at a vertical level lower than the uppermost end of the third upper electrode layer 236 and higher than the uppermost end of the second upper electrode layer 234.

[0090] The second wiring contact plug MC2 may pass through the charge insulation layer 260 and the logic capping layer 160 and may extend up to the logic bit line BLP. In some embodiments, the second wiring contact plug MC2 may extend to the inside of the logic bit line BLP.

[0091] Each of the first wiring contact plug MC1 and the second wiring contact plug MC2 may include a wiring contact conductive layer 310, and the wiring contact conductive layer 310 may include a wiring contact barrier layer 312 and a wiring contact charge layer 314. The wiring contact barrier layer 312 may be formed on the inner surface (e.g., sidewall and lower surface) of each of the first wiring contact hole MCH1 and the second wiring contact hole MCH2 (e.g., to conformally cover the inner surface of each of the first wiring contact hole MCH1 and the second wiring contact hole MCH2), and the wiring contact charge layer 314 may be formed on the wiring contact barrier layer 312 (e.g., to cover the wiring contact barrier layer 312) and (at least partially) fill each of the first wiring contact hole MCH1 and the second wiring contact hole MCH2. For example, the wiring contact barrier layer 312 may include Ti, Ta, TiN and / or TaN. For example, the wiring contact charge layer 314 may include a metal such as W.

[0092] A plurality of wiring lines 320 connected (e.g., electrically connected) to the first wiring contact plug MC1 and the second wiring contact plug MC2 may be formed on the charge insulating layer 260 formed with the first wiring contact plug MC1 and the second wiring contact plug MC2, and thus, the semiconductor memory device 1 may be manufactured. The plurality of wiring lines 320 may include, for example, a metal such as aluminum (Al), Cu, or W.

[0093] exist FIG. 16A to FIG. 16C , along the line corresponding to Figure 2 A cross-sectional view taken along the line BB' corresponding to Figure 2 The cross-sectional view taken along the line CC' corresponding to Figure 2 The cross-sectional view taken along the line DD′ is not shown separately, but the elements below the first upper electrode layer 232 may be connected to the Fig. 10B , Fig. 10C and Fig. 10D The diagrams are basically the same, so you can refer to Fig. 10B , Fig. 10C and Fig. 10D .

[0094] The semiconductor memory device 1 may include: a substrate 110 including a plurality of active regions 118 and a plurality of logic active regions 117; a plurality of gate dielectric layers 122, a plurality of word lines 120, and a plurality of buried insulating layers 124, which are sequentially formed in the plurality of word line trenches 120T on the plurality of active regions 118 in the substrate 110 (e.g., crossing or overlapping the plurality of active regions 118 in a third direction); a stacked structure of a first insulating layer pattern 112 and a second insulating layer pattern 114, each of which is formed on the device isolation layer; The device isolation layer 116, the plurality of active regions 118 and the plurality of buried insulating layers 124 are formed on the device isolation layer 116, the plurality of active regions 118 and the plurality of buried insulating layers 124 (for example, crossing or overlapping the device isolation layer 116, the plurality of active regions 118 and the plurality of buried insulating layers 124 in a third direction); a plurality of bit line structures 140, on the stacked structure of the first insulating layer pattern 112 and the second insulating layer pattern 114; a plurality of insulating spacer structures 150, covering two sidewalls of each of the plurality of bit line structures 140; a plurality of gate line structures 140P , on the multiple logic active areas 117; multiple gate insulating spacers 150P, on two (opposite in the first horizontal direction) side walls of each gate line structure in the multiple gate line structures 140P (for example, covering or overlapping the two side walls in the first horizontal direction); multiple buried contacts 170, (at least partially) filling the lower part of the space defined by the multiple insulating fences 180 and the multiple insulating spacer structures 150 and connected (for example, electrically connected) to the multiple active areas 118; multiple landing pads 190, (at least partially) filling the upper part of the space and extending to the upper part of the bit line structure 140; multiple capacitor structures 200, each including multiple lower electrodes 210, a capacitor dielectric layer 220 and an upper electrode 230 connected (for example, electrically connected) to the multiple landing pads 190; a first wiring contact plug MC1, connected (for example, electrically connected) to the upper electrode 230; and a second wiring contact plug MC2, connected (for example, electrically connected) to the logic bit line BLP.

[0095] The upper electrode 230 may include a first upper electrode layer 232, a second upper electrode layer 234 on the first upper electrode layer 232 (e.g., covering or overlapping the first upper electrode layer 232 in the first horizontal direction and / or the third direction), and a third upper electrode layer 236 on the second upper electrode layer 234 (e.g., covering or overlapping the second upper electrode layer 234 in the first horizontal direction and / or the third direction). The first upper electrode layer 232 may be on the capacitor dielectric layer 220 (e.g., covering or overlapping the capacitor dielectric layer 220 in the first horizontal direction and the third direction), and may be disposed in the space between the plurality of lower electrodes 210 (e.g., may at least partially fill the space).

[0096] In some embodiments, the first upper electrode layer 232 may include, for example, doped polycrystalline SiGe and / or doped polycrystalline silicon. In some embodiments, the second upper electrode layer 234 may include a stacked structure of a conductive barrier layer and a metal material layer on the conductive barrier layer (e.g., covering or overlapping the conductive barrier layer). The conductive barrier layer may function as an adhesive layer that attaches the second upper electrode layer 234 to the first upper electrode layer 232. The conductive barrier layer may include, for example, Ti, TiN, Ta, and / or TaN. In some embodiments, the conductive barrier layer may include, for example, Ti. The metal material layer may include, for example, W, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba, Sr) RuO), CRO (CaRuO), BaRuO, and / or La (Sr, Co) O. In some embodiments, the metal material layer may include, for example, a metal material. In some embodiments, the metal material layer may include, for example, W. The third upper electrode layer 236 may include, for example, doped polycrystalline SiGe and / or doped polycrystalline silicon. In some embodiments, the third upper electrode layer 236 may include, for example, the same material as that of the first upper electrode layer 232. For example, the first upper electrode layer 232 and the third upper electrode layer 236 may include polycrystalline SiGe.

[0097] The semiconductor memory device 1 may further include a word line contact plug CPE and a logic active area contact plug CPF. The word line contact plug CPE may be referred to as a first contact plug CPE, and the logic active area contact plug CPF may be referred to as a second contact plug CPF. The word line contact plug CPE may extend (e.g., pass through) the second interlayer insulating layer 174, the first interlayer insulating layer 172, the second insulating layer pattern 114, the first insulating layer pattern 112, the buried insulating layer 124, and the upper word line layer 120b, and may be connected (e.g., electrically connected) to the lower word line layer 120a. For example, the word line contact plug CPE may extend in the upper portion of the lower word line layer 120a. The logic active area contact plug CPF may extend (e.g., pass through) the second interlayer insulating layer 174, the first interlayer insulating layer 172, the second insulating layer pattern 114, and the first insulating layer pattern 112, and may be connected (e.g., electrically connected) to the logic active area 117. For example, the logic active region contact plug CPF may extend in the upper portion of the logic active region 117 .

[0098] A plurality of logic bit lines BLP may be disposed on the insulating cover line 148 and the second interlayer insulating layer 174. In some embodiments, the logic bit line BLP may include a stack structure of Ti, TiN, or Ti / TiN and W.

[0099] The semiconductor memory device 1 may further include a first wiring contact hole MCH1 and a second wiring contact hole MCH2. The second wiring contact plug MC2 may have a vertical height having a value greater than that of the first wiring contact plug MC1. For example, the second wiring contact plug MC2 may have a greater height than the first wiring contact plug MC1 in a third direction (e.g., Z direction). For example, the upper surface of the first wiring contact plug MC1 and the upper surface of the second wiring contact plug MC2 may be disposed at the same vertical level, and the lower surface of the first wiring contact plug MC1 may be disposed at a vertical level higher than that of the lower surface of the second wiring contact plug MC2. The first wiring contact plug MC1 may electrically connect the wiring line 320 to the upper electrode 230. The second wiring contact plug MC2 may electrically connect the wiring line 320 to the logic bit line BLP. In some embodiments, the second wiring contact plug MC2 and the logic bit line BLP connected to the second wiring contact plug MC2 can electrically connect the wiring line 320 to the gate line 147P, connect (e.g., electrically connect) the wiring line 320 to the word line 120, or connect (e.g., electrically connect) the wiring line 320 to the logic active area 117.

[0100] The first wiring contact plug MC1 may extend in the charge insulation layer 260 (i.e., the cover insulation layer 264) (e.g., pass through the charge insulation layer 260) and may extend up to the third upper electrode layer 236. For example, the first wiring contact plug MC1 may extend to (extend in) the interior (e.g., the upper portion) of the third upper electrode layer 236. In some embodiments, the first wiring contact plug MC1 may include a lower surface disposed at a vertical level higher than the uppermost end of the second upper electrode layer 234, such that the first wiring contact plug MC1 is spaced apart from the second upper electrode layer 234 without contacting each other.

[0101] The second wiring contact plug MC2 may extend in (e.g., pass through) the charge insulation layer 260 (i.e., the capping insulation layer 264 and the buried insulation layer 262) and the logic capping layer 160, and may extend up to the logic bit line BLP. For example, the second wiring contact plug MC2 may extend to (extend in) the inside (e.g., the upper part) of the logic bit line BLP.

[0102] Reference FIG. 3A to FIG. 16CIn the semiconductor memory device 1 according to an embodiment, the buried insulating layer 262 may be formed by performing a CMP process using the third upper electrode layer 236 as a process stopper. The semiconductor memory device 1 according to an embodiment may not include a separate etching stop layer on the upper electrode 230 (e.g., covering the upper electrode 230). For example, the semiconductor memory device 1 may not include a layer including a nitride between the upper electrode 230 and the charge insulating layer 260. Therefore, in the process of forming the first wiring contact hole MCH1 and the second wiring contact hole MCH2, it may not be necessary to pass through a separate etching stop layer, and thus, the difficulty level of the process of forming the semiconductor memory device 1 may be reduced. In addition, since the difficulty level of the process is reduced, the occurrence of defects such as "non-opening" may be reduced (e.g., prevented) in the process of forming the first wiring contact hole MCH1 and the second wiring contact hole MCH2, and thus, the electrical connection reliability between the first wiring contact plug MC1 and the upper electrode 230 and the electrical connection reliability between the second wiring contact plug MC2 and the logic bit line BLP may be improved, thereby ensuring the reliability of the semiconductor memory device 1.

[0103] FIG. 17A to FIG. 17C is an enlarged cross-sectional view of a semiconductor memory device according to an example embodiment. Specifically, FIG. 17A to FIG. 17C yes Fig.16A An enlarged cross-sectional view of region XVII of FIG.

[0104] Reference Fig.17A The capacitor structure 200 may include a lower electrode 210, a capacitor dielectric layer 220, and an upper electrode 230. The upper electrode 230 may have a stack structure of a first upper electrode layer 232, a second upper electrode layer 234, and a third upper electrode layer 236.

[0105] The first upper electrode layer 232 may have a first thickness T1a in a vertical direction (e.g., a third direction or a Z direction) from the uppermost end of the capacitor dielectric layer 220. The second upper electrode layer 234 may have a second thickness T2a in a vertical direction (e.g., a third direction or a Z direction). The third upper electrode layer 236 may have a third thickness T3a in a vertical direction (e.g., a third direction or a Z direction). The second thickness T2a may have a value greater than each of the first thickness T1a and the third thickness T3a. For example, the second thickness T2a may be (approximately) to (approximately) In some embodiments, the first thickness T1a and the third thickness T3a may have (substantially) the same value. For example, each of the first thickness T1a and the third thickness T3a may be (approximately) to (approximately)

[0106] Reference Fig. 17BThe capacitor structure 200 may include a lower electrode 210, a capacitor dielectric layer 220, and an upper electrode 230. The upper electrode 230 may have a stack structure of a first upper electrode layer 232, a second upper electrode layer 234, and a third upper electrode layer 236.

[0107] The first upper electrode layer 232 may have a first thickness T1b in a vertical direction (e.g., a third direction or a Z direction) from the uppermost end of the capacitor dielectric layer 220. The second upper electrode layer 234 may have a second thickness T2b in a vertical direction (e.g., a third direction or a Z direction). The third upper electrode layer 236 may have a third thickness T3b in a vertical direction (e.g., a third direction or a Z direction). The first thickness T1b may have a value greater than the value of the third thickness T3b. The second thickness T2b may have a value greater than the value of the third thickness T3b. For example, the second thickness T2b may be (approximately) to (approximately) The first thickness T1b may have a value greater than the value of the third thickness T3b. In some embodiments, the first thickness T1b and the second thickness T2b may have (substantially) the same value. For example, the first thickness T1b may be (approximately) to (approximately) For example, the third thickness T3b may be (approximately) to (approximately)

[0108] Reference Fig. 17C The capacitor structure 200 may include a lower electrode 210, a capacitor dielectric layer 220, and an upper electrode 230. The upper electrode 230 may have a stack structure of a first upper electrode layer 232, a second upper electrode layer 234, and a third upper electrode layer 236.

[0109] The first upper electrode layer 232 may have a first thickness T1c in a vertical direction (e.g., a third direction or a Z direction) from the uppermost end of the capacitor dielectric layer 220. The second upper electrode layer 234 may have a second thickness T2c in a vertical direction (e.g., a third direction or a Z direction). The third upper electrode layer 236 may have a third thickness T3c in a vertical direction (e.g., a third direction or a Z direction). The second thickness T2c may have a value greater than that of the first thickness T1c. The first thickness T1c may have a value greater than that of the third thickness T3c. For example, the second thickness T2c may be (approximately) to (approximately) For example, the first thickness T1c may be (approximately) to (approximately) For example, the third thickness T3c may be (approximately) to (approximately)

[0110] Fig.18 is a cross-sectional view illustrating a semiconductor memory device 2 according to an example embodiment.

[0111] Reference Fig.18 , the semiconductor memory device 2 may include a first wiring contact plug MC1a filling (at least partially) the first wiring contact hole MCH1a, instead of FIG. 16A to FIG. 16C The semiconductor memory device 1 is shown with a first wiring contact plug MC1 filling (at least partially) the first wiring contact hole MCH1.

[0112] The upper electrode 230 may be exposed at (exposed by) the lower surface of the first wiring contact hole MCH1a. The first wiring contact hole MCH1a may extend in (e.g., pass through) the covering insulating layer 264 and may extend up to the upper electrode 230. In some embodiments, the first wiring contact hole MCH1a may extend to (extend in) the interior (e.g., the upper portion) of the upper electrode 230. The second upper electrode layer 234 may be exposed at (exposed by) the lower surface of the first wiring contact hole MCH1a. In some embodiments, the first wiring contact hole MCH1a may extend to (extend in) the interior (e.g., the upper portion) of the second upper electrode layer 234. For example, the first wiring contact hole MCH1a may extend in the charge insulating layer 260 (e.g., the cover insulating layer 264) and the third upper electrode layer 236 (e.g., pass through the charge insulating layer 260 and the third upper electrode layer 236), and may extend to (extend therein) the inside (e.g., the upper portion) of the second upper electrode layer 234, but may not extend to (not extend therein) the first upper electrode layer 232. The vertical level of the lower surface of the first wiring contact hole MCH1a may be set at a vertical level lower than the uppermost end of the second upper electrode layer 234 and higher than the uppermost end of the first upper electrode layer 232.

[0113] The first wiring contact plug MC1a may electrically connect the wiring line 320 to the upper electrode 230. The first wiring contact plug MC1a may extend in the charge insulation layer 260 (i.e., the cover insulation layer 264) and the third upper electrode layer 236 (e.g., pass through the charge insulation layer 260 and the third upper electrode layer 236), and may extend up to the second upper electrode layer 234 (extend in the second upper electrode layer 234). For example, the first wiring contact plug MC1a may extend to the inside (e.g., the upper portion) of the second upper electrode layer 234 (extend in the inside (e.g., the upper portion) of the second upper electrode layer 234). In some embodiments, the first wiring contact plug MC1a may include a lower surface disposed at a vertical level that is higher than the uppermost end of the first upper electrode layer 232 and lower than the uppermost end of the second upper electrode layer 234, so that the first wiring contact plug MC1a is spaced apart from the first upper electrode layer 232 without contacting each other.

[0114] Fig.19 is a layout diagram showing a semiconductor memory device 3 according to an example embodiment, Fig. 20 It is along Fig.19 A cross-sectional view taken along line X1-X1' and line Y1-Y1'.

[0115] Reference Fig.19 and Fig. 20 , the semiconductor memory device 3 may include a substrate 410, a plurality of first conductive lines 420, a channel layer 430, a gate electrode 440, a gate insulating layer 450, and a capacitor structure 480. The semiconductor memory device 3 may be a memory device including a vertical channel transistor (VCT). The VCT may have a structure in which the channel length of the channel layer 430 extends from the substrate 410 in a vertical direction (e.g., a third direction or a Z direction).

[0116] The lower insulating layer 412 may be disposed on the substrate 410, and on the lower insulating layer 412, the plurality of first conductive lines 420 may be spaced apart from each other in a first horizontal direction (e.g., X direction) and may extend in a second horizontal direction (e.g., Y direction). A plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 to fill the spaces between the plurality of first conductive lines 420. The plurality of first insulating patterns 422 may extend in a second horizontal direction (e.g., Y direction), and the upper surfaces of the plurality of first insulating patterns 422 may be disposed at the same level as the upper surfaces of the plurality of first conductive lines 420. For example, the plurality of first insulating patterns 422 and the plurality of first conductive lines 420 may be alternately arranged in a first horizontal direction (e.g., X direction). The plurality of first conductive lines 420 may be used as bit lines of the semiconductor memory device 3.

[0117] In an embodiment, the plurality of first conductive lines 420 may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, and / or a combination thereof. For example, the plurality of first conductive lines 420 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x And / or a combination thereof, but not limited thereto. Each of the plurality of first conductive lines 420 may include a single layer or multiple layers of the above-mentioned materials. In an embodiment, the plurality of first conductive lines 420 may include a two-dimensional (2D) semiconductor material, for example, the 2D semiconductor material may include graphene, carbon nanotubes and / or a combination thereof.

[0118] The channel layer 430 may be arranged in a matrix form on the plurality of first conductive lines 420, wherein the plurality of channel layers 430 are arranged spaced apart from each other in a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction). The channel layer 430 may have a first width in a first horizontal direction (e.g., X direction) and a first height in a third direction (e.g., Z direction), and the first height may be greater than the first width. For example, the first height may be (approximately) 2 to 10 times the first width, but is not limited thereto. The lower portion of the channel layer 430 may be used as a first source / drain region (not shown), the upper portion of the channel layer 430 may be used as a second source / drain region (not shown), and the portion of the channel layer 430 between the first source / drain region and the second source / drain region may be used as a channel region (not shown).

[0119] In an embodiment, the channel layer 430 may include, for example, an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Snx O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga y O and / or a combination thereof. The channel layer 430 may include a single layer or multiple layers of the oxide semiconductor. In some embodiments, the material (e.g., oxide semiconductor) included in the channel layer 430 and / or the channel layer 430 may have a band gap energy greater than the band gap energy of silicon. For example, the channel layer 430 may have a band gap energy of (approximately) 1.5eV to (approximately) 5.6eV. In some embodiments, the channel layer 430 may have a band gap energy of (approximately) 2.0eV to (approximately) 4.0eV. For example, the channel layer 430 may be polycrystalline or amorphous, but is not limited thereto. In an embodiment, the channel layer 430 may include a 2D semiconductor material, for example, the 2D semiconductor material may include graphene, carbon nanotubes and / or a combination thereof.

[0120] The gate electrode 440 may extend in a first horizontal direction (e.g., X direction) on both sidewalls (e.g., opposite sidewalls in the second horizontal direction) of the channel layer 430. The gate electrode 440 may include a first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 and a second sub-gate electrode 440P2 facing the second sidewall of the channel layer 430 (which faces the first sidewall). For example, the first sub-gate electrode 440P1 may be on the first sidewall of the channel layer 430, and the second sub-gate electrode 440P2 may be on the second sidewall of the channel layer 430. The first sidewall and the second sidewall of the channel layer 430 may be opposite to each other in the second horizontal direction (e.g., Y direction). One channel layer 430 may be disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, and thus, the semiconductor memory device 3 may have a dual-gate transistor structure. However, the present invention is not limited thereto, and the second sub-gate electrode 440P2 (or the first sub-gate electrode 440P1) may be omitted, and only the first sub-gate electrode 440P1 (or the second sub-gate electrode 440P2) facing the first side wall (or the second side wall) of the channel layer 430 may be formed, thereby realizing a single-gate transistor structure.

[0121] The gate electrode 440 may include, for example, doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, and / or a combination thereof. For example, the gate electrode 440 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x and / or combinations thereof, but are not limited thereto.

[0122] The gate insulating layer 450 may extend around the sidewalls of the channel layer 430 (eg, surround the sidewalls of the channel layer 430), and may be disposed between the channel layer 430 and the gate electrode 440 (in the second horizontal direction). Fig.19 As shown, all sidewalls of the channel layer 430 may be surrounded by the gate insulating layer 450, and a portion of the sidewall of the gate electrode 440 may contact the gate insulating layer 450. In some embodiments, the gate insulating layer 450 may extend in the extension direction of the gate electrode 440 (i.e., the first horizontal direction (e.g., the X direction)), and only two sidewalls of the sidewalls of the channel layer 430 facing the gate electrode 440 (e.g., opposite sidewalls of the channel layer 430 in the second horizontal direction) may contact the gate insulating layer 450.

[0123] In an embodiment, the gate insulating layer 450 may include, for example, a high-k dielectric film (having a dielectric constant higher than that of a silicon oxide film), a silicon oxynitride film, a silicon oxide film, and / or a combination thereof. The high-k dielectric film may include, for example, a metal oxide and / or a metal oxynitride. For example, the high-k dielectric film of the gate insulating layer 450 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 and / or combinations thereof, but are not limited thereto.

[0124] A plurality of second insulating patterns 432 may extend in a second horizontal direction (e.g., Y direction) on the plurality of first insulating patterns 422, and the channel layer 430 may be disposed between two adjacent second insulating patterns 432 among the plurality of second insulating patterns 432. In addition, a first buried layer 434 and a second buried layer 436 may be disposed in a space between two adjacent channel layers 430 between two adjacent second insulating patterns 432. The first buried layer 434 may be disposed at a lower portion of the space between the two adjacent channel layers 430, and the second buried layer 436 may be formed on the first buried layer 434 to be disposed in another portion of the space between the two adjacent channel layers 430 (e.g., at least partially fill the other portion). The upper surface of the second buried layer 436 may be disposed at the same level as the upper surface of the channel layer 430, and the second buried layer 436 may be on the upper surface of the gate electrode 440 (e.g., cover or overlap the upper surface of the gate electrode 440 in the third direction). In some embodiments, the plurality of second insulating patterns 432 may include a material layer continuous with the plurality of first insulating patterns 422, or the second buried layer 436 may include a material layer continuous with the first buried layer 434. For example, each of the plurality of second insulating patterns 432 and a corresponding one of the plurality of first insulating patterns 422 may form an integral structure. For example, the second buried layer 436 and the first buried layer 434 may form an integral structure.

[0125] The capacitor contact 460 may be disposed on the channel layer 430. The capacitor contact 460 may be disposed to overlap the channel layer 430 (in a third direction (e.g., Z direction)) and may be arranged in a matrix form, wherein a plurality of capacitor contacts 460 are arranged spaced apart from each other in a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction). The capacitor contact 460 may include, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x and / or a combination thereof, but are not limited thereto. The upper insulating layer 462 may extend around (eg, surround) the sidewalls of the capacitor contact 460 on the plurality of second insulating patterns 432 and the second buried layer 436 .

[0126] An etch stop layer 470 may be disposed on the upper insulating layer 462, and a capacitor structure 480 may be disposed on the etch stop layer 470. The capacitor structure 480 may include a lower electrode 482, a capacitor dielectric layer 484, and an upper electrode 486.

[0127] The lower electrode 482 may extend in the etch stop layer 470 (e.g., through the etch stop layer 470) and may be electrically connected to (the upper surface of) the capacitor contact 460. The lower electrode 482 may be formed in a column shape (columnar type) extending in a third direction (e.g., the Z direction), but is not limited thereto. In an embodiment, the lower electrode 482 may be disposed to overlap the capacitor contact 460 (in the third direction) and may be arranged in a matrix form, wherein a plurality of lower electrodes 482 are arranged spaced apart from each other in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). In some embodiments, a landing pad (not shown) may be further disposed between the capacitor contact 460 and the lower electrode 482, and the lower electrode 482 may be arranged in a hexagonal shape.

[0128] The lower electrode 482 and the capacitor dielectric layer 484 may be each FIG. 10A to FIG. 18 The lower electrode 210 and the capacitor dielectric layer 220 shown in FIG. 4, the upper electrode 486 may be FIG. 12A to FIG. 18 The upper electrode 230 is shown in FIG.

[0129] The upper electrode 486 may have a stacked structure of a first upper electrode layer 486a, a second upper electrode layer 486b, and a third upper electrode layer 486c. The first upper electrode layer 486a, the second upper electrode layer 486b, and the third upper electrode layer 486c may each be FIG. 12A to FIG. 18 2 and 3. The first upper electrode layer 232, the second upper electrode layer 234, and the third upper electrode layer 236 are shown in FIG. The first upper electrode layer 486a and the third upper electrode layer 486c may include, for example, a semiconductor material, and the second upper electrode layer 486b may include, for example, a metal group material. For example, the first upper electrode layer 486a and the third upper electrode layer 486c may include SiGe, and the second upper electrode layer 486b may include W.

[0130] The semiconductor memory device 3 may further include a second wiring contact plug MC2 and a Fig.16A and Fig.18 One of the first wiring contact plugs MC1 and MC1a shown in FIG.

[0131] Fig.21 is a layout diagram showing a semiconductor memory device 3a according to an example embodiment, Fig. 22 is a perspective view illustrating a semiconductor memory device 3 a according to an example embodiment.

[0132] Reference Fig.21 and Fig. 22 , the semiconductor memory device 3a may include a substrate 410A, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, and a capacitor structure 480. The semiconductor memory device 3a may be a memory device including a VCT.

[0133] A plurality of active regions AC may be defined on the substrate 410A by the first device isolation layer 412A and the second device isolation layer 414A. A channel structure 430A may be disposed in each active region AC, and the channel structure 430A may include a first active pillar 430A1 and a second active pillar 430A2 each extending in a vertical direction and a connection portion 430L connected to a lower portion of the first active pillar 430A1 and a lower portion of the second active pillar 430A2. A first source / drain region SD1 may be disposed in the connection portion 430L, and a second source / drain region SD2 may be disposed in an upper portion of each of the first active pillar 430A1 and the second active pillar 430A2. Each of the first active pillar 430A1 and the second active pillar 430A2 may configure an independent unit memory cell.

[0134] The plurality of first conductive lines 420A may extend in a direction intersecting each of the plurality of active regions AC, for example, may extend in a second horizontal direction (e.g., Y direction). One of the plurality of first conductive lines 420A may be disposed on a connection portion 430L between a first active pillar 430A1 and a second active pillar 430A2, and the first conductive line 420A may be disposed on a first source / drain region SD1. Another first conductive line 420A adjacent to the first conductive line 420A may be disposed between two (adjacent) channel structures 430A. One of the plurality of first conductive lines 420A may be used as a common bit line included in two unit memory cells, and the two unit memory cells are configured with a first active pillar 430A1 and a second active pillar 430A2 disposed at both sides (opposite sides in the first horizontal direction) of the first conductive line 420A.

[0135] One contact gate electrode 440A may be disposed between two channel structures 430A adjacent to each other along a second horizontal direction (e.g., Y direction). For example, the contact gate electrode 440A may be disposed between a first active pillar 430A1 included in one channel structure 430A and a second active pillar 430A2 of a channel structure 430A adjacent thereto, and one contact gate electrode 440A may be shared by the first active pillar 430A1 and the second active pillar 430A2 disposed on its two sidewalls (e.g., opposite sidewalls in the second horizontal direction). The gate insulating layer 450A may be disposed between the contact gate electrode 440A and the first active pillar 430A1 and between the contact gate electrode 440A and the second active pillar 430A2. The plurality of second conductive lines 442A may extend in a first horizontal direction (e.g., X direction) on the upper surface of the contact gate electrode 440A. The plurality of second conductive lines 442A may be used as word lines of the semiconductor memory device 3a.

[0136] The capacitor contact 460A may be disposed on the channel structure 430A. The capacitor contact 460A may be disposed on the second source / drain region SD2, and the capacitor structure 480 may be disposed on the capacitor contact 460A.

[0137] The capacitor structure 480 may be as described above with reference to FIG. 12A to FIG. 18 As described above, the capacitor structure 200 , the capacitor structure 480 may include FIG. 12A to FIG. 18 The upper electrode 230 is shown in FIG.

[0138] The semiconductor memory device 3a may further include a second wiring contact plug MC2 and a Fig.16A and Fig.18 One of the first wiring contact plugs MC1 and MC1a shown in FIG.

[0139] In the above, example embodiments have been described in the drawings and the specification. The embodiments have been described by using the terms described herein, but this is only used to describe the inventive concept and is not used to limit the meaning or the scope of the inventive concept defined in the appended claims. Therefore, it can be understood by those of ordinary skill in the art that various modifications and other equivalent embodiments can be implemented from the inventive concept. Therefore, the scope of the inventive concept can be limited based on the scope of the appended claims.

[0140] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

[0141] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0164494 filed in the Korean Intellectual Property Office on November 23, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: substrate; a capacitor structure comprising a lower electrode on the substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer; a charge insulating layer on the capacitor structure; as well as a wiring contact plug extending in the charge insulating layer and electrically connected to the upper electrode, wherein the upper electrode comprises a first upper electrode layer on the capacitor dielectric layer, a second upper electrode layer on the first upper electrode layer, and a third upper electrode layer on the second upper electrode layer, and The first upper electrode layer includes a first semiconductor material, the second upper electrode layer includes a metal group material, and the third upper electrode layer includes a second semiconductor material.

2. The semiconductor memory device according to claim 1, wherein the charge insulating layer comprises a buried insulating layer and a capping insulating layer on the buried insulating layer, and An upper surface of the buried insulating layer and an uppermost surface of the third upper electrode layer are coplanar with each other. 3 . The semiconductor memory device according to claim 2 , wherein a lower surface of the cover insulating layer is in contact with the uppermost surface of the third upper electrode layer. 4 . The semiconductor memory device according to claim 2 , wherein a side surface of the buried insulating layer is in contact with each of the first upper electrode layer, the second upper electrode layer, and the third upper electrode layer.

5. The semiconductor memory device according to claim 1 , wherein the first upper electrode layer has a first thickness in a vertical direction from an upper surface of the capacitor dielectric layer, the second upper electrode layer has a second thickness in the vertical direction, and the third upper electrode layer has a third thickness in the vertical direction, wherein the vertical direction is perpendicular to the lower surface of the substrate, and The third thickness is smaller than the second thickness.

6. The semiconductor memory device according to claim 1, wherein each of the first semiconductor material and the second semiconductor material comprises silicon germanium, and The metal group material includes tungsten.

7. The semiconductor memory device according to claim 1, further comprising: a wiring line on the charge insulating layer, wherein the wiring contact plug contacts the third upper electrode layer and is spaced apart from the second upper electrode layer, and The wiring line is electrically connected to the upper electrode through the wiring contact plug.

8. The semiconductor memory device according to claim 1, further comprising: a wiring line on the charge insulating layer, wherein the wiring contact plug is in contact with the second upper electrode layer and the third upper electrode layer, wherein the wiring contact plug is spaced apart from the first upper electrode layer, and The wiring line is electrically connected to the upper electrode through the wiring contact plug.

9. A semiconductor memory device comprising: A substrate including a memory cell region, wherein the memory cell region includes a plurality of active regions; a plurality of word lines extending in a first horizontal direction, wherein the plurality of word lines overlap the plurality of active regions in a vertical direction; a plurality of bit lines on the plurality of active regions, wherein the plurality of bit lines extend in a second horizontal direction perpendicular to the first horizontal direction; a plurality of buried contacts, wherein each of the plurality of buried contacts contacts a corresponding one of the plurality of active regions and is in a lower portion of a space between adjacent bit lines among the plurality of bit lines; a plurality of landing pads, wherein each of the plurality of landing pads is in an upper portion of the space between the adjacent bit lines among the plurality of bit lines and overlaps one bit line among the adjacent bit lines among the plurality of bit lines in the vertical direction; a plurality of capacitor structures including a plurality of lower electrodes electrically connected to the plurality of landing pads, respectively, a capacitor dielectric layer on the plurality of lower electrodes, and an upper electrode on the capacitor dielectric layer; as well as a charge insulating layer on the plurality of capacitor structures, wherein the first horizontal direction and the second horizontal direction are parallel to the lower surface of the substrate, wherein the vertical direction is perpendicular to the lower surface of the substrate, wherein the upper electrode comprises a first upper electrode layer on the capacitor dielectric layer, a second upper electrode layer on the first upper electrode layer, and a third upper electrode layer on the second upper electrode layer, wherein the first upper electrode layer comprises a semiconductor material, wherein the second upper electrode layer comprises metal, The third upper electrode layer comprises the semiconductor material.

10. The semiconductor memory device according to claim 9, wherein the first upper electrode layer has a first thickness in the vertical direction from the uppermost end of the capacitor dielectric layer, the second upper electrode layer has a second thickness in the vertical direction, and the third upper electrode layer has a third thickness in the vertical direction, wherein the second thickness is greater than or equal to the first thickness, and The third thickness is smaller than the second thickness.

11. The semiconductor memory device according to claim 10, wherein when the second thickness is greater than the first thickness, the third thickness is less than or equal to the first thickness, and When the second thickness is equal to the first thickness, the third thickness is less than the first thickness.

12. The semiconductor memory device according to claim 9, wherein the charge insulating layer comprises: Bury the insulation layer; and a covering insulating layer, on the buried insulating layer, wherein the buried insulating layer is arranged in the vertical direction to be lower than or equal to the uppermost end of the third upper electrode layer, wherein the cover insulating layer is arranged in the vertical direction to be higher than or equal to the uppermost end of the third upper electrode layer, and The lower surface of the cover insulating layer is in direct contact with the uppermost surface of the third upper electrode layer.

13. The semiconductor memory device according to claim 12, wherein a side surface of the buried insulating layer is in contact with each of the first upper electrode layer, the second upper electrode layer, and the third upper electrode layer, and An upper surface of the buried insulating layer contacts the lower surface of the cover insulating layer.

14. The semiconductor memory device according to claim 9, wherein the semiconductor material comprises polycrystalline silicon germanium, and The metal includes tungsten.

15. The semiconductor memory device according to claim 9, further comprising: A wiring circuit on the charge insulating layer; and a wiring contact plug extending in the charge insulating layer, wherein the wiring line is electrically connected to the upper electrode through the wiring contact plug, and The lower surface of the wiring contact plug is arranged to be higher than the uppermost end of the first upper electrode layer in the vertical direction. 16 . The semiconductor memory device according to claim 15 , wherein the lower surface of the wiring contact plug is disposed lower than an uppermost end of the second upper electrode layer in the vertical direction. 17 . The semiconductor memory device according to claim 15 , wherein the lower surface of the wiring contact plug is disposed in the vertical direction to be lower than an uppermost end of the third upper electrode layer and higher than an uppermost end of the second upper electrode layer.

18. A semiconductor memory device comprising: A substrate, comprising a memory cell region and a peripheral region, wherein the memory cell region comprises a plurality of active regions, and the peripheral region comprises at least one logic active region; a gate line on the at least one logic active area; a logic bit line on the gate line; a plurality of word lines extending in a first horizontal direction, wherein the plurality of word lines overlap the plurality of active regions in a vertical direction; a plurality of bit lines on the plurality of active regions, wherein the plurality of bit lines extend in a second horizontal direction perpendicular to the first horizontal direction; a plurality of buried contacts in contact with the plurality of active regions, wherein one buried contact among the plurality of buried contacts is in a lower portion of a space between adjacent bit lines among the plurality of bit lines; a plurality of landing pads, wherein one of the plurality of landing pads is in an upper portion of the space between the adjacent bit lines among the plurality of bit lines and overlaps with one of the adjacent bit lines among the plurality of bit lines in the vertical direction, wherein at least a portion of each of the plurality of landing pads is at the same height as the logic bit line in the vertical direction; a plurality of capacitor structures including a plurality of lower electrodes electrically connected to the plurality of landing pads, respectively, a capacitor dielectric layer on the plurality of lower electrodes, and an upper electrode on the capacitor dielectric layer; a charge insulating layer on the logic bit lines and the plurality of capacitor structures; a plurality of wiring lines on the charge insulating layer; a first wiring contact plug extending in the charge insulating layer, wherein a first wiring line among the plurality of wiring lines is electrically connected to the upper electrode through the first wiring contact plug; as well as a second wiring contact plug extending in the charge insulating layer, wherein a second wiring line among the plurality of wiring lines is electrically connected to the logic bit line through the second wiring contact plug, wherein the upper electrode comprises a first upper electrode layer on the capacitor dielectric layer, a second upper electrode layer on the first upper electrode layer, and a third upper electrode layer on the second upper electrode layer, wherein the first upper electrode layer comprises polycrystalline silicon germanium, wherein the second upper electrode layer comprises tungsten, wherein the third upper electrode layer comprises polycrystalline silicon germanium, wherein the first horizontal direction and the second horizontal direction are parallel to the lower surface of the substrate, and The vertical direction is perpendicular to the lower surface of the substrate.

19. The semiconductor memory device according to claim 18, wherein the charge insulating layer comprises a buried insulating layer and a capping insulating layer on the buried insulating layer, wherein the buried insulating layer is arranged in the vertical direction to be lower than or equal to the uppermost end of the third upper electrode layer, wherein the cover insulating layer is arranged in the vertical direction to be higher than or equal to the uppermost end of the third upper electrode layer, wherein the lower surface of the cover insulating layer contacts the uppermost surface of the third upper electrode layer and the upper surface of the buried insulating layer, wherein the upper surface of the buried insulating layer and the uppermost surface of the third upper electrode layer are coplanar with each other, and A side surface of the buried insulating layer is in contact with each of the first upper electrode layer, the second upper electrode layer, and the third upper electrode layer.

20. The semiconductor memory device according to claim 18, wherein the first upper electrode layer has a first thickness in the vertical direction from the uppermost end of the capacitor dielectric layer, the second upper electrode layer has a second thickness in the vertical direction, and the third upper electrode layer has a third thickness in the vertical direction, wherein the second thickness is greater than the first thickness, and The third thickness is smaller than the second thickness.

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