Memory device and manufacturing method thereof
By forming a multi-layered conductive layer and dielectric layer in the substrate of the memory device, adjusting the thickness and contact relationship of each layer, the problem of difficulty in balancing GIDL and SWB in the prior art is solved, and efficient data reading and low leakage current are achieved.
Patent Information
- Application Number
- CN202510175721.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-09-24
- Filing Date
- 2025-02-18
- Publication Date
- 2025-05-23
AI Technical Summary
Existing memory devices are difficult to meet the requirements of efficient data read and low leakage current when balancing gate-induced drain leakage current (GIDL) and short write back (SWB) standards.
By forming trenches in the substrate and forming a multi-layered conductive layer and dielectric layer therein, including a first conductive layer, a second conductive layer and a cover layer, and a corresponding gate dielectric layer, the thickness and contact relationship of each layer are adjusted to balance the GIDL and SWB.
It is realized that the GIDL of the memory device is reduced without increasing the operating time and the SWB standard is met, thereby improving the overall performance of the memory device.
Smart Images
Figure CN120035138A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a memory device and a method for manufacturing the same. Background Art
[0002] A dual work function word line structure is a common word line structure in a memory device. The dual work function word line structure includes two conductive layers with different work functions, and source / drain regions are formed on both sides of the conductive layer with a lower work function to reduce gate-induced drain leakage (GIDL) in the memory device. On the other hand, short write-back (SWB) is a key standard of a memory device, and means that the write-back operation is operated to be able to reach a certain amount of charge in the memory device to read data within a certain short duration. GIDL and SWB should be balanced so that the GIDL of the memory device is not too high and the memory device meets the SWB standard at the same time. Summary of the invention
[0003] Some embodiments of the present invention provide a method for forming a memory device, the method comprising: forming a groove in a substrate; forming a first dielectric layer lining the groove; forming a first conductive layer in the groove; etching back the first conductive layer to form a native oxide layer on the first conductive layer; performing an etching process to remove the native oxide layer to expose the first conductive layer and trim a portion of the first dielectric layer exposed by the first conductive layer; and forming a second conductive layer in the groove in contact with the first conductive layer.
[0004] In some embodiments, the second conductive layer is wider than the first conductive layer.
[0005] In some embodiments, after the etching process is completed, a thickness of the first dielectric layer protruding from the first conductive layer is smaller than a thickness of the first dielectric layer covered by the first conductive layer.
[0006] In some embodiments, the method further includes: etching back the second conductive layer; and forming a second dielectric layer lining the trench after forming the second conductive layer, wherein the second dielectric layer contacts the second conductive layer.
[0007] In some embodiments, the method further includes forming a capping layer in the trench after etching back the second dielectric layer.
[0008] In some embodiments, the first dielectric layer and the second dielectric layer form a gate dielectric layer, and a thickness of the gate dielectric layer along a sidewall of the second conductive layer is less than a thickness of the gate dielectric layer along a sidewall of the capping layer.
[0009] In some embodiments, the first dielectric layer and the second dielectric layer form a gate dielectric layer, and a thickness of the gate dielectric layer along a sidewall of the second conductive layer is less than a thickness of the gate dielectric layer along a sidewall of the first conductive layer.
[0010] In some embodiments, the first dielectric layer and the second dielectric layer are made of the same material.
[0011] In some embodiments, the work function value of the second conductive layer is lower than the work function value of the first conductive layer.
[0012] In some embodiments, the first conductive layer is made of metal nitride.
[0013] Some embodiments of the present invention provide a memory device, comprising a substrate, a word line structure and a gate dielectric layer. The word line structure is embedded in the substrate and comprises a first conductive layer, a second conductive layer and a cover layer, wherein the second conductive layer is located on the first conductive layer, and the cover layer is located on the second conductive layer. The gate dielectric layer is lined along the sidewall of the word line structure and comprises a first portion, a second portion and a third portion, wherein the first portion is along the sidewall of the first conductive layer, the second portion is along the sidewall of the second conductive layer, and the third portion is along the sidewall of the cover layer, wherein the thickness of the second portion of the gate dielectric layer is less than the thickness of the first portion of the gate dielectric layer.
[0014] In some embodiments, a thickness of the second portion of the gate dielectric layer is less than a thickness of the third portion of the gate dielectric layer.
[0015] In some embodiments, the thickness of the third portion of the gate dielectric layer is greater than the thickness of the first portion of the gate dielectric layer.
[0016] In some embodiments, the gate dielectric layer further includes a fourth portion between the second conductive layer and the capping layer.
[0017] In some embodiments, a thickness of the fourth portion of the gate dielectric layer is less than a thickness of the third portion of the gate dielectric layer.
[0018] In some embodiments, the first conductive layer contacts the second conductive layer.
[0019] In some embodiments, the work function value of the second conductive layer is lower than the work function value of the first conductive layer.
[0020] In some embodiments, the first conductive layer is made of metal nitride.
[0021] In some embodiments, the second conductive layer is wider than the first conductive layer.
[0022] In some embodiments, the first portion of the gate dielectric layer contacts a bottom surface of the second conductive layer.
[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The present invention may be more fully understood by reading the following detailed description of the embodiments with reference to the following drawings:
[0025] Figure 1 A circuit diagram illustrating a memory device in some embodiments of the present invention.
[0026] Figures 2 to 11 A cross-sectional view illustrating a method of manufacturing a memory device in some embodiments of the present invention. DETAILED DESCRIPTION
[0027] Some embodiments of the present invention relate to a memory device, wherein word lines of the memory device of the present invention can be controlled without coupling to reduce the operation time of the memory device. In addition, the thickness of the gate dielectric layer of the present invention can be designed to balance the gate-induced drain leakage (GIDL) and short write-back (SWB) of the memory device.
[0028] Figure 1 A circuit diagram illustrating a memory device in some embodiments of the present invention. Figure 1 , a memory device (e.g., a dynamic random access memory, DRAM) may include a plurality of memory cells MC. A typical DRAM memory cell MC combines a capacitor CA and a transistor TR, wherein the capacitor CA temporarily stores data based on the charge state of the capacitor CA. The bit line BL is electrically connected to the source / drain region of the transistor TR, and the word line structure WL is electrically connected to the gate region of the transistor TR. The capacitor CA is electrically connected to the other source / drain region of the respective transistor TR. The word line structure WL in the present invention is a dual work function word line structure. The following discussion will emphasize the manufacturing process of the transistor TR and the word line structure WL, and will not mention the manufacturing method of the bit line BL and the capacitor CA.
[0029] Figures 2 to 11 A cross-sectional view illustrating a method of manufacturing a memory device in some embodiments of the present invention. Figure 2, a substrate 100 is provided, and an isolation structure 102 is formed in the substrate 100. The substrate 100 includes a doped region 104 located at an upper portion of the substrate 100. The substrate 100 and the doped region 104 have different conductivity types. For example, if the substrate 100 is an n-type substrate, the doped region 104 is a p-type region. If the substrate 100 is a p-type substrate, the doped region 104 is an n-type region. The p-type substrate and the p-type region include a p-type dopant, such as boron, gallium, or aluminum. The n-type substrate and the n-type region include an n-type dopant, such as phosphorus, arsenic, or antimony. The doped region 104 is used as Figure 1 The source / drain region of the transistor TR in FIG. 1 and the substrate 100 are used as Figure 1 In some embodiments, the substrate 100 may be made of a semiconductor material, such as silicon. In some embodiments, the isolation structures 102 may be made of a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof. For example, each of the isolation structures 102 may include a first portion 102A of the isolation structure made of silicon oxide and a second portion 102B of the isolation structure made of silicon nitride.
[0030] Subsequently, a hard mask layer HM is formed on the substrate 100, and the substrate 100 is etched through the hard mask layer HM to form a trench T in the substrate 100. The bottom of the trench T is lower than the bottom of the doped region 104. In some embodiments, the trench T is further formed in the isolation structure 102, and the bottom of the trench T in the isolation structure 102 is lower than the bottom of the trench T in the substrate 100.
[0031] refer to Figure 3 , lining the trench T in the substrate 100 and the trench T in the isolation structure 102 to form a dielectric layer 110. The dielectric layer 110 is further formed along the top surface and sidewalls of the hard mask layer HM. In some embodiments, the dielectric layer 110 can be formed by atomic layer deposition (ALD), in situ steam generation (ISSG), or a combination thereof. In situ steam generation (ISSG) can be, for example, water vapor or hydrogen (H 2 ) and oxygen (O 2) is carried out by a combination of gases such as silicon oxide and silicon nitride to oxidize the surface of the substrate 100 to form a dielectric layer 110. In some embodiments, the dielectric layer 110 is made of silicon oxide. In some embodiments, the thickness of the dielectric layer 110 formed by ALD or the thickness of the dielectric layer 110 formed by ISSG can be adjusted to balance the GIDL and SWB of the memory device. In particular, gate-induced drain leakage (GIDL) is a tunneling leakage current generated at the overlap of the gate and the drain. On the other hand, short write-back (SWB) is a key criterion for the memory device, and means that the write-back operation is operated to be able to reach a certain amount of charge in the memory device to read data within a certain short duration. Typically, SWB is achieved at a higher GIDL. However, excessive GIDL will have an adverse effect on the memory device. Therefore, GIDL and SWB should be balanced so that the GIDL of the memory device is not too high and the memory device meets the SWB standard at the same time.
[0032] refer to Figure 4 , forming a conductive layer 120 that overfills the trench T. That is, the conductive layer 120 is not only formed in the trench T, but also covers the hard mask layer HM and the dielectric layer 110. The conductive layer 120 is made of a conductive material. In some embodiments, the conductive layer 120 is made of a metal nitride, such as titanium nitride (TiN).
[0033] refer to Figure 5 , the conductive layer 120 is etched back to lower the top surface of the conductive layer 120. In some embodiments, the top surface of the conductive layer 120 is not higher than the bottom of the doped region 104. In some embodiments, etching back the conductive layer 120 may oxidize the top surface of the conductive layer, thereby forming a native oxide layer 130 on the conductive layer 120. The native oxide layer 130 may affect the subsequent manufacturing process of the memory device. After the conductive layer 120 is etched back, a portion of the dielectric layer 110 is exposed.
[0034] refer to Figure 6, an etching process is performed on the conductive layer 120 to remove the native oxide layer 130, so as to expose the conductive layer 120 and trim the portion of the dielectric layer 110 exposed by the conductive layer 120. In some embodiments, trimming the portion of the dielectric layer 110 exposed by the conductive layer 120 may include laterally etching the dielectric layer 110 during the removal of the native oxide layer 130. This will result in the thickness of the dielectric layer 110 protruding from the conductive layer 120 being less than the thickness of the dielectric layer 110 covered by the conductive layer 120. The amount by which the dielectric layer 110 is trimmed is adjusted to balance the GIDL and the SWB. In some embodiments, the thickness of the dielectric layer 110 after the lateral etching is about 1 nm to 5 nm.
[0035] refer to Figure 7 , the conductive layer 140 is formed in the trench T and contacts the conductive layer 120. Figure 8 , an etch-back process is performed on the conductive layer 140 to lower the top surface of the conductive layer 140. Because the dielectric layer 110 in contact with the conductive layer 140 is trimmed, the conductive layer 140 is wider than the conductive layer 120. Therefore, the dielectric layer 110 is in contact with the bottom surface of the conductive layer 140. The conductive layer 140 and the conductive layer 120 are made of different materials. In some embodiments, the work function value of the conductive layer 140 is lower than the work function value of the conductive layer 120. The materials of the conductive layer 120 and the conductive layer 140 are appropriately selected, so that the materials of the conductive layer 120 and the conductive layer 140 will not diffuse into each other. In some embodiments, the conductive layer 140 is made of polysilicon. Since the native oxide layer 130 is removed in the previous stage, it is ensured that the conductive layer 140 is in contact with the conductive layer 120, and it will be beneficial to the operation of the word line in the memory device in the present invention.
[0036] refer to Fig. 9 , forming a dielectric layer 150 lining the trench T and contacting the conductive layer 140. The dielectric layer 150 further extends along the top surface and sidewalls of the hard mask layer HM. In some embodiments, the dielectric layer 150 and the dielectric layer 110 are made of the same material, such as silicon oxide. In some embodiments, the thickness of the dielectric layer 150 is about 1.5 nanometers to 5 nanometers.
[0037] refer to Fig.10 , a capping layer 160 is formed in the trench T and over the conductive layer 140 and the dielectric layer 150. The dielectric layer 150 is along the sidewall and bottom of the capping layer 160, and a portion of the dielectric layer 150 is located between the conductive layer 140 and the capping layer 160. The dielectric layer 150 is further in contact with the dielectric layer 110. In some embodiments, the capping layer 160 is made of a dielectric material, and the material of the capping layer 160 is different from the materials of the dielectric layer 110 and the dielectric layer 150. In some embodiments, the capping layer 160 is made of silicon nitride. In some embodiments, each conductive layer 120 and its corresponding conductive layer 140 and capping layer 160 may be referred to as Figure 1 The word line structure WL in the dielectric layer 110 and its corresponding dielectric layer 150 may be referred to as a gate dielectric layer GD. The gate dielectric layer GD is used as Figure 1 The gate dielectric layer of the transistor TR in .
[0038] refer to Fig.11 , a planarization process such as CMP is performed on the cap layer 160 until the doped region 104 of the substrate 100 is exposed. During the planarization process, the hard mask layer HM may also be removed. Thereafter, a bit line BL and a capacitor CA electrically connected to the doped region 104 may be formed.
[0039] The resulting memory device is Fig.11 The memory device includes a substrate 100, a word line structure WL, and a gate dielectric layer GD. The word line structure WL is embedded in the substrate 100 and includes a conductive layer 120, a conductive layer 140, and a capping layer 160. The conductive layer 140 is above the conductive layer 120. The capping layer is above the conductive layer 140.
[0040] Because of the cleaning process performed in the present invention, the conductive layer 140 is in contact with the conductive layer 120. The direct contact between the conductive layer 140 and the conductive layer 120 can simplify the operation of the memory structure in the present invention. For example, the conductive layer 140 is electrically connected to the conductive layer 120, so the conductive layer 140 and the conductive layer 120 can be controlled without coupling. Specifically, the materials of the conductive layer 120 and the conductive layer 140 are appropriately selected, so the materials of the conductive layer 120 and the conductive layer 140 will not diffuse into each other. Therefore, there is no need to form an additional layer between the conductive layer 120 and the conductive layer 140 to avoid diffusion between the conductive layer 120 and the conductive layer 140. The conductive layer 140 and the conductive layer 120 of the word line structure WL can be controlled without coupling, and the operation time of the word line structure WL in the present invention can be reduced accordingly.
[0041] The gate dielectric layer GD includes a dielectric layer 110 and a dielectric layer 150. The gate dielectric layer GD is located between the substrate 100 and the word line structure WL. The gate dielectric layer GD is along the sidewall of the word line structure WL, and includes a first portion P1, a second portion P2, a third portion P3, and a fourth portion P4. The first portion P1 is along the sidewall of the conductive layer 120, the second portion P2 is along the sidewall of the conductive layer 140, the third portion P3 is along the sidewall of the cover layer 160, and the fourth portion P4 is located between the conductive layer 140 and the cover layer 160. The first portion P1 of the gate dielectric layer GD further contacts the bottom surface of the conductive layer 140. The manufacturing process of the dielectric layer 110 and the dielectric layer 150 results in a difference in thickness between different portions of the gate dielectric layer GD. Specifically, by forming the dielectric layer 110 ( Figure 3 ), trimming the dielectric layer 110 protruding from the conductive layer 120 ( Figure 6 ) and forming a dielectric layer 150 ( Fig. 9 The gate dielectric layer GD is formed by forming a second portion P2 of the gate dielectric layer GD (including the trimmed dielectric layer 110). Therefore, the thickness of the second portion P2 of the gate dielectric layer GD (including the untrimmed dielectric layer 110) is less than the thickness of the first portion P1 of the gate dielectric layer GD (including the untrimmed dielectric layer 110) and the thickness of the third portion P3 of the gate dielectric layer GD (including the combination of the trimmed dielectric layer 110 and the dielectric layer 150). The thickness of the fourth portion P4 of the gate dielectric layer GD (including the dielectric layer 150) is less than the thickness of the third portion P3 of the gate dielectric layer GD (including the combination of the trimmed dielectric layer 110 and the dielectric layer 150). In some embodiments, the thickness of the third portion P3 of the gate dielectric layer GD (including the combination of the trimmed dielectric layer 110 and the dielectric layer 150) is greater than the thickness of the first portion P1 of the gate dielectric layer GD (including the untrimmed dielectric layer 110). In some embodiments, the thickness of the fourth portion P4 of the gate dielectric layer GD (including the dielectric layer 150) can be greater than the thickness of the second portion P2 of the gate dielectric layer GD (including the trimmed dielectric layer 110). Specifically, the different thicknesses of different portions of the gate dielectric layer GD can be adjusted to balance the GIDL and SWB of the memory device. For example, since no additional dielectric layer is formed after the dielectric layer 110 is laterally etched and before the conductive layer 140 is formed, the gate dielectric layer 150 can be adjusted by adjusting the thickness of the fourth portion P4 of the gate dielectric layer GD. Figure 6 The etching amount of the dielectric layer 110 can well control the thickness of the second portion P2 of the gate dielectric layer GD. Such a configuration will result in a physical contact between the conductive layer 140 and the conductive layer 120 of the word line structure WL, and therefore there is no coupling between the conductive layer 140 and the conductive layer 120 of the word line structure WL during operation of the word line structure WL. The adjustment of the second portion P2 of the gate dielectric layer GD does not need to consider the process of manufacturing the dielectric layer formed between the conductive layer 140 and the conductive layer 120. In some embodiments, the dielectric layer 110 and the dielectric layer 150 are made of the same material, and therefore the first portion P1, the second portion P2, the third portion P3, and the fourth portion P4 of the gate dielectric layer GD are made of the same material.
[0042] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0043] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention, with the proviso that the modifications and variations fall within the scope of the following claims.
[0044]
Explanation of symbols
[0045] 100:Substrate
[0046] 102: Isolation Structure
[0047] 102A: The first part of the isolation structure
[0048] 102B: The second part of the isolation structure
[0049] 104: Doping area
[0050] 110, 150: dielectric layer
[0051] 120, 140: conductive layer
[0052] 130: Native Oxide
[0053] 160: Covering layer
[0054] BL: Bit Line
[0055] CA:Capacitor
[0056] GD: Gate dielectric layer
[0057] HM: Mask layer
[0058] MC:Memory Cell
[0059] P1: Part 1
[0060] P2: Part 2
[0061] P3: Part 3
[0062] P4: Part 4
[0063] T: Groove
[0064] TR: Transistor
[0065] WL: character line structure.
Claims
1. A method for forming a memory device, characterized in that: The following steps are involved: forming a trench in a substrate; forming a first dielectric layer lining the trench; forming a first conductive layer in the trench; Etching back the first conductive layer to form a native oxide layer on the first conductive layer; performing an etching process to remove the native oxide layer to expose the first conductive layer, and trimming a portion of the first dielectric layer exposed by the first conductive layer; and A second conductive layer is formed in the trench in contact with the first conductive layer.
2. The method according to claim 1, characterized in that The second conductive layer is wider than the first conductive layer.
3. The method according to claim 1, characterized in that After the etching process is completed, the thickness of the first dielectric layer protruding from the first conductive layer is smaller than the thickness of the first dielectric layer covered by the first conductive layer.
4. The method according to claim 1, characterized in that: Further including: Etching back the second conductive layer; and After forming the second conductive layer, a second dielectric layer lining the trench is formed, wherein the second dielectric layer contacts the second conductive layer.
5. The method according to claim 4, characterized in that Further including: A capping layer is formed in the trench after etching back the second dielectric layer.
6. The method according to claim 5, characterized in that The first dielectric layer and the second dielectric layer form a gate dielectric layer, and a thickness of the gate dielectric layer along a sidewall of the second conductive layer is smaller than a thickness of the gate dielectric layer along a sidewall of the capping layer.
7. The method according to claim 5, characterized in that The first dielectric layer and the second dielectric layer form a gate dielectric layer, and a thickness of the gate dielectric layer along a sidewall of the second conductive layer is smaller than a thickness of the gate dielectric layer along a sidewall of the first conductive layer.
8. The method according to claim 5, characterized in that The first dielectric layer and the second dielectric layer are made of the same material.
9. The method according to claim 1, characterized in that: The work function value of the second conductive layer is lower than the work function value of the first conductive layer.
10. The method according to claim 1, characterized in that The first conductive layer is made of metal nitride.
11. A memory device, characterized in that: include: substrate; A word line structure is embedded in the substrate and includes: a first conductive layer; A second conductive layer is located on the first conductive layer; and a covering layer located on the second conductive layer; and A gate dielectric layer lining the word line structure and comprising: A first portion along a sidewall of the first conductive layer; a second portion along a sidewall of the second conductive layer; and A third portion is along the sidewall of the capping layer, wherein the thickness of the second portion of the gate dielectric layer is less than the thickness of the first portion of the gate dielectric layer.
12. The memory device according to claim 11, wherein: The thickness of the second portion of the gate dielectric layer is less than the thickness of the third portion of the gate dielectric layer.
13. The memory device according to claim 11, wherein: The thickness of the third portion of the gate dielectric layer is greater than the thickness of the first portion of the gate dielectric layer.
14. The memory device according to claim 11, wherein: The gate dielectric layer further includes a fourth portion between the second conductive layer and the capping layer.
15. The memory device according to claim 14, wherein: The thickness of the fourth portion of the gate dielectric layer is less than the thickness of the third portion of the gate dielectric layer.
16. The memory device according to claim 11, wherein: The first conductive layer contacts the second conductive layer.
17. The memory device according to claim 11, wherein: The work function value of the second conductive layer is lower than the work function value of the first conductive layer.
18. The memory device according to claim 11, wherein: The first conductive layer is made of metal nitride.
19. The memory device according to claim 11, wherein: The second conductive layer is wider than the first conductive layer.
20. The memory device according to claim 11, wherein: The first portion of the gate dielectric layer contacts a bottom surface of the second conductive layer.