Semiconductor structure, semiconductor memory and preparation method of semiconductor structure

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a semiconductor memory and a preparation method of the semiconductor structure. The semiconductor structure comprises a substrate, an insulating layer and a control gate layer which are sequentially stacked from bottom to top; the control gate layer comprises a floating gate region and an erasure gate region which are arranged at an interval along a first direction, and a tunneling oxide layer is filled between the floating gate region and the erasure gate region; the first direction is a direction perpendicular to the thickness direction of the substrate; the floating gate region comprises a floating gate and a control gate which are arranged from bottom to top; the thickness of the tunneling oxide layer between the floating gate and the erasing gate region is larger than the thickness of the region, corresponding to the floating gate, of the insulating layer, so that electrons during erasing operation and writing operation are achieved through different oxide layer channels, the erasing voltage is small, and then the reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure, a semiconductor memory and a method for preparing the semiconductor structure. Background Art

[0002] Memory refers to a container that can hold certain transactions. Memory is usually used as a memory device in a computer system to store programs and data. According to the storage medium, memory includes semiconductor memory, magnetic memory and laser memory. Among them, semiconductor memory has the advantages of high integration, large capacity, small size and fast access speed, making it a research hotspot in related fields.

[0003] See also Figure 1 , which shows a schematic diagram of the structure of a semiconductor memory in the prior art. The semiconductor memory at least includes a substrate, a gate oxide layer, a floating gate, a dielectric layer and a control gate arranged in sequence from bottom to top. When performing a write operation, a voltage is applied to the control gate so that electrons enter the floating gate through the gate oxide layer; when performing an erase operation, a voltage is applied to the substrate so that electrons are sucked out of the floating gate through the gate oxide layer. However, since the electrons pass through the planar gate oxide layer in both the write and erase operations of the above-mentioned existing memory devices, multiple electron penetrations are likely to cause damage to the gate oxide layer, thereby reducing its reliability. Summary of the invention

[0004] To solve the above technical problems, on the one hand, the present application discloses a semiconductor structure, which includes a substrate, an insulating layer and a control gate layer stacked sequentially from bottom to top;

[0005] The control gate layer includes a floating gate region and an erase gate region spaced apart along a first direction, and a tunneling oxide layer is filled between the floating gate region and the erase gate region; the first direction is a direction perpendicular to the thickness direction of the substrate;

[0006] The floating gate region includes a floating gate and a control gate arranged from bottom to top;

[0007] The thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the region of the insulating layer corresponding to the floating gate.

[0008] Further, the floating gate includes a first side surface and a second side surface opposite to each other; the first side surface and the second side surface are arranged along a first direction; and the second side surface is close to the erase gate region;

[0009] The distance between the second side surface and the side surface of the control gate close to the second side surface is greater than the distance between the first side surface and the side surface of the control gate close to the first side surface;

[0010] Further, the floating gate includes a first floating gate region, a second floating gate region, and a third floating gate region that are sequentially arranged and connected in a first direction;

[0011] The position of the second floating gate region corresponds to that of the control gate;

[0012] The width of the first floating gate region is greater than the width of the third floating gate region, or the width of the first floating gate region is less than the width of the third floating gate region.

[0013] Further, a preset distance exists between the top of the second floating gate region and the tops of the first floating gate region and the third floating gate region respectively.

[0014] Further, it includes two floating gate regions;

[0015] The erase gate region is located between the two floating gate regions.

[0016] Further, the erase gate region includes a first structure, a second structure, and a third structure that are sequentially arranged and connected from bottom to top;

[0017] The width of the first structure is less than the width of the third structure;

[0018] The width of the second structure gradually increases along the arrangement direction;

[0019] An interlayer dielectric layer is provided between the floating gate and the control gate; the interlayer dielectric layer and the second structure are in the same plane.

[0020] Further, the tunneling oxide layer includes a connected first oxide structure and a second oxide structure;

[0021] The first oxide structure is located between the floating gate and the erase gate;

[0022] The second oxide structure is located between the control gate and the erase gate, and the second oxide structure is a composite structure.

[0023] Further, the thickness of the first oxide structure is greater than the thickness of the first region of the insulating layer; the first region is the region corresponding to the projection of the floating gate on the insulating layer.

[0024] Further, the control gate layer further includes a word line arranged in the first direction and having a preset interval from the floating gate region;

[0025] A gap oxide layer is filled between the floating gate region and the word line; the thickness of the gap oxide layer is greater than the thickness of the first oxide structure;

[0026] The first side is close to the word line.

[0027] On the other hand, a method for manufacturing a semiconductor structure is also disclosed, which includes the following steps:

[0028] Provide an initial semiconductor structure; the initial semiconductor structure includes a substrate, an insulating layer, and an initial control gate layer stacked in sequence from bottom to top; the initial control gate layer includes a floating gate material layer and a control gate located on the floating gate material layer; sidewalls are respectively provided on opposite sides of the control gate.

[0029] Perform patterning on the initial semiconductor structure to remove a preset area of the floating gate material layer, and form a floating gate on the insulating layer to obtain an intermediate semiconductor structure; the control gate is located on the floating gate.

[0030] Form a first oxide layer and an erase gate region on the surface of the intermediate semiconductor structure in sequence to obtain a target semiconductor structure; the erase gate region is spaced from the floating gate in a first direction; the first direction is a direction perpendicular to the thickness direction of the substrate; a tunneling oxide layer is filled between the floating gate region and the erase gate region; the thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the corresponding floating gate region of the insulating layer.

[0031] Furthermore, a second oxide layer is provided on the surface of the initial control gate layer; the initial control gate layer includes two control gates spaced in the first direction; performing patterning on the initial semiconductor structure to remove the second oxide layer in a first preset area on the initial control gate layer; the first preset area is located on the side of the control gate away from the erase gate blank area; the erase gate blank area is the area between the two control gates.

[0032] Remove the floating gate material layer in the first preset area and the floating gate material layer in the erase gate blank area to form a floating gate on the insulating layer to obtain an intermediate semiconductor structure.

[0033]

[0034] Furthermore, forming a first oxide layer and an erase gate region on the surface of the intermediate semiconductor structure to obtain a target semiconductor structure includes:

[0035] Form a first oxide layer on the surface of the intermediate semiconductor structure.

[0036] Deposit a conductive material in the first preset area to form a word line on the insulating layer; at the same time, deposit a conductive material in the erase gate blank area to form an erase gate region on the insulating layer to obtain a target semiconductor structure.

[0037] On the other hand, a semiconductor memory is also disclosed, and the storage device includes the above semiconductor structure.

[0038] On the other hand, an electronic device is also disclosed, and the electronic device includes the above semiconductor memory.

[0039] ​By adopting the above technical solution, the semiconductor structure provided by the present application has the following beneficial effects:

[0040] The semiconductor structure includes a substrate, an insulating layer and a control gate layer stacked in sequence from bottom to top; the control gate layer includes a floating gate region and an erase gate region spaced apart along a first direction, and a tunneling oxide layer is filled between the floating gate region and the erase gate region; the first direction is a direction perpendicular to the thickness direction of the substrate; the floating gate region includes a floating gate and a control gate arranged from bottom to top, and when a subsequent write operation is performed, electrons enter the floating gate through the insulating layer below the floating gate, and when an erase operation is performed, electrons in the floating gate are sucked out through the tunneling oxide layer, and the write and erase operations are realized through different oxide layer channels, thereby reducing the number of electron penetrations of the insulating layer and effectively improving the life of the semiconductor structure.

[0041] The thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the region of the insulating layer corresponding to the floating gate. Therefore, the tunneling oxide layer between the floating gate and the erase gate can be thicker than the insulating layer. This structure can achieve the erase operation with a smaller voltage, and also improves the reliability of the electron penetration channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 It is a schematic diagram of the structure of a semiconductor memory in the prior art;

[0044] Figure 2 is a structural schematic diagram of a first semiconductor structure provided in an embodiment of the present application;

[0045] Figure 3 is a structural schematic diagram of a second semiconductor structure provided in an embodiment of the present application;

[0046] Figure 4 is a structural schematic diagram of a third semiconductor structure provided in an embodiment of the present application;

[0047] Figure 5 It is a schematic diagram of a preparation process of a semiconductor structure provided in an embodiment of the present application;

[0048] Figure 6 is a schematic structural diagram of an initial semiconductor structure provided in an embodiment of the present application;

[0049] Figure 7is a schematic structural diagram of an initial semiconductor structure after the second oxide layer in the first preset area is removed, provided in an embodiment of the present application;

[0050] Figure 8 is a structural schematic diagram of an intermediate semiconductor structure provided in an embodiment of the present application;

[0051] Fig. 9 It is a structural schematic diagram of an initial semiconductor structure after ion implantation into a preset area provided in an embodiment of the present application;

[0052] Fig.10 It is a structural schematic diagram of another intermediate semiconductor structure provided in an embodiment of the present application.

[0053] The following is a supplementary description of the attached drawings:

[0054] 1-substrate; 2-insulating layer; 3-control gate layer; 4-floating gate region; 401-floating gate; 4011-first floating gate region; 4012-second floating gate region; 4013-third floating gate region; 402-control gate; 5-erase gate region; 501-first structure; 502-second structure; 503-third structure; 6-tunneling oxide layer; 601-first oxide structure; 602-second oxide structure; 7-interlayer dielectric layer; 8-word line; 9-gap oxide layer; 10-floating gate material layer; 11-second oxide layer; 12-first preset region; 13-erase gate blank region; 14-word line low resistance region; 15-source line low resistance region. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0057] For the purpose of the following detailed description, it should be understood that the present invention may adopt various alternative changes and step sequences, unless expressly specified to the contrary. In addition, except in any operating examples, or otherwise indicated, all numbers representing the amount of ingredients used in the specification and claims should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise indicated, the numerical parameters set forth in the following specification and the attached claims are approximate values ​​that vary according to the desired performance to be obtained by the present invention. At least it is not intended to limit the application of the doctrine of equivalents to the scope of the claims, and each numerical parameter should at least be interpreted according to the number of reported significant figures and by applying ordinary rounding techniques.

[0058] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0059] When a numerical range is disclosed herein, the above range is deemed to be continuous and includes the minimum and maximum values ​​of the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all sub-ranges included therein. For example, a specified range from "1 to 10" should be deemed to include any and all sub-ranges between a minimum of 1 and a maximum of 10. Exemplary sub-ranges of ranges 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0060] pass Figure 1 It can be seen from the semiconductor memory in the prior art shown that the semiconductor memory at least includes a substrate, a gate oxide layer, a floating gate, a dielectric layer and a control gate arranged in sequence from bottom to top. A voltage is applied to the control gate so that electrons enter the floating gate through the gate oxide layer to achieve a write operation; a voltage is applied to the substrate so that electrons are sucked out of the floating gate through the gate oxide layer to achieve an erase operation. Specifically, when performing an erase operation, when a voltage of 10.5V is applied to the substrate and a voltage of -8.8V is applied to the control gate, the deviation voltage (i.e., the erase voltage) is 19.3V and the corresponding current on the gate oxide layer is about 90A. Obviously, the applied erase voltage is large, which can easily cause side breakdown problems. However, if the erase voltage is reduced and is too small, the device may not be completely erased, resulting in read failure. Therefore, how to design a semiconductor memory that can reduce the erase voltage and ensure clean erasure has become one of the urgent problems to be solved. In addition, since the above-mentioned existing memory devices, whether performing write operations or erase operations, electrons are realized through the planar gate oxide layer, so multiple electron penetrations can easily cause damage to the gate oxide layer, thereby reducing its reliability.

[0061] To do this, see Figure 2 , which is a schematic diagram of the structure of a semiconductor structure provided by an embodiment of the present application, wherein the semiconductor structure includes a substrate 1, an insulating layer 2 and a control gate layer 3 stacked in sequence from bottom to top; the control gate layer 3 includes a floating gate region 4 and an erase gate region 5 spaced apart along a first direction, and a tunneling oxide layer 6 is filled between the floating gate region 4 and the erase gate region 5; the first direction is a direction perpendicular to the thickness direction of the substrate 1; the floating gate region 4 includes a floating gate 401 and a control gate 402 arranged from bottom to top; the thickness of the tunneling oxide layer 6 between the floating gate 401 and the erase gate region 5 is greater than the thickness of the region of the insulating layer 2 corresponding to the floating gate 401. Thus, when performing an erase operation, electrons are sucked out of the floating gate 401 through the tunneling oxide layer 6, rather than the insulating layer 2. This dual-channel structure can improve the reliability of the device. Optionally, the first direction may refer to Figure 2 The x direction in the substrate 1 may refer to the thickness direction of Figure 2 In this embodiment, the first direction may specifically refer to the positive direction of the x-axis, and the thickness direction of the substrate 1 may specifically refer to the positive direction of the y-axis.

[0062] In a specific embodiment, the floating gate 401 includes a first side surface and a second side surface opposite to each other; the first side surface and the second side surface are arranged along a first direction; the second side surface is close to the erase gate region 5; the distance between the second side surface and the side surface of the control gate 402 close to the second side surface is greater than the distance between the first side surface and the side surface of the control gate 402 close to the first side surface; that is, by designing the floating gate 401 into an asymmetric structure, that is, the area close to the erase gate region 5 is wider, the tunneling oxide layer 6 between the floating gate 401 and the erase gate can be designed to be thicker than the insulating layer 2. Since the tunneling oxide layer 6 is a two-dimensional structure distributed along the y direction, it will have field strengths in two directions. When the same voltage is applied, the field strength can be stronger, so even if the tunneling oxide layer 6 is designed to be thicker, the erasing effect at a lower erase voltage can be achieved. Moreover, the thicker tunneling oxide layer 6 can also improve the reliability of the structure and reduce channel damage.

[0063] In a specific embodiment, when Figure 2 The semiconductor structure shown in FIG. 1 is applied with an erase voltage of 12V to implement an erase operation. At this time, the tunnel oxide layer 6 between the floating gate 401 and the erase gate region 5 is subjected to a current of about 130A. Figure 1 From the erase test results of the conventional semiconductor memory shown (erasing voltage is 19.3V), the semiconductor structure provided by the present application can achieve erasing at a lower erasing voltage.

[0064] In some possible embodiments, see Figure 3 , the floating gate 401 includes a first floating gate region 4011, a second floating gate region 4012 and a third floating gate region 4013 which are sequentially arranged and connected along a first direction; the second floating gate region 4012 corresponds to the position of the control gate 402; the first floating gate region 4011 is close to the erase gate region 5, and the width of the first floating gate region 4011 is greater than the width of the third floating gate region 4013. Optionally, the width of the second floating gate region 4012 is equal to the width of the control gate 402. Since the widths of the regions on both sides of the second floating gate region 4012 of the floating gate 401 are not equal, an asymmetric structure is formed, so that an oxide layer with a bent structure can be formed between the erase gate region 5 and the floating gate 401, which can improve the reliability of the structure while reducing the erase voltage. In other feasible embodiments, when the region close to the erase gate region 5 is defined as the third floating gate region 4013, the width of the first floating gate region 4011 is less than the width of the third floating gate region 4013.

[0065] In some feasible embodiments, the top of the second floating gate region 4012 is at a preset distance from the top of the first floating gate region 4011 and the top of the third floating gate region 4013. Thus, the second floating gate region 4012 is higher than the first floating gate region 4011 and the second floating gate region 4012 by a certain height, which is specifically formed by preparing the sidewalls on both sides of the control gate 402. Figure 3 As shown, the sidewalls may be of an ON structure, ie, silicon oxide layer / silicon nitride layer, with an oxide layer disposed near the control gate 402, or an ONO structure, ie, silicon oxide layer / silicon nitride layer / silicon oxide layer.

[0066] In this embodiment, an isolation protection layer is further provided on the control gate 402. The material of the isolation protection layer may be one of silicon oxide, silicon nitride, silicon oxynitride and carbon-containing silicon oxide, or a composite structure of any of the above, and the thickness thereof may range from 800 to 900 angstroms. The specific implementation thickness of the isolation protection layer may be 800 angstroms, 810 angstroms, 820 angstroms, 830 angstroms, 840 angstroms, 850 angstroms, 860 angstroms, 870 angstroms, 880 angstroms, 890 angstroms and 900 angstroms. Optionally, as Figure 2 As shown, the isolation protection layer can be a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer.

[0067] In some possible embodiments, see Figure 2 The semiconductor structure includes two floating gate regions 4; the erase gate region 5 is located between the two floating gate regions 4. Optionally, the two floating gate regions 4 may be, but are not limited to, mirror images of each other with respect to the central axis of the erase gate region 5.

[0068] In some possible embodiments, see Figure 3 , the erase gate region 5 includes a first structure 501, a second structure 502 and a third structure 503 which are sequentially arranged and connected from bottom to top; the width of the first structure 501 is smaller than the width of the third structure 503; the width of the second structure 502 gradually increases along the arrangement direction. Specifically, the cross-section of the second structure 502 may be an inverted trapezoid, and the first structure 501 and the third structure 503 may be rectangular, such as a rectangle or a square, which is determined according to the actual device performance and size requirements. Optionally, an interlayer dielectric layer 7 is provided between the floating gate 401 and the control gate 402, and the material of the interlayer dielectric layer 7 may be one of silicon oxide, silicon nitride, silicon oxynitride and carbon-containing silicon oxide, or a composite structure of any of the above, and the thickness thereof may range from 130 to 180 angstroms. The specific implementation thickness of the interlayer dielectric layer 7 may be 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, 170 angstroms and 180 angstroms. Optionally, as Figure 3 As shown, the interlayer dielectric layer 7 may be a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer. Optionally, the interlayer dielectric layer 7 and the second structure 502 are located in the same plane.

[0069] In some feasible embodiments, the tunneling oxide layer 6 includes a first oxide structure 601 and a second oxide structure 602 connected; the first oxide structure 601 is located between the floating gate 401 and the erase gate; the second oxide structure 602 is located between the control gate 402 and the erase gate, and the second oxide structure 602 is a composite structure. Optionally, the first oxide structure 601 can be a single-layer structure of a material, such as silicon oxide, and its thickness can range from 110 to 150 angstroms. The specific implementation thickness of the first oxide structure 601 can be 110 angstroms, 120 angstroms, 130 angstroms, 140 angstroms, and 150 angstroms. Optionally, the second oxide structure 602 can be a composite structure of any of silicon oxide, silicon nitride, silicon oxynitride, and carbon-containing silicon oxide.

[0070] In some feasible embodiments, the thickness of the first oxide structure 601 is greater than the thickness of the first region of the insulating layer 2; the first region is the region corresponding to the projection of the floating gate 401 on the insulating layer 2. During a write operation, electrons enter the floating gate 401 through the first region, and during an erase operation, electrons are sucked out of the floating gate 401 through the first oxide structure 601, so the reliability of the structure can be effectively improved by the above-mentioned thickness setting method of this embodiment. Optionally, the insulating layer 2 can be specifically a silicon oxide material, and the thickness of the first region can range from 80 to 100 angstroms, and the specific implementation thickness of the first region can be 80 angstroms, 850 angstroms, 900 angstroms, 950 angstroms and 100 angstroms.

[0071] For some possible embodiments, please refer to Figure 3 , the control gate layer 3 also includes a word line 8 arranged along the first direction and having a preset interval with the floating gate region 4; a gap oxide layer 9 is filled between the floating gate region 4 and the word line 8; the thickness of the gap oxide layer 9 is greater than the thickness of the first oxide structure 601; the first side is close to the word line 8. Optionally, the gap oxide layer 9 can be a silicon oxide layer or a silicon nitride layer. Optionally, the thickness of the gap oxide layer 9 can range from 200 to 260 angstroms, and the specific implementation thickness of the gap oxide layer 9 can be 200 angstroms, 210 angstroms, 220 angstroms, 230 angstroms, 240 angstroms, and 260 angstroms. The thickness of the gap oxide layer 9 is greater than the thickness of the first oxide structure 601. Optionally, in the case where the control gate layer 3 includes two floating gate regions 4, it also includes two corresponding word lines 8. The arrangement of the two word lines 8, the two floating gate regions 4 and the erase gate region 5 along the first direction is one word line 8, one floating gate region 4, the erase gate region 5, another floating gate region 4 and another word line 8. The overall structure can be a mirror structure of the central axis of the erase gate region 5.

[0072] In the embodiment of the present application, the first oxidation structure 601 is a silicon oxide layer with a thickness of 130 angstroms, and the second oxidation structure 602 is a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer. The interlayer dielectric layer 7 between the floating gate 401 and the control gate 402 is a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer. The side walls on both sides of the control gate 402 can be a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer, wherein the side wall of the control gate 402 close to the erase gate is the upper second oxidation structure 602; the outer silicon oxide layer in the side wall of the control gate 402 close to the word line 8 belongs to the above-mentioned gap oxide layer 9. An isolation protection layer is also provided on the control gate 402, and the isolation protection layer is a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer. The thickness of the first region of the insulating layer 2 is 90 angstroms, and the insulating layer 2 also includes a second region and a third region, wherein the second region refers to the region where the erase gate is projected on the insulating layer 2, and the thickness of the second region can range from 280 to 350 angstroms, and the specific implementation thickness of the second region can be 280 angstroms, 290 angstroms, 300 angstroms, 310 angstroms, 320 angstroms, 330 angstroms and 350 angstroms. The thickness of the second region is greater than the thickness of the first region, and the second region is designed to be thicker, so that the erase voltage applied to the erase gate region 5 can only be applied to the floating gate 401 in order to avoid the erase voltage affecting the source line low resistance region 15 during the erase operation; the third region refers to the region where the word line 8 is projected on the insulating layer 2, and the thickness of the third region can range from 10 to 30 angstroms, and the specific implementation thickness of the third region can be 10 angstroms, 15 angstroms, 20 angstroms, 25 angstroms and 30 angstroms. The thickness of the third region is determined according to the type of device to be prepared. For example, if a 1.5V semiconductor memory device is prepared, the third region is relatively thin. It can also be a 3.3V, 5V, 12V, etc. device type. In fact, the semiconductor structure provided by the present application also includes a peripheral structure, that is, a logic area. The semiconductor structure described above is mainly a control area. In the actual preparation process, some structures of the control area and the logic area are prepared as a whole. For example, the third region of the insulating layer 2, the thickness of the oxide layer required to be prepared for the device corresponding to the third region and the logic area is consistent.

[0073] It can be understood that the sidewalls provided on both sides of the control gate 402 are a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer. Since the silicon nitride layer has better chemical stability and a higher K value, the sidewalls of this structure can have a larger capacitance when made thinner, and are not easily broken down, which is beneficial to reducing the size of the structure and is applied to high-integration devices. In order to further ensure the above effect, the bottom of the silicon nitride layer can be designed to be lower than the bottom of the control layer. Specifically, when the interlayer dielectric layer 7 is a composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer, the bottom of the silicon nitride layer of the sidewall is lower than the bottom of the silicon nitride layer of the interlayer dielectric layer 7.

[0074] In the embodiments of this application, please refer to Figure 4 The semiconductor structure further includes a word line low resistance region 14 and a source line low resistance region 15, wherein the source line low resistance region 15 is located in a region of the substrate 1 close to the top thereof and corresponds to the erase gate region 5, and is used to be connected to the source. In the case where the word lines 8 include two, the word line low resistance region 14 also includes two, and each word line 8 corresponds to a word line 8 low group region under the word line 8, and the word line low resistance region 14 is located in a region of the substrate 1 close to the top thereof. The above-mentioned word line low resistance region 14 and source line low resistance region 15 can be obtained by ion doping a preset region.

[0075] In this embodiment, the control gate layer 3 further includes a bit line, which is located at the side of the word line 8 and is filled with an oxide layer between the bit line and the word line 8 .

[0076] The semiconductor structure of the present application includes a floating gate region 4 and an erase gate region 5 which are arranged in a transverse interval, and a tunneling oxide layer 6 is filled between the floating gate region 4 and the erase gate region 5, and the floating gate region 4 includes a floating gate 401 and a control gate 402 which are arranged from bottom to top, so that when performing the subsequent erasing and writing operations, the electrons are realized by penetrating different channels, which reduces the number of electron penetrations of the insulating layer 2, and effectively improves the life of the semiconductor structure. And by designing the tunneling oxide layer 6 between the floating gate 401 and the erase gate to be a thicker structure than the insulating layer 2, it can be realized by using a smaller voltage when performing the erasing operation, and the reliability of the electron penetration channel is also improved.

[0077] See also Figure 5 The present invention discloses a method for preparing a semiconductor structure, which comprises the following steps:

[0078] S501: Provide an initial semiconductor structure; the initial semiconductor structure includes a substrate 1, an insulating layer 2 and an initial control gate layer 3 stacked in sequence from bottom to top; the initial control gate layer 3 includes a floating gate material layer 10 and a control gate 402 located on the floating gate material layer 10; sidewalls are respectively provided on opposite sides of the control gate 402.

[0079] In the embodiments of this application, please refer to Figure 3 , which shows a schematic diagram of the structure of an initial semiconductor provided by an embodiment of the present application. The initial semiconductor structure may refer to a structure that has completed partial structure preparation, such as the control gate 402; the preparation method involved in the present application is mainly a large plate forming process, that is, a process of preparing multiple devices of the same specification on a whole wafer. Figure 6Corresponding to a control region of a semiconductor memory. In fact, the semiconductor memory further includes a logic region. This application mainly focuses on the research of the preparation of each layer structure of the control region, so the preparation of the logic region will not be described in detail here. During the process of forming a large board, a floating gate material layer 10 of the above-mentioned initial semiconductor structure will form a plurality of control structures at preset intervals, such as Figure 6 As shown, each control structure includes a control gate 402, and oxide layers located below and above the control gate 402. The oxide layer located below the control gate 402 can be referred to as an interlayer dielectric layer 7. The material of the interlayer dielectric layer 7 can be one or any combination of silicon oxide, silicon nitride, silicon oxynitride, and carbon-containing silicon oxide. The oxide layer located above the control gate 402 can be referred to as an isolation protection layer, and the material of the isolation protection layer can be one or any combination of silicon oxide, silicon nitride, silicon oxynitride, and carbon-containing silicon oxide.

[0080] In an embodiment of this application, a second oxide layer 11 is provided on the surface of the initial control gate layer 3. The material of the second oxide layer 11 can be any one of silicon oxide, silicon nitride, silicon oxynitride, and carbon-containing silicon oxide. Optionally, the initial control gate layer 3 includes two control gates 402 spaced apart along a first direction. The first direction is a direction perpendicular to the thickness direction of the substrate. As Figure 6 shown, the first direction can refer to the positive x-axis direction.

[0081] In an embodiment of this application, the material of the floating gate material layer 10 can include polysilicon, silicon nitride, or a conductive nanocrystal material. The material of the control gate layer 3 can include polysilicon, silicon nitride, or a conductive nanocrystal material. The material of the word line 8 can include polysilicon.

[0082] In an embodiment of this application, the sidewall can be an ON structure, that is, a silicon oxide layer / silicon nitride layer, with an oxide layer provided near the control gate 402, or an ONO structure, that is, a silicon oxide layer / silicon nitride layer / silicon oxide layer.

[0083] S503: Perform patterning on the initial semiconductor structure to remove a preset area of the floating gate material layer 10, form a floating gate 401 on the insulating layer 2, and obtain an intermediate semiconductor structure; the control gate 402 is located on the floating gate 401.

[0084] In an embodiment of the present application, the floating gate 401 includes a first side surface and a second side surface relative to each other; the first side surface and the second side surface are arranged along a first direction; the second side surface is close to the erase gate region 5; the distance between the second side surface and the side surface of the control gate 402 close to the second side surface is greater than the distance between the first side surface and the side surface of the control gate 402 close to the first side surface; that is, by designing the floating gate 401 into an asymmetric structure, that is, the area close to the erase gate region 5 is wider, the tunneling oxide layer 6 between the floating gate 401 and the erase gate in the subsequent preparation process can be designed to be a structure thicker than the insulating layer 2, so that when performing an erase operation, a smaller voltage can be used to achieve it, and the reliability of the electron penetration channel is also improved.

[0085] In some feasible embodiments, in step S503, the initial semiconductor structure is patterned to remove the preset area of ​​the floating gate material layer 10, and the floating gate 401 is formed on the insulating layer 2. The specific implementation method of obtaining the intermediate semiconductor structure may include: the initial semiconductor structure is patterned to remove the second oxide layer 11 of the first preset area 12 on the initial control gate layer 3; the first preset area 12 is located on the side of the control gate 402 away from the erase gate blank area 13; the erase gate blank area 13 is the area between the two control gates 402; the floating gate material layer 10 of the first preset area 12 and the floating gate material layer 10 of the erase gate blank area 13 are removed to form the floating gate 401 on the insulating layer 2 to obtain the intermediate semiconductor structure. Specifically, the second oxide layer 11 of the first preset area 12 can be removed by wet etching, dry etching, or a combination of the two. The following will specifically explain the removal of the second oxide layer 11 of the first preset area 12 by wet etching: by first forming a photoresist on the surface of the initial semiconductor structure, specifically, a spin coating method can be used to form a photoresist with uniform thickness on the surface of the initial semiconductor structure, and a mask with a preset pattern is placed above the initial semiconductor structure. According to the different properties of the photoresist, it is necessary to select a suitable mask. For example, positive photoresist can be removed by a developing solution after exposure, while negative photoresist is the opposite. The example of this application is an etching method of positive photoresist, as shown in 7. The black area of ​​the mask is the graphic area thereon, and light cannot pass through it, while the white area is a blank area. Light can pass through the white area of ​​the mask to react with the photoresist to undergo a curing reaction. After the photoresist is exposed according to the preset exposure parameters, it is developed and etched with a solution in sequence, so that the following can be obtained. Figure 7 In the structure shown, the second oxide layer 11 from which the photoresist is removed can be removed by a corresponding etching solution. In fact, during the etching process, the solution will also etch a portion of the silicon nitride layer near the first preset area 12, resulting in the silicon nitride layer near the first preset area 12 having a width smaller than the silicon nitride layer on the other side of the control gate 402.

[0086] Further, the residual photoresist is removed. At this time, the first sidewall of the control gate 402 is a three-layer composite structure of silicon oxide layer / silicon nitride layer / silicon oxide layer. The first sidewall is close to the erase blank area, and the erase gate blank area 13 is the area between the two control gates 402; the second sidewall of the control gate 402 opposite to the first sidewall is a two-layer composite structure of silicon oxide layer / silicon nitride layer. After etching the floating gate material layer 10 in the erase blank area, and etching the floating gate material layer 10 in the two first preset areas 12, an asymmetric floating gate 401 can be formed to obtain an intermediate semiconductor structure (such as Figure 8 structure shown).

[0087] In some feasible embodiments, while etching the floating gate material layer 10 in the blank area for erasure, the second oxide layer 11 disposed on the upper layer of the floating gate material layer 10 is also removed, that is, the floating gate material layer 10 in the first preset area 12 and the blank area for erasure is etched simultaneously. In other feasible embodiments, the floating gate material layer 10 in the blank area for erasure may be etched first, and then the floating gate material layer 10 in the two first preset areas 12, or, conversely, the floating gate material layer 10 in the two first preset areas 12 may be etched first, and then the floating gate material layer 10 in the blank area for erasure is etched, and while etching the floating gate material layer 10 in the blank area for erasure, the second oxide layer 11 disposed on the upper layer of the floating gate material layer 10 is also removed. The remaining second oxide layer 11 may be removed later as needed. According to different etching processes, the etching of the floating gate material layer 10 may specifically include the following embodiments. In some feasible embodiments, a masked dry etching process may be used to remove the floating gate material layer 10 in the blank erased area and the floating gate material layer 10 in the two first preset areas 12, that is, a barrier layer needs to be formed on the surface of the intermediate semiconductor first. In other feasible embodiments, a maskless dry etching process may be used to remove the floating gate material layer 10 in the blank erased area and the floating gate material layer 10 in the two first preset areas 12. The maskless dry etching process means that during etching, it is not necessary to form a photoresist on the surface of the intermediate semiconductor, and it is not necessary to perform exposure, development and other steps, thereby improving the etching efficiency. In other feasible embodiments, a combination of dry etching and wet etching can be used to remove the floating gate material layer 10 in the erase blank area and the floating gate material layer 10 in the two first preset areas 12; for example, dry etching can be used to first remove the second oxide layer 11 in the erase blank area, and then wet etching can be used to remove the floating gate material layer 10 in the erase blank area and the floating gate material layer 10 in the two first preset areas 12.

[0088] In the embodiment of the present application, after step S501, the method further includes: performing a first ion implantation on a preset area of ​​the substrate 1 from a first implantation surface to form a word line low resistance region 14 in the substrate 1, and obtaining Fig. 9The structure shown. The first implantation surface may be the surface of the second oxide layer 11 of the second preset area, and the second preset area is a groove area located away from the erase blank area. Optionally, the ion type for ion implantation may be P-type ions or N-type ions, and the N-type ions may be elements corresponding to Group V, such as phosphorus, arsenic or antimony; the P-type ions may include boron ions, boron fluoride ions or indium ions.

[0089] In the embodiment of the present application, after step S503, the method further includes: performing a second ion implantation on a preset area of ​​the substrate 1 from the second implantation surface to form a source line low resistance region 15 in the substrate 1, and obtaining Fig.10 The structure shown. The second implantation surface can be the surface of the second oxide layer 11 of the erased blank area. Optionally, the ion type for ion implantation can be P-type ions or N-type ions, and the N-type ions can be elements corresponding to Group V, such as phosphorus, arsenic or antimony; the P-type ions can include boron ions, boron fluoride ions or indium ions. Optionally, the process of performing the second ion implantation can also be performed between step S501 and step S503, and can be performed before the first ion implantation, or after the first ion implantation, or simultaneously.

[0090] S505: A first oxide layer and an erase gate region 5 are sequentially formed on the surface of the intermediate semiconductor structure to obtain a target semiconductor structure; the erase gate region 5 and the floating gate 401 are spaced apart along a first direction; the first direction is a direction perpendicular to the thickness direction of the substrate; a tunneling oxide layer 6 is filled between the floating gate region 4 and the erase gate region 5; the thickness of the tunneling oxide layer 6 between the floating gate 401 and the erase gate region 5 is greater than the thickness of the region of the insulating layer 2 corresponding to the floating gate 401.

[0091] In some feasible embodiments, in step S505, a first oxide layer and an erase gate region 5 are formed on the surface of the intermediate semiconductor structure to obtain a specific implementation of the target semiconductor structure may include: forming a first oxide layer on the surface of the intermediate semiconductor structure; depositing a conductive material in a first preset area 12 to form a word line 8 on the insulating layer 2; and depositing a conductive material in the erase gate blank area 13 to form an erase gate region 5 on the insulating layer 2 to obtain a target semiconductor structure (such as Figure 3 The structure shown in FIG. 1 is a block diagram of a semiconductor structure of FIG. 1 . Optionally, the conductive material may be the same material as the material of the control gate layer 3, and may specifically include polysilicon, silicon nitride, or a conductive nanocrystalline material. Optionally, the deposition process may be molecular beam epitaxy or chemical vapor deposition. Optionally, after the conductive material is deposited, the conductive material at the top of the entire intermediate semiconductor structure will be connected into one piece, so it is necessary to remove the excess conductive material by grinding, etching, or a combination of the two, and finally form a semiconductor structure of FIG. 1 . Figure 3The target semiconductor structure shown, ie, the conductive material in the first predetermined area 12 and the conductive material in the erased blank area, are independent structures.

[0092] It should be noted that, in the process of preparing the target semiconductor structure from the intermediate semiconductor structure, the relevant preparation of the logic area is also included, and the preparation of the bit line is also included as needed, and the following structure is finally obtained, namely, it includes a substrate 1, an insulating layer 2 and a control gate layer 3 stacked in sequence from bottom to top; the control gate layer 3 includes two bit lines, two floating gate regions 4, two word lines 8 and an erase gate region 5 spaced apart along a first direction, and a tunneling oxide layer 6 is filled between the floating gate region 4 and the erase gate region 5; the first direction is a direction perpendicular to the thickness direction of the substrate 1; the floating gate region 4 includes a floating gate 401 and a control gate 402 arranged from bottom to top; the arrangement of the two bit lines, the two word lines 8, the two floating gate regions 4 and the erase gate region 5 along the first direction is one bit line, one word line 8, one floating gate region 4, the erase gate region 5, another floating gate region 4, another word line 8 and another bit line. The bit line and word line 8, word line 8 and floating gate region 4, and floating gate region 4 and erase gate region 5 are all filled with an oxide layer, which may be a composite structure of one or more of silicon oxide, silicon nitride, silicon oxynitride and carbon-containing silicon oxide.

[0093] By performing the first ion implantation and the second ion implantation on the substrate 1, a word line low resistance region 14 and a source line low resistance region 15 can be formed in the substrate 1, so that Figure 4 The target semiconductor structure shown in FIG. 1 is a semiconductor structure in which the source line low resistance region 15 is located in a region near the top of the substrate 1 and corresponds to the erase gate region 5 and is used to connect to the source. In the case where the word lines 8 include two, the word line low resistance region 14 also includes two, one word line 8 low group region corresponds to each word line 8, and the word line low resistance region 14 is located in a region near the top of the substrate 1.

[0094] The thickness of the layer structure in the semiconductor structure has been mentioned in the above description of the semiconductor structure, and the preparation method of the semiconductor structure will not be described in detail.

[0095] When the semiconductor structure prepared by the above method is subsequently erased and written, electrons are realized by penetrating different channels, which reduces the number of electron penetrations of the insulating layer 2 and effectively improves the life of the semiconductor structure. In addition, by asymmetric etching of the floating gate 401, an asymmetric floating gate 401 is obtained, which makes it possible to achieve the erase operation with a smaller erase voltage, further improving the reliability of the structure.

[0096] The embodiment of the present application also provides a semiconductor memory, and the memory device includes the above-mentioned semiconductor structure. In the semiconductor structure, it includes a floating gate region 4 and an erase gate region 5 that are arranged laterally at intervals, and a tunneling oxide layer 6 is filled between the floating gate region 4 and the erase gate region 5, and the floating gate region 4 and the erase gate region 5 are both located on the insulating layer 2 on the substrate 1, so that the electrons during the erasing and writing operations are realized through different oxide layer channels, thereby improving the reliability of the semiconductor structure, and the thickness of the tunneling oxide layer is greater than the thickness of the region of the insulating layer 2 corresponding to the floating gate 401, so that the semiconductor structure can use a smaller erase voltage to realize the erase operation. Therefore, the memory device also has similar advantages.

[0097] An embodiment of the present application provides an electronic device, and the electronic device includes the semiconductor memory as described above.

[0098] The electronic device described in the embodiments of the present application may be any electronic product or device such as a smart phone, a desktop computer, a tablet computer, a laptop computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, an intelligent voice interaction device, a smart home appliance, a smart wearable device, a vehicle-mounted terminal device, or the like.

[0099] The electronic device described in the embodiment of the present application comprises the above-mentioned semiconductor memory, and the semiconductor memory comprises the above-mentioned semiconductor structure, in which the floating gate region 4 and the erase gate region 5 are arranged laterally and spaced apart, and a tunneling oxide layer 6 is filled between the floating gate region 4 and the erase gate region 5, and the floating gate region 4 and the erase gate region 5 are both located on the insulating layer 2 on the substrate 1, so that the electrons during the erasing and writing operations are realized through different oxide layer channels, thereby improving the reliability of the semiconductor structure, and the thickness of the tunneling oxide layer is greater than the thickness of the region of the insulating layer 2 corresponding to the floating gate 401, so that the semiconductor structure can use a smaller erasing voltage to realize the erasing operation. Therefore, the electronic device also has similar advantages.

[0100] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0101] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0102] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0103] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A semiconductor structure, It is characterized in that It includes a substrate, an insulating layer and a control gate layer stacked sequentially from bottom to top; The control gate layer includes a floating gate region and an erase gate region spaced apart along a first direction, and a tunneling oxide layer is filled between the floating gate region and the erase gate region; the first direction is a direction perpendicular to the thickness direction of the substrate; The floating gate region includes a floating gate and a control gate arranged from bottom to top; The thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the insulating layer in a region corresponding to the floating gate.

2. The semiconductor structure according to claim 1, It is characterized in that The floating gate includes a first side surface and a second side surface opposite to each other; the first side surface and the second side surface are arranged along the first direction; the second side surface is close to the erase gate region; A distance between the second side surface and a side surface of the control gate close to the second side surface is greater than a distance between the first side surface and a side surface of the control gate close to the first side surface.

3. The semiconductor structure according to claim 2, It is characterized in that The floating gate includes a first floating gate region, a second floating gate region and a third floating gate region which are sequentially arranged and connected along the first direction; The second floating gate region corresponds to the position of the control gate; The width of the first floating gate region is greater than the width of the third floating gate region, or the width of the first floating gate region is less than the width of the third floating gate region.

4. The semiconductor structure according to claim 3, It is characterized in that A top of the second floating gate region is at a preset distance from a top of the first floating gate region and a top of the third floating gate region.

5. The semiconductor structure according to claim 1, It is characterized in that comprising two floating gate regions; The erase gate region is located between the two floating gate regions.

6. The semiconductor structure according to any one of claims 1 to 5, It is characterized in that The erase gate region includes a first structure, a second structure and a third structure which are sequentially arranged and connected from bottom to top; The width of the first structure is smaller than the width of the third structure; The width of the second structure gradually increases along the arrangement direction; An interlayer dielectric layer is provided between the floating gate and the control gate; the interlayer dielectric layer and the second structure are located in the same plane.

7. The semiconductor structure according to claim 3, It is characterized in that The tunneling oxide layer includes a first oxide structure and a second oxide structure; The first oxide structure is located between the floating gate and the erase gate; The second oxidation structure is located between the control gate and the erase gate, and the second oxidation structure is a composite structure.

8. The semiconductor structure according to claim 7, It is characterized in that The thickness of the first oxide structure is greater than the thickness of the first region of the insulating layer; the first region is a region corresponding to the projection of the floating gate on the insulating layer.

9. The semiconductor structure according to claim 7, It is characterized in that The control gate layer further includes a word line arranged along the first direction and having a preset interval with the floating gate region; A gap oxide layer is filled between the floating gate region and the word line; the thickness of the gap oxide layer is greater than the thickness of the first oxide structure; The first side surface is close to the word line.

10. A method for preparing a semiconductor structure, It is characterized in that The following steps are involved: An initial semiconductor structure is provided; the initial semiconductor structure comprises a substrate, an insulating layer and an initial control gate layer stacked in sequence from bottom to top; the initial control gate layer comprises a floating gate material layer and a control gate located on the floating gate material layer; sidewalls are respectively provided on opposite sides of the control gate; Performing a patterning process on the initial semiconductor structure to remove a preset area of ​​the floating gate material layer, forming a floating gate on the insulating layer, and obtaining an intermediate semiconductor structure; The control gate is located on the floating gate; A first oxide layer and an erase gate region are sequentially formed on the surface of the intermediate semiconductor structure to obtain a target semiconductor structure; the erase gate region and the floating gate are spaced apart along a first direction; the first direction is a direction perpendicular to the thickness direction of the substrate; a tunneling oxide layer is filled between the floating gate region and the erase gate region; the thickness of the tunneling oxide layer between the floating gate and the erase gate region is greater than the thickness of the region of the insulating layer corresponding to the floating gate.

11. The preparation method according to claim 10, It is characterized in that The surface of the initial control gate layer is provided with a second oxide layer; the initial control gate layer includes two control gates spaced apart along the first direction; the initial semiconductor structure is patterned to remove a preset area of ​​the floating gate material layer, and a floating gate is formed on the insulating layer to obtain an intermediate semiconductor structure, including: The initial semiconductor structure is patterned to remove the second oxide layer in a first preset area on the initial control gate layer; the first preset area is located on a side of the control gate away from the erase gate blank area; the erase gate blank area is an area between two control gates; The floating gate material layer in the first preset area and the floating gate material layer in the erase gate blank area are removed to form a floating gate on the insulating layer to obtain the intermediate semiconductor structure.

12. The preparation method according to claim 11, It is characterized in that The step of forming a first oxide layer and erasing a gate region on the surface of the intermediate semiconductor structure to obtain a target semiconductor structure includes: forming the first oxide layer on the surface of the intermediate semiconductor structure; A conductive material is deposited in the first preset area to form a word line on the insulating layer; and a conductive material is deposited in the erase gate blank area to form an erase gate area on the insulating layer to obtain the target semiconductor structure.

13. A semiconductor memory, It is characterized in that The memory device comprises the semiconductor structure according to any one of claims 1 to 9.

14. An electronic device, It is characterized in that The electronic device includes the semiconductor memory according to claim 13.

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