Ferroelectric capacitor storage unit, ferroelectric memory and electronic equipment

Abstract

The invention provides a ferroelectric capacitor storage unit, a ferroelectric tunnel junction storage unit, a ferroelectric transistor storage unit, a ferroelectric memory and electronic equipment, relates to the technical field of electronics, and aims to solve the problem of poor durability of data stored by ferroelectricity. The ferroelectric capacitor storage unit comprises a transistor and a ferroelectric capacitor, the ferroelectric capacitor comprises a first electrode layer, a second electrode layer and a first ferroelectric layer, and the first ferroelectric layer is arranged between the first electrode layer and the second electrode layer; the first ferroelectric layer is made of an anion-doped hafnium oxide-based ferroelectric material; the transistor is electrically connected to the first electrode layer. The ferroelectric capacitor storage unit is used for storing data.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a ferroelectric capacitor storage unit, a ferroelectric tunnel junction storage unit, a ferroelectric transistor storage unit, a ferroelectric memory and an electronic device. Background Art

[0002] Ferroelectric memory stores data based on the polarization state of ferroelectric materials. Since ferroelectric memory completes the writing action by controlling the polarization state of ferroelectric materials in the ferroelectric memory through an external electric field, ferroelectric memory devices have the advantages of low power consumption, high read and write speeds, radiation resistance and non-volatility, and are expected to be used to build a new generation of memory chips.

[0003] Compared with traditional ferroelectric materials, the thickness of hafnium oxide-based ferroelectric materials can be reduced to 10 nanometers or even sub-10 nanometers, which can achieve high-density integration and even three-dimensional integration. Therefore, hafnium oxide-based ferroelectric materials have their unique advantages in building ultra-high-density memory chips. In addition, the preparation process of hafnium oxide-based ferroelectric materials is also well compatible with mature silicon-based semiconductor processes. Therefore, storage cells made of hafnium oxide-based ferroelectric materials are expected to become the core units of new ferroelectric memory in the future.

[0004] However, during repeated use, memory cells made of hafnium oxide-based ferroelectric materials are prone to produce conductive channels that penetrate the hafnium oxide-based ferroelectric film, causing the hafnium oxide-based ferroelectric film to be broken down, limiting the durability of the memory cell, and further affecting the service life of the ferroelectric memory prepared by the memory cell. Therefore, how to improve the service life of memory cells prepared by hafnium oxide-based ferroelectric materials is an urgent problem to be solved. Summary of the invention

[0005] The present application provides a ferroelectric capacitor storage unit, a ferroelectric tunnel junction storage unit, a ferroelectric transistor storage unit, a ferroelectric memory and an electronic device, which are used to solve the problem of poor durability of data storage using ferroelectricity.

[0006] To achieve the above purpose, this embodiment adopts the following technical solutions:

[0007] In a first aspect, the present application provides a ferroelectric capacitor storage unit, which includes a transistor and a ferroelectric capacitor, the ferroelectric capacitor includes a first electrode layer, a second electrode layer and a first ferroelectric layer, the first ferroelectric layer is arranged between the first electrode layer and the second electrode layer; the first ferroelectric layer is an anion-doped hafnium oxide-based ferroelectric material; the transistor is electrically connected to the first electrode layer.

[0008] In the ferroelectric capacitor of the ferroelectric capacitor storage unit, the first ferroelectric layer is arranged to space the first electrode layer and the second electrode layer, and the first ferroelectric layer is an anion-doped hafnium oxide-based ferroelectric material. In the first ferroelectric layer, the anions have a strong binding force with the metal ions in the hafnium oxide-based ferroelectric material, so the anions can distort the lattice in the hafnium oxide-based ferroelectric material, strengthen the bonds between the oxygen ions and the atoms around the oxygen ions, increase the generation energy of oxygen vacancy defects, reduce the rate of oxygen vacancy defect generation, inhibit the enrichment of oxygen vacancy defects near the grain boundary or domain boundary, delay or avoid the formation of a current path in the first ferroelectric layer, thereby delaying or avoiding the breakdown failure of the ferroelectric capacitor, improving the durability of the ferroelectric capacitor, and further improving the service life of the ferroelectric capacitor storage unit.

[0009] In a possible implementation of the first aspect, the first ferroelectric layer is in contact with both the first electrode layer and the second electrode layer. In this way, the only film layer providing ferroelectricity between the first electrode layer and the second electrode layer is the first ferroelectric layer. Therefore, when the total thickness of the ferroelectric capacitor remains unchanged, the thickness of the first ferroelectric layer of the ferroelectric capacitor in the ferroelectric capacitor storage unit is increased. Since the first ferroelectric layer can improve the durability of the ferroelectric capacitor, the service life of the ferroelectric capacitor storage unit can be further improved.

[0010] In a possible implementation of the first aspect, the ferroelectric capacitor further includes a second ferroelectric layer, the second ferroelectric layer is disposed between the first electrode layer and the second electrode layer, and the second ferroelectric layer is a hafnium oxide-based ferroelectric material that is not anion-doped. In this way, the second ferroelectric layer of the hafnium oxide-based ferroelectric material that is not anion-doped has a more stable ferroelectric phase, and therefore, arranging the first ferroelectric layer and the second ferroelectric layer between the first electrode layer and the second electrode layer can make the ferroelectric capacitor have a stable ferroelectric phase while improving the durability of the ferroelectric capacitor.

[0011] In a possible implementation of the first aspect, the first ferroelectric layer includes a first sublayer and a second sublayer, and the second ferroelectric layer is disposed between the first sublayer and the second sublayer. Both the first sublayer and the second sublayer can delay or block the current path caused by oxygen vacancy defects, so that the first sublayer and the second sublayer can delay or block the formation of the current path from both sides of the second ferroelectric layer, further improving the durability of the ferroelectric capacitor. At the same time, when the second ferroelectric layer is disposed between the first sublayer and the second sublayer, the first sublayer separates the second ferroelectric layer from the first electrode layer or the second electrode layer, and the second sublayer separates the second ferroelectric layer from the second electrode layer or the first electrode layer, thereby reducing the influence of the first electrode layer and the second electrode layer on the formation of oxygen vacancy defects in the second ferroelectric layer.

[0012] In a possible implementation of the first aspect, the thickness of the first sublayer and the second sublayer are both 1 nm to 5 nm. In this way, the thickness of the first sublayer and the second sublayer can be limited, and in a ferroelectric capacitor of the same thickness, the thickness of the second ferroelectric layer can be increased, thereby improving the ferroelectric stability of the ferroelectric capacitor.

[0013] In a possible implementation of the first aspect, the thickness of the first sublayer is equal to that of the second sublayer, so that the possibility of forming defects in the first sublayer and the second sublayer is almost equal, that is, the possibility of forming current paths on both sides of the second ferroelectric layer is almost equal.

[0014] In a possible implementation of the first aspect, the ratio of the thickness of the second ferroelectric layer to the thickness of the first sublayer or the second sublayer is greater than or equal to 2. In this way, the thickness of the second ferroelectric layer can be greater than or equal to the sum of the thicknesses of the first sublayer and the second sublayer, thereby ensuring the ferroelectric stability of the ferroelectric capacitor.

[0015] In a possible implementation of the first aspect, the second ferroelectric layer includes a third sublayer and a fourth sublayer, and the first ferroelectric layer is disposed between the third sublayer and the fourth sublayer. In this way, the first ferroelectric layer disposed between the third sublayer and the fourth sublayer can also delay or block the formation of a current path between the barrier layer and the second electrode layer, thereby preventing the ferroelectric capacitor from being broken down and failing.

[0016] In a possible implementation of the first aspect, the ferroelectric capacitor includes a plurality of first ferroelectric layers and a plurality of second ferroelectric layers, and the plurality of first ferroelectric layers and the plurality of second ferroelectric layers are alternately arranged between the first electrode layer and the second electrode layer. In this way, the plurality of first ferroelectric layers can be arranged so that adjacent second ferroelectric layers are separated by the first ferroelectric layers, thereby reducing the possibility that defects formed in the plurality of second ferroelectric layers form a current path between the first electrode layer and the second electrode layer.

[0017] In a possible implementation of the first aspect, the anions are one or more of fluorine (F) ions, chloride (Cl) ions, bromine (Br) ions, and carbon (C) ions. Thus, after the hafnium oxide-based ferroelectric material is doped with the anions, the lattice of the hafnium oxide-based ferroelectric material can be distorted, thereby increasing defect generation energy.

[0018] In a possible implementation of the first aspect, in the first ferroelectric layer, the ratio of the number of anions to the number of oxygen ions in the hafnium oxide-based ferroelectric material is (0.005-0.1): 1. In this way, the number of lattices in which the hafnium oxide-based ferroelectric material is distorted can be ensured, the number of defects per unit area in the hafnium oxide-based ferroelectric material can be reduced, the formation of a current path can be slowed down or avoided, and the durability can be improved.

[0019] In a possible implementation of the first aspect, the hafnium oxide-based ferroelectric material includes a main material and a doping material, wherein the main material is hafnium oxide (HfOx ) hafnium zirconium oxide (HfZrO x ) or hafnium oxide (HfO x ) and hafnium zirconium oxide (HfZrO x ), where x is 1 or 2, and the doping material includes at least one of potassium (K), scandium (Sc), rubidium (Rb), selenium (Se), tin (Sn), magnesium (Mg), calcium (Ca), barium (Ba), indium (In), vanadium (V), niobium (Nb), lanthanum (La), titanium (Ti), yttrium (Y), strontium (Sr), gadolinium (Gd), silicon (Si), and aluminum (Al). Thus, by adjusting the coordination number of oxygen ions and the local chemical stress of oxygen ions in the host material through the ionic radius of the doping material, the hafnium oxide-based ferroelectric material has a stable ferroelectric phase.

[0020] In a second aspect, the present application provides a ferroelectric tunnel junction memory cell, including: a transistor and a ferroelectric tunnel junction, the ferroelectric tunnel junction includes a first electrode layer, a second electrode layer, and a first ferroelectric layer, and the first ferroelectric layer is disposed between the first electrode layer and the second electrode layer; the first ferroelectric layer is an anion-doped hafnium oxide-based ferroelectric material; the transistor is electrically connected to the first electrode layer. For the same reason as in the first aspect, when the first ferroelectric layer is an anion-doped hafnium oxide-based ferroelectric material, the breakdown failure of the ferroelectric tunnel junction can be delayed or avoided, the durability of the ferroelectric tunnel junction can be improved, and further the service life of the ferroelectric tunnel junction memory cell can be improved.

[0021] In a possible implementation manner of the second aspect, the ferroelectric tunnel junction further includes a second ferroelectric layer, the second ferroelectric layer is disposed between the first electrode layer and the second electrode layer, and the second ferroelectric layer is a hafnium oxide-based ferroelectric material without anion doping. Thus, the second ferroelectric layer of the hafnium oxide-based ferroelectric material without anion doping has a more stable ferroelectric phase. Therefore, setting the first ferroelectric layer and the second ferroelectric layer between the first electrode layer and the second electrode layer can make the ferroelectric tunnel junction have a stable ferroelectric phase while improving the durability of the ferroelectric tunnel junction.

[0022] In a possible implementation manner of the second aspect, the first ferroelectric layer includes a first sub-layer and a second sub-layer, and the second ferroelectric layer is disposed between the first sub-layer and the second sub-layer. Both the first sub-layer and the second sub-layer can delay or block the current path caused by oxygen vacancy defects. Thus, the first sub-layer and the second sub-layer can delay or block the formation of the current path from both sides of the second ferroelectric layer, further improving the durability of the ferroelectric capacitor.

[0023] In a possible implementation manner of the second aspect, the anion is one or more of fluorine (F) ions, chlorine (Cl) ions, bromine (Br) ions, and carbon (C) ions. Thus, after doping the hafnium oxide-based ferroelectric material with the above anions, the lattice of the hafnium oxide-based ferroelectric material can be distorted, increasing the defect formation energy.

[0024] In a third aspect, the present application provides a ferroelectric transistor storage unit, comprising a substrate, the substrate having a source region, a drain region and a channel, the channel being arranged between the source region and the drain region; the substrate also comprises a dielectric layer, a first ferroelectric layer and a gate layer sequentially arranged on the channel, the first ferroelectric layer being an anion-doped hafnium oxide-based ferroelectric material.

[0025] In the ferroelectric transistor storage unit, the dielectric layer and the gate layer are separated by a first ferroelectric layer, and the first ferroelectric layer is an anion-doped hafnium oxide-based ferroelectric material, thereby delaying or preventing the ferroelectric capacitor from being broken down and failing, improving the durability of the first ferroelectric layer, and thereby improving the service life of the ferroelectric transistor storage unit.

[0026] In a possible implementation of the third aspect, a second ferroelectric layer is further included, the second ferroelectric layer is disposed between the dielectric layer and the gate layer, and the second ferroelectric layer is a hafnium oxide-based ferroelectric material that is not anion-doped. In this way, the second ferroelectric layer of the hafnium oxide-based ferroelectric material that is not anion-doped has a more stable ferroelectric phase, so that the ferroelectric transistor storage unit can have a stable ferroelectric phase while improving the service life of the ferroelectric transistor storage unit.

[0027] In a possible implementation of the third aspect, the first ferroelectric layer includes a first sublayer and a second sublayer, and the second ferroelectric layer is disposed between the first sublayer and the second sublayer. The first sublayer and the second sublayer can both delay or block the current path caused by the oxygen vacancy defect, so that the first sublayer and the second sublayer can delay or block the formation of the current path from both sides of the second ferroelectric layer, further improving the service life of the ferroelectric transistor storage unit.

[0028] In a possible implementation of the third aspect, the anions are one or more of fluorine (F) ions, chloride (Cl) ions, bromine (Br) ions, and carbon (C) ions. Thus, after the hafnium oxide-based ferroelectric material is doped with the anions, the lattice of the hafnium oxide-based ferroelectric material can be distorted, thereby increasing defect generation energy.

[0029] In a fourth aspect, the present application provides a ferroelectric memory, comprising a controller and a ferroelectric capacitor storage unit as described in any one of the first aspect, a ferroelectric tunnel junction storage unit as described in any one of the second aspect, or a ferroelectric transistor storage unit as described in any one of the third aspect. Since these storage units have a long service life, the ferroelectric memory also has a long service life.

[0030] In a fifth aspect, the present application provides an electronic device, comprising: a processor and a ferroelectric memory as in the fourth aspect, wherein the processor is electrically connected to the ferroelectric memory. Thus, because the ferroelectric memory of the electronic device improves durability, the durability of the electronic device is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of an electronic device provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of a ferroelectric memory provided in an embodiment of the present application;

[0033] Figure 3 is a schematic diagram of the failure of a ferroelectric capacitor;

[0034] Figure 4 for Figure 3 Schematic diagram of the variation trend of the residual polarization intensity and leakage current density of the ferroelectric layer with the number of electrical cycles;

[0035] Figure 5 A schematic diagram of a ferroelectric capacitor storage unit provided in an embodiment of the present application;

[0036] Figure 6 for Figure 5 A magnified view of a ferroelectric capacitor;

[0037] Figure 7 for Figure 6 Schematic diagram of oxygen vacancy defects generated in a ferroelectric capacitor;

[0038] Figure 8 Schematic diagram of the change of functional phase free energy of hafnium oxide-based ferroelectric materials before and after fluorine anion doping;

[0039] Fig. 9 A schematic diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0040] Fig.10 A schematic diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0041] Fig.11 A schematic diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0042] Fig.12 A schematic diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0043] Fig.13 A schematic diagram of a ferroelectric tunnel junction memory cell provided in an embodiment of the present application;

[0044] Fig.14 A schematic diagram of a ferroelectric transistor storage unit provided in an embodiment of the present application;

[0045] Fig.15 A flow chart of a method for preparing a ferroelectric capacitor storage unit provided in an embodiment of the present application;

[0046] Fig.16 A flow chart of preparing a ferroelectric layer is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by those skilled in the art in the ordinary sense. The terms "first", "second", "third" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0048] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to the change of the orientation of the chip or semiconductor packaging structure.

[0049] Figure 1 An electronic device 200 is provided in an embodiment of the present application. The electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The electronic device 200 includes a bus 205 and a system on chip (SoC) 210 connected to the bus 205.

[0050] The system on chip 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the system on chip 210 may include one or more processors, such as an application processor (application processor, AP) 211 for processing applications, a graphics processing unit (Graphics Processing Unit, GPU) 212 for processing image data, and the system on chip 210 may also include a first random access memory (Random Access Memory, RAM) 213 for caching high-speed data. The first random access memory 213 may be electrically connected to the processor of the system on chip 210, and the first random access memory 213 may be a static random access memory (Static Random Access Memory, SRAM) or an embedded flash (embedded flash, eflash), etc.

[0051] The application processor 211 , the image processing unit 212 and the first random access memory 213 may be integrated into one die, or may be separately disposed in a plurality of die.

[0052] The electronic device 200 may further include a second random access memory 220 electrically connected to the system on chip 210 via the bus 205. The second random access memory 220 may be a dynamic random access memory (DRAM). The second random access memory 220 may be used to store volatile data, such as temporary data generated by the system on chip 210. The storage capacity of the second random access memory 220 is generally greater than that of the first random access memory 213, but the reading speed is generally slower than that of the first random access memory 213.

[0053] In addition, the electronic device 200 may also include a communication chip 230 and a power management chip 240 connected to the system on chip 210 through the bus 205. The communication chip 230 can be used for processing the protocol stack, or amplifying, filtering, and other processing of analog RF signals, or realizing the above functions at the same time. The power management chip 240 can be used to power other chips. In one embodiment, the system on chip 210 and the second random access memory 220 can be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster data transmission rate between chips.

[0054] Figure 2 FIG. 3 is a schematic diagram of a ferroelectric memory 300 provided in an embodiment of the present application. In one implementation, the ferroelectric memory 300 may be as follows: Figure 1 The first random access memory 213 shown may also be the second random access memory 220. The present application does not limit the application scenario of the ferroelectric memory 300.

[0055] The ferroelectric memory 300 includes a memory array 310. The ferroelectric memory 300 also includes a controller, which may include one or more circuit structures of a decoder 320, a driver 330, a timing controller 340, a buffer 350, or an input / output driver 360.

[0056] In one embodiment, the memory array 310 includes a plurality of memory cells 400 arranged in an array, and the memory cell 400 may be a ferroelectric memory cell, that is, the ferroelectricity of the ferroelectric material is used to store data, for example, 1 bit (bit) or multiple bits of data may be stored by the polarization direction of the ferroelectric material. The memory array 310 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to a corresponding signal line. One or more of the above signal lines may be used to select a memory cell 400 to be read or written in the memory array by receiving a control level output by a controller, so as to change the polarization direction of the ferroelectric material in the memory cell 400, thereby realizing data read and write operations.

[0057] The decoder 320 is used to implement the decoding of the address of the storage unit 400. The decoder 320 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, so as to implement the access to the specified storage unit 400. The buffer 350 is used to cache the read data, for example, FIFO (first-in first-out) can be used for caching. The timing controller 340 is used to control the timing of the buffer 350, and control the driver 330 to drive the signal line in the storage array 310. The input and output driver 360 is used to drive the transmission signal, for example, drive the received data signal and drive the data signal to be sent, so that the data signal can be transmitted over a long distance. The above-mentioned storage array 310, decoder 320, driver 330, timing controller 340, buffer 350 and input and output driver 360 can be integrated into one chip, or integrated into multiple chips respectively.

[0058] The memory cell 400 may be a random memory cell formed by a ferroelectric capacitor (referred to herein as a ferroelectric capacitor memory cell), a random memory cell formed by a ferroelectric tunnel junction (referred to herein as a ferroelectric tunnel junction (FTJ) memory cell), or a random memory cell formed by a ferroelectric field effect transistor (referred to herein as a ferroelectric field effect transistor memory cell).

[0059] The key component for storing data in these different types of memory cells 400 is the ferroelectric layer. Since the preparation of hafnium oxide-based ferroelectric materials is compatible with semiconductor processes, the ferroelectric layer can be made of hafnium oxide-based ferroelectric materials. After the ferroelectric layer is used to form these memory cells, a voltage level can be applied to the ferroelectric layer when reading and writing data to the memory cells 400 to set the polarization direction of the ferroelectric layer to the polarization direction corresponding to the pre-stored data. However, as the number of read and write times increases, oxygen vacancy defects will continue to be generated in the hafnium oxide-based ferroelectric material constituting the ferroelectric layer.

[0060] In some embodiments, in order to apply a voltage level to the ferroelectric layer, an electrode layer may be provided on one or both sides of the ferroelectric layer. In order to form a good contact with the ferroelectric layer, the electrode layer may directly contact the ferroelectric layer. When the electrode layer is made of a metal material, since the metal material has a strong ability to bind oxygen, during the continuous reading and writing process of the storage unit, the electrode layer may also take away oxygen from the ferroelectric layer 110, thereby exacerbating the formation of oxygen vacancy defects.

[0061] In addition, in some embodiments, in order to increase the ferroelectric stability of the hafnium oxide-based ferroelectric material, a doping material such as a metal material or a semiconductor material may be doped into the hafnium oxide-based ferroelectric material. However, the binding ability of these doping materials with oxygen is weaker than that of hafnium with oxygen (except Si). Although the ferroelectric phase can be stabilized after doping, as the number of read and write operations increases, oxygen vacancy defects are more likely to occur compared to undoped hafnium oxide-based ferroelectric materials.

[0062] The following describes the process of ferroelectric layer failure by taking a ferroelectric capacitor as an example.

[0063] Figure 3 The ferroelectric capacitor 100 failure schematic diagram in the ferroelectric capacitor storage unit, the ferroelectric capacitor 100 comprises a first electrode layer 120, a second electrode layer 130 and a ferroelectric layer 110, and the ferroelectric layer 120 is arranged between the first electrode layer 120 and the second electrode layer 130. In the process of continuously reading and writing data to the storage unit, oxygen vacancy defects 140 will be generated in the ferroelectric layer 110 of the ferroelectric capacitor 100, and the oxygen vacancy defects 140 will gradually be enriched in the grain boundary of the ferroelectric phase and the non-ferroelectric phase or the domain boundary between adjacent ferroelectric domains after formation. Due to the presence of oxygen vacancy defects 140, trap energy levels appear in the system electronic structure, and the trap energy levels are not completely occupied by electrons, so external electrons can transition between these trap energy levels. When a large number of oxygen vacancy defects 140 exist at the grain boundary or domain boundary of the ferroelectric layer 110, a large number of traps will become an electronic channel, and under the action of the voltage level, the ferroelectric layer 110 will have leakage current phenomenon and be broken down, and the performance of the ferroelectric layer 110 will degrade or fail.

[0064] Figure 4Schematic diagram of the variation trend of the residual polarization intensity and leakage current density of the ferroelectric layer with the number of electrical cycles, wherein an electrical cycle refers to applying a voltage level in one direction to the ferroelectric capacitor 100 and then applying a voltage level in the opposite direction to the previous direction. For example, an electrical cycle may be applying a voltage level in a direction from the first electrode layer 120 to the second electrode layer 130 to the ferroelectric capacitor 100, and then applying a voltage level in a direction from the second electrode layer 130 to the first electrode layer 120. Because when a storage unit is written, when the written data is different from the data stored in the previous state, a voltage level is applied to the ferroelectric layer 110 to change the polarization direction of the ferroelectric layer 110. Therefore, the number of electrical cycles can be simply considered to be the number of read and write operations, and the number of electrical cycles is proportional to the service life of the ferroelectric capacitor 100.

[0065] The remanent polarization intensity is used to characterize the ferroelectricity of the ferroelectric layer 110 . In the present application, the remanent polarization intensity is obtained by measuring the amount of electricity per unit area. Figure 4 In the residual polarization intensity curve, the electrical cycle is about 10 9 It then rises sharply. Obviously, it is not caused by bound charges that generate residual polarization intensity, but by free charges in the ferroelectric layer 110. That is, there are a large number of free charges in the ferroelectric layer 110. At this time, the ferroelectric layer 110 has been broken down by the current and failed. In addition, it can be seen from the leakage current density curve that the leakage current gradually increases with the increase of the number of electrical cycles. When the number of electrical cycles reaches about 10 7 After that, the leakage current begins to increase sharply, and it can be considered that the ferroelectric layer 110 is broken down.

[0066] It is easy to understand that the same problem also exists in FTJ memory cells and ferroelectric transistor memory cells, resulting in a shorter service life of the memory cells.

[0067] In order to increase the service life of the storage unit 400, the present application also provides a ferroelectric capacitor storage unit, a FTJ storage unit and a ferroelectric transistor storage unit.

[0068] Figure 5 1 is a schematic diagram of the structure of a ferroelectric capacitor storage unit 410 provided in an embodiment of the present application. The ferroelectric capacitor storage unit 410 includes a transistor T and a ferroelectric capacitor 100. The ferroelectric capacitor 100 includes a first ferroelectric layer 111, a first electrode layer 120 and a second electrode layer 130. The first ferroelectric layer 111 is arranged between the first electrode layer 120 and the second electrode layer 130. The source or drain of the transistor T is electrically connected to the first electrode layer 120, and can be used to control whether a voltage level is applied to the ferroelectric capacitor 100. The transistor T can be a transistor of a type such as a MOS (Metal Oxide Semiconductor) tube.

[0069] When reading data from the ferroelectric capacitor storage unit 410, the transistor T is turned on, and a read level is applied to the first ferroelectric layer 111 in the ferroelectric capacitor 100 through the first electrode layer 120 and the second electrode layer 130. The read level can be in the form of an electric pulse. If the direction of the electric field generated between the first electrode layer 120 and the second electrode layer 130 by the read level is the same as the polarization direction of the first ferroelectric layer 111, the polarization direction of the first ferroelectric layer 111 remains unchanged; if it is the opposite, the polarization direction of the first ferroelectric layer 111 will be reversed; in these two cases, there is a difference in the electrical signal output by the ferroelectric capacitor 100, and the polarization direction of the first ferroelectric layer 111 can be determined by the difference, and the data stored in the ferroelectric capacitor storage unit 410 can be obtained. In addition, since the polarization direction of the first ferroelectric layer 111 is consistent with the direction of the magnetic field generated by the read level after the data is read out, in some cases, the data needs to be rewritten after reading the data.

[0070] When writing data to the ferroelectric capacitor storage unit 410, the transistor T is turned on and a voltage level is applied between the first electrode layer 120 and the second electrode layer 130. When the directions of the voltage levels applied between the first electrode layer 120 and the second electrode layer 130 are different, electric fields with different directions can be generated between the first electrode layer 120 and the second electrode layer 130, and the electric field can make the polarization direction of the ferroelectric layer 110 the same as that of the ferroelectric layer 110, thereby controlling the polarization direction of the ferroelectric layer 110. The different polarization directions of the ferroelectric layer 110 can be used to indicate that the stored data is "0" or "1".

[0071] It should be noted that in Figure 5 Only the 1T1C (1Transistor 1Capacitor) storage unit architecture is introduced. In some implementations, the ferroelectric capacitor storage unit may also be a 1TnC, 2TnC or other storage architecture.

[0072] In some embodiments, in order to improve the performance of the ferroelectric capacitor 100, other non-ferroelectric film layers, such as buffer layers, may be provided between the first ferroelectric layer 111 and the first electrode layer 120 and the second electrode layer 130, respectively, and this application does not impose any limitation on this.

[0073] The material of the first electrode layer 120 may be metal, for example, titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), ruthenium oxide (RuO), iridium oxide (IrO), indium tin oxide (ITO), etc. The first electrode layer 120 may also be non-metal, for example, it may be P-type heavily doped or N-type heavily doped silicon.

[0074] In some embodiments, in order to obtain a ferroelectric capacitor 100 with strong ferroelectricity, the first electrode layer 120 may be a clamping electrode. In the embodiment of the present application, the electrode whose absolute value of the difference between the thermal expansion coefficient and the thermal expansion coefficient of hafnium oxide is less than the difference threshold is called the clamping electrode. The difference threshold can be set according to the requirements, for example, the difference threshold can be ±1×10 -6 / ℃.

[0075] During the annealing and crystallization of hafnium oxide, the clamping electrode will expand and contract due to temperature changes. During the expansion and contraction of the clamping electrode, tensile stress will be generated, and the tensile stress will help the hafnium oxide unit cell in the ferroelectric barrier layer to transform from symmetry to asymmetry. In addition, the smaller the absolute value of the difference between the thermal expansion coefficient of the clamping electrode and the thermal expansion coefficient of hafnium oxide, the more the tensile stress generated during the expansion and contraction of the clamping electrode will help to form asymmetric hafnium oxide unit cells. The use of the clamping electrode can obtain more asymmetric hafnium oxide unit cells; the more asymmetric hafnium oxide unit cells there are, the stronger the ferroelectricity of the first electrode layer 120 is. Therefore, the ferroelectricity of the first electrode layer 120 is higher, and the corresponding ferroelectric capacitor has higher ferroelectricity.

[0076] Furthermore, in order to obtain a ferroelectric capacitor with good conductivity, good mechanical properties and suitable for micro-nano processing technology, in some feasible implementations, the clamping electrode can be a titanium nitride (TiN) electrode, a tungsten (W) electrode, a ruthenium dioxide (RuO 2 )electrode.

[0077] It is easy to understand that the second electrode layer 130 can be made of the same material as the first electrode layer 120, or can be made of a different material from the first electrode layer 120. In order to obtain a ferroelectric capacitor with stronger ferroelectricity, the second electrode layer 130 can also be a clamping electrode.

[0078] Figure 6 It is an enlarged view of the ferroelectric capacitor 100 in the ferroelectric capacitor storage unit 410. The first ferroelectric layer 111 is a negative ion-doped hafnium oxide-based ferroelectric material.

[0079] The hafnium oxide-based ferroelectric material includes a main material and a doping material. The main material is an oxide containing hafnium, for example, hafnium oxide (HfO x ), hafnium zirconium oxide (HfZrO x ) or hafnium oxide (HfO x ) and hafnium zirconium oxide (HfZrO x ), wherein x is 1 or 2. Hafnium oxide (HfO x ) and hafnium zirconium oxide (HfZrO x ) can also be expressed as Hf yZr(1 - y)O, where 0 < y < 1. By doping the host material, the ferroelectric phase of the host material can be stabilized, enabling the host material to have stable ferroelectricity. The doping material can be a metal material or a semiconductor material. For example, the doping material can be at least one of potassium (K), scandium (Sc), rubidium (Rb), selenium (Se), tin (Sn), magnesium (Mg), calcium (Ca), barium (Ba), indium (In), vanadium (V), niobium (Nb), lanthanum (La), titanium (Ti), yttrium (Y), strontium (Sr), gadolinium (Gd), silicon (Si), aluminum (Al). That is to say, one doping material can be doped into hafnium oxide, or multiple doping materials can be doped simultaneously. When multiple doping materials are doped, it is co - doping of multiple doping materials. After doping the above - mentioned doping materials, the coordination number of oxygen ions and the local chemical stress of oxygen ions in the host material can be adjusted by the ionic radius of the doping material to stabilize the ferroelectric phase.

[0080] In some embodiments, the doped anion can be one or more of fluoride (F) ion, chloride (Cl) ion, bromide (Br) ion, nitrogen (N) ion, carbon (C) ion. That multiple anions can be the aforementioned anions means that multiple anions can be doped simultaneously in the hafnium - based ferroelectric material. For example, fluoride (F) ion and chloride (Cl) ion are doped simultaneously.

[0081] In some embodiments, the doping concentration of the anion can be expressed by the number ratio of the above - doped anion in the first ferroelectric layer 111 to the oxygen ions in the hafnium - based ferroelectric material. Specifically, in the first ferroelectric layer 111, the range of the number ratio of the anion to the oxygen ions in the hafnium - based ferroelectric material is (0.005 - 0.1):1. For example, it can be 0.005:1, 0.01:1, 0.05:1, or 0.1:1.

[0082] As Figure 7 shown, in the first ferroelectric layer 111 formed after anion doping, the binding force between the anion and the metal ions in the hafnium - based ferroelectric material is strong. Therefore, the anion can distort the lattice in the hafnium - based ferroelectric material, strengthen the bond between the oxygen ions and the surrounding atoms, increase the formation energy of the oxygen vacancy defect 140, thereby reducing the defect generation rate, inhibiting the enrichment of the oxygen vacancy defect 140 near the grain boundary or domain boundary, and thus slowing down or avoiding the formation of a current path in the ferroelectric layer 110, improving the durability of the ferroelectric capacitor 100.

[0083] To illustrate that the hafnium-based ferroelectric material doped with anions has improved durability compared to the hafnium-based ferroelectric material without anion doping, please refer to Table 1. Table 1 shows the defect formation energies of oxygen ions and F ions in the hafnium-based ferroelectric material doped with fluorine anions and the defect formation energy of oxygen ions in the hafnium-based ferroelectric material without anion doping, calculated according to the first-principles theory. The doping concentration of fluorine anions is 0.01:1. It is easy to understand that in the hafnium-based ferroelectric material doped with anions, in addition to oxygen vacancy defects, fluorine vacancy defects may also be generated. Specifically, the defect formation energy of oxygen vacancies (denoted as V O @HZO) in the hafnium-based ferroelectric material without anion doping is 5.89 eV; the defect formation energy of oxygen vacancies (denoted as V O @HZOF) in the hafnium-based ferroelectric material doped with fluorine anions is 6.12 eV; the defect formation energy of fluorine vacancies (denoted as V F @HZOF) in the hafnium-based ferroelectric material doped with fluorine anions is 6.21 eV. It can be seen that both the defect formation energy of oxygen vacancies and the defect formation energy of fluorine vacancies in the hafnium-based ferroelectric material doped with fluorine anions are higher than the defect formation energy of oxygen vacancies in the hafnium-based ferroelectric material without fluorine anion doping. Therefore, doping with fluorine anions can reduce the defect concentration and improve the durability of the ferroelectric capacitor 100.

[0084] Table 1

[0085] Defect Type <![CDATA[V O @HZO]]> <![CDATA[V O @HZOF]]> <![CDATA[V F @HZOF]]> Defect generation energy 5.89eV 6.12eV 6.21eV

[0086] Meanwhile, Figure 8 shows the change in the free energy of the functional phase of the hafnium-based ferroelectric material before and after doping with fluorine anions obtained from theoretical calculations. Similarly, the doping concentration of fluorine anions is 0.01:1. Among them, the functional phase refers to the orthorhombic phase with ferroelectricity and the antiferroelectric phase (i.e., the tetragonal phase) that can be transformed into the ferroelectric orthorhombic phase. From Figure 8 it can be seen that the free energy of the ferroelectric phase of the hafnium-based ferroelectric material without anion doping is 77 meV / f.u., and the free energy of the antiferroelectric phase is 136 meV / f.u.; while the free energy of the ferroelectric phase of the hafnium-based ferroelectric material doped with fluorine anions is 65 meV / f.u., and the free energy of the antiferroelectric phase is 120 meV / f.u. That is to say, after doping with fluorine anions, both the free energy of the ferroelectric phase and the free energy of the antiferroelectric phase of the hafnium-based ferroelectric material decrease. The decrease in free energy can improve the stability of the hafnium-based ferroelectric material, which is also beneficial to improving the durability of the ferroelectric capacitor 100.

[0087] The anion-doped hafnium oxide-based ferroelectric material may be formed by an atomic layer deposition (ALD) process. The following example is exemplified by taking hafnium oxide as the main material and fluorine anions as the doped anions. Specifically, a hafnium precursor is supplied to the surface of the preformed anion-doped hafnium oxide-based ferroelectric material. For example, the hafnium precursor may be HfCl 4 、[(CH 3 )(C 2 H 5 )N] 4 Hf or Hf(CpMe) 2 Me 2 Then supply a purge gas, such as argon (Ar), etc.; then supply an oxidant to react with the hafnium precursor to generate hafnium oxide, the oxidant may be O 3 ; Then, the purge gas is supplied. The aforementioned steps are repeated to generate a hafnium oxide material of a certain thickness. When anion doping is performed, the oxidant gas in some of the aforementioned cycles can be replaced with a fluorine precursor, such as HF, so that the doping of fluorine anions can be achieved. The fluorine anion doping concentration can be controlled by controlling the number of cycles in which the oxidant is replaced with a fluorine precursor.

[0088] It is easy to understand that in order to stabilize the ferroelectric phase of the hafnium oxide-based ferroelectric material, as mentioned above, in some embodiments, doping elements such as metals or semiconductors can be added to the hafnium oxide. When doping, the hafnium precursor in some of the aforementioned cycles can be replaced with a doping precursor of a corresponding metal or semiconductor or other doping element, or, in some cycles, after the hafnium precursor is introduced, the doping precursor to be doped is continued to be introduced. Similarly, the doping concentration can be controlled by the number of replacement cycles or the number of increased cycles.

[0089] Please continue to see Figure 6 In some embodiments, the first ferroelectric layer 111 may be in contact with the first electrode layer 120 and the second electrode layer 130, that is, the first ferroelectric layer 111 is the only film layer providing ferroelectricity between the first electrode layer 120 and the second electrode layer 130. In some embodiments, an insulating layer, an interface layer or other film layer may be provided between the first ferroelectric layer 111 and the first electrode layer 120, and / or between the first ferroelectric layer 111 and the second electrode layer 130 to improve the performance of the ferroelectric capacitor 100.

[0090] In other embodiments, Figure 9-12 As shown, the ferroelectric capacitor 100 may further include a second ferroelectric layer 112 , which is a hafnium oxide-based ferroelectric material that is not anion-doped. The second ferroelectric layer 112 is also disposed between the first electrode layer 120 and the second electrode layer 130 .

[0091] For example, Fig. 9 As shown, the first ferroelectric layer 111 and the second ferroelectric layer 112 are both arranged between the first electrode layer 120 and the second electrode layer 130, and the first ferroelectric layer 111 and the second ferroelectric layer 112 are arranged adjacent to each other. Since the first ferroelectric layer 111 is an anion-doped hafnium oxide-based ferroelectric material, it is not easy to form a current path caused by oxygen vacancy defects in the first ferroelectric layer 111. Although the second ferroelectric layer 112 is arranged between the first electrode layer 120 and the second electrode layer 130, since the first ferroelectric layer 111 is arranged between the first electrode layer 120 and the second electrode layer 130, it is difficult to form a current path between the first electrode layer 120 and the second electrode layer 130 in the ferroelectric capacitor 100, that is, such an arrangement can also effectively improve the service life of the ferroelectric capacitor 100. In addition, due to the presence of the second ferroelectric layer 112, the ferroelectric stability of the ferroelectric capacitor 100 can also be improved.

[0092] At this time, the thickness of the first ferroelectric layer 111 may be smaller than the thickness of the second ferroelectric layer 112. For example, the thickness of the second ferroelectric layer 112 is 2 times, 5 times or 10 times the thickness of the first ferroelectric layer.

[0093] For example, Fig.10 As shown, the first ferroelectric layer 111 includes a first sublayer 111a and a second sublayer 111b, that is, the first sublayer 111a and the second sublayer 111b are both anion-doped hafnium oxide-based ferroelectric materials. The second ferroelectric layer 112 is arranged between the first sublayer 111a and the second sublayer 111b, that is, the first sublayer 111a is arranged between the second ferroelectric layer 112 and the first electrode layer 120, and the second sublayer 111b is arranged between the second ferroelectric layer 112 and the second electrode layer 130. Therefore, the formation of the current path caused by the oxygen vacancy defect can be blocked from both sides of the second ferroelectric layer 112. At the same time, the second ferroelectric layer 112 can avoid contacting with the first electrode layer 120 and the second electrode layer 130, increase the distance between the second ferroelectric layer 112 and the first electrode layer 120 and the second electrode layer 130, and reduce the influence of the first electrode layer 120 and the second electrode layer 130 on the formation of oxygen vacancy defects in the second ferroelectric layer 112. Similarly, the first sublayer 111a and the second sublayer 111b can slow down or avoid the formation of a current path between the first electrode layer 120 and the second electrode layer 130, thereby improving the durability of the ferroelectric capacitor 100. In some possible implementations, the thickness of the first sublayer 111a and the second sublayer 111b are 1 nm to 5 nm, for example, 1 nm, 2 nm or 5 nm. At this time, the first sublayer 111a and the second sublayer 111b can effectively slow down or avoid the generation of a current path caused by oxygen vacancy defects, thereby increasing the thickness of the second ferroelectric layer 112 and improving the ferroelectric stability of the ferroelectric capacitor 100.

[0094] It is easy to understand that the first sublayer 111a and the second sublayer 111b not only provide ferroelectricity for the ferroelectric capacitor 100, but also slow down or prevent the ferroelectric capacitor 100 from being broken down. Since the first sublayer 111a and the second sublayer 111b are hafnium oxide-based ferroelectric materials doped with anions, their ferroelectric stability may be inferior to that of hafnium oxide-based ferroelectric materials that are not doped with anions, that is, the ferroelectric stability of the first sublayer 111a and the second sublayer 111b may be inferior to that of the second ferroelectric layer 112. Therefore, in some possible embodiments, in order to ensure that the ferroelectric capacitor 100 has sufficient ferroelectric stability, the ratio of the thickness of the second ferroelectric layer 112 to the thickness of the first sublayer 111a, or the ratio of the thickness of the second ferroelectric layer 112 to the thickness of the second sublayer 111b is greater than or equal to 2, for example, the ratio of the thickness of the second ferroelectric layer to the thickness of the first sublayer or the second sublayer is 2, 5, 10, 50 or 200.

[0095] For example, Fig.11 As shown, the second ferroelectric layer 112 includes a third sublayer 112a and a fourth sublayer 112b, that is, the third sublayer 112a and the fourth sublayer 112b are both hafnium oxide-based ferroelectric materials that are not anion-doped. The first ferroelectric layer 111 is arranged between the third sublayer 112a and the fourth sublayer 112b. In this case, although the durability of the third sublayer 112a and the fourth sublayer 112b is not changed, since the first ferroelectric layer 111 is arranged in the third sublayer 112a and the fourth sublayer 112b, the first ferroelectric layer 111 can slow down or avoid the formation of a current path caused by oxygen vacancy defects, slow down or avoid the formation of a current path between the first electrode layer 120 and the second electrode layer 130, and also improve the service life of the ferroelectric capacitor 100. Similarly, in order to ensure that the ferroelectric capacitor 100 has sufficient ferroelectric stability, the thickness of the third sublayer 112a and the thickness of the fourth sublayer 112b are both greater than or equal to the thickness of the first ferroelectric layer 111.

[0096] For example, Fig.12As shown, the ferroelectric capacitor 100 includes a plurality of first ferroelectric layers 111 and a plurality of second ferroelectric layers 112, and the plurality of first ferroelectric layers 111 and the plurality of second ferroelectric layers 112 are alternately arranged between the first electrode layer 120 and the second electrode layer 130, that is, a second ferroelectric layer 112 is arranged between any two adjacent layers in the plurality of first ferroelectric layers 111, and a first ferroelectric layer 111 is arranged between any two adjacent layers in the plurality of second ferroelectric layers 112. Therefore, the current path that may be formed between the first electrode layer 120 and the second electrode layer 130 is blocked multiple times by the plurality of first ferroelectric layers 111, so as to further reduce the possibility of forming the current path and improve the durability of the ferroelectric capacitor 100. In this embodiment, the thickness of the plurality of first ferroelectric layers 111 may be equal, and the thickness of the plurality of second ferroelectric layers 112 may also be equal. The thickness of a first ferroelectric layer 111 may be less than or equal to the thickness of a second ferroelectric layer 112.

[0097] Fig.13 FIG. 4 is a schematic diagram of a ferroelectric tunnel junction (FTJ) memory cell 420 provided in an embodiment of the present application. The FTJ memory cell 420 includes a transistor T and a ferroelectric tunnel junction 500 connected to a source or a drain of the transistor T.

[0098] The ferroelectric tunnel junction 500 includes a first ferroelectric layer 511, a first electrode layer 520, and a second electrode layer 530. The first ferroelectric layer 511 is disposed between the first electrode layer 520 and the second electrode layer 530, and the first ferroelectric layer 511 is an anion-doped hafnium oxide-based ferroelectric material. The source or drain of the transistor T is electrically connected to the first electrode layer 520, and can be used to control whether a voltage level is applied to the ferroelectric tunnel junction 500.

[0099] It is easy to understand that the ferroelectric tunnel junction 500 and the ferroelectric capacitor 100 in the above embodiment may have the same film layer arrangement, and the corresponding film layers may also be made of the same material. For example, the first ferroelectric layer 511 of the ferroelectric tunnel junction 500 may be made of the same material as the first ferroelectric layer 111 of the ferroelectric capacitor 100 in the above embodiment, and the first ferroelectric layer 511 of the ferroelectric tunnel junction 500 may also include a first sublayer and a second sublayer; for another example, the ferroelectric tunnel junction 500 may also include a second ferroelectric layer, and the arrangement and material of the second ferroelectric layer may be the same as those of the ferroelectric capacitor 100 in the above embodiment. Therefore, this embodiment will not be described in detail.

[0100] The difference between the ferroelectric tunnel junction 500 and the ferroelectric capacitor 100 is only the thickness of the film layer (hereinafter collectively referred to as the ferroelectric layer) providing ferroelectricity between the first electrode layer and the second electrode layer. The thickness of the ferroelectric layer in the ferroelectric tunnel junction 500 may be less than or equal to 5nm, and the thickness of the ferroelectric layer in the ferroelectric capacitor 100 may range from 5nm to 1000nm. For example, in some embodiments, the film layer providing ferroelectricity is only the first ferroelectric layer, and the thickness of the first ferroelectric layer in the ferroelectric tunnel junction 500 is less than the thickness of the first ferroelectric layer in the ferroelectric capacitor 100. Specifically, the thickness of the first ferroelectric layer in the ferroelectric tunnel junction 500 may be less than or equal to 5nm, and the thickness of the first ferroelectric layer in the ferroelectric capacitor 100 may range from 5nm to 1000nm.

[0101] When writing data to the FTJ memory cell 420, the transistor T is turned on and a voltage level is applied between the first electrode layer 520 and the second electrode layer 530. When the directions of the voltage levels applied between the first electrode layer 520 and the second electrode layer 530 are different, electric fields with different directions can be generated between the first electrode layer 520 and the second electrode layer 530, thereby controlling the polarization direction of the ferroelectric layer. Different polarization directions of the ferroelectric layer are used to indicate that the stored data is "0" or "1".

[0102] Since the thickness of the ferroelectric layer is small, when a small level is applied, the level can be in the form of an electric pulse, and a current signal can be detected on the ferroelectric tunnel junction 500. Therefore, when reading data from the FTJ storage unit 420, the transistor T is turned on. Since the polarization direction of the ferroelectric layer can affect the resistance of the ferroelectric layer, the resistance can be obtained by detecting the current, and then the polarization direction of the ferroelectric layer can be determined, that is, the data stored in the FTJ storage unit 420 can be obtained. It is easy to understand that when reading data, a very small electric pulse is applied to the ferroelectric tunnel junction 500, and the electric pulse is not enough to change the polarization direction of the ferroelectric layer. Since the electric pulse does not change the polarization direction of the ferroelectric layer, there is no need to rewrite the data after reading the data.

[0103] Fig.14 A ferroelectric transistor storage unit 430 is provided in an embodiment of the present application. The ferroelectric transistor storage unit 430 includes a substrate 431 and a ferroelectric device 600. The substrate 431 is formed with a source region 432, a drain region 433 and a channel 434. Electrodes (not shown in the figure) are respectively arranged on the source region 432 and the drain region 433. The ferroelectric device 600 is arranged on the channel 434. The ferroelectric device 600 includes a dielectric layer 620, a first ferroelectric layer 611 and a gate layer 630. That is, the dielectric layer 620, the first ferroelectric layer 611 and the gate layer 630 are sequentially arranged on the channel 434. The source region 432, the drain region 433, the channel 434 and the ferroelectric device 600 can form a ferroelectric transistor.

[0104] In this embodiment, the first ferroelectric layer 611 in the ferroelectric device 600 may have the same configuration and may be made of the same material as the first ferroelectric layer 111 in the ferroelectric capacitor 100 in the above embodiment. Similarly, the ferroelectric device 600 may also include a second ferroelectric layer, and the first ferroelectric layer 611 may also include a first sublayer and a second sublayer. The structural configuration and material of these film layers providing ferroelectricity (also collectively referred to as ferroelectric layers) may be the same as those of the ferroelectric capacitor 100 in the above embodiment.

[0105] The gate layer 630 in the ferroelectric device 600 may be arranged in the same manner and in the same material as the first electrode layer 120 or the second electrode layer 130 in the ferroelectric capacitor 100. The present application will not repeat the above similarities.

[0106] The ferroelectric device 600 provided in this embodiment is different from the ferroelectric capacitor 100 in that: when the gate layer 630 in the ferroelectric device 600 and the first electrode layer 120 in the ferroelectric capacitor 100 adopt the same configuration, the ferroelectric device 600 does not include the second electrode layer 130; when the gate layer 630 in the ferroelectric device 600 and the second electrode layer 130 in the ferroelectric capacitor 100 adopt the same configuration, the ferroelectric device 600 does not include the first electrode layer 120. Instead, the ferroelectric device 600 includes a dielectric layer 620.

[0107] The dielectric layer 620 may be silicon dioxide (SiO 2 ) or other high-K dielectric materials. When the dielectric layer 620 is silicon dioxide, the dielectric layer 620 can be a silicon dioxide layer formed by oxidation of a portion of the substrate 431. The dielectric layer 620 has the function of preventing the ferroelectric layer and the substrate 431 from diffusing with each other, or providing a buffer for the ferroelectric layer and the substrate 431 to prevent the lattice mismatch between the ferroelectric layer and the substrate 431 from causing stress.

[0108] When writing data to the ferroelectric transistor storage unit 430, a voltage level is applied to the gate layer 630, and an electric field is formed in the ferroelectric layer, thereby changing the polarization state of the ferroelectric layer. The polarization state of the ferroelectric layer will produce built-in electric fields in different directions, and the built-in electric field can affect the switching state of the ferroelectric transistor, and the switching state is used to indicate that the stored data is "0" or "1". It is easy to understand that in some embodiments, the built-in electric field of the ferroelectric layer is not sufficient to change the switching state of the ferroelectric transistor. Therefore, the resistance between the source and the drain of the ferroelectric transistor can be used to indicate that the stored data is "0" or "1". In some possible embodiments, multiple bits of data can also be stored by different resistance states between the source and the drain. For example, there are four resistance value states, namely R 1 , R 2 , R 3 , R 4, the corresponding data is "00", "01", "10", "11".

[0109] When reading data from the ferroelectric field effect transistor memory cell 430, the stored data can be determined by the different resistance states between the source and the drain.

[0110] In addition, the embodiments of the present application also provide a method for preparing a ferroelectric capacitor storage unit, such as Fig.15 As shown, the preparation steps include:

[0111] S10, forming a first electrode layer.

[0112] In some embodiments, the ferroelectric capacitor 100 is formed on a substrate, so in the above steps, the first electrode layer 120 is formed on the substrate. The substrate can be formed of silicon, or other Group III elements, Group IV elements, and / or Group V elements (e.g., silicon, germanium, gallium, arsenic, and combinations thereof). The substrate can also be in the form of a silicon-on-insulator (SOI). A SOI substrate may include a layer of semiconductor material (e.g., silicon, germanium, and / or the like) formed on an insulator layer (e.g., buried oxide and / or the like), the insulator layer being formed on a silicon substrate body.

[0113] In some embodiments, before forming the first electrode layer 120 on the substrate, an active layer is pre-formed on the substrate, and the active layer can be used to form a source, a drain or a channel of a transistor.

[0114] In some possible implementations, before forming the first electrode layer 120 on the substrate, the substrate may be pretreated. The pretreatment process may be: using acetone, water, or alcohol to clean and treat the polished silicon wafer to provide a clean and flat surface.

[0115] The materials that can be used for the first electrode layer 120 are as described above. There are many ways to form the first electrode layer 120, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), magnetron sputtering, etc. The first electrode layer 120 can be formed by selecting a suitable preparation process according to the specific selected material. For example, when the material of the first electrode layer 120 is TiN, a magnetron sputtering process can be selected.

[0116] S20, forming a first ferroelectric layer on one side of the first electrode layer, wherein the first ferroelectric layer is an anion-doped hafnium oxide-based ferroelectric material.

[0117] After the first electrode layer 120 is formed, a first ferroelectric layer 111 is formed on a side of the first electrode layer 120 away from the substrate. The first ferroelectric layer 111 is an anion-doped hafnium oxide-based ferroelectric material.

[0118] In some embodiments, the first ferroelectric layer 111 is formed by an ALD process. After forming the first electrode layer 120, the substrate is transferred to an ALD process chamber. In some possible embodiments, if the process for forming the first electrode layer 120 is also an ALD process, the substrate may not be transferred, and the first ferroelectric layer 111 may be formed directly in the original ALD process chamber.

[0119] Please continue to refer to Fig.16 The first ferroelectric layer 111 may be formed by an ALD process (taking the main material of the hafnium oxide-based ferroelectric material in the first ferroelectric layer 111 as hafnium oxide, the doping material as aluminum, and the doped anions as fluorine anions as an example) including the following steps:

[0120] S201, forming a hafnium precursor on the surface of the pre-formed first ferroelectric layer 111. Forming the hafnium precursor on the surface of the pre-formed first ferroelectric layer 111, that is, the surface of the first electrode layer 120, includes supplying the hafnium precursor to the ALD process chamber, so that the hafnium precursor is adsorbed on at least a portion of the region on the substrate where the first ferroelectric layer 111 is pre-formed. The hafnium precursor may be HfCl 4 、[(CH 3 )(C 2 H 5 )N] 4 Hf or Hf(CpMe) 2 Me 2 wait.

[0121] S202, forming an aluminum precursor on the surface where the hafnium precursor is formed. The aluminum precursor (dopant material precursor) is supplied to the ALD process chamber to form the aluminum precursor on the surface of the preformed first ferroelectric layer 111. The formation of the aluminum precursor may include supplying the aluminum precursor into the ALD process chamber so that the aluminum precursor is adsorbed on at least a portion of the surface of the preformed first ferroelectric layer 111, thereby covering the portion not covered by the hafnium precursor.

[0122] S203, supplying an oxidant or an anion dopant to the ALD process chamber. When an oxidant is supplied, after the oxidant is supplied to the ALD process chamber, the hafnium precursor or / and the aluminum precursor reacts with the oxidant, including the formation of an aluminum-doped hafnium oxide atomic layer on the surface of the pre-formed first ferroelectric layer 111; when an anion dopant is supplied, after the anion dopant is supplied to the ALD process chamber, the hafnium precursor or / and the aluminum precursor reacts with the anion dopant, including the formation of an atomic layer on the surface of the pre-formed first ferroelectric layer 111. The oxidant may be O 3, the anion dopant may be HF.

[0123] The supplying and adsorption in the above steps may be achieved via any known ALD operation for supplying a precursor onto a layer.

[0124] Steps S201 to S203 are continuously repeated until the thickness of the anion-doped hafnium oxide film reaches the target thickness of the first ferroelectric layer 111. It is easy to understand that after each step in steps S201 to S203 is completed, a purge gas can be introduced to clean the residual substances in the ALD process chamber to prevent the residual substances from reacting with the subsequently introduced substances.

[0125] During the cycle, the anion doping concentration can be controlled by controlling the ratio of the times of introducing the oxidant and the anion dopant in step S203 , that is, controlling the ratio of the number of anions in the first ferroelectric layer 111 to the number of oxygen ions in the hafnium oxide-based ferroelectric material.

[0126] Similarly, the doping concentration of the aluminum precursor can be controlled by controlling the coverage area of ​​the hafnium precursor on the pre-formed first ferroelectric layer 111 in step S201. In some cycles, the coverage area of ​​the hafnium precursor on the pre-formed first ferroelectric layer 111 in step S201 can be 0, that is, the hafnium precursor is not introduced, and step S201 is omitted. It is easy to understand that in some cycles, the hafnium precursor in step S201 can completely cover the pre-formed first ferroelectric layer 111, and therefore, step S202 can be omitted.

[0127] In order to make the formed anion-doped hafnium oxide film layer have ferroelectricity, it is necessary to anneal the film layer to crystallize the film layer, thereby forming the first ferroelectric layer 111. The hafnium oxide-based film layer is crystallized by annealing to form an asymmetric unit cell. The positive and negative charge centers inside the asymmetric hafnium oxide unit cell do not overlap, generating an electric dipole to form spontaneous polarization. Under the action of an external electric field, the polarization direction changes and exhibits ferroelectricity.

[0128] In some embodiments, the second ferroelectric layer 112 is formed. The second ferroelectric layer 112 is a hafnium oxide-based ferroelectric material that is not anion-doped. The second ferroelectric layer 112 can be formed by the above steps S201 to S203. In the step S203 of all cycles of forming the second ferroelectric layer 112, only an oxidant is supplied to the ALD process chamber. Fig. 9 As shown, the second ferroelectric layer 112 can be formed on one side of the first electrode layer 120 after forming the first electrode layer 120 and before forming the first ferroelectric layer 111. In some embodiments, the second ferroelectric layer 112 can also be formed on a side of the first ferroelectric layer 111 away from the first electrode layer 120 after forming the first ferroelectric layer 111.

[0129] In some embodiments, Fig.10 As shown, the first ferroelectric layer 111 includes a first sublayer 111a and a second sublayer 111b. The first ferroelectric layer 111 is formed on one side of the first electrode layer 120, that is, the first sublayer 111a and the second sublayer 111b are formed on one side of the first electrode layer 120, including forming a second ferroelectric layer 112 between the first sublayer 111a and the second sublayer 111b, and the second ferroelectric layer 112 is a hafnium oxide-based ferroelectric material that is not anion-doped. That is, after the first electrode layer 120 is formed and before the second ferroelectric layer 112 is formed, the first sublayer 111a is formed on one side of the first electrode layer 120; and the second ferroelectric layer 112 is formed on the side of the formed first sublayer 111a away from the first electrode layer 120. After the second ferroelectric layer 112 is formed, the second sublayer 111b is formed on the side of the second ferroelectric layer 112 away from the first sublayer 111a.

[0130] In some possible implementations, such as Fig.11 As shown, the second ferroelectric layer 112 includes a third sublayer 112a and a fourth sublayer 112b. That is, the third sublayer 112a and the fourth sublayer 112b are hafnium oxide-based ferroelectric materials that are not anion-doped. The second ferroelectric layer 112 is formed, that is, the third sublayer 112a and the fourth sublayer 112b are formed, specifically including forming the third sublayer 112a on one side of the first electrode layer 120 before forming the first ferroelectric layer 111; after forming the first ferroelectric layer 111 and before forming the second electrode layer 130, forming the fourth sublayer 112b on the side of the first ferroelectric layer 111 away from the first electrode layer 120.

[0131] In some embodiments, Fig.12 As shown, multiple layers of first ferroelectric layer 111 and second ferroelectric layer 112 may be formed on one side of first electrode layer 120, and multiple layers of first ferroelectric layer 111 and multiple layers of second ferroelectric layer 112 are alternately formed. Among them, the first ferroelectric layer 111 or the second ferroelectric layer 112 may be close to the first electrode layer 120.

[0132] S30, forming a second electrode layer on a side of the first ferroelectric layer away from the first electrode layer.

[0133] After the first ferroelectric layer 111 is formed, the second electrode layer 130 is formed on a side of the first ferroelectric layer 111 away from the first electrode layer 120 .

[0134] The present application also provides a method for preparing a ferroelectric tunnel junction memory cell, which is the same as the method for preparing a ferroelectric capacitor memory cell and will not be described in detail in the present application.

[0135] At the same time, the present application also provides a method for preparing a ferroelectric tunnel junction memory cell, which is different from the method for preparing a ferroelectric capacitor memory cell in that:

[0136] In step S10, the first electrode layer 120 is not formed on the substrate, but a dielectric layer is formed, and no transistor is formed on the substrate, a source region, a drain region and a channel are formed on the substrate, and the dielectric layer is formed on the channel. The dielectric layer can be formed by a deposition process, that is, a dielectric material is deposited on the substrate to form the dielectric layer. When the dielectric layer is silicon dioxide, the substrate is a silicon substrate or a silicon-on-insulator substrate, and the insulator layer of the silicon-on-insulator substrate is silicon material, the substrate can be thermally oxidized to oxidize a portion of the silicon on the substrate to form a silicon dioxide dielectric layer.

[0137] In step S30 , a gate layer is formed, but the gate layer and the second electrode layer can be formed using the same method.

[0138] The present application will not repeat the same points as the preparation method of the ferroelectric capacitor storage unit.

[0139] The above are only specific implementations of the present application, but the protection scope of the application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A ferroelectric capacitor storage unit, It is characterized in that include: transistor; A ferroelectric capacitor, comprising a first electrode layer, a second electrode layer and a first ferroelectric layer, wherein the first ferroelectric layer is arranged between the first electrode layer and the second electrode layer; the first ferroelectric layer is an anion-doped hafnium oxide-based ferroelectric material; Wherein, the transistor is electrically connected to the first electrode layer.

2. The ferroelectric capacitor storage unit according to claim 1, It is characterized in that The first ferroelectric layer is in contact with the first electrode layer and the second electrode layer.

3. The ferroelectric capacitor storage unit according to claim 1, It is characterized in that The ferroelectric capacitor further includes a second ferroelectric layer, which is disposed between the first electrode layer and the second electrode layer, and is a hafnium oxide-based ferroelectric material that is not doped with anions.

4. The ferroelectric capacitor storage unit according to claim 3, It is characterized in that The first ferroelectric layer includes a first sublayer and a second sublayer, and the second ferroelectric layer is disposed between the first sublayer and the second sublayer.

5. The ferroelectric capacitor storage unit according to claim 4, It is characterized in that The thickness of the first sublayer and the second sublayer are both 1 nm to 5 nm.

6. The ferroelectric capacitor storage unit according to claim 4 or 5, It is characterized in that The first sub-layer and the second sub-layer have the same thickness.

7. The ferroelectric capacitor storage unit according to any one of claims 4 to 6, It is characterized in that A ratio of a thickness of the second ferroelectric layer to a thickness of the first sublayer or the second sublayer is greater than or equal to 2.

8. The ferroelectric capacitor storage unit according to claim 3, It is characterized in that The second ferroelectric layer includes a third sublayer and a fourth sublayer, and the first ferroelectric layer is disposed between the third sublayer and the fourth sublayer.

9. The ferroelectric capacitor storage unit according to claim 3, It is characterized in that The ferroelectric capacitor includes a plurality of first ferroelectric layers and a plurality of second ferroelectric layers, and the plurality of first ferroelectric layers and the plurality of second ferroelectric layers are alternately arranged between the first electrode layer and the second electrode layer.

10. The ferroelectric capacitor storage unit according to any one of claims 1 to 9, It is characterized in that The anions are one or more of fluoride (F) ions, chloride (Cl) ions, bromide (Br) ions, and carbon (C) ions.

11. The ferroelectric capacitor storage unit according to any one of claims 1 to 10, It is characterized in that In the first ferroelectric layer, the ratio of the number of the anions to the number of the oxygen ions in the hafnium oxide-based ferroelectric material is (0.005-0.1):

1.

12. The ferroelectric capacitor storage unit according to any one of claims 1 to 11, It is characterized in that The hafnium oxide-based ferroelectric material comprises a main material and a doping material. The main material is hafnium oxide (HfO x ), hafnium zirconium oxide (HfZrO x ) or hafnium oxide (HfO x ) and hafnium zirconium oxide (HfZrO x ), x is 1 or 2, and the doping material includes at least one of potassium (K), scandium (Sc), rubidium (Rb), selenium (Se), tin (Sn), magnesium (Mg), calcium (Ca), barium (Ba), indium (In), vanadium (V), niobium (Nb), lanthanum (La), titanium (Ti), yttrium (Y), strontium (Sr), gadolinium (Gd), silicon (Si), and aluminum (Al).

13. A ferroelectric tunnel junction memory cell, It is characterized in that include: transistor; A ferroelectric tunnel junction, wherein the ferroelectric tunnel junction comprises a first electrode layer, a second electrode layer and a first ferroelectric layer, wherein the first ferroelectric layer is arranged between the first electrode layer and the second electrode layer; the first ferroelectric layer is an anion-doped hafnium oxide-based ferroelectric material; Wherein, the transistor is electrically connected to the first electrode layer.

14. The ferroelectric tunnel junction memory cell according to claim 13, It is characterized in that The ferroelectric tunnel junction further includes a second ferroelectric layer, which is disposed between the first electrode layer and the second electrode layer, and is a hafnium oxide-based ferroelectric material that is not doped with anions.

15. The ferroelectric tunnel junction memory cell according to claim 14, It is characterized in that The first ferroelectric layer includes a first sublayer and a second sublayer, and the second ferroelectric layer is disposed between the first sublayer and the second sublayer.

16. The ferroelectric tunnel junction memory cell according to any one of claims 13 to 15, It is characterized in that The anions are one or more of fluoride (F) ions, chloride (Cl) ions, bromide (Br) ions, and carbon (C) ions.

17. A ferroelectric transistor memory cell, It is characterized in that include: A substrate, wherein the substrate is formed with a source region, a drain region and a channel, and the channel is arranged between the source region and the drain region; A dielectric layer, a first ferroelectric layer and a gate layer are sequentially arranged on the channel, wherein the first ferroelectric layer is a hafnium oxide-based ferroelectric material doped with anions.

18. The ferroelectric transistor memory cell according to claim 17, It is characterized in that The invention also comprises a second ferroelectric layer, wherein the second ferroelectric layer is arranged between the dielectric layer and the gate layer, and the second ferroelectric layer is a hafnium oxide-based ferroelectric material which is not doped with anions.

19. The ferroelectric transistor memory cell of claim 18, It is characterized in that The first ferroelectric layer includes a first sublayer and a second sublayer, and the second ferroelectric layer is disposed between the first sublayer and the second sublayer.

20. The ferroelectric transistor memory cell according to any one of claims 17 to 19, It is characterized in that The anions are one or more of fluoride (F) ions, chloride (Cl) ions, bromide (Br) ions, and carbon (C) ions.

21. A ferroelectric memory, It is characterized in that The invention comprises a controller, and a ferroelectric capacitor storage unit according to any one of claims 1 to 12, a ferroelectric tunnel junction storage unit according to any one of claims 13 to 16, or a ferroelectric transistor storage unit according to any one of claims 17 to 20.

22. An electronic device, It is characterized in that include: A processor and the ferroelectric memory as claimed in claim 21, wherein the processor is electrically connected to the ferroelectric memory.

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