Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a first region and a second region surrounding the first region, the first region comprises first well regions and second well regions which extend along a first direction and are alternately arranged along a second direction, the first well regions are arranged at the head and tail of the first region along the second direction, and the second region comprises a third well region; the doping type of the third well region is the same as that of the first well region, and the doping type of the first well region is different from that of the second well region; the emitter is located on the substrate of the first well region; the collector electrode is located on the substrate of the second well region; the base electrode is located on the substrate of the third well region. According to the invention, the current gain is improved, so that the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Bipolar transistors are a good choice for ultra-high frequency devices. First, they utilize the energy band difference of Si (silicon) to improve the carrier injection efficiency of the emission region and increase the current amplification factor of the device. Secondly, they utilize the high doping of the external base region to reduce the base resistance and increase the characteristic frequency. Therefore, bipolar transistors have become one of the mainstream ultra-high frequency devices.

[0003] The extensive use of bipolar transistors requires integration with CMOS devices, and improvements in integration processes will make bipolar transistors more competitive.

[0004] Currently, the performance of bipolar transistors still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the working performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first region, and a second region surrounding the first region, the first region including a first well region and a second well region extending along a first direction and alternately arranged along a second direction, and along the second direction, the first well regions are arranged at the beginning and end of the first region, the second region includes a third well region, and the third well region has the same doping type as the first well region, and the first well region has a different doping type from the second well region; an emitter is located on the substrate of the first well region; a collector is located on the substrate of the second well region; and a base is located on the substrate of the third well region.

[0007] Optionally, the doping type of the substrate is the same as the doping type of the first well region.

[0008] Optionally, the semiconductor structure also includes: a plurality of fins extending along the first direction and arranged in parallel along the second direction on the substrate of the first region and the second region, respectively; a plurality of gate structures extending along the second direction and spanning the fins of the corresponding regions on the substrate of the first well region, the second well region and the third well region, respectively, and arranged in parallel along the first direction; the emitter is located in the first well region, on the fins on both sides of the gate structure; the collector is located in the second well region, on the fins on both sides of the gate structure; the base is located in the third well region, on the fins on both sides of the gate structure.

[0009] Optionally, in the first region, the number of gate structures is 6 to 20.

[0010] Optionally, in the first well region, the number of fins is 4 to 12.

[0011] Optionally, the material of the emitter includes silicon phosphide; the material of the collector includes silicon phosphide; and the material of the base includes silicon germanium.

[0012] Optionally, in the first region, the total number of the first well regions and the second well regions is 2n+1, where 1≤n≤5.

[0013] Optionally, the substrate includes a plurality of first regions arranged in an array, and a plurality of second regions surrounding the first regions are interconnected in a grid shape.

[0014] Accordingly, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first region, and a second region surrounding the first region, the first region comprising a first well region and a second well region extending along a first direction and alternately arranged along a second direction, and along the second direction, the first well regions are arranged at the beginning and end of the first region, the second region comprises a third well region, and the third well region has the same doping type as the first well region, and the first well region has a different doping type from the second well region; forming an emitter on the substrate of the first well region; forming a collector on the substrate of the second well region; and forming a base on the substrate of the third well region.

[0015] Optionally, in the step of providing a substrate, the doping type of the substrate is the same as the doping type of the first well region.

[0016] Optionally, the method for forming a semiconductor structure also includes: forming a plurality of fins extending along a first direction and arranged in parallel along a second direction on the substrates of the first region and the second region, respectively; forming a plurality of gate structures extending along the second direction and spanning corresponding regions on the substrates of the first well region, the second well region and the third well region, respectively; in the step of forming an emitter, the emitter is located in the first well region, on the fins on both sides of the gate structure; in the step of forming a collector, the collector is located in the second well region, on the fins on both sides of the gate structure; in the step of forming a base, the base is located in the third well region, on the fins on both sides of the gate structure.

[0017] Optionally, in the step of forming the gate structure, the number of the gate structures in the first region is 6 to 20.

[0018] Optionally, in the step of forming the fins, the number of the fins in the first well region is 4 to 12.

[0019] Optionally, in the step of forming the emitter, the material of the emitter includes silicon phosphide; in the step of forming the collector, the material of the collector includes silicon phosphide; in the step of forming the base, the material of the base includes silicon germanium.

[0020] Optionally, in the step of providing a substrate, in the first region, a total number of first well regions and second well regions is 2n+1, where 1≤n≤5.

[0021] Optionally, in the step of providing a substrate, the substrate includes a plurality of first regions arranged in an array, and a plurality of second regions surrounding the first regions are interconnected in a grid shape.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0023] In the semiconductor structure provided by the embodiment of the present invention, the substrate includes a first region and a second region surrounding the first region, the first region includes a first well region and a second well region extending along the first direction and alternately arranged along the second direction, and along the second direction, the first well regions are arranged at the beginning and end of the first region, the second region includes a third well region, and the third well region has the same doping type as the first well region, and the first well region has a different doping type from the second well region, the emitter is located on the substrate of the first well region, the collector is located on the substrate of the second well region, and the base is located on the substrate of the third well region; in the embodiment of the present invention, the first well region and the second well region are adjacent and alternately arranged in the first region, and correspondingly, the emitter and the collector are adjacent and alternately arranged in the first region, which is conducive to minimizing the space between the emitter and the collector, making the emitter and the collector compactly arranged, which is conducive to improving the integration of the semiconductor structure, and the emitter and the collector are adjacent, which is conducive to reducing the current path from the collector to the emitter, thereby facilitating improving the current gain, and further facilitating improving the performance of the semiconductor structure.

[0024] In the formation method provided in the embodiment of the present invention, a substrate is provided, including a first region and a second region surrounding the first region, the first region including a first well region and a second well region extending along the first direction and alternately arranged along the second direction, and along the second direction, the first well regions are arranged at the beginning and end of the first region, the second region includes a third well region, and the third well region has the same doping type as the first well region, and the first well region has a different doping type from the second well region, an emitter is formed on the substrate of the first well region, a collector is formed on the substrate of the second well region, and a base is formed on the substrate of the third well region; in the embodiment of the present invention, the first well region and the second well region are adjacent and alternately arranged in the first region, and correspondingly, the emitter and the collector are adjacent and alternately arranged in the first region, which is conducive to minimizing the space between the emitter and the collector, making the emitter and the collector compactly arranged, which is conducive to improving the integration of the semiconductor structure, and the emitter and the collector are adjacent, which is conducive to reducing the current path from the collector to the emitter, thereby facilitating improving the current gain, and further facilitating improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 3 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0026] Figures 4 to 8 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, usually, in a bipolar junction transistor (BJT), the base is designed between the emitter and the collector to reduce the base resistance. However, this structure will increase the base width, resulting in a decrease in the current gain β, affecting the performance of the transistor. In addition, the electron recombination current in the base will also increase due to the excessive base width, resulting in poor temperature linearity, which also affects the performance of the transistor.

[0028] In the prior art, in order to control the base width well, a vertical NPNBJT formed by SiP / PW / DNW is used. However, this structure must use an additional mask of DNW, which will increase the mass production cost.

[0029] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first region, and a second region surrounding the first region, the first region including a first well region and a second well region extending along a first direction and alternately arranged along a second direction, and along the second direction, the first well regions are arranged at the beginning and end of the first region, the second region includes a third well region, and the third well region has the same doping type as the first well region, and the first well region has a different doping type from the second well region; an emitter is located on the substrate of the first well region; a collector is located on the substrate of the second well region; and a base is located on the substrate of the third well region.

[0030] In the embodiment of the present invention, the first well region and the second well region are adjacent to each other and are alternately arranged in the first region. Correspondingly, the emitter and the collector are adjacent to each other and are alternately arranged in the first region, which is beneficial to minimizing the space between the emitter and the collector, making the emitter and the collector arranged compactly, which is beneficial to improving the integration of the semiconductor structure. Moreover, the emitter and the collector are adjacent to each other, which is beneficial to reducing the current path from the collector to the emitter, thereby facilitating improving the current gain, and further facilitating improving the performance of the semiconductor structure.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 3 is a schematic structural diagram of a first embodiment of a semiconductor structure of the present invention, wherein: Figure 1 and Figure 3 is a top view, Figure 2 for Figure 1 Cross-sectional view along the AA direction.

[0033] Combined with reference Figures 1 to 3The semiconductor structure includes: a substrate 100, including a first region 110a, and a second region 120a surrounding the first region 110a, the first region 110a including a first direction (such as Figure 1 X direction) and extends along the second direction (as shown in Figure 1 The first well region 121a and the second well region 122a are alternately arranged (as shown in the Y direction), and along the second direction, the first well region 121a is arranged at the beginning and end of the first region 110a, the second region 120a includes a third well region 123a, and the third well region 123a has the same doping type as the first well region 121a, and the first well region 121a and the second well region 122a have different doping types; the emitter 210 is located on the substrate 100 of the first well region 121a; the collector 220 is located on the substrate 100 of the second well region 122a; the base 230 is located on the substrate 100 of the third well region 123a.

[0034] The substrate 100 is used to provide a process operation basis for forming a semiconductor structure.

[0035] In this embodiment, a bipolar junction transistor (BJT) is taken as an example for description.

[0036] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, silicon germanium, gallium arsenide, indium gallium, or silicon on insulator.

[0037] The first region 110 a is a region for forming a first well region 121 a and a second well region 122 a .

[0038] The second region 120 a is a region for forming a third well region 123 a .

[0039] The first well region 121 a is a region for forming an emitter 210 , the second well region 122 a is a region for forming a collector 220 , and the third well region 123 a is a region for forming a base 230 .

[0040] In this embodiment, the first well region 121 a , the second well region 122 a , and the third well region 123 a are used to provide an N-type substrate or a P-type substrate required for the corresponding transistors to work, and to achieve electrical isolation between adjacent transistors.

[0041] In this embodiment, the first well region 121a, the second well region 122a and the third well region 123a all have well ions, wherein the conductivity type of the well ions is opposite to the channel conductivity type of the corresponding transistor. That is, the well ions corresponding to the NMOS transistor are P-type ions, and the well ions corresponding to the PMOS transistor are N-type ions.

[0042] Specifically, in this embodiment, the doping types of the first well region 121a and the second well region 122a are different, and the doping types of the first well region 121a and the third well region 123a are the same. As an example, the well region ions of the first well region 121a are P-type ions, the well region ions of the second well region 122a are N-type ions, and the well region ions of the third well region 123a are P-type ions.

[0043] In this embodiment, the doping type of the substrate 100 is the same as the doping type of the first well region 121 a .

[0044] The doping type of the substrate 100 is the same as that of the first well region 121 a , and correspondingly, the doping type of the substrate 100 is also the same as that of the third well region 123 a , so that the first well region 121 a and the third well region 123 a can be electrically connected through the substrate 100 .

[0045] Specifically, in this embodiment, the substrate 100 is a P-type substrate.

[0046] In this embodiment, the emitter 210 is located on the substrate 100 in the first well region 121 a ; the collector 220 is located on the substrate 100 in the second well region 122 a ; and the base 230 is located on the substrate 100 in the third well region 123 a .

[0047] Correspondingly, in the present embodiment, the first region 110a is used to form the emitter 210 and the collector 220. The first well region 121a is arranged at the head and tail of the first region 110a along the second direction. That is to say, in the first region 110a, the emitter 210 and the collector 220 are arranged alternately along the second direction, and the emitter 210 is arranged at the head and tail. Then, in the first region 110a, there are emitters 210 at the head and tail along the second direction to form a bipolar transistor. The second region 120a surrounding the first region 110a is used to form the base 230. That is to say, the base 230 surrounds the area formed by the emitter 210 and the collector 220. Then, the emitter 210 and the collector 220 of the first region 110a share the base 230 of the second region 120a.

[0048] In this embodiment, the collector 220 , the base 230 , and the emitter 210 form a bipolar transistor.

[0049] Specifically, the bipolar transistor is composed of three different doped semiconductor regions, namely, the emitter 210, the base 230 and the collector 220. The charge flow in the transistor is mainly due to the diffusion and drift motion of the carriers at the PN junction. As an example, taking an NPN transistor as an example, the electrons of the emitter 210 move to the base 230 by diffusion, in which the holes are the majority carriers and the electrons are the minority carriers. Since the base 230 is very thin, the electrons reach the collector 220 by drift motion, thereby forming the collector 220 current.

[0050] In the present embodiment, the first well region 121a and the second well region 122a are adjacent to each other and are alternately arranged in the first region 110a. Correspondingly, the emitter 210 and the collector 220 are adjacent to each other and are alternately arranged in the first region 110a, which is beneficial to minimize the space between the emitter 210 and the collector 220, so that the emitter 210 and the collector 220 are arranged compactly, which is beneficial to improve the integration of the semiconductor structure. Moreover, the emitter 210 and the collector 220 are adjacent to each other, which is beneficial to reduce the current path from the collector 220 to the emitter 210, thereby facilitating the improvement of the current gain and further facilitating the improvement of the performance of the semiconductor structure.

[0051] In this embodiment, the material of the emitter 210 includes silicon phosphide; the material of the collector 220 includes silicon phosphide; and the material of the base 230 includes silicon germanium.

[0052] In this embodiment, the collectors 220 are connected in parallel.

[0053] The collectors 220 are connected in parallel so that the same voltage is applied to each collector 220 to achieve the normal function of the bipolar transistor.

[0054] In this embodiment, a plurality of emitters 210 are connected in parallel.

[0055] The plurality of emitters 210 are connected in parallel so that the same voltage is applied to each emitter 210 , thereby achieving the normal function of the bipolar transistor.

[0056] In this embodiment, in the first region 110 a , the total number of the first well regions 121 a and the second well regions 122 a is 2n+1, where 1≤n≤5.

[0057] That is to say, in this embodiment, in the first region 110 a , the total number of emitters 210 and collectors 220 is 2n+1, where 1≤n≤5.

[0058] In the first region 110a, if the total number of the emitter 210 and the collector 220 is too large, it is easy to cause the area of ​​the first region 110a to be too large, resulting in unnecessary waste, and it is also easy to cause the resistance of the semiconductor structure to be too large, affecting the performance of the semiconductor structure. To this end, in this embodiment, in the first region 110a, the total number of the emitter 210 and the collector 220 is 2n+1, where 1≤n≤5, and correspondingly, in the first region 110a, the total number of the first well region 121a and the second well region 122a is 2n+1, where 1≤n≤5.

[0059] refer to Figure 3 In this embodiment, the substrate 100 includes a plurality of first regions 110a arranged in an array, and a plurality of second regions 120a surrounding the first regions 110a are interconnected in a grid shape. The plurality of first regions 110a arranged in an array share a base 230 of the second regions 120a connected in a grid shape, so that the semiconductor structure has a higher degree of integration.

[0060] In the present embodiment, the semiconductor structure further includes: a plurality of fins 200 extending along the first direction and arranged in parallel along the second direction on the substrate 100 in the first region 110 a and the second region 120 a , respectively.

[0061] The fin 200 is used as a channel of a transistor.

[0062] In this embodiment, the substrate 100 further includes a plurality of active regions 210 extending along the first direction and arranged in parallel along the second direction on the substrate 100 in the first region 110 a and the second region 120 a , respectively. Accordingly, the fins 200 are formed in the active regions 210 .

[0063] In this embodiment, the semiconductor structure further includes: fins 200 extending along the second direction across corresponding regions on the substrate 100 in the first well region 121a, the second well region 122a and the third well region 123a respectively and a plurality of gate structures 300 arranged in parallel along the first direction.

[0064] The gate structure 300 is used to control the opening and closing of the channel of the transistor.

[0065] Specifically, in this embodiment, the gate structure 300 is a metal gate structure.

[0066] In this embodiment, the gate structure 300 includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer.

[0067] The material of the gate dielectric layer includes HfO 2 、ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 、SiO2 and La 2 O 3 In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO 2 、ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 wait.

[0068] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the material of the gate oxide layer may be silicon oxide.

[0069] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0070] In this embodiment, the gate electrode layer includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0071] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0072] Correspondingly, in this embodiment, the emitter 210 is located in the first well region 121a, on the fins 200 on both sides of the gate structure 300; the collector 220 is located in the second well region 122a, on the fins 200 on both sides of the gate structure 300; the base 230 is located in the third well region 123a, on the fins 200 on both sides of the gate structure 300.

[0073] It should be noted that, in the present embodiment, in the first region 110a, the gate structure 300 and the fin 200 can control the area of ​​the first region 110a and correspondingly control the emission area. In order to obtain a suitable emission area while ensuring the performance of the semiconductor structure and not making the area of ​​the first region 110a too large and wasteful, and not making the resistance of the semiconductor structure too large, in the present embodiment, in the first region 110a, the number of gate structures 300 is 6 to 20; in the first well region 121a, the number of fins 200 is 4 to 12.

[0074] In this embodiment, the semiconductor structure further includes: an interconnect plug 400, which is located on the top of the emitter 210 and electrically connected to the emitter 210, located on the top of the collector 220 and electrically connected to the collector 220, and located on the top of the base 230 and electrically connected to the base 230.

[0075] The interconnection plug 400 located on the top of the emitter 210 is used to electrically lead out the emitter 210 to achieve voltage loading on the emitter 210 .

[0076] The interconnection plug 400 located on the top of the collector 220 is used to electrically lead out the collector 220 to achieve voltage loading on the collector 220 .

[0077] The interconnection plug 400 located on the top of the base 230 is used to electrically lead out the base 230 to achieve voltage loading on the base 230 .

[0078] In this embodiment, the interconnection plug 400 is made of tungsten. In other embodiments, the interconnection plug may also be made of cobalt or ruthenium.

[0079] Figures 4 to 8 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention.

[0080] Combined with reference Figure 4 and Figure 5 , Figure 4 It is a top view. Figure 5 yes Figure 4 In the cross-sectional view along the AA direction, the substrate 100 includes a first region 110a and a second region 120a surrounding the first region 110a. The first region 110a includes a first region 110a and a second region 120a surrounding the first region 110a. Figure 4 X direction) and extends along the second direction (as shown in Figure 4 The first well region 121a and the second well region 122a are arranged alternately (as shown in the Y direction in the middle), and along the second direction, the first well region 121a is arranged at the beginning and end of the first region 110a, the second region 120a includes a third well region 123a, and the third well region 123a has the same doping type as the first well region 121a, and the first well region 121a and the second well region 122a have different doping types.

[0081] The substrate 100 is used to provide a process operation basis for forming a semiconductor structure.

[0082] In this embodiment, a semiconductor structure that is a bipolar junction transistor (BJT) is taken as an example for description.

[0083] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, silicon germanium, gallium arsenide, indium gallium, or silicon on insulator.

[0084] The first region 110 a is a region for forming a first well region 121 a and a second well region 122 a .

[0085] The second region 120 a is a region for forming a third well region 123 a .

[0086] The first well region 121 a is a region for forming an emitter, the second well region 122 a is a region for forming a collector, and the third well region 123 a is a region for forming a base.

[0087] In this embodiment, the first well region 121 a , the second well region 122 a , and the third well region 123 a are used to provide an N-type substrate or a P-type substrate required for the corresponding transistors to work, and to achieve electrical isolation between adjacent transistors.

[0088] In this embodiment, the first well region 121a, the second well region 122a and the third well region 123a all have well ions, wherein the conductivity type of the well ions is opposite to the channel conductivity type of the corresponding transistor. That is, the well ions corresponding to the NMOS transistor are P-type ions, and the well ions corresponding to the PMOS transistor are N-type ions.

[0089] Specifically, in this embodiment, the doping types of the first well region 121a and the second well region 122a are different, and the doping types of the first well region 121a and the third well region 123a are the same. As an example, the well region ions of the first well region 121a are P-type ions, the well region ions of the second well region 122a are N-type ions, and the well region ions of the third well region 123a are P-type ions.

[0090] In this embodiment, in the step of providing the substrate 100 , the doping type of the substrate 100 is the same as the doping type of the first well region 121 a .

[0091] The doping type of the substrate 100 is the same as that of the first well region 121 a , and correspondingly, the doping type of the substrate 100 is also the same as that of the third well region 123 a , so that the first well region 121 a and the third well region 123 a can be electrically connected through the substrate 100 .

[0092] Specifically, in this embodiment, the substrate 100 is a P-type substrate.

[0093] In the present embodiment, in the step of providing the substrate 100 , in the first region 110 a , the total number of the first well regions 121 a and the second well regions 122 a is 2n+1, where 1≤n≤5.

[0094] That is to say, in this embodiment, in the first region 110 a , the total number of emitters and collectors formed subsequently is 2n+1, where 1≤n≤5.

[0095] In the first region 110a, if the total number of emitters and collectors is too large, it is easy to cause the area of ​​the first region 110a to be too large, resulting in unnecessary waste, and it is also easy to cause the resistance of the semiconductor structure to be too large, affecting the performance of the semiconductor structure. To this end, in this embodiment, in the first region 110a, the total number of emitters and collectors is 2n+1, where 1≤n≤5, and correspondingly, in the first region 110a, the total number of first well regions 121a and second well regions 122a is 2n+1, where 1≤n≤5.

[0096] Combined with reference Figures 6 to 8 , Figure 6 and Figure 8 is a top view, Figure 7 for Figure 6 In the cross-sectional view along the AA direction, an emitter 210 is formed on the substrate 100 of the first well region 121 a ; a collector 220 is formed on the substrate 100 of the second well region 122 a ; and a base 230 is formed on the substrate 100 of the third well region 123 a .

[0097] Correspondingly, in the present embodiment, the first region 110a is used to form the emitter 210 and the collector 220. The first well region 121a is arranged at the head and tail of the first region 110a along the second direction. That is to say, in the first region 110a, the emitter 210 and the collector 220 are arranged alternately along the second direction, and the emitter 210 is arranged at the head and tail. Then, in the first region 110a, there are emitters 210 at the head and tail along the second direction to form a bipolar transistor. The second region 120a surrounding the first region 110a is used to form the base 230. That is to say, the base 230 surrounds the area formed by the emitter 210 and the collector 220. Then, the emitter 210 and the collector 220 of the first region 110a share the base 230 of the second region 120a.

[0098] In this embodiment, the collector 220 , the base 230 , and the emitter 210 form a bipolar transistor.

[0099] Specifically, the bipolar transistor is composed of three different doped semiconductor regions, namely, the emitter 210, the base 230 and the collector 220. The charge flow in the transistor is mainly due to the diffusion and drift motion of the carriers at the PN junction. As an example, taking an NPN transistor as an example, the electrons of the emitter 210 move to the base 230 by diffusion, in which the holes are the majority carriers and the electrons are the minority carriers. Since the base 230 is very thin, the electrons reach the collector 220 by drift motion, thereby forming the collector 220 current.

[0100] In the present embodiment, the first well region 121a and the second well region 122a are adjacent to each other and are alternately arranged in the first region 110a. Correspondingly, the emitter 210 and the collector 220 are adjacent to each other and are alternately arranged in the first region 110a, which is beneficial to minimize the space between the emitter 210 and the collector 220, so that the emitter 210 and the collector 220 are arranged compactly, which is beneficial to improve the integration of the semiconductor structure. Moreover, the emitter 210 and the collector 220 are adjacent to each other, which is beneficial to reduce the current path from the collector 220 to the emitter 210, thereby facilitating the improvement of the current gain and further facilitating the improvement of the performance of the semiconductor structure.

[0101] In this embodiment, in the step of forming the emitter 210, the material of the emitter 210 includes silicon phosphide; in the step of forming the collector 220, the material of the collector 220 includes silicon phosphide; in the step of forming the base 230, the material of the base 230 includes silicon germanium.

[0102] In this embodiment, in the step of forming the collector electrodes 220 , the collector electrodes 220 are connected in parallel.

[0103] The collectors 220 are connected in parallel so that the same voltage is applied to each collector 220 to achieve the normal function of the bipolar transistor.

[0104] In this embodiment, in the step of forming the emitter 210 , a plurality of emitters 210 are connected in parallel.

[0105] The plurality of emitters 210 are connected in parallel so that the same voltage is applied to each emitter 210 , thereby achieving the normal function of the bipolar transistor.

[0106] refer to Figure 8 In this embodiment, in the step of providing the substrate 100, the substrate 100 includes a plurality of first regions 110a arranged in an array, and a plurality of second regions 120a surrounding the first regions 110a are interconnected in a grid shape. The plurality of first regions 110a arranged in an array share a base 230 of the second regions 120a connected in a grid shape, so that the semiconductor structure has a higher degree of integration.

[0107] In this embodiment, the method for forming the semiconductor structure further includes: forming a plurality of fins 200 extending along the first direction and arranged in parallel along the second direction on the substrate 100 in the first region 110 a and the second region 120 a respectively.

[0108] The fin 200 is used as a channel of a transistor.

[0109] In this embodiment, in the step of providing the substrate 100 , the substrate 100 also includes a plurality of active regions 210 extending along the first direction and arranged in parallel along the second direction on the substrate 100 in the first region 110 a and the second region 120 a , respectively. Accordingly, the fins 200 are formed in the active regions 210 .

[0110] In this embodiment, the method for forming a semiconductor structure also includes: forming fins 200 extending along the second direction across corresponding areas on the substrate 100 in the first well region 121a, the second well region 122a and the third well region 123a respectively and a plurality of gate structures 300 arranged in parallel along the first direction.

[0111] The gate structure 300 is used to control the opening and closing of the channel of the transistor.

[0112] Specifically, in this embodiment, the gate structure 300 is a metal gate structure.

[0113] In this embodiment, the gate structure 300 includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer.

[0114] The material of the gate dielectric layer includes HfO 2 、ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 、SiO 2 and La 2 O 3 In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO 2 、ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 wait.

[0115] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the material of the gate oxide layer may be silicon oxide.

[0116] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0117] In this embodiment, the gate electrode layer includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0118] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0119] Correspondingly, in the present embodiment, in the step of forming the emitter 210, the emitter 210 is located in the first well region 121a, on the fins 200 on both sides of the gate structure 300; in the step of forming the collector 220, the collector 220 is located in the second well region 122a, on the fins 200 on both sides of the gate structure 300; in the step of forming the base 230, the base 230 is located in the third well region 123a, on the fins 200 on both sides of the gate structure 300.

[0120] It should be noted that, in the present embodiment, in the first region 110a, the gate structure 300 and the fin 200 can control the area of ​​the first region 110a and correspondingly control the emission area. In order to obtain a suitable emission area while ensuring the performance of the semiconductor structure and not making the area of ​​the first region 110a too large and wasteful, and not making the resistance of the semiconductor structure too large, in the present embodiment, in the step of forming the gate structure 300, in the first region 110a, the number of gate structures 300 is 6 to 20; in the step of forming the fin 200, in the first well region 121a, the number of fins 200 is 4 to 12.

[0121] In this embodiment, the method for forming the semiconductor structure also includes: forming an interconnect plug 400, which is located at the top of the emitter 210 and electrically connected to the emitter 210, is also located at the top of the collector 220 and electrically connected to the collector 220, and is also located at the top of the base 230 and electrically connected to the base 230.

[0122] The interconnection plug 400 located on the top of the emitter 210 is used to electrically lead out the emitter 210 to achieve voltage loading on the emitter 210 .

[0123] The interconnection plug 400 located on the top of the collector 220 is used to electrically lead out the collector 220 to achieve voltage loading on the collector 220 .

[0124] The interconnection plug 400 located on the top of the base 230 is used to electrically lead out the base 230 to achieve voltage loading on the base 230 .

[0125] In this embodiment, the interconnection plug 400 is made of tungsten. In other embodiments, the interconnection plug may also be made of cobalt or ruthenium.

[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: A substrate, comprising a first region and a second region surrounding the first region, wherein the first region comprises a first well region and a second well region extending along a first direction and arranged alternately along a second direction, and along the second direction, the first well regions are arranged at the beginning and the end of the first region, and the second region comprises a third well region, and the third well region has the same doping type as the first well region, and the first well region has a different doping type from the second well region; An emitter, located on the substrate of the first well region; a collector electrode, located on the substrate of the second well region; The base is located on the substrate of the third well region.

2. The semiconductor structure according to claim 1, It is characterized in that The doping type of the substrate is the same as the doping type of the first well region.

3. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further includes: a plurality of fins extending along the first direction and arranged in parallel along the second direction on the substrate in the first region and the second region respectively; A plurality of gate structures respectively extending along the second direction across the fins of the corresponding regions on the substrates of the first well region, the second well region and the third well region and arranged in parallel along the first direction; The emitter is located in the first well region and on the fins on both sides of the gate structure; The collector is located in the second well region and on the fins on both sides of the gate structure; The base is located in the third well region and on the fins on both sides of the gate structure.

4. The semiconductor structure according to claim 3, It is characterized in that In the first region, the number of the gate structures is 6 to 20.

5. The semiconductor structure according to claim 3, It is characterized in that In the first well region, the number of the fins is 4 to 12.

6. The semiconductor structure according to claim 3, It is characterized in that The material of the emitter includes silicon phosphide; the material of the collector includes silicon phosphide; and the material of the base includes silicon germanium.

7. The semiconductor structure according to claim 1, It is characterized in that In the first region, the total number of the first well regions and the second well regions is 2n+1, where 1≤n≤5.

8. The semiconductor structure according to claim 1, It is characterized in that The substrate includes a plurality of first regions arranged in an array, and a plurality of second regions surrounding the first regions are interconnected to form a grid.

9. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, comprising a first region and a second region surrounding the first region, wherein the first region comprises a first well region and a second well region extending along a first direction and arranged alternately along a second direction, and along the second direction, the first well regions are arranged at the beginning and the end of the first region, and the second region comprises a third well region, and the third well region has the same doping type as the first well region, and the first well region has a different doping type from the second well region; forming an emitter on the substrate of the first well region; forming a collector electrode on a substrate of the second well region; A base is formed on the substrate of the third well region.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that In the step of providing the substrate, the doping type of the substrate is the same as the doping type of the first well region.

11. The method for forming a semiconductor structure according to claim 9, It is characterized in that The method for forming the semiconductor structure further includes: forming a plurality of fins extending along the first direction and arranged in parallel along the second direction on the substrate in the first region and the second region respectively; Forming a plurality of gate structures extending along the second direction and crossing the fins of the corresponding regions on the substrates of the first well region, the second well region and the third well region respectively and arranged in parallel along the first direction; In the step of forming the emitter, the emitter is located in the first well region and on the fins on both sides of the gate structure; In the step of forming the collector, the collector is located in the second well region and on the fins on both sides of the gate structure; In the step of forming the base, the base is located in the third well region and on the fins on both sides of the gate structure.

12. The method for forming a semiconductor structure according to claim 11, It is characterized in that In the step of forming the gate structure, the number of the gate structures in the first region is 6 to 20.

13. The method for forming a semiconductor structure according to claim 11, It is characterized in that In the step of forming the fins, the number of the fins in the first well region is 4 to 12.

14. The method for forming a semiconductor structure according to claim 11, It is characterized in that In the step of forming the emitter, the material of the emitter includes silicon phosphide; In the step of forming the collector, the material of the collector includes silicon phosphide; In the step of forming the base, the material of the base includes silicon germanium.

15. The method for forming a semiconductor structure according to claim 9, It is characterized in that In the step of providing the substrate, in the first region, the total number of the first well regions and the second well regions is 2n+1, where 1≤n≤5.

16. The method for forming a semiconductor structure according to claim 9, It is characterized in that In the step of providing the substrate, the substrate includes a plurality of first regions arranged in an array, and a plurality of second regions surrounding the first regions are interconnected in a grid shape.

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