Lateral metal oxide semiconductor device, grid electrode thereof and manufacturing method of grid electrode

Abstract

The embodiment of the invention discloses a lateral metal oxide semiconductor (MOS) device, a grid electrode thereof and a manufacturing method thereof. In fabricating a lateral MOS device, source and drain regions of the lateral MOS device are formed in a base semiconductor. A gate oxide layer is disposed on the base semiconductor, and a gate layer is disposed on the gate oxide layer. Performing photoetching patterning etching on the grid electrode layer to form a first side of the grid electrode facing the source electrode; a lithographic patterned etch is performed on the gate layer to form a second side of the gate facing the drain of the lateral MOS device, and a cavity partially extending below the second side of the gate is also etched. A dielectric layer is formed on at least the first side and the second side of the gate, and the dielectric layer fills a portion of the cavity extending below the second side of the gate.

Description

Technical Field

[0001] The disclosed embodiments relate to a lateral metal oxide semiconductor device and a gate thereof and a manufacturing method thereof. Background Art

[0002] The following relates to semiconductor manufacturing technology, lateral metal oxide semiconductor (MOS) devices and their manufacturing and fabrication, lateral double diffused MOS devices and their fabrication, high power electronic devices and related technologies. Summary of the invention

[0003] In a non-limiting illustrative embodiment, a method for fabricating a lateral metal oxide semiconductor (MOS) device is disclosed. The method includes: forming a source of the lateral MOS device in a base semiconductor; forming a drain of the lateral MOS device; disposing a gate oxide layer on the base semiconductor; disposing a gate layer on the gate oxide layer; photolithographically patterning and etching the gate layer to form a first side of the gate facing the source of the lateral MOS device; photolithographically patterning and etching the gate layer to form a second side of the gate facing the drain of the lateral MOS device, and etching a cavity partially extending below the second side of the gate; forming a dielectric layer on at least the first and second sides of the gate, and the dielectric layer fills the cavity partially extending below the second side of the gate.

[0004] In a non-limiting illustrative embodiment, a lateral MOS device includes: a base semiconductor; a gate oxide disposed on the base semiconductor; a gate disposed on the gate oxide; a source region disposed on a first side of the gate and laterally offset from the gate; a drain region disposed on a second side of the gate and laterally offset from the gate; and a dielectric layer disposed on a sidewall of the gate and including an extension of the dielectric layer extending partially below the second side of the gate.

[0005] In a non-limiting illustrative embodiment, a method for manufacturing a gate lateral MOS device is disclosed. The method includes: disposing a gate layer on a gate oxide layer; performing photolithographic patterning etching on the gate layer to form a first side of the gate facing the source of the lateral MOS device; performing photolithographic patterning etching on the gate layer to form a second side of the gate facing the drain of the lateral MOS device, and etching a cavity partially extending below the second side of the gate, including: (i) a first etching to remove an upper portion of the gate layer to expose an upper portion of the second side of the gate, and (ii) a second etching to remove a lower portion of the gate layer to completely expose the second side of the gate, and further remove a portion of the gate layer below the second side of the gate to form a cavity partially extending below the second side of the gate; forming a dielectric layer on at least the first side and the second side of the gate, and the dielectric layer fills the cavity partially extending below the second side of the gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features may be increased or decreased arbitrarily.

[0007] Figure 1 and Figure 2 Schematically shows a side cross-sectional view of a lateral MOS device ( Figure 1 ) and top view ( Figure 2 ).

[0008] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I and Figure 3J Schematically illustrates a side cross-sectional view of a gate region of a lateral MOS device at successive manufacturing stages.

[0009] Figure 4 A side cross-sectional view of a gate region of a lateral MOS device having the dimensions shown is schematically shown. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] Lateral metal oxide semiconductor (MOS) devices are used in a variety of applications. For example, lateral double diffused MOS (LDMOS) devices are commonly used in high power circuits and devices, such as microwave power amplifiers, radio frequency power amplifiers, audio amplifiers, and other types of amplifiers, and are used in a variety of systems such as mobile phone devices. The advantage of lateral MOS devices for high power applications is that they have a high breakdown voltage, such as greater than 50 volts in some designs. Double diffused or other dopant distribution designs provide flexibility in designing doping profiles to accommodate high electric fields in power devices.

[0013] In LDMOS designs, breakdown at the breakdown voltage typically occurs on the gate-to-drain side of the LDMOS device. For silicon devices, the electric field at which breakdown occurs is typically about 3×10 5 V-cm -1 One way to increase the breakdown voltage is to increase the gate-to-drain length so that the voltage drop is spread over a longer length, thereby reducing the peak electric field. However, this increases the footprint of the device, thereby reducing LDMOS device array density and increasing wafer cost.

[0014] In the simulation of LDMOS devices, it was found that the peak electric field at breakdown usually occurs near the gate side facing the drain of the LDMOS device. In the simulation, the breakdown occurs in the n / p depletion region around the gate edge on the drain-facing side of the gate. The simulation analyzes key performance indicators, including hot carrier injection (HCI) and HCI-time dependent dielectric breakdown (HCI-TDDB).

[0015] Typically, the dielectric layer is disposed on the sidewalls of the gate, such as surrounding or circumferentially coating the sidewalls of the gate. As disclosed herein, the breakdown voltage can be increased by including an extension of the dielectric layer that extends partially below the drain-facing side of the gate. For example, in some embodiments, the extension of the dielectric layer is disposed between the bottom of the drain-facing side of the gate and the gate oxide below. The extension of the dielectric layer reduces the electric field at the edge of the gate, thereby increasing the breakdown voltage. This improvement in breakdown voltage is advantageously obtained without increasing the gate-to-drain length of the LDMOS device or otherwise modifying the LDMOS design. Although described herein with respect to LDMOS devices, it is expected that this improvement can also be achieved for other types of lateral MOS devices.

[0016] A method of manufacturing is also disclosed herein, which can self-align to form a dielectric layer configured on the sidewall of the gate, and the extension of this dielectric layer is configured under the portion of the gate facing the drain side. The disclosed method uses a two-step etching process to pattern the gate from the deposited gate layer. The two-step etching process includes a series of first etching and second etching. The first etching removes the upper portion of the gate layer to expose the upper portion of the gate facing the drain side, while leaving a thinned portion of the gate layer, which extends laterally away from the drain-facing side of the gate (not completely exposed at this time). The first etching is an anisotropic dry etching that provides a high aspect ratio etching, such as reactive ion etching (RIE) or deep reactive ion etching (DRIE). The first dry etching is performed using selected etching parameters (e.g., radio frequency (RF) field) to provide a high aspect ratio anisotropic etching. Then, the first etching is followed by a second etching, which is isotropic, or has a lower anisotropy than the first etching (i.e., providing a less high aspect ratio etching). The second etching removes the remaining thinned portion of the gate layer to completely expose the drain-facing side of the gate, and also removes a portion of the gate layer below the drain-facing side of the gate to form a hole extending partially below the drain-facing side of the gate. By controlling the etching time of the first etching, the thickness of the remaining thinned portion of the gate layer can be controlled. By controlling the etching parameters of the second etching, the amount of etching anisotropy (or, in the extreme case, isotropic etching) can be obtained to obtain a hole with a desired size extending partially below the drain-facing side of the gate. After the second etching is completed, a dielectric layer is formed, for example, by chemical vapor deposition (CVD) or thermal oxidation, and the dielectric layer is formed on the sidewalls of the gate and fills the inside of the hole extending partially below the drain-facing side of the gate, thereby partially forming an extension of the dielectric layer below the drain-facing side of the gate.

[0017] This process has significant advantages. In order to obtain an extension of the dielectric layer of the lower portion of the drain-facing side of the gate, the modification of the manufacturing process is minimal. For example, in a non-limiting illustrative example, the modification requires changing one or more etching parameters during the dry etching process of forming the drain-facing side of the gate to provide the desired reduction in anisotropy (i.e., a reduction in the aspect ratio of the etching) to switch from a first etching process to a second etching process. Alternatively, two different etching process scans can be used, for example, the first etching process is an anisotropic dry etching process, and the second etching process is an isotropic wet etching process. The dielectric material of the extension is the same as the dielectric material of the dielectric layer coating the sidewalls of the gate, which provides a robust manufacturing process and an expected yield.

[0018] refer to Figure 1 and Figure 2 , respectively, through the side section view ( Figure 1 ) and top view ( Figure 2) schematically shows a lateral MOS device. The lateral MOS device is fabricated on a base semiconductor 10. The base semiconductor may be a silicon wafer, a silicon layer of a silicon-on-insulator (SOI) wafer, an epitaxial silicon layer deposited on a semiconductor wafer, etc. Although the description is made using a silicon-based lateral MOS device as an example, more generally, the lateral MOS device may be fabricated using another semiconductor material system, such as silicon-germanium, other Group IV alloys (e.g., SiC), gallium arsenide (GaAs), or other Group III-V materials (e.g., GaAs, GaP, Al x Ga (1-x) As, GaN, etc.), various combinations thereof, etc. In some embodiments, the base semiconductor 10 has a doping level, for example, a p-type doping level is adopted in the illustrative embodiments herein.

[0019] Appropriate doping of the base semiconductor 10 is performed to form n-type and / or p-type doping regions and / or spatially varying doping profiles of the lateral MOS. For example, n-type doping may be performed to form a source (or source region) 12 of the lateral MOS device and a drain (or drain region) 14 of the lateral MOS device. Figure 1 Indicated schematically only, in one non-limiting illustrative example, the lateral MOS device is a lateral double diffused MOS (LDMOS) device that includes a double diffused n+ / n doped region, wherein a larger n-type region (also referred to herein as a drift region 16) is formed by a first n-type dopant diffusion process, followed by a second n-type dopant diffusion process to form an n+ drain 14 within the n-type drift region 16. Optionally, the n+ source region 12 may be formed in the same dopant diffusion process as the n+ drain region 14. The notation of the n+ drain 14 within the n-type drift region 16 indicates that the n-type doping concentration of the drain 14 is higher than the n-type doping concentration of the n-doped drift region 16. The p-type well or body region 18 may be optionally formed by p-type diffusion into the base semiconductor 10 to produce a p-type well 18 having a higher p-type doping concentration than the p-type doping concentration of the base semiconductor 10.

[0020] like Figure 1 and Figure 2 It can be further seen that the gate 20 is interposed between the source 12 and the drain 14. The gate 20 is disposed on a gate oxide 22, which in turn is disposed on the base semiconductor 10. The length L of the lateral channel region 24 (only Figure 1 ) is located between the p-type well 18 and the n-type drift region 16. In a proper operating mode, the source 12 is grounded, the drain 14 has a high voltage (HV) applied, and a control voltage (Vtg) is applied to the gate 20 to modulate the current flowing between the source 12 and the drain 14 via the channel region 24.

[0021] It should be understood that Figure 1The doped regions 16, 18 shown are non-limiting illustrative examples, and the disclosed methods including extensions of the gate sidewall coating dielectric layer extending partially below the drain-facing side of the gate may be employed in conjunction with substantially any type of lateral MOS device design. By way of some non-limiting illustrative examples, in some variant lateral MOS designs, it is contemplated that: one or both of the doped regions 16 and / or 18 shown may be omitted; and the drift region may be extended below the p-type well; additional p+-type regions may be added, embedded in the p-type well 18 and contacting the n+ source 12 to suppress the body effect; the doping polarity of the lateral MOS may be reversed (i.e., switching the n-type region to the p-type region and vice versa); various combinations thereof; and / or the like.

[0022] The sidewall of the exemplary gate 20 is a rectangular cylindrical sidewall having four sides: a first side 30 (i.e., a side 30 facing the source); a second side 32 (i.e., a side 32 facing the drain); and third and fourth sides 36 and 38 extending between the source-facing and drain-facing sides 30 and 32, respectively. The first (source-facing) side 30 of the gate 20 and the second (drain-facing) side 32 of the gate 20 are opposite to the sidewalls of the rectangular cylindrical sidewall. The source region 12 is disposed on the first (i.e., source-facing) side 30 of the gate 20, laterally offset from the gate, and the drain region 14 is disposed on the second (i.e., drain-facing) side 32 of the gate 20, laterally offset from the gate 20.

[0023] The dielectric layer 40 circumferentially covers all four sides 30 , 32 , 36 , 38 of the rectangular cylindrical sidewall of the gate 20 . An extension 40E of the sidewall coating dielectric layer 40 partially extends below the second side 32 of the gate 20 . Figure 1 The side cross-sectional view of FIG. 4 shows a cross-sectional view of the extension 40E of the dielectric layer 40 . Figure 2 The top view of FIG. 4 shows the extension 40E of the dielectric layer 40 by hidden lines. In the illustrative example, the extension 40E of the dielectric layer 40 partially extends under the second (drain-facing) side 32 of the gate 20; no corresponding extension extends under the first (source-facing) side 30 of the gate 20. Figure 2 As shown, the extension 40E of the dielectric layer 40 extends along the length of the second (drain-facing) side 32 of the gate 40. That is, in some embodiments, the extension 40E of the dielectric layer 40 extends along the length of the second (drain-facing) side 32 of the gate 40. Figure 2 The length in the Y direction is shown to be coextensive with the length of the (drain-facing) side 32 of the gate 40 in the Y direction.

[0024] like Figure 2It can be further seen that there is no corresponding extension extending below the connection sides 36 and 38. In other words, the dielectric layer 40 circumferentially covers the sidewalls of the gate 20, and the extension 40E of the dielectric layer 40 only partially extends below the gate 20 on the second (drain-facing) side 32 of the gate 20. In addition, as shown in FIG. Figure 1 As shown in the side cross-sectional view of , the dielectric layer 40 covers the sidewalls of the gate 20, but does not cover the top of the gate 20, so as to provide a channel to the gate 20 for applying the control voltage Vtg. Figure 1 In the embodiment shown, an optional additional spacer 42 may be applied to the dielectric layer 40. Note that Figure 2 The spacer 42 is not shown in the top view of FIG. 4 to emphasize the structure of the gate 20 , the dielectric layer 40 , and the extension 40E of the dielectric layer 40 .

[0025] Without loss of generality, for descriptive purposes, Figure 1 and Figure 2 The axes or directions of the Cartesian coordinate system are marked, including the X axis or direction, the Y axis or direction, and the Z axis or direction. Figure 1 The side section view is taken along the XZ plane. Figure 2 The top view is the view along the Z direction. Figure 1 Also shown is a graph of the electric field (E-field) during reverse biasing of the LDMOS device versus the X position along the surface of the base semiconductor 10. The coordinate X shown in this figure p corresponds to the X position of the second (drain-facing) side 32 of the gate 20 . Figure 1 The plot of the electromagnetic simulation results of the operating LDMOS device shows that the peak electric field during reverse bias occurs at position X p At or near the surface of the base semiconductor 10. The location of the peak reverse bias electric field is at Figure 1 Indicated as position (X p ,Z p ). In the position (X p ,Z p ), it was found that the peak electric field at 40E was reduced by including the extension 40E of the dielectric layer 40. In an experimental comparison of LDMOS devices actually manufactured with and without the extension 40E or the dielectric layer 40, it was found that the breakdown voltage V bd The breakdown voltage V bd The increase in is believed to be attributable to the increase in the second (drain-facing) side 32 (i.e., position (X p ,Z p )The reduction of the peak electric field.

[0026] In some non-limiting illustrative embodiments, base semiconductor 10 comprises silicon, gate oxide 22 comprises silicon dioxide, gate 20 comprises metal, metal alloy, polysilicon material, silicide material, or a combination of silicide and polysilicon materials, and dielectric layer 40 (including extension 40E) comprises oxide material, nitride material, carbide material, oxynitride material, oxycarbide material, nitride carbide material, or polymer material. These are just some non-limiting illustrative examples. Due to the improvement (e.g., breakdown voltage V bd The increase in peak electric field is believed to be due to the geometric changes at the second (drain-facing) side 32 introduced by the extension 40E, resulting in a reduction in the peak electric field, and thus improvements in performance indicators, such as breakdown voltage, are expected to be obtained by including the extension 40E of the dielectric layer 40, independent of the material of the lateral MOS device and independent of the detailed structure (e.g., the distribution of doping regions 16, 18).

[0027] Another advantage is that the advantages of including the extension 40E of the dielectric layer 40 can be achieved with minimal modification to the lateral MOS device manufacturing process.

[0028] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I and Figure 3J The schematic diagram shows a side cross-sectional view of the gate region of a lateral MOS device at successive manufacturing stages. Since this manufacturing process involves the formation of the gate 20, in particular the manufacture of the dielectric layer 40 and its extension 40E, the doping step involves the doping region of the lateral MOS device (e.g., Figure 1 The formation of doped regions 16 and 18 shown in the non-limiting illustrative example of FIG. 1 is not discussed. However, as is known in the art, in some lateral MOS device manufacturing process flows, gates may be used to control the spatial extent of certain doped regions. Thus, doping steps (e.g., dopant diffusion and / or dopant implantation steps) may be interspersed in successive steps. Figures 3A-3J The steps described in .

[0029] Figure 3AA side cross-sectional view of a gate region being fabricated is shown after depositing a gate oxide layer 22L and a gate layer 20L (which will be patterned to form a gate oxide 22 and a gate 20, respectively), a hard mask layer 50, and a photoresist layer 52. The gate oxide layer 22L may be a silicon dioxide layer formed by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable techniques. Other oxide materials may also be considered for the gate oxide layer 22L. As some non-limiting illustrative examples, the gate layer 20L may include a metal, a metal alloy, a polysilicon material, a silicide material, or a combination of silicide and polysilicon materials, and may be deposited on the gate oxide layer 22L by CVD or another deposition technique suitable for the selected gate material. For example, the hard mask layer 50 may be disposed on the gate layer 20L by CVD deposition of a hard mask layer 50 including silicon oxynitride, but other suitable hard materials and corresponding deposition techniques may also be considered. As a non-limiting illustrative example, the photoresist layer 52 may be formed by a spin coating process.

[0030] Figure 3B A side cross-sectional view of the gate region being fabricated is shown after patterning a photoresist layer 52 by photolithographic exposure and development to form an opening 54 with an edge 56 aligned with a first (source-facing) side 30 of the gate being fabricated.

[0031] Figure 3C A side cross-sectional view of the gate region being fabricated is shown after etching the gate layer 20L to form the first (source-facing) side 30 of the gate. This etching step also etches the portion of the hard mask layer 50 that is located above the removed portion of the gate layer to align with the portion of the gate oxide layer 22L that is located below the removed portion of the gate layer. The etching step suitably uses an anisotropic dry etch that provides a high aspect ratio etch, such as reactive ion etching (RIE) or deep reactive ion etching (DRIE), so that the first (source-facing) side 30 of the formed gate is aligned with the edge 56 of the opening 54 in the patterned photoresist.

[0032] exist Figure 3C Thereafter, the patterned photoresist layer 52 is stripped using an appropriate photoresist stripping solvent or the like.

[0033] Figure 3D A side cross-sectional view of the gate region being fabricated is shown after stripping of the (first) photoresist layer 52 and depositing of the (second) photoresist layer 62 by a spin coating process or the like.

[0034] Figure 3E A side cross-sectional view of the gate region being fabricated is shown after patterning a (second) photoresist layer 62 by photolithographic exposure and development to form edges 66 of openings 64 thereof aligned with the second (drain-facing) side 32 of the gate being fabricated.

[0035] Figure 3F A side cross-sectional view of the gate region being fabricated is shown after partially etching the gate layer 20L to form an upper portion 32U of the second (drain facing) side 32 of the gate. This etching step also etches portions of the hard mask layer 50 covering the removed portion of the gate layer, and appropriately uses an anisotropic dry etch that provides a high aspect ratio etch, such as RIE or DRIE, so that the upper portion 32U of the second (drain facing) side 32 of the gate is aligned with the edge 66 of the opening 64 of the patterned photoresist layer.

[0036] It is worth noting that Figure 3C The etching steps for forming the first (source-facing) side 30 of the gate shown in FIG. Figure 3F The etching process shown in FIG. 6 does not completely remove the gate layer below the opening 64. Instead, the etching is the first etching process of a two-stage etching process, and the first stage etching process leaves a thinned portion 20 of the gate layer. 减薄 , which thinned portion extends laterally away from the drain-facing side of the gate (which is not fully exposed at this time) (i.e., the upper portion 32U of the drain-facing side). The majority of the formed gate 20' is formed at this stage of the manufacturing process, except for the remaining thinned portion 20 of the gate layer extending away from the now majority of the formed gate 20'. 减薄 Besides.

[0037] Figure 3G The remaining thinned portion 20 of the gate layer is removed by the second stage etching process of the two-stage etching process. 减薄 A side cross-sectional view of the gate region being fabricated. The second etching process removes the thinned portion 20 of the gate layer. 减薄 , and a portion of the gate layer below the edge is also removed to form a cavity 70 that extends partially below the second side 32 of the (now fully formed) gate 20. In the illustrative example, the cavity 70 extends partially below the second side 32 of the gate 20. To achieve the removal of the thinned portion 20 of the gate layer 减薄 The second etching process is an isotropic etching process or a process for exposing the second side 32 of the upper portion 32U (see Figure 3F ) is an etching process with less anisotropy than the first etching process.

[0038] To this end, in some embodiments, the upper portion 32U ( Figure 3F The first dry etch of ( ) is performed with selected etching parameters (e.g., RF field) to provide the desired high aspect ratio anisotropic etch. The first etch is then followed by a second etch ( Figure 3G), in this example, the second etch may be a dry etch technique, such as RIE or DRIE, but uses different etch parameters to perform less anisotropy than the first etch (i.e., provide a less high aspect ratio etch). Thus, this more isotropic second etch process provides a significant lateral etch direction component to form the void 70. It should be understood that the size of the void 70 can be adjusted by adjusting the process parameters, such as the etching time of the first etch process (where a shorter first etch will leave a larger thickness of the remaining thinned portion 20 减薄 , so that the second etch produces higher voids 70 in the Z direction) and an aspect ratio of the second etch process, where a lower aspect ratio corresponds to a less anisotropic second etch (or equivalently, a more isotropic second etch) and therefore deeper voids 70 in the X direction.

[0039] In the foregoing examples, both the first etching process and the second etching process are dry etching processes, and in some embodiments can be performed in a single dry etching chamber using a single etching recipe, where the recipe switches etching parameters to switch from a more anisotropic first etching to a less anisotropic (or more isotropic) second etching. However, other approaches are contemplated, such as using different etching modes for the first etching process and the second etching process. For example, in another embodiment, the second etching process is implemented as an isotropic wet etching process.

[0040] Figure 3H 1 shows a side cross-sectional view of the gate region being fabricated after stripping the (second) patterned photoresist layer 62 using a suitable photoresist stripping solvent or the like. Figure 3H As shown, this leaves a fully formed gate 20 having a first (source-facing) side 30 and a second (drain-facing) side 32 , with the cavity extending partially under the second side of the gate 20 .

[0041] Fig. 3I A side cross-sectional view of the gate region being fabricated after the dielectric layer 40L is deposited is shown. The dielectric layer 40L is suitably deposited via CVD to conformally cover the dielectric layer, or is formed via thermal oxidation, etc. The dielectric layer 40L may, for example, include an oxide material, a nitride material, a carbide material, an oxynitride material, an oxycarbide material, a nitride carbide material, or a polymer material. The dielectric layer 40L is formed using an isotropic (or nearly isotropic) deposition process, so that the dielectric material of the dielectric layer 40L is deposited approximately conformally, including coating the sidewalls of the gate 20 and filling the cavity 70 extending partially below the second side 32 of the gate 20. The dielectric material filling the cavity 70 forms an extension 40E of the sidewall coating dielectric layer.

[0042] Figure 3JA side cross-sectional view of the gate region is shown after portions of dielectric layer 40L are subsequently etched to leave coating dielectric layer 40 circumferentially covering all four sides 30, 32, 36, 38 of the rectangular cylindrical sidewalls of gate 20 and an extension 40E of coating dielectric layer 40 extending partially under second side 32 of gate 20. Figure 3J In the exemplary embodiment of FIG. 4 , the extension 40E of the sidewall-coating dielectric layer 40 extends partially below the second side 32 of the gate 20 , and is thus disposed between the gate oxide 22 and the second side 32 of the gate 20 .

[0043] Reference now Figure 4 , showing a side cross-sectional view of the gate region of a lateral MOS device. Figure 4 Shows Figure 4 A gate oxide 22 is disposed on the base semiconductor 10 , and a gate 20 is disposed on the gate oxide 22 . Figure 4 Also marked are the first (source-facing) side 30 and the second (drain-facing) side 32 of the gate 20, the sidewall-coating dielectric layer 40 having an extension 40E, and the optional spacer 42. In addition, Figure 4 Certain dimensions are indicated in the Dimensions X 栅极 represents the width of the gate 20 along the channel direction. In other words, the dimension X 栅极 Dimension Z represents the lateral spacing between the first side 30 and the second side 32 of the gate 20. 栅极 The height of the gate 20 is indicated by the extension 40E of the dielectric layer 40 below the second side 32 of the gate 20. The dimension X E represents the lateral distance of the extension 40E of the dielectric layer 40 below the second side 32 of the gate 20, and dimension Z E represents the height of the extension portion 40E of the dielectric layer 40 .

[0044] In some non-limiting illustrative embodiments, the lateral distance X of the extension 40E of the dielectric layer 40 below the second side 32 of the gate 20 is E The lateral spacing X between the first side 30 and the second side 32 of the gate 20 栅极 The ratio X E / X 栅极 Between 0.01 and 0.1. The breakdown voltage V due to the extension 40E bd The increase in the ratio X is expected to E / X 栅极 However, if the ratio X E / X 栅极 If the value is too large, it is expected to increase the risk of damage to the structural integrity of the gate 20. Therefore, 0.01 < X E / X 栅极 <0.1 is expected to increase Vbd and maintaining a high yield in the fabricated lateral MOS devices.

[0045] In some non-limiting illustrative embodiments, the lateral distance X of the extension 40E of the dielectric layer 40 below the second side 32 of the gate 20 is E The lateral spacing X between the first side 30 and the second side 32 of the gate 20 栅极 The ratio X E / X 栅极 is at least 0.01.

[0046] In some non-limiting illustrative embodiments, the height Z of the extension 40E of the dielectric layer 40 is E The height Z of the gate 20 栅极 The ratio Z E / Z 栅极 Between 0.01 and 0.5. The breakdown voltage V due to the extension 40E bd The increase in the ratio Z is expected to E / Z 栅极 However, if the ratio Z E / Z 栅极 If Z is too large, it is expected to increase the risk of damage to the structural integrity of the gate 20. Therefore, 0.01 < Z E / Z 栅极 <0.5 is expected to increase V bd The present invention provides an appropriate balance between the desire to achieve the desired performance and maintaining the yield of the fabricated lateral MOS devices.

[0047] In some non-limiting illustrative embodiments, the height Z of the extension 40E of the dielectric layer 40 is E The height Z of the gate 20 栅极 The ratio Z E / Z 栅极 is at least 0.01.

[0048] In the following, some further embodiments are described.

[0049] In a non-limiting illustrative embodiment, a method for fabricating a lateral metal oxide semiconductor (MOS) device is disclosed. The method includes: forming a source of the lateral MOS device in a base semiconductor; forming a drain of the lateral MOS device; disposing a gate oxide layer on the base semiconductor; disposing a gate layer on the gate oxide layer; photolithographically patterning and etching the gate layer to form a first side of the gate facing the source of the lateral MOS device; photolithographically patterning and etching the gate layer to form a second side of the gate facing the drain of the lateral MOS device, and etching a cavity partially extending below the second side of the gate; forming a dielectric layer on at least the first and second sides of the gate, and the dielectric layer fills the cavity partially extending below the second side of the gate.

[0050] In some embodiments, photolithographically patterning and etching the gate layer to form the second side of the gate and etching the cavity extending partially below the second side of the gate includes: disposing a hard mask layer on the gate layer; disposing a photoresist layer on the hard mask layer; patterning the photoresist layer and the hard mask layer to form an edge; performing a first etching process to remove an upper portion of the gate layer in a region extending to the edge, the first etching process forming an upper portion of the second side of the gate aligned with the edge and leaving a thinned portion of the gate layer laterally away from the extending edge; performing a second etching process to remove the thinned portion of the gate layer to form a lower portion of the second side of the gate aligned with the edge, and removing a portion of the gate layer below the edge to form the cavity extending partially below the second side of the gate. In some embodiments, the first etching process is more anisotropic than the second etching process. In some embodiments, the first etching process is an anisotropic dry etching process; and the second etching process is an isotropic or less anisotropic dry etching process than the first etching process. In some embodiments, configuring the hard mask layer on the gate layer includes depositing the hard mask layer comprising silicon oxynitride by chemical vapor deposition. In some embodiments, forming the dielectric layer on at least the first side and the second side of the gate and the dielectric layer filling the cavity extending partially below the second side of the gate includes: depositing the dielectric layer by chemical vapor deposition or forming the dielectric layer by thermal oxidation. In some embodiments, the base semiconductor includes silicon; the gate oxide includes silicon dioxide; the gate includes a metal, a metal alloy, a polysilicon material, a silicide material, or a combination of a silicide and a polysilicon material; and the dielectric layer includes an oxide material, a nitride material, a carbide material, an oxynitride material, an oxycarbon material, a nitride carbide material, or a polymer material. In some embodiments, photolithographically patterning and etching the gate layer to form the first side of the gate does not include etching a cavity below the first side of the gate.

[0051] In a non-limiting illustrative embodiment, a lateral MOS device includes: a base semiconductor; a gate oxide disposed on the base semiconductor; a gate disposed on the gate oxide; a source region disposed on a first side of the gate and laterally offset from the gate; a drain region disposed on a second side of the gate and laterally offset from the gate; and a dielectric layer disposed on a sidewall of the gate and including an extension of the dielectric layer extending partially below the second side of the gate.

[0052] In some embodiments, the dielectric layer circumferentially covers the sidewall of the gate, and the extension of the dielectric layer only partially extends under the second side of the gate. In some embodiments, the sidewall of the gate is a rectangular columnar sidewall having four sides, including the first side of the gate and the second side of the gate, the first side and the second side of the gate being opposite sides of the rectangular columnar sidewall of the gate; the dielectric layer circumferentially covers all four sides of the rectangular columnar sidewall; and the extension of the dielectric layer partially extends under the second side of the gate and does not extend under the first side of the gate. In some embodiments, the lateral metal oxide semiconductor device comprises a lateral double diffused metal oxide semiconductor device, comprising a double diffusion region, the double diffusion region comprising: a first n-type doped region forming a drift region of the lateral double diffused metal oxide semiconductor device, and a second n-type doped region disposed in the first n-type doped region and forming the drain region, the second n-type doped region having a higher n-type doping concentration than the first n-type doped region. In some embodiments, the dielectric layer and the extension of the dielectric layer include an oxide material, a nitride material, a carbide material, an oxynitride material, an oxycarbon material, a nitride carbide material, or a polymer material. In some embodiments, the base semiconductor includes silicon; the gate oxide includes silicon dioxide; and the gate includes a metal, a metal alloy, a polysilicon material, a silicide material, or a combination of silicide and polysilicon materials. In some embodiments, the ratio of the lateral distance of the extension of the dielectric layer below the second side of the gate to the lateral spacing between the first side and the second side of the gate is between 0.01 and 0.1. In some embodiments, the ratio of the height of the extension of the dielectric layer to the height of the gate is between 0.01 and 0.5.

[0053] In a non-limiting illustrative embodiment, a method for manufacturing a gate lateral MOS device is disclosed. The method includes: disposing a gate layer on a gate oxide layer; performing photolithographic patterning etching on the gate layer to form a first side of the gate facing the source of the lateral MOS device; performing photolithographic patterning etching on the gate layer to form a second side of the gate facing the drain of the lateral MOS device, and etching a cavity partially extending below the second side of the gate, including: (i) a first etching to remove an upper portion of the gate layer to expose an upper portion of the second side of the gate, and (ii) a second etching to remove a lower portion of the gate layer to completely expose the second side of the gate, and further remove a portion of the gate layer below the second side of the gate to form a cavity partially extending below the second side of the gate; forming a dielectric layer on at least the first side and the second side of the gate, and the dielectric layer fills the cavity partially extending below the second side of the gate.

[0054] In some embodiments, the second etch is isotropic or less anisotropic than the first etch. In some embodiments, the first etch is a dry etch and the second etch is a dry etch. In some embodiments, the gate layer comprises a polysilicon layer, and the dielectric layer comprises an oxide material, a nitride material, a carbide material, an oxynitride material, an oxycarbon material, a nitride carbide material, or a polymer material.

[0055] In a non-limiting illustrative embodiment, in manufacturing a MOS device, source and drain regions are formed by n-doping a base semiconductor. A gate oxide layer is disposed on the base semiconductor, and a gate layer is disposed on the gate oxide layer. The gate layer is photolithographically patterned and etched to form a first side of the gate facing the source. The gate layer is photolithographically patterned and etched to form a second side of the gate facing the drain, and a cavity is also etched that partially extends below the second side of the gate. A dielectric layer is formed on at least the first and second sides of the gate, and the dielectric layer fills the cavity that partially extends below the second side of the gate.

[0056] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a lateral metal oxide semiconductor device, characterized in that: The method comprises: forming a source of the lateral metal oxide semiconductor device in a base semiconductor; forming a drain of the lateral metal oxide semiconductor device; disposing a gate oxide layer on the base semiconductor; disposing a gate layer on the gate oxide layer; Performing photolithographic patterning and etching on the gate layer to form a first side of the gate facing the source of the lateral metal oxide semiconductor device; Performing photolithographic patterning etching on the gate layer to form a second side of the gate facing the drain of the lateral metal oxide semiconductor device and etching a cavity partially extending below the second side of the gate; and A dielectric layer is formed on at least the first side and the second side of the gate, and the dielectric layer fills a portion of the cavity extending below the second side of the gate.

2. The method for manufacturing a lateral metal oxide semiconductor device according to claim 1, wherein the step of photolithographically patterning and etching the gate layer to form the second side of the gate and etching the cavity partially extending below the second side of the gate comprises: Disposing a hard mask layer on the gate layer; Disposing a photoresist layer on the hard mask layer; patterning the photoresist layer and the hard mask layer to form an edge; performing a first etching process to remove an upper portion of the gate layer in a region extending to the edge, the first etching process forming an upper portion of the second side of the gate aligned with the edge and leaving a thinned portion of the gate layer laterally away from extending the edge; A second etching process is performed to remove the thinned portion of the gate layer to form a lower portion of the second side of the gate aligned with the edge and to remove a portion of the gate layer below the edge to form the cavity extending partially below the second side of the gate. 3 . The method for fabricating a lateral MOS device according to claim 2 , wherein the first etching process is more anisotropic than the second etching process.

4. The method for manufacturing a lateral metal oxide semiconductor device according to claim 2, wherein: The first etching process is an anisotropic dry etching process; as well as The second etching process is an isotropic dry etching process or a dry etching process with less anisotropy than the first etching process.

5. A lateral metal oxide semiconductor device, characterized in that include: Basic semiconductors; a gate oxide disposed on the base semiconductor; A gate, disposed on the gate oxide; a source region disposed on a first side of the gate and laterally offset from the gate; a drain region disposed on a second side of the gate and laterally offset from the gate; as well as A dielectric layer is disposed on the sidewall of the gate and includes an extension of the dielectric layer partially extending below the second side of the gate. 6 . The lateral MOS device of claim 5 , wherein the dielectric layer circumferentially covers the sidewalls of the gate, and the extension of the dielectric layer extends under the gate only partially under the second side of the gate.

7. The lateral MOS device of claim 5, wherein: The sidewall of the gate is a rectangular columnar sidewall having four sides, including the first side of the gate and the second side of the gate, and the first side and the second side of the gate are opposite sides of the rectangular columnar sidewall of the gate; The dielectric layer circumferentially covers all four sides of the rectangular columnar sidewall; and The extension of the dielectric layer partially extends below the second side of the gate and does not extend below the first side of the gate.

8. The lateral MOS device of claim 5, wherein a ratio of a lateral distance of the extension of the dielectric layer below the second side of the gate to a lateral spacing between the first side and the second side of the gate is between 0.01 and 0.

1. 9 . The lateral MOS device of claim 5 , wherein a ratio of a height of the extension of the dielectric layer to a height of the gate is between 0.01 and 0.

5.

10. A method for manufacturing a gate of a lateral metal oxide semiconductor device, characterized in that: The method comprises: disposing a gate layer on the gate oxide layer; Performing photolithographic patterning and etching on the gate layer to form a first side of the gate of the lateral metal oxide semiconductor device; The gate layer is photolithographically patterned and etched to form a second side of the gate and to etch a hole partially extending below the second side of the gate, comprising: a first etch to remove an upper portion of the gate layer to expose an upper portion of the second side of the gate, and a second etch to remove a lower portion of the gate layer to completely expose the second side of the gate and further remove a portion of the gate layer below the second side of the gate to form the cavity extending partially below the second side of the gate; and A dielectric layer is formed on at least the first side and the second side of the gate, and the dielectric layer fills a portion of the cavity extending below the second side of the gate.

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