Integrated channel diode SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and preparation method

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses an integrated channel diode SiC MOSFET device and a preparation method, the integrated channel diode SiC MOSFET device is formed by a plurality of MOS cells in parallel, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a side P + layer and a P well layer, the grid electrode comprises a left grid electrode and a right grid electrode, the profile of the cross section of the left grid electrode and the profile of the cross section of the right grid electrode are both in an L shape, the left grid electrode and the right grid electrode are distributed on the left side and the right side of the MOS cell in an axial symmetry mode, and a P-filling layer is arranged in the grid oxide layer and located between the left grid electrode and the right grid electrode. The P-filling layer is introduced between the left gate and the right gate, the top end of the P-filling layer is connected with the source electrode, the bottom end of the P-filling layer is directly connected with the N drift layer, a low-resistance path is provided to activate the body diode function, reverse follow current is achieved, the requirement for externally-hung diodes is avoided, system layout is simplified, and parasitic inductance is reduced.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to an integrated channel diode SiC MOSFET device and a manufacturing method thereof. Background Art

[0002] Traditional SiC MOSFET devices usually use an external diode to achieve the reverse freewheeling function, which not only increases the system complexity and parasitic inductance, but also results in problems such as high on-resistance and large switching losses. In addition, the existing device structures have deficiencies in gate design, electric field distribution optimization, and body diode performance, making it difficult to balance high breakdown voltage, low on-resistance, and fast reverse recovery characteristics, thus limiting their application in high-efficiency power electronic systems.

[0003] A prior patent discloses a SiC-MOSFET device and a manufacturing method thereof with an integrated channel diode and Schottky diode structure (publication number CN118263321A), belonging to the field of semiconductor devices. The integrated channel diode of this device is composed of a virtual gate, an N-region, an N-drift region, an N+ substrate region, and a gate oxide layer. Among them, the N-region serves as the drain, the N+ substrate region serves as the source, and the virtual gate serves as the gate to form the channel diode. The SiC MOSFET device disclosed in this patent relies on an external diode to achieve reverse freewheeling, resulting in high system complexity, large parasitic inductance, relatively high on-resistance, and significant switching losses. At the same time, the disclosed structure has limitations in gate design, electric field distribution optimization, and body diode performance, making it difficult to balance high breakdown voltage, low on-resistance, and fast reverse recovery characteristics, thus limiting the application of the device in high-frequency and high-efficiency power electronic systems. Summary of the Invention

[0004] The present invention provides an integrated channel diode SiC MOSFET device and a manufacturing method thereof to solve the existing technical problems, and solves the problem that the SiC MOSFET device relies on an external diode to achieve reverse freewheeling.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, an integrated channel diode SiC MOSFET device includes a plurality of MOS cells arranged in parallel. Each MOS cell includes a drain, a source, a gate, a gate oxide layer, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, an N well layer, a side P+ layer, and a P well layer. The gate includes a left gate and a right gate. The cross-sectional profiles of the left gate and the right gate are both in the shape of "L", and the left gate and the right gate are symmetrically distributed on the left and right sides of the MOS cell.

[0006] Further, a P-fill layer is provided inside the gate oxide layer and between the left gate and the right gate, wherein the top end of the P-fill layer is in ohmic contact with the source electrode, and the bottom end of the P-fill layer is in direct contact with the N-drift layer.

[0007] Further, a plurality of metal pillars are provided inside the gate oxide layer and between the left gate and the right gate, and the metal pillars are only in contact with the source electrode.

[0008] Further, an intermediate N-well and an intermediate P-well are provided inside the gate oxide layer and between the left gate and the right gate; wherein, the intermediate N-well is located above the intermediate P-well and is in ohmic contact with the source electrode, and the intermediate P-well is in direct contact with the N-drift layer.

[0009] Further, an intermediate P+ layer is formed by ion implantation in the middle of the intermediate N-well, and the intermediate P+ layer divides the intermediate N-well into left and right parts; The top end of the intermediate P+ layer is in ohmic contact with the source electrode, and the bottom end of the intermediate P+ layer is in contact with the intermediate P-well.

[0010] Further, a filling P+ layer is formed by ion implantation in the middle of the intermediate P-well, and the filling P+ layer divides the intermediate P-well into left and right parts; Inside the intermediate N-well and directly above the filling P+ layer, filling metal is provided, and the upper and lower ends of the filling metal are respectively in contact with the source electrode and the filling P+ layer.

[0011] A preparation method of an integrated channel diode SiC MOSFET device, the specific steps are as follows: S1. Epitaxially grow an N-drift layer on an N-substrate layer; S2. Form symmetric P-well layers, N-well layers and side P+ layers on the surface of the N-drift layer by ion implantation; S3. Synchronously implant to form an intermediate P-well and an intermediate N-well, wherein the intermediate N-well is located directly above the intermediate P-well; S4. Photolithography and dry etching are performed to form symmetric left and right "L"-shaped grooves, the "L"-shaped grooves penetrate through the N-well layer and the P-well layer, and the depth of the "L"-shaped grooves reaches the N-drift layer; S5. Thermally oxidize and grow a gate oxide layer in the grooves; S6. Inject at the center of the intermediate N-well to form an intermediate P+ layer; S7. Deposit polysilicon in the "L"-shaped grooves to form axially symmetric left and right gates; S8. Deposit source metal and form ohmic contacts with the N-well layer, the side P+ layer and the intermediate P+ layer.

[0012] Further, in the step S6, a filled P+ layer may be formed by implanting at the center of the middle P well, and at the same time, a filled metal is deposited directly above it to connect the source electrode and the filled P+ layer.

[0013] An integrated channel diode SiC MOSFET device and a manufacturing method provided by the present invention, compared with the prior art, the effects achieved by this method are as follows: 1. By adopting an axisymmetric "L"-shaped left gate and right gate structure, the present invention penetrates through the N well layer and the P well layer to the N drift layer, forming a double-channel design, significantly increasing the channel width, reducing the on-resistance by 20%-30%, and at the same time optimizing the electric field distribution to improve the breakdown voltage of the device.

[0014] 2. By introducing a P-fill layer between the left and right gates, with its top connected to the source electrode and its bottom directly connected to the N drift layer, the present invention provides a low-resistance path to activate the body diode function, realizing reverse freewheeling, avoiding the need for an external diode, simplifying the system layout, and reducing the parasitic inductance.

[0015] 3. By setting metal pillars that only contact the source electrode in the inter-gate region, the present invention releases the electric field congestion between the gates, homogenizes the electric field distribution, thereby increasing the breakdown voltage, and at the same time reducing the gate parasitic capacitance to improve the high-frequency performance of the device.

[0016] 4. By using a stacked structure of a middle N well and a middle P well, and implanting a middle P+ layer at the center of the middle N well, the present invention enhances the hole injection efficiency, accelerates the turn-on speed of the body diode, reduces the reverse recovery charge by 40%, and significantly reduces the switching loss.

[0017] 5. By implanting a filled P+ layer at the center of the middle P well and directly connecting the source electrode through a filled metal, the present invention provides a vertical low-resistance path, reducing the contact resistance by 50%, and at the same time suppressing the parasitic transistor effect, improving the anti-latch-up ability and high-temperature stability of the device. Description of the Drawings

[0018] Figure 1 It is a schematic diagram of the first embodiment in the present invention; Figure 2 It is a schematic diagram of the second embodiment in the present invention; Figure 3 It is a schematic diagram of the third embodiment in the present invention; Figure 4 It is a schematic diagram of the fourth embodiment in the present invention; Figure 5 It is a schematic diagram of the fifth embodiment in the present invention; Figure 6 It is a schematic diagram of the principle of the fourth embodiment in the present invention.

[0019] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Gate oxide layer; 5. N-well layer; 6. Side P+ layer; 7. P-well layer; 8. N-substrate layer; 9. N-drift layer; 10. P-fill layer; 11. Metal pillar; 12. Intermediate P+ layer; 13. Intermediate N-well; 14. Intermediate P-well; 15. Fill P+ layer; 16. Fill metal; 301. Left gate; 302. Right gate. Detailed implementation manners

[0020] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] As Figures 1-5 shown, according to one aspect of the present invention, a preparation method of an integrated channel diode SiC MOSFET device is provided, and the specific steps are as follows: Step 1: Epitaxially grow an N-drift layer 9 on an N-substrate layer 8.

[0022] Step 2: Form symmetric P-well layers 7, N-well layers 5 and side P+ layers 6 on the surface of the N-drift layer 9 by ion implantation; the ion implantation realizes precise symmetric doping of the P-well layers 7, N-well layers 5 and side P+ layers 6, avoiding electrical performance fluctuations caused by photolithography offset; the side P+ layers 6 enhance the body region contact, suppress the parasitic bipolar transistor effect, and improve the device reliability.

[0023] Step 3: Synchronously implant to form an intermediate P-well 14 and an intermediate N-well 13, wherein the intermediate N-well 13 is located directly above the intermediate P-well 14; the synchronous implantation process reduces the number of photolithography times, reduces the process complexity and cost; the stacked structure of the intermediate N-well 13 / P-well 14 provides a fast carrier recombination path for the integrated body diode, significantly shortening the reverse recovery time (reducing by >30%), and reducing the switching loss.

[0024] Step 4: Photolithograph and dry-etch to form left and right symmetric "L"-shaped trenches, the "L"-shaped trenches penetrate through the N-well layer 5 and the P-well layer 7, and the depth of the "L"-shaped trenches reaches the N-drift layer 9; the dry-etching realizes steep sidewalls of the trenches (angle >88°), ensuring precise symmetry of the "L" shape; the trench depth reaches the N-drift layer 9, expanding the gate control area, reducing the on-resistance by 20%-30%, and optimizing the electric field distribution to improve the breakdown voltage capability.

[0025] Step 5: Thermally oxidize the gate oxide layer 4 in the trenches; the thermal oxidation generates a high-quality SiO2 gate dielectric layer, improving the gate reliability and suppressing the threshold voltage drift; uniformly covering the inner walls of the "L"-shaped trenches, ensuring stable channel mobility and reducing the switching noise.

[0026] Step 6: Inject in the center of the middle N well 13 to form the middle P+ layer 12; in this step, it is also possible to inject in the center of the middle P well 14 to form the filling P+ layer 15, and at the same time deposit the filling metal 16 directly above it to connect the source electrode 2 and the filling P+ layer 15. The middle P+ layer 12 enhances the hole injection efficiency and accelerates the turn-on speed of the body diode (the reverse recovery charge is reduced by 40%); the optional filling metal 16 directly connects the source electrode 2 and the filling P+ layer 15, and the vertical conduction path reduces the contact resistance by 50% and suppresses the latching risk.

[0027] Step 7: Deposit polysilicon in the "L"-shaped trench to form the axially symmetric left gate 301 and right gate 302; the polysilicon filling process has strong compatibility, forming an axially symmetric left gate 301 / right gate 302 structure. The double-channel parallel design doubles the effective channel width, significantly reducing it; the optimized gate resistance improves the switching frequency to the MHz level.

[0028] Step 8: Deposit the source electrode 2 metal and form ohmic contacts with the N well layer 5, the side P+ layer 6, and the middle P+ layer 12. The integrated metal deposition covers the N well layer 5, the side P+ layer 6, and the middle P+ layer 12 to achieve an ultra-low contact resistance; the current distribution uniformity improves the device's surge tolerance and ensures stability under high-temperature conditions.

[0029] Embodiment 1 As Figure 1 shown, an integrated channel diode SiC MOSFET device includes a plurality of MOS cells arranged side by side. A single MOS cell includes a drain electrode 1, a source electrode 2, a gate electrode 3, a gate oxide layer 4, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer 8, an N drift layer 9, an N well layer 5, a side P+ layer 6, and a P well layer 7. The gate electrode 3 includes a left gate 301 and a right gate 302. The cross-sectional profiles of the left gate 301 and the right gate 302 are both in the shape of an "L", and the left gate 301 and the right gate 302 are axially symmetrically distributed on the left and right sides of the MOS cell. The axially symmetric "L"-shaped left gate 301 and right gate 302 penetrate the N well layer 5 and the P well layer 7 to the N drift layer 9 to form a double-channel structure. The "L"-shaped gate increases the channel width and significantly reduces the on-resistance; and the symmetric design optimizes the electric field distribution and improves the device's breakdown voltage capability.

[0030] Embodiment 2 As Figure 2 shown, a P- filling layer 10 is provided inside the gate oxide layer 4 and between the left gate 301 and the right gate 302. The top of the P- filling layer 10 is in ohmic contact with the source electrode 2, and the bottom of the P- filling layer 10 is in direct contact with the N drift layer 9. Introduce the P- filling layer 10 between the left and right gates, with its top connected to the source electrode 2 and its bottom directly connected to the N drift layer 9. The P- filling layer 10 provides a low-resistance path, activates the body diode function, and realizes reverse freewheeling; avoids an external diode, simplifies the system layout, and reduces the parasitic inductance.

[0031] Example 3 As Figure 3 shown, several metal pillars 11 are provided inside the gate oxide layer 4 and between the left gate 301 and the right gate 302. The metal pillar 11 is only in contact with the source electrode 2. By setting the metal pillar 11 in the inter-gate region and only contacting the source electrode 2, it is suspended in the gate oxide layer 4. The metal pillar 11 releases the electric field congestion between the gates and homogenizes the electric field distribution; it increases the breakdown voltage while reducing the gate parasitic capacitance.

[0032] Example 4 As Figure 4 、 6 shown, an intermediate N-well 13 and an intermediate P-well 14 are provided inside the gate oxide layer 4 and between the left gate 301 and the right gate 302. Among them, the intermediate N-well 13 is located above the intermediate P-well 14 and is in ohmic contact with the source electrode 2, and the intermediate P-well 14 is in direct contact with the N-drift layer 9. An intermediate P+ layer 12 is formed in the middle of the intermediate N-well 13 by ion implantation. The intermediate P+ layer 12 divides the intermediate N-well 13 into left and right parts; the top end of the intermediate P+ layer 12 is in ohmic contact with the source electrode 2, and the bottom end of the intermediate P+ layer 12 is in contact with the intermediate P-well 14. An intermediate N-well 13 / intermediate P-well 14 stacked layer is provided in the inter-gate 3. The top of the N-well is connected to the source electrode 2, and the bottom of the P-well is connected to the drift layer 9; a P+ layer 12 is implanted in the intermediate N-well to divide the double channel. And the P+ layer 12 enhances the hole injection efficiency and accelerates the turn-on of the body diode.

[0033] Moreover, the above design will form a four-charge channel inside a single MOS cell (such as the black part shown in Figure 6 ). Four charge paths are formed between the drain 1 and the source electrode 2 in the four-charge channels respectively. These four charge paths can effectively optimize the carrier conduction path and reduce the reverse recovery loss.

[0034] Example 5 As Figure 5 shown, an intermediate N-well 13 and an intermediate P-well 14 are provided inside the gate oxide layer 4 and between the left gate 301 and the right gate 302. Among them, the intermediate N-well 13 is located above the intermediate P-well 14 and is in ohmic contact with the source electrode 2, and the intermediate P-well 14 is in direct contact with the N-drift layer 9. A filling P+ layer 15 is formed in the middle of the intermediate P-well 14 by ion implantation. The filling P+ layer 15 divides the intermediate P-well 14 into left and right parts; a filling metal 16 is provided inside the intermediate N-well and directly above the filling P+ layer 15. The upper and lower ends of the filling metal 16 are in contact with the source electrode 2 and the filling P+ layer 15 respectively. By injecting the filling P+ layer 15 in the center of the intermediate P-well 14 and directly connecting the source electrode 2 through the filling metal 16, the filling metal 16 provides a vertical low-resistance path, significantly reducing the source region contact resistance; the P+ layer 15 suppresses the parasitic transistor effect and improves the device's anti-latch-up ability.

[0035] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. An integrated channel diode SiC MOSFET device, which is composed of a plurality of MOS cells arranged side by side. Each of the MOS cells includes a drain (1), a source (2), a gate (3), a gate oxide layer (4), and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer (8), an N drift layer (9), an N well layer (5), a side P+ layer (6), and a P well layer (7), and is characterized in that: The gate (3) includes a left gate (301) and a right gate (302). The cross-sectional profiles of the left gate (301) and the right gate (302) are both in an "L" shape, and the left gate (301) and the right gate (302) are axially symmetrically distributed on the left and right sides of the MOS cell.

2. The integrated trench diode SiC MOSFET device according to claim 1, wherein: Inside the gate oxide layer (4) and between the left gate (301) and the right gate (302), a P-fill layer (10) is provided. The top of the P-fill layer (10) is in ohmic contact with the source electrode (2), and the bottom of the P-fill layer (10) is in direct contact with the N-drift layer (9).

3. The integrated trench diode SiC MOSFET device according to claim 1, wherein: Inside the gate oxide layer (4) and between the left gate (301) and the right gate (302), a number of metal pillars (11) are provided, and the metal pillars (11) are only in contact with the source electrode (2).

4. The integrated trench diode SiC MOSFET device according to claim 1, characterized in that: Inside the gate oxide layer (4) and between the left gate (301) and the right gate (302), an intermediate N-well (13) and an intermediate P-well (14) are provided; Among them, the intermediate N-well (13) is located above the intermediate P-well (14) and is in ohmic contact with the source electrode (2), and the intermediate P-well (14) is in direct contact with the N-drift layer (9).

5. The integrated trench diode SiC MOSFET device according to claim 4, wherein: An intermediate P+ layer (12) is formed by ion implantation at the middle of the intermediate N-well (13), and the intermediate P+ layer (12) divides the intermediate N-well (13) into two parts on the left and right; The top of the intermediate P+ layer (12) is in ohmic contact with the source electrode (2), and the bottom of the intermediate P+ layer (12) is in contact with the intermediate P-well (14).

6. The integrated channel diode SiC MOSFET device according to claim 4, characterized in that: A fill P+ layer (15) is formed by ion implantation at the middle of the intermediate P-well (14), and the fill P+ layer (15) divides the intermediate P-well (14) into two parts on the left and right; Inside the intermediate N-well (13) and directly above the fill P+ layer (15), a fill metal (16) is provided, and the upper and lower ends of the fill metal (16) are in contact with the source electrode (2) and the fill P+ layer (15) respectively.

7. A preparation method of an integrated channel diode SiC MOSFET device, characterized in that, Applied to the integrated channel diode SiC MOSFET device according to any one of claims 1-6, the preparation method of the integrated channel diode SiC MOSFET device specifically includes the following steps: S1. Epitaxially grow an N-drift layer (9) on an N-substrate layer (8); S2. Form symmetric P-well layers (7), N-well layers (5) and side P+ layers (6) on the surface of the N-drift layer (9) by ion implantation; S3. Synchronously implant to form an intermediate P-well (14) and an intermediate N-well (13), where the intermediate N-well (13) is located directly above the intermediate P-well (14); S4. Photolithograph and dry-etch to form left-right symmetric "L"-shaped trenches, which penetrate through the N-well layer (5) and the P-well layer (7), and the depth of the "L"-shaped trenches reaches the N-drift layer (9); S5. Thermally oxidize and grow a gate oxide layer (4) in the trenches; S6. Inject at the center of the intermediate N-well (13) to form an intermediate P+ layer (12); S7. Deposit polysilicon in the "L"-shaped trenches to form axially symmetric left gate (301) and right gate (302); S8. Deposit the source (2) metal and form ohmic contacts with the N-well layer (5), the side P+ layer (6), and the middle P+ layer (12).

8. The manufacturing method of the integrated trench diode SiC MOSFET device according to claim 7, characterized in that: In the step S6, a filling P+ layer (15) can also be formed by implanting at the center of the middle P-well (14). Meanwhile, a filling metal (16) is deposited directly above it to connect the source (2) and the filling P+ layer (15).

Images