Method for manufacturing depletion mode transistor and depletion mode transistor

Abstract

The present disclosure relates to a method for manufacturing a depletion mode transistor and a depletion mode transistor. The method comprises: providing a substrate of a first ion type; forming a drift region of a second ion type on one side of the substrate of the first ion type; forming a first trench, a second trench and a third trench on top of the substrate of the first ion type; forming a field oxide layer on the drift region of the second ion type; forming a gate oxide layer on the substrate of the first ion type, a polysilicon layer on the gate oxide layer and a well region of the first ion type in the substrate of the first ion type by using a self-alignment process; forming a lightly doped region of the second ion type in the substrate of the first ion type; forming polysilicon gate sidewalls on both sides of the polysilicon layer; forming a source of the first ion type in the well region of the first ion type and a drain of the second ion type in the drift region of the second ion type. At least the use of additional masks can be reduced, the number of photomask plates can be reduced, and the production cost of the transistor can be reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and particularly relates to a preparation method of a depletion mode transistor and the depletion mode transistor. BACKGROUND

[0002] With the continuous development of integrated circuit manufacturing technology, MOSFETs are divided into enhancement mode and depletion mode according to whether there is a primary conduction channel. Taking N-type MOSFET as an example, for an enhancement mode NMOS, a conduction channel is formed only when the gate-to-source voltage VGS>0, and a large source-drain current is generated when a voltage is loaded between the source and the drain. For a depletion mode NMOS, there is a primary conduction channel, and a large source-drain current is generated when a voltage is loaded between the source and the drain even if the gate bias VGS=0. Only when VGS<0 and increases to a certain value, the primary conduction channel disappears, and the NMOS tube is turned off. In some specific applications, such as surge and high-voltage protection, anti-reverse connection protection, or solid-state relays, a high-voltage depletion mode is required, that is, the device needs to be turned on when VGS=0, and the device needs to withstand a certain drain voltage when it is turned on or turned off. DEMOS has the advantages of high voltage resistance and low on-resistance, and can be used as a high-voltage switch and a high-voltage large-current driving device. It is a good choice as a high-voltage depletion mode.

[0003] Traditional depletion modes usually form a primary conduction channel in two ways. One is to perform ion implantation in the gate oxide layer to attract substrate electrons / holes to form a conduction channel. The other is to perform ion implantation directly below the gate oxide to form a primary conduction channel. The common point of these two methods is that an additional mask is needed for ion implantation, which increases the manufacturing cost. SUMMARY

[0004] Therefore, it is necessary to provide a preparation method of a depletion mode transistor and the depletion mode transistor to at least reduce the use of additional masks, reduce the number of photomask plates, and reduce the production cost of the transistor.

[0005] To achieve the above object and other objects, in a first aspect, the present disclosure provides a method for manufacturing a depletion mode transistor, comprising: providing a substrate of a first ion type; forming a drift region of a second ion type on one side of the substrate of the first ion type; forming a first trench, a second trench and a third trench on the substrate of the first ion type, the first trench being close to one side of the substrate of the first ion type, the third trench being close to the other side of the substrate of the first ion type, the second trench being between the third trench and the drift region of the second ion type, the first trench being at least partially in the drift region of the second ion type; forming a field oxide layer on the drift region of the second ion type, a top surface of the field oxide layer being higher than a top surface of the substrate of the first ion type, a bottom surface of the field oxide layer being higher than a bottom surface of the drift region of the second ion type; forming a gate oxide layer on the substrate of the first ion type, a polysilicon layer on the gate oxide layer, and a well region of the first ion type in the substrate of the first ion type by using a self-alignment process, the gate oxide layer being in contact with the drift region of the second ion type, the field oxide layer and the substrate of the first ion type, the polysilicon layer being in contact with the field oxide layer, the well region of the first ion type laterally spanning the second trench and being in contact with the third trench; forming a lightly doped region of the second ion type in the substrate of the first ion type, the lightly doped region of the second ion type being between the drift region of the second ion type and the well region of the first ion type, a top surface of the lightly doped region of the second ion type being in contact with a bottom surface of the gate oxide layer, one side of the lightly doped region of the second ion type being in contact with the well region of the first ion type; forming polysilicon gate sidewalls on both sides of the polysilicon layer; forming a source of the first ion type in the well region of the first ion type and a drain of the second ion type in the drift region of the second ion type.

[0006] In the method for manufacturing a depletion mode transistor in the above embodiments, in the process of forming the depletion mode transistor, the gate oxide layer, the polysilicon layer and the well region are formed in one step based on the self-alignment process, without the need of using different masks and plates in the photolithography process when forming the gate oxide layer, the polysilicon layer and the well region, thereby reducing the use of extra masks, reducing the number of layers of the photolithography plate and lowering the production cost of the transistor.

[0007] In one of the embodiments, the forming of the drift region of the second ion type on one side of the substrate of the first ion type comprises: forming a first pad oxide layer on the substrate of the first ion type by a furnace tube thermal oxidation process; performing photolithography on the pad oxide layer to form a first mask layer, the first mask layer exposing a first pattern required for forming the drift region of the second ion type; performing ion implantation of the second ion type with the first mask layer as a mask to form the drift region of the second ion type on one side of the substrate of the first ion type.

[0008] In one of the embodiments, the implantation energy of the ion implantation of the second ion type with the first mask layer as a mask is 30 KeV to 600 KeV, and the implantation dose is 1e12 to 1e14. To .

[0009] In one embodiment, the step of forming the first trench, the second trench and the third trench on the top of the substrate of the first ion type comprises: removing the first mask layer, and forming a second pad oxide layer on the substrate of the first ion type by a furnace tube thermal oxidation process; forming a first dielectric layer on the second pad oxide layer, the first dielectric layer serving as a barrier layer for chemical mechanical polishing; performing photolithography and etching with the second pad oxide layer and the dielectric layer as mask layers to form the first trench, the second trench and the third trench on the top of the substrate of the first ion type; filling the first trench, the second trench and the third trench based on a high-density plasma-enhanced chemical vapor deposition process, and performing annealing to repair lattice damage; using chemical mechanical grinding to the first dielectric layer, and using wet method to remove the remaining dielectric layer to form the active region and the isolation region in the substrate of the first ion type.

[0010] In one embodiment, the step of forming the field oxide layer on the drift region of the second ion type comprises: forming a second dielectric layer on the top surface of the substrate of the first ion type based on a furnace tube thermal oxidation process; using the second dielectric layer as a barrier layer for field region oxidation, defining a field oxide region by using photolithography and etching process to form the field oxide barrier layer; forming the field oxide layer by using thermal oxidation process, and removing the second dielectric layer and the second pad oxide layer by using wet method to form the field oxide layer.

[0011] In one embodiment, the step of forming the gate oxide layer on the substrate of the first ion type and forming the polysilicon layer on the gate oxide layer comprises: forming the gate oxide layer on the top surface of the substrate of the first ion type based on a thermal oxidation process; depositing the polysilicon layer on the gate oxide layer, and defining the region where the polysilicon layer needs to be left by using photolithography and etching; defining the well region of the first ion type, the polysilicon layer and the gate oxide layer by using a self-alignment process, through photolithography, etching and ion implantation of the first ion type.

[0012] In one embodiment, the implantation energy of the ion implantation of the first ion type is 20 KeV to 280 KeV, and the implantation dose is To .

[0013] In one embodiment, the step of forming the lightly doped region of the second ion type in the substrate of the first ion type comprises: performing ion implantation of the lightly doped region of the first ion type at a preset ion implantation angle; wherein the preset ion implantation angle is 15° to 45°, the implantation energy of the ion implantation of the lightly doped region of the first ion type is 50 KeV to 80 KeV, and the implantation dose of the ion implantation of the lightly doped region of the first ion type is To .

[0014] In one of the embodiments, the step of forming the source of the first ion type in the well region of the first ion type and forming the drain of the second ion type in the drift region of the second ion type comprises: performing ion implantation of the source of the first ion type and performing ion implantation of the drain of the second ion type; wherein the implantation energy of the ion implantation of the source of the first ion type is 30 KeV to 50 KeV, and the implantation dose is to ; the implantation energy of the ion implantation of the drain of the second ion type is 10 KeV to 15 KeV, and the implantation dose is to .

[0015] In a second aspect, the embodiments of the present disclosure further provide a depletion mode transistor, comprising: a substrate of a first ion type; a drift region of a second ion type located on one side of the substrate of the first ion type; a first trench, a second trench and a third trench located on top of the substrate of the first ion type, the first trench being close to one side of the substrate of the first ion type, the third trench being close to the other side of the substrate of the first ion type, the second trench being located between the third trench and the drift region of the second ion type, the first trench being at least partially located in the drift region of the second ion type; a field oxide layer located in the drift region of the second ion type, the top surface of the field oxide layer being higher than the top surface of the substrate of the first ion type, and the bottom surface of the field oxide layer being higher than the bottom surface of the drift region of the second ion type; a gate oxide layer and a polysilicon layer, the gate oxide layer being located on the substrate of the first ion type, and the polysilicon layer being located on the gate oxide layer, the gate oxide layer being in contact with the drift region of the second ion type, the field oxide layer and the substrate of the first ion type, and the polysilicon layer being in contact with the field oxide layer; a well region of the first ion type located in the substrate of the first ion type, the well region of the first ion type laterally spanning the second trench and being in contact with the third trench; a lightly doped region of the second ion type located in the substrate of the first ion type, the lightly doped region of the second ion type being located between the drift region of the second ion type and the well region of the first ion type, the top surface of the lightly doped region of the second ion type being in contact with the bottom surface of the gate oxide layer, and one side of the lightly doped region of the second ion type being in contact with the well region of the first ion type; a polysilicon gate sidewall located on both sides of the polysilicon layer; a source of the first ion type located in the well region of the first ion type and a drain of the second ion type located in the drift region of the second ion type.

[0016] The depletion mode transistor in the above embodiments forms the gate oxide layer, the polysilicon layer and the well region in one step based on the self-alignment process, without the need to use different masks and plates in photolithography when forming the gate oxide layer, the polysilicon layer and the well region, thereby reducing the use of additional masks, reducing the number of layers of photolithography plates and reducing the production cost of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only represent some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0018] Figure 1 A flowchart of a preparation method of a depletion mode transistor provided in an embodiment;

[0019] Figure 2 A structural diagram of a structure obtained in step S2000 in the preparation method of the depletion mode transistor provided in an embodiment;

[0020] Figure 3 A structural diagram of a structure obtained in step S4000 in the preparation method of the depletion mode transistor provided in an embodiment;

[0021] Figure 4 A longitudinal sectional structural diagram of a structure obtained in step S5000 in the preparation method of the depletion mode transistor provided in an embodiment Figure 1 ;

[0022] Figure 5 A structural diagram of a structure obtained in step S5000 in the preparation method of the depletion mode transistor provided in an embodiment Figure 2 ;

[0023] Figure 6 A structural diagram of a structure obtained in step S7000 in the preparation method of the depletion mode transistor provided in an embodiment.

[0024] Explanation of reference signs:

[0025] 201, substrate of a first ion type; 202, drift region of a second ion type; 301, first trench; 302, second trench; 303, third trench; 304, field oxide layer; 401, gate oxide layer; 502, polysilicon layer; 503, well region of the first ion type; 601, lightly doped region of the second ion type; 602, polysilicon gate sidewall; 603, source of the first ion type; 604, drain of the second ion type. DETAILED DESCRIPTION

[0026] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the related drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the disclosure.

[0028] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type.

[0029] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the included spatial description terminology is interpreted accordingly.

[0030] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" as used in this specification, particularly in the claims, should not be construed as limiting the present disclosure to the listed components unless the context clearly dictates otherwise. Additionally, the term "and / or" as used in the context of this specification, particularly in the claims, includes any and all combinations of one or more of the associated listed items. Also, the term "and / or" as used in the context of this specification, particularly in the claims, includes any and all combinations of one or more of the associated listed items.

[0031] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present disclosure.

[0032] Reference is made to Figures 1-6 The embodiments of the present disclosure provide a method for manufacturing a contact hole 1001, comprising the following steps:

[0033] Step S1000: providing a substrate 201 of a first ion type.

[0034] Step S2000: forming a drift region 202 of a second ion type on one side of the substrate 201 of the first ion type.

[0035] Step S3000: forming a first trench 301, a second trench 302 and a third trench 303 on the substrate 201 of the first ion type.

[0036] The first trench 301 is close to one side of the substrate 201 of the first ion type, the third trench 303 is close to the other side of the substrate 201 of the first ion type, the second trench 302 is between the third trench 303 and the drift region 202 of the second ion type, and the first trench 301 is at least partially located in the drift region 202 of the second ion type.

[0037] Step S4000: forming a field oxide layer 304 on the drift region 202 of the second ion type.

[0038] The top surface of the field oxide layer 304 is higher than the top surface of the substrate 201 of the first ion type, and the bottom surface of the field oxide layer 304 is higher than the bottom surface of the drift region 202 of the second ion type.

[0039] Step S5000: Forming a gate oxide layer 401 on the substrate 201 of the first ion type by using a self-alignment process, forming a polysilicon layer 502 on the gate oxide layer 401, and forming a well region 503 of the first ion type in the substrate 201 of the first ion type.

[0040] The gate oxide layer 401 is in contact with the drift region 202 of the second ion type, the field oxide layer 304, and the substrate 201 of the first ion type, the polysilicon layer 502 is in contact with the field oxide layer 304, and the well region 503 of the first ion type laterally spans the second trench 302 and is in contact with the third trench 303.

[0041] Step S6000: Forming a lightly doped region 601 of the second ion type in the substrate 201 of the first ion type.

[0042] The lightly doped region 601 of the second ion type is located between the drift region 202 of the second ion type and the well region 503 of the first ion type, the top surface of the lightly doped region 601 of the second ion type is in contact with the bottom surface of the gate oxide layer 401, and one side of the lightly doped region 601 of the second ion type is in contact with the well region 503 of the first ion type.

[0043] Step S7000: Forming a polysilicon gate sidewall 602 on both sides of the polysilicon layer 502.

[0044] Step S8000: Forming a source 603 of the first ion type in the well region 503 of the first ion type, and forming a drain 604 of the second ion type in the drift region 202 of the second ion type.

[0045] In the preparation method of the depletion mode transistor in the above embodiment, in the process of forming the depletion mode transistor, the gate oxide layer 401, the polysilicon layer 502, and the well region are formed in one step based on the self-alignment process, without the need to use different masks and plates during lithography when forming the gate oxide layer 401, the polysilicon layer 502, and the well region, thereby reducing the use of additional masks, reducing the number of lithography plates, and reducing the production cost of the transistor.

[0046] In step S2000, please refer to Figures 1-2 Taking the depletion mode DENMOS as an example, the first ion type is P type, and the second ion type is N type. A pad oxide layer (PAD OX) is generated on the surface of the silicon substrate by furnace tube thermal oxidation, then the required ion implantation area is formed by lithography, and then N type ion implantation is performed. Finally, the photoresist is removed to form a drift region which can bear a high voltage at the drain end.

[0047] Specifically, forming the drift region 202 of the second ion type on one side of the substrate 201 of the first ion type comprises: forming a first pad oxide layer on the substrate 201 of the first ion type by a furnace tube thermal oxidation process; performing photolithography on the pad oxide layer to form a first mask layer, the first mask layer exposing a first pattern required for forming the drift region 202 of the second ion type; performing ion implantation of the second ion type with the first mask layer as a mask to form the drift region 202 of the second ion type on one side of the substrate 201 of the first ion type.

[0048] Wherein, the implantation energy of the ion implantation of the second ion type with the first mask layer as a mask is 30 KeV to 600 KeV, and the implantation dose is to .

[0049] As an example, the implantation energy of the ion implantation of the second ion type with the first mask layer as a mask can be 30 KeV, 70 KeV, 150 KeV, 230 KeV, 310 KeV, 430 KeV, 500 KeV, 520 KeV, 600 KeV, etc.

[0050] As an example, the implantation dose of the ion implantation of the second ion type with the first mask layer as a mask can be , , , , etc.

[0051] In step S3000, the step of forming the first trench 301, the second trench 302 and the third trench 303 on the top of the substrate 201 of the first ion type comprises: removing the first mask layer, and forming a second pad oxide layer on the substrate 201 of the first ion type by a furnace tube thermal oxidation process; forming a first dielectric layer on the second pad oxide layer, the first dielectric layer used as a barrier layer for chemical mechanical polishing; performing photolithography and etching with the second pad oxide layer and the dielectric layer as mask layers to form the first trench 301, the second trench 302 and the third trench 303 on the top of the substrate 201 of the first ion type; filling the first trench 301, the second trench 302 and the third trench 303 based on a high-density plasma-enhanced chemical vapor deposition process, and performing annealing to repair lattice damage; using chemical mechanical grinding to the first dielectric layer, and using wet method to remove the remaining dielectric layer to form the active region and the isolation region in the substrate 201 of the first ion type.

[0052] In step S4000, the field oxide layer 304 is formed on the drift region 202 of the second ion type, including: forming a second dielectric layer on the top surface of the substrate 201 of the first ion type based on a furnace tube thermal oxidation process; using the second dielectric layer as a barrier layer for field oxidation, defining a field oxidation area by using photolithography and etching process to form a field oxide barrier layer; forming the field oxide layer 304 by using thermal oxidation process, and removing the second dielectric layer and the second pad oxide layer by wet method to form the field oxide layer 304.

[0053] As an example, after removing the first mask layer after ion implantation, a layer of PAD OX is regrown by thermal oxidation, and then a layer of first dielectric layer (SiN) is grown as a barrier layer for CMP, and then three trenches are formed by photolithography and etching, and then the three trenches are filled by using high-density plasma-enhanced chemical vapor deposition (HD-PECVD) and annealing to repair lattice damage, and then chemical mechanical polishing (CMP) is used to polish to SIN, and the remaining SiN is removed by wet method to form the active region and the isolation region. Then a layer of second dielectric layer (SiN) is regrown by furnace tube, as a barrier layer for field oxidation, and then the field oxidation area is defined by photolithography and etching, and the field oxide layer 304 is grown by using thermal oxidation process, and finally the SiN and the PAD OX are removed by wet method to form the field oxide region. The field oxide layer can increase the breakdown voltage.

[0054] As an example, please refer to Figure 3 , Figure 3 The transistor structure after forming the first trench 301, the second trench 302, the third trench 303 and the field oxide layer 304 is shown. The first trench 301 is close to one side of the substrate 201 of the first ion type, the third trench 303 is close to the other side of the substrate 201 of the first ion type, the second trench 302 is located between the third trench 303 and the drift region 202 of the second ion type, the first trench 301 is at least partially located in the drift region 202 of the second ion type, the top surface of the field oxide layer 304 is higher than the top surface of the substrate 201 of the first ion type, and the bottom surface of the field oxide layer 304 is higher than the bottom surface of the drift region 202 of the second ion type.

[0055] In step S5000, the gate oxide layer 401 is formed on the substrate 201 of the first ion type, and the polysilicon layer 502 is formed on the gate oxide layer 401, including: forming the gate oxide layer 401 on the top surface of the substrate 201 of the first ion type based on the thermal oxidation process; depositing the polysilicon layer 502 on the gate oxide layer 401, and defining the area where the polysilicon layer 502 needs to be left by using photolithography and etching; and defining the well region 503 of the first ion type, the polysilicon layer 502 and the gate oxide layer 401 by using self-alignment process, photolithography, etching and first ion implantation.

[0056] Here, taking the depletion mode DENMOS device as an example, the well region of the first ion type (P type) is tangent to the polysilicon gate, so that a large number of P type ions on the surface of the channel after ion implantation can be avoided, which makes the device unable to exist in the original N type conductive channel.

[0057] As an example, please refer to Figures 4-5 , the gate oxide layer 401 is in contact with the drift region 202 of the second ion type, the field oxide layer 304 and the substrate 201 of the first ion type, the polysilicon layer 502 is in contact with the field oxide layer 304, and the well region 503 of the first ion type is transversely across the second trench 302 and in contact with the third trench 303.

[0058] Among them, the implantation energy of the ion implantation of the first ion type is 20 KeV to 280 KeV, and the implantation dose is to .

[0059] As an example, the implantation energy of the ion implantation of the first ion type can be 20 KeV, 90 KeV, 115 KeV, 200 KeV, 280 KeV, etc.

[0060] As an example, the implantation dose of the ion implantation of the first ion type can be , , , etc.

[0061] In step S6000, the step of forming a lightly doped region 601 of the second ion type in the substrate 201 of the first ion type includes: performing a first ion type light doping region ion implantation at a preset ion implantation angle.

[0062] Among them, the preset ion implantation angle is 15° to 45°, the implantation energy of the first ion type light doping region ion implantation is 50 KeV to 80 KeV, and the implantation dose of the first ion type light doping region ion implantation is to .

[0063] Here, performing the first ion type light doping region ion implantation can not only inhibit the hot carrier effect, but also neutralize the first ion type region under the gate oxide, so that the original conductive channel of the second ion type is formed under the channel after ion implantation annealing.

[0064] As an example, the preset ion implantation angle can be 15°, 25°, 40°, 45°, etc.

[0065] As an example, the implantation energy of the first ion type light doping region ion implantation can be 50 KeV, 60 KeV, 65 KeV, 70 KeV, 80 KeV, etc.

[0066] As an example, the ion implantation dose of the lightly doped region of the first ion type can be , , , and so on.

[0067] Here, the present application forms the well region by using the self-alignment process and combines the oblique ion implantation, so that the ions naturally diffuse to form the conductive channel after annealing.

[0068] In step S7000, the step of forming the source 603 of the first ion type in the well region 503 of the first ion type and forming the drain 604 of the second ion type in the drift region 202 of the second ion type includes: performing ion implantation of the source 603 of the first ion type, and performing ion implantation of the drain 604 of the second ion type.

[0069] The implantation energy of the source ion implantation of the first ion type is 30 KeV to 50 KeV, and the implantation dose is to ; the implantation energy of the drain ion implantation of the second ion type is 10 KeV to 15 KeV, and the implantation dose is to .

[0070] As an example, the implantation energy of the source 603 ion implantation of the first ion type can be 30 KeV, 40 KeV, 50 KeV.

[0071] As an example, the implantation dose of the source 603 ion implantation of the first ion type is , , , and so on.

[0072] As an example, the implantation energy of the drain 604 ion implantation of the second ion type is 10 KeV, 12 KeV, 15 KeV, and so on.

[0073] As an example, the implantation dose of the drain 604 ion implantation of the second ion type is , , , and so on.

[0074] As an example, please refer to Figure 6The lightly doped region 601 of the second ion type is located in the substrate 201 of the first ion type, the lightly doped region 601 of the second ion type is located between the drift region 202 of the second ion type and the well region 503 of the first ion type, the top surface of the lightly doped region 601 of the second ion type is in contact with the bottom surface of the gate oxide layer 401, and one side of the lightly doped region 601 of the second ion type is in contact with the well region 503 of the first ion type. The polysilicon gate sidewall 602 is located on both sides of the polysilicon layer 502. The source 603 of the first ion type is located in the well region 503 of the first ion type, and the drain 604 of the second ion type is located in the drift region 202 of the second ion type.

[0075] In the preparation method of the depletion transistor in the above embodiment, in the process of forming the depletion transistor, the gate oxide layer 401, the polysilicon layer 502 and the well region are formed in one step based on a self-alignment process. Different masks and plates are not required in the process of forming the gate oxide layer 401, the polysilicon layer 502 and the well region, the use of additional masks is reduced, the number of layers of the photolithography plate is reduced, and the production cost of the transistor is reduced.

[0076] It should be understood that, although Figure 1 The steps in the flowchart of the method are displayed in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps in the method can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0077] Based on the same inventive concept, the disclosure embodiments also provide a depletion transistor obtained based on the preparation method of the depletion transistor in the foregoing embodiments. The implementation scheme for solving the problem provided by the depletion transistor is similar to the implementation scheme described in the above method, so the specific limitations in one or more depletion transistor embodiments provided below can refer to the limitations of the preparation method of the depletion transistor in the foregoing embodiments, which will not be repeated here.

[0078] In some embodiments, please refer to Figure 6A depletion mode transistor comprises: a substrate 201 of a first ion type; a drift region 202 of a second ion type located on one side of the substrate 201 of the first ion type; a first trench 301, a second trench 302 and a third trench 303 located on top of the substrate 201 of the first ion type, the first trench 301 being located close to the one side of the substrate 201 of the first ion type, the third trench 303 being located close to the other side of the substrate 201 of the first ion type, the second trench 302 being located between the third trench 303 and the drift region 202 of the second ion type, the first trench 301 being at least partially located within the drift region 202 of the second ion type; a field oxide layer 304 located on the drift region 202 of the second ion type, a top surface of the field oxide layer 304 being higher than a top surface of the substrate 201 of the first ion type, a bottom surface of the field oxide layer 304 being higher than a bottom surface of the drift region 202 of the second ion type; a gate oxide layer 401 and a polysilicon layer 502, the gate oxide layer 401 being located on the substrate 201 of the first ion type, the polysilicon layer 502 being located on the gate oxide layer 401, the gate oxide layer 401 being in contact with the drift region 202 of the second ion type, the field oxide layer 304 and the substrate 201 of the first ion type, the polysilicon layer 502 being in contact with the field oxide layer 304; a well region 503 of the first ion type located within the substrate 201 of the first ion type, the well region 503 of the first ion type laterally spanning the second trench 302 and being in contact with the third trench 303; a lightly doped region 601 of the second ion type located within the substrate 201 of the first ion type, the lightly doped region 601 of the second ion type being located between the drift region 202 of the second ion type and the well region 503 of the first ion type, a top surface of the lightly doped region 601 of the second ion type being in contact with a bottom surface of the gate oxide layer 401, one side of the lightly doped region 601 of the second ion type being in contact with the well region 503 of the first ion type; a polysilicon gate sidewall 602 located on both sides of the polysilicon layer 502; a source 603 of the first ion type located within the well region 503 of the first ion type and a drain 604 of the second ion type located within the drift region 202 of the second ion type.

[0079] The depletion mode transistor in the above embodiment is based on a self-alignment process, and the gate oxide layer 401, the polysilicon layer 502 and the well region are formed in one step, so that different masks and plates are not needed in the process of forming the gate oxide layer 401, the polysilicon layer 502 and the well region, the use of additional masks is reduced, the number of layers of the plate is reduced, and the production cost of the transistor is reduced. The technical features of the above embodiment can be combined in any manner. In order to make the description simple, all possible combinations of the technical features of the above embodiment are not described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.

[0080] The above embodiments only express several implementation ways of the present disclosure, and the description is specific and detailed, but it should not be understood as a limitation to the patent scope. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, which are all within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A method of fabricating a depletion mode transistor, comprising: The method comprises: providing a substrate of a first ion type; forming a drift region of a second ion type on one side of the substrate of the first ion type; forming a first trench, a second trench and a third trench on top of the substrate of the first ion type, the first trench being close to one side of the substrate of the first ion type, the third trench being close to the other side of the substrate of the first ion type, the second trench being between the third trench and the drift region of the second ion type, the first trench being at least partially in the drift region of the second ion type; forming a field oxide layer on the drift region of the second ion type, the top surface of the field oxide layer being higher than the top surface of the substrate of the first ion type, the bottom surface of the field oxide layer being higher than the bottom surface of the drift region of the second ion type; forming a gate oxide layer on the substrate of the first ion type, a polysilicon layer on the gate oxide layer and a well region of the first ion type in the substrate of the first ion type by a self-alignment process, the gate oxide layer being in contact with the drift region of the second ion type, the field oxide layer and the substrate of the first ion type, the polysilicon layer being in contact with the field oxide layer, the well region of the first ion type laterally spanning the second trench and being in contact with the third trench; forming a lightly doped region of the second ion type in the substrate of the first ion type, the lightly doped region of the second ion type being between the drift region of the second ion type and the well region of the first ion type, the top surface of the lightly doped region of the second ion type being in contact with the bottom surface of the gate oxide layer, one side of the lightly doped region of the second ion type being in contact with the well region of the first ion type; forming polysilicon gate sidewalls on both sides of the polysilicon layer; forming a source of the first ion type in the well region of the first ion type and a drain of the second ion type in the drift region of the second ion type.

2. The production method according to claim 1, characterized by, forming a drift region of a second ion type on one side of the substrate of the first ion type comprises: forming a first pad oxide layer on the substrate of the first ion type by a furnace tube thermal oxidation process; performing photolithography on the pad oxide layer to form a first mask layer, the first mask layer exposing a first pattern required for forming the drift region of the second ion type; performing ion implantation of the second ion type with the first mask layer as a mask to form the drift region of the second ion type on one side of the substrate of the first ion type.

3. The production method according to claim 2, characterized by, The implantation energy of the ion implantation of the second ion type with the first mask layer as a mask plate is 30 KeV to 600 KeV, and the implantation dose is 1.2×10 12 cm -2 to 2×10 12 cm -2 .

4. The method of claim 1, wherein, the step of forming a first trench, a second trench and a third trench on top of the substrate of the first ion type comprises: removing the first mask layer and forming a second pad oxide layer on the substrate of the first ion type by a furnace tube thermal oxidation process; forming a first dielectric layer on the second pad oxide layer, the first dielectric layer being used as a barrier layer for chemical mechanical polishing; performing photolithography and etching with the second pad oxide layer and the dielectric layer as mask layers to form the first trench, the second trench and the third trench on top of the substrate of the first ion type; filling the first trench, the second trench and the third trench based on a high-density plasma-enhanced chemical vapor deposition process and performing annealing to repair lattice damage; Forming active region and isolation region in the substrate of the first ion type by chemical mechanical polishing to the first dielectric layer and removing the remaining dielectric layer by wet method.

5. The preparation method according to claim 4, characterized in that, Forming field oxide layer on the drift region of the second ion type, comprising: Forming second dielectric layer on the top surface of the substrate of the first ion type based on furnace tube thermal oxidation process furnace tube; Using the second dielectric layer as the barrier layer of field region oxidation, defining field oxide area by photolithography and etching process to form field oxide barrier layer; Forming field oxide layer by thermal oxidation process and removing the second dielectric layer and the second pad oxide layer by wet method to form field oxide layer.

6. The method of claim 1, wherein, Forming gate oxide layer on the substrate of the first ion type and forming polysilicon layer on the gate oxide layer, comprising: Forming gate oxide layer on the top surface of the substrate of the first ion type based on thermal oxidation process; Depositing polysilicon layer on the gate oxide layer and defining the area where polysilicon layer needs to be left by photolithography and etching; Defining the first ion type well region, polysilicon layer and gate oxide layer by photolithography, etching and first ion type ion implantation through self-alignment process.

7. The preparation method according to claim 6, characterized in that, The implantation energy of the ion implantation of the first ion type is 20 KeV to 280 KeV, and the implantation dose is 2.8 x 10 12 cm -2 to 8 x 10 12 cm -2 .

8. The method of claim 1, wherein, The step of forming the second ion type lightly doped region in the substrate of the first ion type comprises: Carrying out first ion type lightly doped region ion implantation with preset ion implantation angle; The preset ion implantation angle is 15° to 45°, the ion implantation energy of the light doping region of the first ion type is 50 KeV to 80 KeV, the ion implantation dose of the light doping region of the first ion type is 1.2×10 13 cm -2 to 1.8×10 13 cm -2 .

9. The method of claim 1, wherein, The step of forming the first ion type source in the well region of the first ion type and forming the second ion type drain in the drift region of the second ion type comprises: Carrying out first ion type source ion implantation and second ion type drain ion implantation; The source ion implantation of the first ion type has an implantation energy of 30 KeV to 50 KeV and an implantation dose of 1.5*10 14 cm -2 to 5*10 15 cm -2 ; and the drain ion implantation of the second ion type has an implantation energy of 10 KeV to 15 KeV and an implantation dose of 3*10 13 cm -2 to 3*10 15 cm -2 .

10. A depletion mode transistor, characterized by Comprising: The substrate of the first ion type; The drift region of the second ion type is located on one side of the substrate of the first ion type; The first trench, the second trench and the third trench are located on the top of the substrate of the first ion type, the first trench is close to one side of the substrate of the first ion type, the third trench is close to the other side of the substrate of the first ion type, the second trench is located between the third trench and the drift region of the second ion type, and the first trench is at least partially located in the drift region of the second ion type; The field oxide layer is located in the drift region of the second ion type, the top surface of the field oxide layer is higher than the top surface of the substrate of the first ion type, and the bottom surface of the field oxide layer is higher than the bottom surface of the drift region of the second ion type; The gate oxide layer and the polysilicon layer, the gate oxide layer is located on the substrate of the first ion type, the polysilicon layer is located on the gate oxide layer, the gate oxide layer is in contact with the drift region of the second ion type, the field oxide layer and the substrate of the first ion type, and the polysilicon layer is in contact with the field oxide layer; The first ion type well region is located in the substrate of the first ion type, and the first ion type well region laterally crosses the second trench and is in contact with the third trench; a lightly doped region of a second ion type within the substrate of the first ion type, the lightly doped region of the second ion type being located between the drift region of the second ion type and the well region of the first ion type, a top surface of the lightly doped region of the second ion type contacting a bottom surface of the gate oxide layer, a side of the lightly doped region of the second ion type forming a contact with the well region of the first ion type; a polysilicon gate sidewall on both sides of the polysilicon layer; a source of the first ion type within the well region of the first ion type and a drain of the second ion type within the drift region of the second ion type.

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