Semiconductor device, power module, power conversion circuit, vehicle, and method for manufacturing semiconductor device

Abstract

The application discloses a semiconductor device, a power module, a power conversion circuit, a vehicle and a preparation method of the semiconductor device, wherein the semiconductor device comprises: a semiconductor body comprising a well region, a first region, a second region and an isolation region, the first region is located on a first surface, the well region is located on a side of the first region away from the first surface; the second region is located on the first surface and extends from the first surface into the semiconductor body; the isolation region is arranged between the second region and the first region; the first surface is provided with a gate trench, and a gate structure is located in the gate trench; a freewheeling structure is arranged on a side of the first surface away from the second region, and the freewheeling structure is used for providing a freewheeling channel; a source electrode is located on the first surface and is electrically connected with the freewheeling structure; and a drain electrode is located on a second surface. The semiconductor device of the application increases the freewheeling channel in the device, reduces the reverse conduction voltage drop, and improves the performance stability and safety of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a power module, a power conversion circuit, a vehicle, and a method for manufacturing the semiconductor device. Background Technology

[0002] Silicon carbide trench devices have advantages such as high current density and small cell pitch, and are widely used. In existing dual-trench devices, a freewheeling diode is integrated between the source and drain. However, when a positive voltage is applied to the source, its reverse conduction voltage drop is too large, which affects the stability and reliability of the device. Summary of the Invention

[0003] This invention provides a semiconductor device, a power module, a power conversion circuit, a vehicle, and a method for fabricating the semiconductor device, thereby increasing the freewheeling channel in the device to reduce the reverse conduction voltage drop and improve the performance stability and safety of the semiconductor device.

[0004] In a first aspect, embodiments of the present invention provide a semiconductor device, comprising:

[0005] A semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body includes a well region, a first region, a second region, and an isolation region. The first region is disposed on the first surface and extends from the first surface into the semiconductor body. The well region is located on the side of the first region away from the first surface. The second region is disposed on the first surface and extends from the first surface into the semiconductor body. The isolation region is disposed between the second region and the first region. The first region and the second region have a first conductivity type, and the well region has a second conductivity type. The first conductivity type and the second conductivity type are different. A gate trench is disposed on the first surface. The gate trench extends from the first surface into the semiconductor body.

[0006] A gate structure is located within the gate trench;

[0007] A current-continuing structure is disposed on the side of the first surface away from the second region, and the orthographic projection of the current-continuing structure on the first surface at least covers the orthographic projection of the second region on the first surface; the current-continuing structure is used to provide a current-continuing channel;

[0008] The source electrode is located on the first surface and is electrically connected to the freewheeling structure;

[0009] The drain electrode is located on the second surface.

[0010] Optionally, the freewheeling structure comprises a first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer which are stacked; the first semiconductor conductive layer is located close to the first surface; the first semiconductor conductive layer and the third semiconductor conductive layer are of the first conductive type, and the second semiconductor conductive layer is of the second conductive type.

[0011] The freewheeling structure further comprises a first insulating layer located away from the first surface of the third semiconductor conductive layer; the first insulating layer covers the third semiconductor conductive layer, and covers the sidewalls of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer is provided with a first opening area, and the first opening area exposes at least part of the third semiconductor conductive layer.

[0012] Optionally, the freewheeling structure further comprises a metal conductive layer located between the first semiconductor conductive layer and the second region.

[0013] Optionally, the semiconductor body further comprises:

[0014] a buried layer located away from the first surface of the gate structure; the buried layer is arranged to extend along a first direction; the buried layer further comprises a second opening area, and a projection of the second opening area on the first surface at least partially overlaps with projections of the gate structure and the freewheeling structure on the first surface; the first direction is parallel to the first surface.

[0015] In a second aspect, an embodiment of the present application provides a power module, comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present application, and the substrate is used to carry the semiconductor device.

[0016] In a third aspect, an embodiment of the present application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion and power factor correction.

[0017] The power conversion circuit comprises a circuit board and at least one semiconductor device as described in any of the embodiments of the present application, and the semiconductor device is electrically connected to the circuit board.

[0018] In a fourth aspect, an embodiment of the present application provides a vehicle, comprising a load and a power conversion circuit as described in any of the embodiments of the present application, and the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current or convert direct current into alternating current, and then input to the load.

[0019] In a fifth aspect, an embodiment of the present application provides a preparation method of a semiconductor device, comprising:

[0020] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged oppositely, the semiconductor body comprising a well region, a first region, a second region and an isolation region, the first region being arranged at the first surface and extending from the first surface into the semiconductor body, the well region being located at a side of the first region away from the first surface; the second region being arranged at the first surface and extending from the first surface into the semiconductor body; the isolation region being arranged between the second region and the first region; the first region and the second region being of a first conductivity type, the well region being of a second conductivity type, the first conductivity type and the second conductivity type being different; the first surface being provided with a gate trench; the gate trench extending from the first surface into the semiconductor body;

[0021] A gate structure is formed in the gate trench;

[0022] A freewheel structure is formed at a side of the first surface away from the second region, a projection of the freewheel structure on the first surface covering at least a projection of the second region on the first surface; the freewheel structure being configured to provide a freewheeling path;

[0023] A source is formed at the first surface, the source being electrically connected with the freewheel structure;

[0024] A drain is formed at the second surface.

[0025] Optionally, forming the freewheel structure at the side of the first surface away from the second region comprises:

[0026] A first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer are sequentially stacked at the first surface;

[0027] A first insulating layer is formed at a side of the third semiconductor conductive layer away from the first surface, the first insulating layer covering the third semiconductor conductive layer and a sidewall of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer being provided with a first opening region, the first opening region exposing at least part of the third semiconductor conductive layer.

[0028] Optionally, the semiconductor body is provided, comprising:

[0029] An epitaxial layer is formed at a side of a substrate;

[0030] A surface of the epitaxial layer away from the substrate is taken as a first surface, a well region is formed at the first surface, the well region extending from the first surface into the epitaxial layer;

[0031] forming the first region with intervals on the first surface, the first region extending from the first surface into the epitaxial layer;

[0032] forming the second region on the first surface of the interval region between adjacent first regions, the second region extending from the first surface into the semiconductor body; the part of the well region on both sides of the second region as the isolation region between the second region and the first region; wherein the first region and the second region are of a first conductive type, the well region is of a second conductive type, and the first conductive type and the second conductive type are different;

[0033] forming a gate trench on the first surface; the gate trench extending from the first surface into the epitaxial layer.

[0034] Optionally, before forming the first semiconductor conductive layer, a metal conductive layer is formed on the surface of the second region, the metal conductive layer being between the first semiconductor conductive layer and the second region.

[0035] Optionally, forming the epitaxial layer on one side of the substrate comprises:

[0036] forming a first epitaxial layer on one side of the substrate;

[0037] forming a buried layer on the surface of the first epitaxial layer away from the substrate in a first direction, the buried layer extending from the surface of the first epitaxial layer away from the substrate to the first epitaxial layer, the buried layer being provided with a second opening region, a projection of the second opening region on the first surface at least partially overlapping with a projection of the gate structure and the freewheel structure on the first surface; the first direction being a direction parallel to the first surface.

[0038] forming a second epitaxial layer on the surface of the first epitaxial layer away from the substrate, the first epitaxial layer and the second epitaxial layer constituting the epitaxial layer.

[0039] The semiconductor device provided in the embodiment of the present application introduces a freewheel structure, the freewheel structure being arranged on the side of the first surface away from the second region, wherein a projection of the freewheel structure on the first surface at least covers a projection of the second region on the first surface, the source electrode is electrically connected with the freewheel structure, and therefore, when the source electrode has a voltage, a freewheel channel is provided by the freewheel structure to reduce the on-voltage, and the current sequentially passes through the source electrode, the freewheel structure, the second region and the epitaxial layer until being output by the drain electrode. Thus, the freewheel channel is added in the device to reduce the reverse on-voltage drop, and the performance stability and safety of the semiconductor device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1A structure schematic diagram of a semiconductor device provided by the embodiment of the present application is provided.

[0041] Figure 2 A flow chart of a preparation method of a semiconductor device provided by the embodiment of the present application is provided.

[0042] Figure 3 A flow chart of a preparation method of a semiconductor device provided by the embodiment of the present application is provided.

[0043] Figures 4-8 A structure schematic diagram of a semiconductor device provided by the embodiment of the present application is provided. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical scheme and advantages of the embodiment of the present application clearer, the technical scheme in the embodiment of the present application will be described clearly and completely below with reference to the drawings in the embodiment of the present application. Obviously, the described embodiment is a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiment in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0045] The silicon carbide trench device has the advantages of large current density and small cell pitch. The silicon carbide trench device generally needs to be integrated with a freewheeling diode. The function of the freewheeling diode is to play a conduction role when the source level is given a positive voltage, thereby reducing power loss. The existing freewheeling diode generally forms a P-N junction between an ion implantation region and an epitaxial layer through an implantation process. The potential barrier of the P-N junction is high, and thus the on-voltage drop is large, thereby increasing the power loss.

[0046] Therefore, Figure 1 A structure schematic diagram of a semiconductor device provided by the embodiment of the present application is provided. Figure 1 , comprising:

[0047] The semiconductor body 100 includes a first surface and a second surface arranged oppositely. The semiconductor body 100 includes a well region 30, a first region 40, a second region 50 and an isolation region 60. The first region 40 is arranged on the first surface and extends from the first surface into the semiconductor body 100. The well region 30 is located on the side of the first region 40 away from the first surface. The second region 50 is arranged on the first surface and extends from the first surface into the semiconductor body 100. The isolation region 60 is arranged between the second region 50 and the first region 40. The first region 40 and the second region 50 are of a first conductivity type, and the well region 30 is of a second conductivity type. The first conductivity type and the second conductivity type are different. The first surface is provided with a gate trench 121. The gate trench 121 extends from the first surface into the semiconductor body 100.

[0048] The gate structure 120 is located in the gate trench 121.

[0049] A freewheel structure 110 is disposed on the side of the first surface away from the second region 50, and a projection of the freewheel structure 110 on the first surface covers at least a projection of the second region 50 on the first surface; the freewheel structure 110 is configured to provide a freewheel channel;

[0050] A source electrode 130 is disposed on the first surface and electrically connected to the freewheel structure 110.

[0051] A drain electrode 140 is disposed on the second surface.

[0052] In particular, the semiconductor device in the embodiment of the present application can be a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET), and the semiconductor body 100 includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40, and a second region 50. The substrate 10 and the epitaxial layer 20 can be made of silicon carbide. The epitaxial layer 20 is formed on one side of the substrate 10. For example, the epitaxial layer 20 can be formed on the surface of the substrate 10 by epitaxial growth. The surface of the epitaxial layer 20 away from the substrate 10 is the first surface. The first region 40 is disposed on the first surface and extends into the epitaxial layer 20 from the first surface. The well region 30 is disposed in the epitaxial layer 20 away from the first surface of the first region 40. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation, or vapor deposition. For example, the well region 30 can be formed on the first surface by ion implantation, and then the first region 40 can be formed on the first surface by ion implantation. The well region 30 and the first region 40 can be used to form a conductive channel of the semiconductor device. The first region 40 is of a first conductivity type, and the well region 30 is of a second conductivity type.

[0053] The first conductive type in the embodiment of the present application can be N-type conductive type, and the second conductive type can be P-type conductive type, or the first conductive type can be P-type conductive type, and the second conductive type can be N-type doping. The N-type conductive type can be obtained by doping ions such as P (phosphorus) or N (nitrogen) ions in a semiconductor, and the P-type conductive type can be obtained by doping ions such as Al (aluminum) ions or B (boron) ions in a semiconductor. P+ and N+ shown in the figure represent that the ion doping concentration of the region is high, and P- and N- represent that the ion doping concentration of the region is low. For example, the first conductive type is N-type conductive type, and the second conductive type is P-type conductive type in the embodiment of the present application. When the semiconductor device is an N-type device, the substrate 10 is of the first conductive type, for example, can be an N+ silicon carbide substrate 10; the epitaxial layer 20 is of the first conductive type, for example, can be an N- silicon carbide epitaxial layer 20; when the semiconductor device is a P-type device, the substrate 10 is of the second conductive type, for example, can be a P+ silicon carbide substrate 10; and the epitaxial layer 20 is of the second conductive type, for example, can be a P- silicon carbide epitaxial layer 20.

[0054] The second region 50 can be formed on the first surface by ion implantation and extend into the epitaxial layer 20. The second region 50 can improve the uniformity of the current entering the epitaxial layer 20 and avoid local current density being too large. The region where the second region 50 contacts the first region 40 is provided with an isolation region 60, which can avoid the second region 50 and the first region 40 from being short-circuited. Part of the well region 30 can be reused as the isolation region 60, that is, the well region 30 is used to isolate the second region 50 and the first region 40 by using the difference in conductive type between the well region 30 and the second region 50 and the first region 40. For example, in the preparation process, part of the well region 30 extends to the first surface along the thickness direction of the device, so that part of the well region 30 has a certain width size between the second region 50 and the first region 40, thereby realizing the isolation between the second region 50 and the first region 40. In the preparation process, the well region 30 can also be formed on the first surface by ion implantation, and then the first region 40 with a pattern is formed on the first surface by ion implantation, and the first region 40 extends into the well region 30. That is, the first region 40 with intervals is formed on the first surface, and the well region 30 between adjacent first regions 40 can be reused as the isolation region 60 in the subsequent structure.

[0055] The gate trench 121 can be formed on the first surface by an etching process, and the gate trench 121 passes through the first region 40 and the well region 30 and extends from the first surface to the epitaxial layer 20. The gate structure 120 is arranged in the gate trench 121, and the well region 30 on both sides of the gate structure 120 can form a vertical conductive channel. The second insulating layer 122 is arranged between the gate structure 120 and the gate trench 121, and the second insulating layer 122 is arranged on the inner wall and the bottom of the gate trench 121. The second insulating layer 122 can be a gate oxide layer, and the gate oxide layer can be a high dielectric constant (K) material. The gate structure 120 can be N+ polysilicon material, and the work function of the N+ polysilicon material is relatively low, which can effectively adjust the threshold voltage of the device.

[0056] The freewheeling structure 110 is located on one side of the gate trench 121. In some embodiments, the freewheeling structure 110 can be arranged on both sides of the gate trench 121, respectively, as shown in Figure 1 The two freewheeling structures 110 can be symmetrically or asymmetrically arranged. The freewheeling structure 110 is used to provide a freewheeling channel. In combination with the structure shown in Figure 1 The third insulating layer 123 is further included between the source and the gate structure 120, and the third insulating layer 123 can be an inter layer dielectric (ILD). The third insulating layer 123 covers the surface of the gate structure 120, and the third insulating layer 123 isolates the gate structure 120 and the source 130. The source 130 can be formed by sputtering or other methods, for example. The source 130 is a metal conductive layer, and the material of the source 130 can be titanium (Ti), nickel (Ni), or silver (Ag).

[0057] The semiconductor device provided in the embodiment of the present application introduces the freewheeling structure 110, and the freewheeling structure 110 is arranged on the side of the first surface away from the second region 50. The orthographic projection of the freewheeling structure 110 on the first surface at least covers the orthographic projection of the second region 50 on the first surface. The source 130 is electrically connected to the freewheeling structure 110. Therefore, when the source 130 has a voltage, the freewheeling channel is provided by the freewheeling structure 110, the on-voltage is reduced, and the current sequentially passes through the source 130, the freewheeling structure 110, the second region 50, and the epitaxial layer 20 and is finally output by the drain. Thus, the freewheeling channel is increased in the device to reduce the reverse on-voltage drop, and the performance stability and safety of the semiconductor device are improved.

[0058] Continuing to refer to Figure 1Optionally, the freewheeling structure 110 comprises a first semiconductor conductive layer 111, a second semiconductor conductive layer 112 and a third semiconductor conductive layer 113 which are stacked; the first semiconductor conductive layer 111 is located close to the first surface; the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 are of a first conductive type, and the second semiconductor conductive layer 112 is of a second conductive type;

[0059] The freewheeling structure 110 further comprises a first insulating layer 114 located away from the first surface on the side of the third semiconductor conductive layer 113; the first insulating layer 114 covers the third semiconductor conductive layer 113, and covers the side walls of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113; the first insulating layer 114 is provided with a first opening area 115, and the first opening area 115 exposes at least part of the third semiconductor conductive layer 113.

[0060] Specifically, the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113 can be made of polysilicon material, wherein the second semiconductor conductive layer 112 is arranged between the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113. According to the above embodiment, the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 can be of the first conductive type, for example, the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 are of N-type conductive type, and the second semiconductor conductive layer 112 is of P-type conductive type. Therefore, the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113 form a thin film transistor (TFT) structure, the first semiconductor conductive layer 111 is located on the first surface and contacts the second region 50, the third semiconductor conductive layer 113 is provided with the first insulating layer 114 on the side away from the first surface, and the first insulating layer 114 can cover the sidewalls of the semiconductor conductive layers to avoid short circuit caused by the contact between the source 130 and the sidewalls of the semiconductor conductive layers. The first insulating layer 114 is further provided with a first opening area 115, the first opening area 115 can expose part of the third semiconductor conductive layer 113, so that the third semiconductor conductive layer 113 can form an electrical connection with the source 130 through the first opening area 115. In the TFT structure formed by the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113, the third semiconductor conductive layer 113 is the source 130 of the TFT, the second semiconductor conductive layer 112 is the channel of the TFT, and the second semiconductor conductive layer 112 is the drain 140 of the TFT. The source 130 acts as the gate of the TFT, that is, the source 130 and the gate are short-circuited in the TFT structure. Therefore, when the source 130 inputs a positive voltage, the gate of the TFT is also a positive voltage, the channel of the TFT is turned on, and the current direction is the source 130, the third semiconductor conductive layer 113, the second semiconductor conductive layer 112, the first semiconductor conductive layer 111, the second region 50, the epitaxial layer 20 and the drain 140. Compared with the P-N junction formed by the ion implantation region and the epitaxial layer 20, the polysilicon in the TFT structure has a small energy band width and a low electron potential barrier between the conduction band and the Fermi level. When the source 130 is given a high potential, it is more conducive to reverse conduction, thereby reducing the reverse conduction voltage drop.

[0061] Continuing to refer to Figure 1 Optionally, the freewheeling structure 110 further includes a metal conductive layer 115 located between the first semiconductor conductive layer 111 and the second region 50.

[0062] Specifically, the first semiconductor conductive layer 111 is provided with a metal conductive layer 115 close to the second region 50, the metal conductive layer 115 has contact with the second region 50, and the contact resistance between the first semiconductor conductive layer 111 and the second region 50 is reduced by the metal conductive layer 115, thereby reducing the influence of the large difference in work function between the first semiconductor conductive layer 111 and the second region 50, and further reducing the on-resistance of the semiconductor device and improving the conduction efficiency of the device. According to the conduction type of the second region 50, the metal material of the metal conductive layer 115 can be selected. For example, the metal material of the metal conductive layer 115 in the embodiment of the present application can be nickel.

[0063] Optionally, the semiconductor body 100 further comprises: a buried layer 70 located between the substrate 10 and the gate structure 120; the buried layer 70 is arranged along the first direction; the first direction is a direction parallel to the first surface, and the buried layer 70 is arranged in the epitaxial layer 20 between the gate structure 120 and the substrate 10 along the first direction; the buried layer 70 is of the second conduction type, wherein, when the buried layer 70 is used in a terminal application, the buried layer 70 needs to have the same potential as the source electrode 130, therefore, a depletion region can be formed between the buried layer 70 and the epitaxial layer 20, thereby playing a role of shielding the electric field of the gate structure 120, improving the problem of gate oxide breakdown, and ensuring the reliability of the device. Further, the buried layer 70 is further provided with a second opening region 71, the second opening region 71 is used to adjust the current flow path of the freewheeling diode formed by the freewheeling structure 110 and the current flow path when the semiconductor device is working. The orthographic projection of the second opening region 71 on the first surface and the orthographic projection of the gate structure 120 and the freewheeling structure 110 on the first surface at least overlap, that is, the second opening region 71 is at least arranged below the freewheeling structure 110 close to the substrate 10, thereby forming a current channel of the freewheeling diode. The second opening region 71 is at least arranged below the gate structure 120 close to the substrate 10, thereby forming a current channel when the semiconductor device is working. Further, the orthographic projection of the buried layer 70 on the first surface and the orthographic projection of the corner region of the gate trench 121 on the first surface at least overlap, that is, a buried layer 70 with a certain width size along the first direction is arranged below the corner region of the gate trench 121 close to the substrate 10, which ensures that the buried layer 70 can shield and protect the corner region of the gate trench 121, and further improves the reliability of the device.

[0064] The embodiment of the present application provides a power module on the basis of the above-mentioned embodiment, which comprises a substrate and the semiconductor device of any embodiment of the present application, and the substrate is used for carrying the semiconductor device.

[0065] The power module provided by the technical scheme of the embodiment of the present application has the same beneficial effects as the semiconductor device of any embodiment of the present application.

[0066] The embodiment of the present application provides a power conversion circuit on the basis of the above-mentioned embodiment, the power conversion circuit is used for one or more of current conversion, voltage conversion and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device as any embodiment of the present application, and the semiconductor device is electrically connected with the circuit board.

[0067] The power conversion circuit provided by the technical scheme of the embodiment of the present application has the same beneficial effects as the semiconductor device of any embodiment of the present application.

[0068] The embodiment of the present application provides a vehicle on the basis of the above-mentioned embodiment, the vehicle comprises a load and a power conversion circuit as any embodiment of the present application, and the power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current or converting direct current into alternating current and then inputting to the load.

[0069] The embodiment of the present application provides a preparation method of a semiconductor device on the basis of the above-mentioned embodiment, Figure 2 It is a flow chart of the preparation method of the semiconductor device provided by the embodiment of the present application, in combination with Figure 1 , referring to Figure 2 , the preparation method comprises the following steps.

[0070] S110, providing a semiconductor body 100, the semiconductor body 100 comprises oppositely arranged first and second surfaces, the semiconductor body 100 comprises a well region 30, a first region 40, a second region 50 and an isolation region 60, the first region 40 is arranged on the first surface and extends from the first surface into the semiconductor body 100, the well region 30 is located on the side of the first region 40 away from the first surface; the second region 50 is arranged on the first surface and extends from the first surface into the semiconductor body 100; the isolation region 60 is arranged between the second region 50 and the first region 40; the first region 40 and the second region 50 are of a first conductive type, the well region 30 is of a second conductive type, the first conductive type and the second conductive type are different; the first surface is provided with a gate trench 121; the gate trench 121 extends from the first surface into the semiconductor body 100;

[0071] Specifically, the semiconductor body 100 comprises a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50. The substrate 10 and the epitaxial layer 20 can be made of silicon carbide. The epitaxial layer 20 is formed on one side of the substrate 10 by epitaxial growth. The epitaxial layer 20 has a first surface on the side away from the substrate 10. The first region 40 is disposed on the first surface and extends into the epitaxial layer 20 from the first surface. The well region 30 is disposed in the epitaxial layer 20 away from the first surface of the first region 40. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation or vapor deposition. In the embodiment of the present application, the well region 30 and the first region 40 are formed by ion implantation. The well region 30 is formed on the first surface by ion implantation and extends into the epitaxial layer 20 from the first surface. The first region 40 is formed on the first surface by ion implantation and extends into the well region 30 from the first surface. The well region 30 and the first region 40 can be used to form a conductive channel of a semiconductor device. The first region 40 is of a first conductivity type and the well region 30 is of a second conductivity type.

[0072] In the embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. When the semiconductor device is an N-type device, the substrate 10 is of the first conductivity type, for example, an N+ silicon carbide substrate 10. The epitaxial layer 20 is of the first conductivity type, for example, an N- silicon carbide epitaxial layer 20. When the semiconductor device is a P-type device, the substrate 10 is of the second conductivity type, for example, a P+ silicon carbide substrate 10. The epitaxial layer 20 is of the second conductivity type, for example, a P- silicon carbide epitaxial layer 20.

[0073] The second region 50 can be formed on the first surface by ion implantation and extend into the epitaxial layer 20. The second region 50 is in contact with the first region 40, and an isolation region 60 is arranged at the contact position of the second region 50 and the first region 40. The isolation region 60 can avoid short circuit between the second region 50 and the first region 40. Part of the well region 30 is reused as the isolation region 60. That is, the well region 30 is used to isolate the second region 50 and the first region 40 by using the difference in conductivity type between the well region 30 and the second region 50 and the first region 40. In the manufacturing process, part of the well region 30 extends to the first surface along the thickness direction of the device, so that part of the well region 30 has a certain width between the second region 50 and the first region 40, thereby achieving isolation between the second region 50 and the first region 40. In the manufacturing process, the well region 30 can also be formed on the first surface by ion implantation, and the well region 30 extends from the first surface into the epitaxial layer 20. Then, the first region 40 with a pattern is formed on the first surface by ion implantation, and the first region 40 extends from the first surface into the well region 30. That is, the first region 40 with a pattern is formed on the first surface, and the well region 30 between adjacent first regions 40 can be reused as the isolation region 60 in the subsequent structure. The gate trench 121 can be formed on the first surface by etching, and the gate trench 121 passes through the first region 40 and the well region 30 and extends from the first surface to the epitaxial layer 20.

[0074] S120, forming a gate structure 120 in the gate trench 121;

[0075] Specifically, the gate structure 120 is arranged in the gate trench 121, and the well region 30 on both sides of the gate structure 120 can form a vertical conductive channel. The second insulating layer 122 is arranged between the gate structure 120 and the gate trench 121, and the second insulating layer 122 is arranged on the inner wall and the bottom of the gate trench 121. The second insulating layer 122 can be a gate oxide layer, and the gate oxide layer can be a high dielectric constant (K) material. The gate structure 120 can be N+ polysilicon material, and the work function of the N+ polysilicon material is relatively low, which can effectively adjust the threshold voltage of the device.

[0076] S130, forming a freewheeling structure 110 on the side of the first surface away from the second region 50, and the orthographic projection of the freewheeling structure 110 on the first surface at least covers the orthographic projection of the second region 50 on the first surface; the freewheeling structure 110 is used to provide a freewheeling channel;

[0077] Specifically, the freewheeling structure 110 is located on one side of the gate trench 121. In some embodiments, the freewheeling structure 110 can be arranged on both sides of the gate trench 121, respectively, as shown in FIG. 1C. Figure 1 The two freewheeling structures 110 can be symmetrically or asymmetrically arranged.

[0078] S140, forming a source electrode 130 on the first surface, the source electrode 130 being electrically connected to the freewheel structure 110;

[0079] In combination Figure 1 As shown in the structure, the source electrode 130 and the gate structure 120 further comprise a third insulating layer 123, the third insulating layer 123 can be an inter layer dielectric (ILD), the third insulating layer 123 covers the surface of the gate structure 120, and the third insulating layer 123 isolates the gate structure 120 and the source electrode 130. For example, the source electrode 130 can be formed by sputtering or other methods, the source electrode 130 is a conductive layer, and the material of the source electrode 130 can be titanium (Ti), nickel (Ni), or silver (Ag).

[0080] S150, forming a drain electrode 140 on the second surface.

[0081] Optionally, the freewheel structure 110 formed on the first surface away from the second region 50 comprises:

[0082] The first semiconductor conductive layer 111, the second semiconductor conductive layer 112, and the third semiconductor conductive layer 113 are sequentially stacked on the first surface;

[0083] The first insulating layer 114 is formed on the side of the third semiconductor conductive layer 113 away from the first surface, the first insulating layer 114 covers the third semiconductor conductive layer 113, and covers the side walls of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112, and the third semiconductor conductive layer 113; the first insulating layer 114 is provided with a first opening area 115, and the first opening area 115 exposes at least part of the third semiconductor conductive layer 113.

[0084] Specifically, the first semiconductor conductive layer 111, the second semiconductor conductive layer 112, and the third semiconductor conductive layer 113 can be made of polysilicon material, wherein the second semiconductor conductive layer 112 is arranged between the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113, and in combination with the above embodiment, the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 can be of a first conductive type, for example, the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 are of N-type conductive type, and the second semiconductor conductive layer 112 is of P-type conductive type. Therefore, the first semiconductor conductive layer 111, the second semiconductor conductive layer 112, and the third semiconductor conductive layer 113 form a TFT structure.

[0085] The first semiconductor conductive layer 111 is located on the first surface and contacts the second region 50. The third semiconductor conductive layer 113 is provided with the first insulating layer 114 on the side away from the first surface. The first insulating layer 114 can cover the sidewalls of each semiconductor conductive layer, avoiding the short circuit caused by the contact between the source 130 and the sidewalls of each semiconductor conductive layer. The first insulating layer 114 is further provided with a first opening area 115. The first opening area 115 can expose part of the third semiconductor conductive layer 113, so that the third semiconductor conductive layer 113 can form an electrical connection with the source 130 through the first opening area 115. In the preparation process, the first insulating layer 114 and the third insulating layer 123 can be deposited simultaneously to obtain an insulating layer. According to the design pattern, the insulating layer needs to expose part of the first region 40 as an ohmic contact area and part of the third semiconductor conductive layer 113, so that the source 130 can be connected to part of the first region 40 and part of the third semiconductor conductive layer 113.

[0086] In the TFT structure formed by the first semiconductor conductive layer 111, the second semiconductor conductive layer 112, and the third semiconductor conductive layer 113, the third semiconductor conductive layer 113 is the source 130 of the TFT, the second semiconductor conductive layer 112 is the channel of the TFT, and the second semiconductor conductive layer 112 is the drain 140 of the TFT. The source 130 acts as the gate of the TFT, that is, the source 130 is short-circuited with the gate in the TFT structure. Therefore, when the source 130 inputs a positive voltage, the gate of the TFT is also a positive voltage, the channel of the TFT is turned on, and the current direction is the source 130, the third semiconductor conductive layer 113, the second semiconductor conductive layer 112, the first semiconductor conductive layer 111, the second region 50, the epitaxial layer 20, and the drain 140. Compared with the P-N junction formed by the ion implantation region and the epitaxial layer 20, the band width of the polysilicon in the TFT structure is small, and the electron potential barrier between the conduction band and the Fermi level is low. When the source 130 is given a high potential, it is more conducive to reverse conduction, thereby reducing the reverse conduction voltage drop.

[0087] As an optional embodiment, the semiconductor device structure is taken as an example, Figure 1 As an optional embodiment, the semiconductor device structure is taken as an example, Figure 3 As an optional embodiment, the semiconductor device structure is taken as an example, Figures 4-8 As an optional embodiment, the semiconductor device structure is taken as an example, Figures 3-8 The preparation method comprises the following steps:

[0088] S210, forming a first epitaxial layer 21 on one side of the substrate 10;

[0089] S220, forming a buried layer 70 away from the surface of the substrate 10 along the first direction, the buried layer 70 extending from the surface of the substrate 10 away from the first epitaxial layer 21 to the first epitaxial layer 21, the buried layer 70 being provided with a second opening area 71, the orthogonal projection of the second opening area 71 on the first surface at least partially overlapping the orthogonal projection of the gate structure 120 and the freewheeling structure 110 on the first surface; the first direction being a direction parallel to the first surface;

[0090] Specifically, the buried layer 70 is arranged in the epitaxial layer 20 between the gate structure 120 and the substrate 10 along the first direction, and the buried layer 70 is of the second conductivity type. When the buried layer 70 is used in a terminal application, the buried layer 70 needs to have the same potential as the source electrode 130. Therefore, a depletion region can be formed between the buried layer 70 and the epitaxial layer 20, so as to shield the electric field of the gate structure 120, improve the breakdown problem of the gate oxide layer, and ensure the reliability of the device. Further, the buried layer 70 is further provided with an opening area, which is used to adjust the current flow path of the freewheeling diode formed by the freewheeling structure 110 and the current flow path during the operation of the semiconductor device. The orthogonal projection of the opening area on the first surface at least partially overlaps the orthogonal projection of the gate structure 120 and the freewheeling structure 110 on the first surface, that is, the opening area is arranged at least below the freewheeling structure 110 close to the substrate 10, so as to form the current channel of the freewheeling diode. The opening area is arranged at least below the gate structure 120 close to the substrate 10, so as to form the current channel during the operation of the semiconductor device. Further, the orthogonal projection of the buried layer 70 on the first surface at least partially overlaps the orthogonal projection of the corner region of the gate trench 121 on the first surface, that is, a buried layer 70 with a certain width along the first direction is arranged below the corner region of the gate trench 121 close to the substrate 10, so as to shield and protect the corner region of the gate trench 121 by the buried layer 70, and further improve the reliability of the device. The structure is shown in Figure 4 .

[0091] S230, forming a second epitaxial layer 22 away from the surface of the substrate 10 on the first epitaxial layer 21, the first epitaxial layer 21 and the second epitaxial layer 22 constituting the epitaxial layer 20. The structure is shown in Figure 5 .

[0092] S240, taking the surface of the epitaxial layer 20 away from the substrate 10 as a first surface, forming a well region 30 on the first surface, the well region 30 extending from the first surface to the epitaxial layer 20;

[0093] S250, forming a first region 40 with a spacing on the first surface, the first region 40 extending from the first surface into the epitaxial layer 20; wherein the implantation position of the first region 40 can be designed according to a preset pattern, and the well region 30 between adjacent first regions 40 can be reused as an isolation region 60 in a subsequent structure. The structure is as shown in Figure 6 .

[0094] S260, forming a second region 50 on the first surface of the spacing region between adjacent first regions 40, the second region 50 extending from the first surface into the semiconductor body 100; the part of the well region 30 on both sides of the second region 50 as an isolation region 60 between the second region 50 and the first region 40; wherein the first region 40 and the second region 50 are of a first conductive type, the well region 30 is of a second conductive type, and the first conductive type and the second conductive type are different;

[0095] Wherein the second region 50 can be formed on the first surface of the epitaxial layer 20 by an ion implantation process, and extends from the first surface into the epitaxial layer 20, and the well region 30 between adjacent first regions 40 is reused as an isolation region 60 by using the difference in conductive type between the well region 30 and the second region 50 and the first region 40, to realize the isolation of the second region 50 and the first region 40.

[0096] S270, forming a gate trench 121 on the first surface; the gate trench 121 extends from the first surface into the epitaxial layer 20. The structure is as shown in Figure 7 .

[0097] S280, forming a gate structure 120 in the gate trench 121.

[0098] S290, sequentially stacking a first semiconductor conductive layer 111, a second semiconductor conductive layer 112 and a third semiconductor conductive layer 113 on the first surface;

[0099] Optionally, before forming the first semiconductor conductive layer 111, a metal conductive layer 115 is formed on the surface of the second region 50, and the metal conductive layer 115 is located between the first semiconductor conductive layer 111 and the second region 50. Specifically, the metal conductive layer 115 is arranged on the side of the first semiconductor conductive layer 111 close to the second region 50, and the metal conductive layer 115 has contact with the second region 50, so as to reduce the contact resistance between the first semiconductor conductive layer 111 and the second region 50, thereby reducing the influence of the large difference in work function between the first semiconductor conductive layer 111 and the second region 50, and further reducing the on-resistance of the semiconductor device and improving the conduction efficiency of the device. According to the conductive type of the second region 50, the metal material of the metal conductive layer 115 can be selected, and the metal material of the metal conductive layer 115 in the embodiment of the present application can be nickel, for example.

[0100] S300, forming a first insulating layer 114 on the side of the third semiconductor conductive layer 113 away from the first surface, the first insulating layer 114 covering the third semiconductor conductive layer 113, and covering the sidewalls of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113; the first insulating layer 114 is provided with a first opening area 115, the first opening area 115 exposing at least part of the third semiconductor conductive layer 113.

[0101] Specifically, the first insulating layer 114 can be deposited simultaneously with the third insulating layer 123 to obtain an insulating layer, according to the design pattern, the insulating layer needs to expose part of the first area 40 as an ohmic contact area, and expose part of the third semiconductor conductive layer 113, so that the source electrode 130 can be connected with part of the first area 40 and part of the third semiconductor conductive layer 113. The structure is as shown in Figure 8

[0102] S310, forming a source electrode 130 and a drain electrode 140 on one side of the substrate 10. The structure is as shown in Figure 1

[0103] It should be noted that according to the convenience of the preparation process, the corresponding step sequence can be adjusted, and no specific limitation is made here.

[0104] Finally, it should be pointed out that: the above examples are only used to illustrate the technical solutions of the present application, and not to limit it; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.​​

Claims

1. A semiconductor device, characterized by, The semiconductor body comprises a first surface and a second surface arranged oppositely, and comprises a well region, a first region, a second region and an isolation region; the first region is arranged at the first surface and extends into the semiconductor body from the first surface; the well region is located at a side of the first region away from the first surface; the second region is arranged at the first surface and extends into the semiconductor body from the first surface; the isolation region is arranged between the second region and the first region; the first region and the second region are of a first conductivity type, the well region is of a second conductivity type, and the first conductivity type and the second conductivity type are different; the first surface is provided with a gate trench; the gate trench extends into the semiconductor body from the first surface; a gate structure is located in the gate trench; a freewheel structure is arranged at a side of the first surface away from the second region, and a projection of the freewheel structure on the first surface at least covers a projection of the second region on the first surface; the freewheel structure is used to provide a freewheel channel; a source electrode is located at the first surface and electrically connected with the freewheel structure; a drain electrode is located at the second surface; the freewheel structure comprises a first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer which are stacked; the first semiconductor conductive layer is located at a side close to the first surface; the first semiconductor conductive layer and the third semiconductor conductive layer are of the first conductivity type, and the second semiconductor conductive layer is of the second conductivity type; the freewheel structure further comprises a first insulating layer located at a side of the third semiconductor conductive layer away from the first surface; the first insulating layer covers the third semiconductor conductive layer, and covers a side wall of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer is provided with a first opening region, and the first opening region exposes at least part of the third semiconductor conductive layer; the freewheel structure further comprises a metal conductive layer located between the first semiconductor conductive layer and the second region; the semiconductor body further comprises a buried layer located at a side of the gate structure away from the first surface; the buried layer extends along a first direction; the buried layer further comprises a second opening region, and a projection of the second opening region on the first surface at least overlaps with projections of the gate structure and the freewheel structure on the first surface; the first direction is a direction parallel to the first surface; the semiconductor device is used in a power conversion circuit; the power conversion circuit is used for one or more of current conversion, voltage conversion and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device as claimed in any one of claims 1-3, and the semiconductor device is electrically connected with the circuit board. The semiconductor body comprises a first surface and a second surface arranged oppositely, and comprises a well region, a first region, a second region and an isolation region; the first region is arranged at the first surface and extends into the semiconductor body from the first surface; the well region is located at a side of the first region away from the first surface; the second region is arranged at the first surface and extends into the semiconductor body from the first surface; the isolation region is arranged between the second region and the first region; the first region and the second region are of a first conductivity type, the well region is of a second conductivity type, and the first conductivity type and the second conductivity type are different; the first surface is provided with a gate trench; the gate trench extends into the semiconductor body from the first surface; a gate structure is located in the gate trench; a freewheel structure is arranged at a side of the first surface away from the second region, and a projection of the freewheel structure on the first surface at least covers a projection of the second region on the first surface; the freewheel structure is used to provide a freewheel channel; a source electrode is located at the first surface and electrically connected with the freewheel structure; a drain electrode is located at the second surface; the freewheel structure comprises a first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer which are stacked; the first semiconductor conductive layer is located at a side close to the first surface; the first semiconductor conductive layer and the third semiconductor conductive layer are of the first conductivity type, and the second semiconductor conductive layer is of the second conductivity type; the freewheel structure further comprises a first insulating layer located at a side of the third semiconductor conductive layer away from the first surface; the first insulating layer covers the third semiconductor conductive layer, and covers a side wall of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer is provided with a first opening region, and the first opening region exposes at least part of the third semiconductor conductive layer; the freewheel structure further comprises a metal conductive layer located between the first semiconductor conductive layer and the second region; the semiconductor body further comprises a buried layer located at a side of the gate structure away from the first surface; the buried layer extends along a first direction; the buried layer further comprises a second opening region, and a projection of the second opening region on the first surface at least overlaps with projections of the gate structure and the freewheel structure on the first surface; the first direction is a direction parallel to the first surface; the semiconductor device is used in a power conversion circuit; the power conversion circuit is used for one or more of current conversion, voltage conversion and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device as claimed in any one of claims 1-3, and the semiconductor device is electrically connected with the circuit board. ​ ​ ​ ​ ​ ​ ​ 2. The semiconductor device according to claim 1, wherein ​ 3. The semiconductor device according to any one of claims 1-2, wherein ​ ​ 4. A power module, characterized by ​ 5. A power conversion circuit, characterized by, ​ ​ 6. A vehicle characterized by comprising: The power conversion circuit as claimed in claim 5 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input to the load.

7. A method of manufacturing a semiconductor device, characterized by Comprise: A semiconductor body is provided, comprising a first surface and a second surface arranged oppositely, the semiconductor body comprising a well region, a first region, a second region and an isolation region, the first region being arranged at the first surface and extending from the first surface into the semiconductor body, the well region being located at a side of the first region away from the first surface; the second region being arranged at the first surface and extending from the first surface into the semiconductor body; the isolation region being arranged between the second region and the first region; the first region and the second region being of a first conductivity type, the well region being of a second conductivity type, the first conductivity type and the second conductivity type being different; the first surface being provided with a gate trench; the gate trench extending from the first surface into the semiconductor body; A gate structure is formed in the gate trench; A freewheel structure is formed at a side of the first surface away from the second region, a projection of the freewheel structure on the first surface covering at least a projection of the second region on the first surface; The freewheel structure is used to provide a freewheeling path; A source electrode is formed on the first surface, the source electrode being electrically connected to the freewheel structure; A drain electrode is formed on the second surface; Wherein, forming the freewheel structure at a side of the first surface away from the second region comprises: A first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer are sequentially stacked on the first surface; A first insulating layer is formed at a side of the third semiconductor conductive layer away from the first surface, the first insulating layer covering the third semiconductor conductive layer and the sidewalls of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer is provided with a first opening region, the first opening region exposing at least part of the third semiconductor conductive layer.

8. The method of producing a semiconductor device according to Claim 7, wherein A semiconductor body is provided, comprising: An epitaxial layer is formed on one side of a substrate; A surface of the epitaxial layer away from the substrate side is used as a first surface, a well region is formed on the first surface, the well region extending from the first surface into the epitaxial layer; The first region is formed on the first surface with a spacing, the first region extending from the first surface into the well region; The second region is formed on the first surface of the spacing region between adjacent first regions, the second region extending from the first surface into the semiconductor body; the well region on both sides of the second region is used as the isolation region between the second region and the first region; wherein, the first region and the second region are of a first conductivity type, the well region is of a second conductivity type, the first conductivity type and the second conductivity type are different; A gate trench is formed in the first surface; the gate trench extends from the first surface into the epitaxial layer.

9. The method of producing a semiconductor device according to Claim 7, wherein Before the first semiconductor conductive layer is formed, a metal conductive layer is formed on the surface of the second region, and the metal conductive layer is located between the first semiconductor conductive layer and the second region.

10. The method of producing a semiconductor device according to Claim 8, wherein Forming an epitaxial layer on one side of a substrate comprises: Forming a first epitaxial layer on one side of a substrate; A buried layer is formed on the surface of the first epitaxial layer away from the substrate in a first direction; the buried layer extends from the surface of the first epitaxial layer away from the substrate to the first epitaxial layer; the buried layer is provided with a second opening region; a projection of the second opening region on the first surface at least partially overlaps with a projection of the gate structure and the freewheel structure on the first surface; the first direction is parallel to the first surface; A second epitaxial layer is formed on the surface of the first epitaxial layer away from the substrate; the first epitaxial layer and the second epitaxial layer constitute the epitaxial layer.

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