Floating gate memory with ultralow operating voltage and preparation method thereof

Abstract

The invention discloses a floating gate memory with ultralow operating voltage and a preparation method thereof, the floating gate memory comprises a substrate layer, and a floating gate layer, a tunneling insulating layer and a channel layer which are sequentially arranged on one side of the substrate layer, the floating gate memory further comprises a source electrode and a drain electrode which are arranged on the channel layer, the source electrode is in contact with one side of the channel layer to form electric connection, and the drain electrode is in contact with the other side of the channel layer. The drain electrode is in contact with the other side of the channel layer to form electric connection, and the contact area of the source electrode and the tunneling insulating layer is larger than that of the drain electrode and the tunneling insulating layer. According to the invention, based on the property that the two-dimensional semiconductor material can still preserve good dielectric property under the condition of extremely thin thickness, the operation voltage of the flash memory can be greatly reduced through the asymmetric design of the source end and the drain end, so that the requirement of standard power supply voltage is met, and the integration difficulty and complexity are greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of floating gate memory, and in particular to a floating gate memory with an ultra-low operating voltage and a preparation method thereof. Background Art

[0002] With the continuous improvement of storage density and the advancement of integrated circuit technology, flash memory technology is also developing. At present, flash memory devices have not only achieved significant improvements in storage capacity, but also made important breakthroughs in read and write speed, durability and power consumption. For example, with the emergence of 3D NAND technology, multiple storage cells are stacked vertically, which further improves storage density and significantly reduces interference and crosstalk between cells.

[0003] However, although the existing flash memory technology has made significant progress, there are still certain challenges in terms of storage density, programming voltage, erase speed, durability and power management. For example, in terms of operating voltage, in the existing three-terminal floating gate flash memory technology, a higher operating voltage is often required to implement programming and erasing operations, which will bring a series of problems. For example, in terms of integration, since the standard power supply voltage in circuit design (up to 5V) is often much lower than the operating voltage of flash memory (more than 10V, or even 50V), the high operating voltage makes integration more difficult, and often requires an additional boost circuit (Boost Converter) or a separate power supply to provide the required programming voltage and erase voltage.

[0004] Chinese patent 201980097143X discloses a flash memory cell suitable for low voltage and / or non-volatile performance. Although it can operate in a low voltage domain, the memory is still based on the structure of a traditional three-terminal floating gate device, and even requires the introduction of more gates to achieve low operating voltage. Compared with a two-terminal floating gate device, a three-terminal floating gate has an extra gate, so there are more corresponding preparation steps in the preparation process, which leads to the complexity of the preparation process and makes the preparation process more cumbersome; secondly, the control gate of the three-terminal floating gate device is a bottom gate in most cases. Since there are many other functional layers between the control gate and the channel layer, the bottom gate has a weaker regulatory effect on the channel layer, and often requires a large voltage to regulate the channel layer. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a floating gate memory with an ultra-low operating voltage and a simple structure and preparation process, and a preparation method thereof, which can significantly reduce the operating voltage of the flash memory and reduce the difficulty of integration.

[0006] Technical solution: To achieve the above-mentioned purpose, a floating gate memory with an ultra-low operating voltage described in the present invention includes a substrate layer and a floating gate layer, a tunneling insulating layer and a channel layer sequentially arranged on one side of the substrate layer, and also includes a source electrode and a drain electrode arranged on the channel layer, the source electrode contacts one side of the channel layer to form an electrical connection, the drain electrode contacts the other side of the channel layer to form an electrical connection, and the contact area between the source electrode and the tunneling insulating layer is greater than the contact area between the drain electrode and the tunneling insulating layer.

[0007] Wherein, the floating gate layer is made of metal material.

[0008] Wherein, the thickness of the floating gate layer is ≥5nm.

[0009] Wherein, the tunneling insulating layer is made of insulating two-dimensional material.

[0010] Wherein, the channel layer adopts semiconductor two-dimensional material.

[0011] Wherein, the thickness of the tunneling insulating layer is 6±5 nm.

[0012] A method for preparing the floating gate memory with an ultra-low operating voltage according to the present invention comprises:

[0013] (1) patterning a floating gate layer on the surface of the substrate layer;

[0014] (4) evaporating metal on the surface of the substrate layer to prepare a floating gate layer;

[0015] (5) stacking a tunnel insulating layer and a channel layer in sequence on the surface of the floating gate layer;

[0016] (4) performing source and drain patterning on the surface of the channel layer;

[0017] (5) Prepare source electrode and drain electrode on the surface of the channel layer.

[0018] The electron beam exposure (EBL) technology is used to pattern the floating gate layer on the surface of the substrate layer or to pattern the source electrode and the drain electrode on the surface of the channel layer.

[0019] Wherein, electron beam evaporation technology is used to evaporate metal on the surface of the substrate layer to prepare a floating gate layer or to prepare a source electrode and a drain electrode on the surface of the channel layer.

[0020] Wherein, a tunneling insulating layer and a channel layer are sequentially stacked on the floating gate layer by using a PVA wet transfer technology.

[0021] Beneficial effects: The present invention has the following advantages: 1. The floating gate memory of the present invention is based on the property that two-dimensional semiconductor materials can still maintain good dielectric properties when the thickness is extremely thin. Through the asymmetric design of the source and drain ends, the operating voltage of the flash memory can be greatly reduced, so that the requirements of the standard power supply voltage are met, and the difficulty and complexity of integration are greatly reduced; 2. Compared with the three-terminal floating gate device, the floating gate memory of the present invention eliminates the need for separate preparation of the control gate, reducing the complexity and difficulty of the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the floating gate memory hierarchical structure;

[0023] Figure 2 A schematic diagram of a floating gate memory structure including various levels of materials;

[0024] Figure 3 Schematic diagram of parasitic capacitance at both ends of the source and drain of a floating gate memory;

[0025] Figure 4 Schematic diagram of the electron transition process when programming a floating gate memory;

[0026] Figure 5 Schematic diagram of the electron transition process when erasing the floating gate memory. DETAILED DESCRIPTION

[0027] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0028] like Figure 1 As shown, the floating gate memory of the present invention comprises a substrate layer and a floating gate layer, a tunnel insulating layer and a channel layer sequentially arranged on one side of the substrate layer, and also comprises a source electrode and a drain electrode arranged on the channel layer. The source electrode contacts one side of the channel layer to form an electrical connection, and the drain electrode contacts the other side of the channel layer to form an electrical connection, and a portion of the top surface of the channel layer exposed between the source electrode and the drain electrode is the channel portion.

[0029] The source electrode and the drain electrode are designed asymmetrically. Compared with the drain electrode, the source electrode is designed to be wider or longer to increase the contact area with the tunneling insulating layer.

[0030] like Figure 2 As shown, in this embodiment, the substrate layer is made of silicon material, the floating gate layer is made of metal material, such as Au, the tunneling insulating layer is made of insulating two-dimensional material, such as hBN, and the channel layer is made of semiconductor two-dimensional material, such as WSe. 2 The source electrode and the drain electrode are also made of metal materials, such as Cr. In addition, the channel layer is a thin and long strip structure, and the thickness of the floating gate layer is ≥5nm.

[0031] For the floating gate memory of the above structure, there are two processes, programming and erasing. The programming process is driven by hot electron injection, and the erasing process is realized by the tunneling effect. In both processes, the "lucky electron" mechanism is used to achieve low voltage operation, that is, when electrons are in the programming process, they move from the source-drain electrode (Cr) to the floating gate layer (Au), passing the first source-drain electrode (Cr) / channel layer (WSe 2 ) potential barrier, since the height of the first barrier is higher than that of the second channel layer (WSe 2 ) / tunneling insulating layer (hBN), so the electrons do not need to consume energy again to overcome the obstruction of the second barrier; similarly, during the erase process, the electrons move from the floating gate layer (Au) to the source and drain electrodes (Cr). When the electrons pass through the first floating gate layer (Au) / tunneling insulating layer (hBN) barrier in the form of quantum tunneling, their energy is already higher than that of the channel layer (WSe 2 ) / tunneling insulating layer (hBN), so there is no need to expend energy to overcome the barrier again. In general, the energy required to overcome the double barrier is reduced to the energy required to overcome a single barrier.

[0032] like Figure 3 , 4 As shown in Figure 5, to achieve the above process, the present invention introduces additional electrodes above the tunneling insulating layer on both sides of the channel layer by designing asymmetric source and drain electrodes, thereby utilizing the parasitic capacitance formed by the tunneling insulating layer (hBN) and the metal electrodes of the upper and lower layers (the upper layer is the source and drain electrode metal (Cr), and the lower layer is the floating gate layer metal (Au)) and the floating gate layer. At this time, there will be corresponding source-side parasitic capacitance C on both sides of the source and drain electrodes. SMIM And the drain parasitic capacitance C dMIM , and these two capacitors are connected in series. For series capacitors, the smaller the capacitance, the greater the voltage division, so it is hoped that the parasitic capacitance on the voltage-applied side, that is, the drain side, is as small as possible, so that the voltage applied to the tunneling layer will be as large as possible, and the band bending amplitude will be larger. For capacitors, C = εs / d, so the smaller the parasitic capacitance area measured by the applied voltage, the better, and the larger the parasitic capacitance area on the grounded side, the better. Through this asymmetric source-drain design, it can be achieved that when a voltage is applied, the induced voltage on both sides of the tunneling insulating layer (hBN) will be large enough, and the generated electric field strength will be large enough, so that the band bending amplitude of the tunneling insulating layer (hBN) is sufficient, so that the source-drain electrode (Cr) / channel layer (WSe 2 ) has a higher barrier height than the channel layer (WSe 2 ) / tunneling layer (hBN) barrier, when electrons cross the source-drain electrode (Cr) / channel layer (WSe 2 ) barrier will not be affected by the channel layer (WSe 2) / the barrier of the tunneling layer (hBN).

[0033] As for the erasing process, when electrons move from the floating gate layer (Au) to the source and drain electrodes (Cr), the barrier height between the floating gate layer (Au) and the tunneling insulating layer (hBN) is higher than that between the channel layer (WSe 2 ) / tunneling layer (hBN), so during the erase process, as long as the electrons can cross the barrier between the floating gate layer (Au) / tunneling insulating layer (hBN), the electrons will naturally not be affected by the channel layer (WSe 2 ) / barrier of tunneling layer (hBN).

[0034] In addition, the thickness of the tunneling insulating layer (hBN) cannot be too thick, because when the electrons overcome the potential barrier during programming / operation, they still need enough energy to migrate back and forth between the channel layer and the floating gate layer, that is, through the bandgap width of hBN. If the tunneling insulating layer (hBN) is too thick, then the electrons may not be able to migrate successfully. Therefore, the thickness of the tunneling insulating layer is 6±0.5nm.

[0035] The present invention further provides a preparation process of the above-mentioned floating gate memory, comprising: (1) patterning a floating gate layer on a silicon substrate by electron beam exposure (EBL) technology; (2) preparing a floating gate layer by evaporating metal on the surface of the substrate by electron beam evaporation technology; (3) stacking a tunneling insulating layer and a channel layer in sequence on the floating gate layer by PVA wet transfer technology; (4) patterning a source electrode and a drain electrode on the channel layer by electron beam exposure (EBL) technology; and (5) preparing a source electrode and a drain electrode on the surface of the channel layer by electron beam evaporation technology.

[0036] The floating gate memory of the present invention can switch between high and low resistance states at a standard voltage below 5V under a room temperature test environment, that is, perform programming and erasing operations.

[0037] In actual application scenarios, low operating voltage can solve the problem of flash memory heating. For example, when writing a large amount of data to or erasing a flash memory (U disk / hard disk), long-term operation will cause significant heating, thereby reducing the life of the flash memory and posing a safety risk. In addition, for various miniaturized devices such as microcontrollers (MCUs) or miniaturized chips, reducing the operating voltage to the standard power supply voltage range can eliminate additional circuit designs, such as boost circuits or separate power supplies, thereby greatly reducing the complexity of circuit design and reducing device area, which can also significantly improve size miniaturization.

Claims

1. A floating gate memory with ultra-low operating voltage, characterized in that: The invention comprises a substrate layer and a floating gate layer, a tunnel insulating layer and a channel layer which are sequentially arranged on one side of the substrate layer, and also comprises a source electrode and a drain electrode which are arranged on the channel layer, wherein the source electrode contacts one side of the channel layer to form an electrical connection, and the drain electrode contacts the other side of the channel layer to form an electrical connection, and the contact area between the source electrode and the tunnel insulating layer is greater than the contact area between the drain electrode and the tunnel insulating layer.

2. The floating gate memory with ultra-low operating voltage according to claim 1, characterized in that: The floating gate layer is made of metal material.

3. The ultra-low operating voltage floating gate memory according to claim 1, characterized in that: The thickness of the floating gate layer is ≥5 nm.

4. The floating gate memory with ultra-low operating voltage according to claim 1, characterized in that: The tunneling insulating layer is made of insulating two-dimensional material.

5. The floating gate memory with ultra-low operating voltage according to claim 1, characterized in that: The channel layer is made of semiconductor two-dimensional material.

6. The floating gate memory with ultra-low operating voltage according to claim 1, characterized in that: The thickness of the tunneling insulating layer is 6±0.5 nm.

7. A method for preparing a floating gate memory with an ultra-low operating voltage as claimed in claim 1, characterized in that: include: (1) patterning a floating gate layer on the surface of the substrate layer; (2) evaporating metal on the surface of the substrate layer to prepare a floating gate layer; (3) stacking a tunnel insulating layer and a channel layer in sequence on the surface of the floating gate layer; (4) performing source and drain patterning on the surface of the channel layer; (5) Prepare source electrode and drain electrode on the surface of the channel layer.

8. The preparation method according to claim 7, characterized in that: The floating gate layer is patterned on the surface of the substrate layer or the source electrode and the drain electrode are patterned on the surface of the channel layer by using electron beam exposure (EBL) technology.

9. The preparation method according to claim 7, characterized in that: Electron beam evaporation technology is used to evaporate metal on the surface of the substrate layer to prepare a floating gate layer or to prepare a source electrode and a drain electrode on the surface of the channel layer.

10. The preparation method according to claim 7, characterized in that: A tunneling insulating layer and a channel layer are sequentially stacked on the floating gate layer by using a PVA wet transfer technique.

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