Gallium nitride HJFET (High Junction Field Effect Transistor) device with cascode structure and preparation method of gallium nitride HJFET device

Abstract

The invention relates to a gallium nitride HJFET (High Junction Field Effect Transistor) device with a cascade structure and a preparation method of the gallium nitride HJFET device. A gallium nitride JFET device and a gallium nitride HEMT device are integrated in a monolithic mode, and a cascade structure is formed by a JFET drain electrode, a JFET grid electrode, a JFET source electrode, an HEMT drain electrode, an HEMT grid electrode and an HEMT source electrode through a special structural design mode. The gallium nitride HEMT device and the gallium nitride JFET device are in cascade connection, the HEMT device is used for controlling a switch, and the JFET device is used for bearing voltage. According to the structure, the advantages of the HEMT device and the JFET device are fully utilized, the normally-off mode is achieved, meanwhile, the high switching speed and the high output and pressure bearing capacity of the device are guaranteed, the device can be applied to a high-speed, high-voltage and high-power-density power electronic system, and the reliability of the device is improved. And the huge potential of breaking through the physical limit of the traditional power device by the gallium nitride power device is shown.

Description

Technical Field

[0001] The invention relates to a gallium nitride HJFET device with a cascode structure and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] Power semiconductor transistors are the core of power electronic systems and are widely used in many fields such as consumer electronics, rail transportation, photovoltaic power generation and industrial control. They undertake many functions such as frequency conversion, rectification, voltage conversion, power amplification and power management. Compared with the first-generation semiconductor silicon (Si), the third-generation semiconductor gallium nitride (GaN) has attracted much attention due to its advantages such as larger bandgap width, higher critical breakdown field strength and faster saturation drift speed. Therefore, GaN-based power transistors can break through the development bottleneck of traditional Si-based power transistors and further meet the needs of the next generation of power electronic systems.

[0003] Thanks to the high-mobility two-dimensional electron gas (2DEG) at the AlGaN / GaN interface, horizontal power devices based on the AlGaN / GaN heterostructure have achieved excellent performance, and GaN-based lateral high electron mobility transistors (HEMTs) on Si substrates with an operating voltage of 650V have been successfully commercialized. However, for applications in high-voltage and high-current scenarios, the vertical configuration is still the best choice. For horizontal power transistors, if higher voltage levels are to be achieved, a larger source-drain spacing is required, which will increase the size of the chip and lead to higher product costs. At the same time, the parasitic elements and pins of horizontal power transistors are proportional to the distance from the gate to the drain. The realization of high-voltage devices by increasing the source-drain spacing will increase parasitic effects and degrade the switching speed of the device.

[0004] Compared with GaN-based horizontal power transistors, GaN vertical power transistors can achieve higher breakdown voltage by increasing the thickness of the drift region without increasing the chip package size. In addition, the source and drain of the GaN vertical power transistor are located on both sides of the wafer, which helps to achieve uniform current distribution and higher current levels. At present, vertical GaN power transistors mainly include trench MOSFETs (T-MOSFETs), current hole vertical electron transistors (CAVETs), fin power field effect transistors (FinFETs) and junction FETs (JFETs). Compared with other major vertical GaN power transistors, JFETs do not require a gate oxide layer, the structure is relatively simple, and because it has an intrinsic PN junction, JFETs have more excellent robust characteristics. However, the ideal state of vertical power transistors is usually normally-off mode, because normally-off devices can achieve lower power consumption and higher system reliability. Currently, commercially available JFETs are mainly normally-on mode. This is because a narrower fin channel is required to achieve the normally-off mode, which limits the output capacity of the device and requires a more stringent process.

[0005] At present, GaN JFETs have good pressure-bearing ability, but they are limited by the fact that the device cannot achieve normally-off mode while ensuring strong output capacity; while GaN P-gate HEMTs have high switching speed and can achieve normally-off mode, their disadvantage is that they cannot withstand pressure well. If the two are cascoded, the advantages of both can be fully utilized, using JFETs to block high voltage and HEMTs for switch control, which can achieve normally-off mode while achieving higher breakdown voltage, and have higher switching speed and output capacity. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a gallium nitride HJFET device with a cascode structure and a method for preparing the same.

[0007] The technical solution of the present invention is as follows:

[0008] A gallium nitride HJFET device with a cascode structure is provided on the basis of a gallium nitride JFET device, wherein a HEMT drain, a HEMT gate and a HEMT source are arranged, and the JFET drain, the JFET gate, the JFET source and the HEMT drain, the HEMT gate and the HEMT source form a cascode structure.

[0009] Preferably according to the present invention, the gallium nitride JFET device comprises, from bottom to top, a substrate, an n-GaN drift layer, a first p-GaN layer, an n-GaN layer, a UID-GaN layer and an AlGaN layer; a JFET drain metal layer is provided under the substrate.

[0010] Further preferably, two grooves are arranged above the n-GaN layer, and the grooves are n-GaN layers from bottom to top. + -GaN layer and JEET source metal layer.

[0011] Further preferably, the area of ​​the AlGaN layer is smaller than that of the UID-GaN layer, an electrical isolation layer is disposed behind the AlGaN layer, and a JFET gate metal layer is disposed behind the electrical isolation layer.

[0012] Preferably according to the present invention, the HEMT drain metal layer is located above the AlGaN layer and is connected to the JEET source metal layer.

[0013] Preferably according to the present invention, the HEMT gate metal layer is located inside the HEMT drain metal layer and above the AlGaN layer, and a second p-GaN layer is between the HEMT gate metal layer and the AlGaN layer.

[0014] Preferably according to the present invention, the HEMT source metal layer is located in the center of the two HEMT drain metal layers and above the AlGaN layer.

[0015] Preferably, according to the present invention, in the cascode structure, the HEMT drain metal layer is connected to the JFET source metal layer; the HEMT source metal layer is connected to the JFET gate metal layer.

[0016] The method for preparing the gallium nitride HJFET device having a cascode structure comprises the following steps:

[0017] (a) Through the MOCVD method, + -Growing an n-GaN drift layer on the GaN substrate;

[0018] (b) forming a first p-GaN layer on both sides of the n-GaN drift layer by an ion implantation method;

[0019] (c) growing an n-GaN layer on the n-GaN drift layer and the first p-GaN layer by MOCVD method. The thickness of the n-GaN layer is smaller than that of the n-GaN drift layer and serves as a current channel between the JFET and the HEMT.

[0020] (d) By ion implantation, n-GaN layers are formed on both sides of the growing n-GaN layer. +-GaN layer, and then continue to form the first p-GaN layer behind the n-GaN layer, so that the first p-GaN layer presents a step shape. + -GaN layer is used for effective connection between HEMT source and JFET gate;

[0021] (e) The MOCVD method is used to deposit the n-GaN layer and the n + -The UID-GaN layer continues to grow on the GaN layer;

[0022] (f) growing an AlGaN layer on the UID-GaN layer by MOCVD;

[0023] (g) growing a second p-GaN layer on the AlGaN layer by an MOCVD method;

[0024] (h) etching away the two sides and the central portion of the second p-GaN layer using a photoresist mask etching method, thereby forming two rectangular regions in the center above the AlGaN layer;

[0025] (i) etching a groove behind the AlGaN layer using a photoresist mask etching method, wherein the groove depth is equal to the thickness of the AlGaN layer;

[0026] (j) growing an electrical isolation layer in the groove obtained in step (i) by a PECVD method;

[0027] (k) etching a hole in the UID-GaN layer and the AlGaN layer to connect the JFET source metal layer and the JFET gate metal layer using a photoresist mask etching method;

[0028] (l) forming a JFET source metal layer and a HEMT drain metal layer with ohmic contacts in the hole of step (k) by electron beam evaporation, forming a HEMT gate metal layer above the two rectangular regions in step (h), forming a HEMT source metal layer in the center of the two rectangular regions in step (h), forming a JFET gate metal layer on the back of the first p-GaN layer, and forming a HEMT gate metal layer on the n-type p-GaN layer. + A JFET drain metal layer is formed under the -GaN substrate to obtain a gallium nitride HJFET device with a cascode structure.

[0029] Any details not provided in the present invention may be referred to the prior art.

[0030] The technical features of the present invention are as follows:

[0031] In the present invention, the JFET source is connected to the HEMT drain, and the HEMT source is connected to the JFET gate, which is used to control the conduction state of the JFET. Specifically, the HEMT gate receives the input signal; the output signal is drawn from the HEMT source. When the HEMT is turned on, the HEMT drain voltage (that is, the JFET source voltage) is close to the ground potential, the JFET device is in the on state, and the entire current flows from the JFET drain to the HEMT source. During the shutdown process of the HEMT device, the source voltage of the JFET (determined by the HEMT drain voltage) begins to increase. At this time, the JFET gate voltage usually remains unchanged (connected to a fixed reference voltage or ground). As the HEMT source voltage increases, the JFET gate-source voltage gradually becomes negative. When the V GS When it becomes negative to a certain extent, the conductive channel of the JFET device begins to narrow, causing it to gradually turn off.

[0032] The beneficial effects of the present invention are as follows:

[0033] 1. The present invention cascodes the GaN HEMT device and the GaN JFET device, uses the HEMT device to control the switch, and uses the JFET device to withstand the pressure. This structure fully utilizes the advantages of the HEMT device and the JFET device, realizes the normally off mode, and ensures the faster switching speed of the device and stronger output and pressure-bearing capacity.

[0034] 2. The present invention integrates HEMT devices and JFET devices monolithically into the same substrate through reasonable design, greatly reducing the package volume and external metal interconnection, avoiding additional parasitic effects, and enhancing the stability of the device; at the same time, HEMT devices and JFET devices are selected from the same material system, avoiding thermal mismatch and lattice mismatch, and no nucleation layer is required, which improves the quality of the crystal and ensures the reliability and yield of the device. The gallium nitride HJFET device can be used in high-speed, high-voltage and high-power density power electronic systems, showing the great potential of gallium nitride power devices to break through the physical limits of traditional power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic structural diagram of a gallium nitride HJFET device with a cascode structure according to the present invention;

[0036] In the figure, 1, JFET drain metal layer; 2, n + -GaN substrate; 3. n-GaN drift layer; 4. first p-GaN layer; 5. n-GaN layer; 6. n +-GaN layer; 7, JEET source metal layer; 8, UID-GaN layer; 9, AlGaN layer; 10, second p-GaN layer; 11, HEMT drain metal layer; 12, HEMT gate metal layer; 13, HEMT source metal layer; 14, electrical isolation layer; 15, JFET gate metal layer.

[0037] Figure 2 It is the equivalent circuit diagram of cascode structure;

[0038] In the figure, D of JFET corresponds to JFET drain metal layer 1, G of JFET corresponds to JFET gate metal layer 15, and S of JFET corresponds to JFET source metal layer 7; D of HEMT corresponds to HEMT drain metal layer 11, G of HEMT corresponds to HEMT gate metal layer 12, and S of HEMT corresponds to HEMT source metal layer 13.

[0039] Figure 3 Flow chart of steps (a) to (d) of the preparation method of the present invention;

[0040] Among them, the left picture in Figure d is a front view, and the right picture is a side view.

[0041] Figure 4 The present invention is a flow chart of steps (e) to (h) of the preparation method.

[0042] Figure 5 is a flow chart of steps (i) to (j) of the preparation method of the present invention;

[0043] Among them, the left picture in Figure i and Figure j is a front view, and the right picture is a side view.

[0044] Figure 6 Flow chart of steps (k) to (l) of the preparation method of the present invention;

[0045] Among them, the left picture in Figure k and Figure l is a front view, and the right picture is a side view. DETAILED DESCRIPTION

[0046] The present invention is further described below in conjunction with embodiments and drawings.

[0047] Unless otherwise specified, the raw materials used in the examples are conventional raw materials and are commercially available; the methods used are all existing methods unless otherwise specified.

[0048] Example 1

[0049] like Figures 1-2As shown, a gallium nitride HJFET device with a cascode structure is a gallium nitride JFET device, which is provided with a HEMT drain, a HEMT gate and a HEMT source, and the JFET drain, the JFET gate, the JFET source and the HEMT drain, the HEMT gate and the HEMT source form a cascode structure.

[0050] Specifically, the gallium nitride JFET device includes n + -GaN substrate 2, n-GaN drift layer 3, first p-GaN layer 4, n-GaN layer 5, UID-GaN layer 8 and AlGaN layer 9; the n + A JFET drain metal layer 1 is arranged below the n-GaN substrate 2; two grooves are arranged above the n-GaN layer 5, and the grooves are n- + -GaN layer 6 and JEET source metal layer 7;

[0051] The AlGaN layer 9 has a smaller area than the UID-GaN layer 8. An electrical isolation layer 14 is disposed behind the AlGaN layer 9, and a JFET gate metal layer 15 is disposed behind the electrical isolation layer 14. The HEMT drain metal layer 11 is located above the AlGaN layer 9 and connected to the JFET source metal layer 7. The HEMT gate metal layer 12 is located inside the HEMT drain metal layer 11 and above the AlGaN layer 9. A second p-GaN layer 10 is disposed between the HEMT gate metal layer 12 and the AlGaN layer 9. The HEMT source metal layer 13 is located in the center of the two HEMT drain metal layers 11 and above the AlGaN layer 9.

[0052] In the cascode structure, the HEMT drain metal layer 11 is connected to the JFET source metal layer 7 ; the HEMT source metal layer 13 is connected to the JFET gate metal layer 15 .

[0053] Example 2

[0054] like Figures 3 to 6 As shown, the method for preparing the gallium nitride HJFET device with a cascode structure described in Example 1 includes the following steps:

[0055] (a) Through the MOCVD method, + -Growing an n-GaN drift layer 3 on the GaN substrate 2;

[0056] (b) forming a first p-GaN layer 4 on both sides of the n-GaN drift layer 3 by an ion implantation method;

[0057] (c) growing an n-GaN layer 5 on the n-GaN drift layer 3 and the first p-GaN layer 4 by MOCVD method. The n-GaN layer 5 has a thickness less than that of the n-GaN drift layer 3 and serves as a current channel between the JFET and the HEMT.

[0058] (d) By ion implantation, n-GaN layers are formed on both sides of the growing n-GaN layer 5. + -GaN layer 6, and continue to form the first p-GaN layer 4 behind the n-GaN layer 5, so that the first p-GaN layer 4 presents a step shape. + -GaN layer 6 is used for effective connection between the HEMT source and the JFET gate;

[0059] (e) The n-GaN layer 5 and the n-GaN layer 6 are deposited by MOCVD. + -The UID-GaN layer 8 continues to grow on the GaN layer 6;

[0060] (f) Continue to grow an AlGaN layer 9 on the UID-GaN layer 8 by MOCVD method;

[0061] (g) growing a second p-GaN layer 10 on the AlGaN layer 9 by MOCVD method;

[0062] (h) etching away the two sides and the central part of the second p-GaN layer 10 by using a photoresist mask etching method, forming two rectangular areas in the center of the AlGaN layer 9;

[0063] (i) etching a groove behind the AlGaN layer 9 using a photoresist mask etching method, wherein the groove depth is equal to the thickness of the AlGaN layer 9;

[0064] (j) growing an electrical isolation layer 14 in the groove obtained in step (i) by a PECVD method;

[0065] (k) etching a hole connecting the JFET source metal layer and the JFET gate metal layer in the UID-GaN layer 8 and the AlGaN layer 9 by using a photoresist mask etching method;

[0066] (l) forming a JFET source metal layer 7 and a HEMT drain metal layer 11 with ohmic contacts in the hole of step (k) by electron beam evaporation, forming a HEMT gate metal layer 12 above the two rectangular regions in step (h), forming a HEMT source metal layer 13 in the center of the two rectangular regions in step (h), forming a JFET gate metal layer 15 on the back of the first p-GaN layer, and forming a HEMT gate metal layer 16 on the back of the first p-GaN layer. + A JFET drain metal layer 1 is formed under the -GaN substrate to obtain a gallium nitride HJFET device with a cascode structure.

[0067] The above-described embodiments are only preferred specific implementation schemes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A gallium nitride HJFET device with a cascode structure, characterized in that: A HEMT drain, a HEMT gate and a HEMT source are arranged on the basis of a gallium nitride JFET device, and the JFET drain, the JFET gate, the JFET source and the HEMT drain, the HEMT gate and the HEMT source form a cascode structure.

2. The gallium nitride HJFET device with a cascode structure according to claim 1, characterized in that: The gallium nitride JFET device comprises, from bottom to top, a substrate, an n-GaN drift layer, a first p-GaN layer, an n-GaN layer, a UID-GaN layer and an AlGaN layer; a JFET drain metal layer is arranged under the substrate.

3. The gallium nitride HJFET device with a cascode structure according to claim 2, characterized in that: Two grooves are arranged above the n-GaN layer, and the grooves are n-GaN layers from bottom to top. + -GaN layer and JEET source metal layer.

4. The gallium nitride HJFET device with a cascode structure according to claim 2, characterized in that: The area of ​​the AlGaN layer is smaller than that of the UID-GaN layer. An electrical isolation layer is arranged behind the AlGaN layer, and a JFET gate metal layer is arranged behind the electrical isolation layer.

5. The gallium nitride HJFET device with a cascode structure according to claim 2, characterized in that: The HEMT drain metal layer is located above the AlGaN layer and is connected to the JEET source metal layer.

6. The gallium nitride HJFET device with a cascode structure according to claim 2, characterized in that: The HEMT gate metal layer is located inside the HEMT drain metal layer and above the AlGaN layer, and a second p-GaN layer is located between the HEMT gate metal layer and the AlGaN layer.

7. The gallium nitride HJFET device with a cascode structure according to claim 2, characterized in that: The HEMT source metal layer is located in the center of the two HEMT drain metal layers and above the AlGaN layer.

8. The gallium nitride HJFET device with a cascode structure according to claim 2, characterized in that: In the cascode structure, the HEMT drain metal layer is connected to the JFET source metal layer; the HEMT source metal layer is connected to the JFET gate metal layer.

9. The method for preparing a gallium nitride HJFET device with a cascode structure according to claim 2, characterized in that: The steps include: (a) Through the MOCVD method, + -Growing an n-GaN drift layer on the GaN substrate; (b) forming a first p-GaN layer on both sides of the n-GaN drift layer by an ion implantation method; (c) growing an n-GaN layer on the n-GaN drift layer and the first p-GaN layer by MOCVD method. The thickness of the n-GaN layer is smaller than that of the n-GaN drift layer and serves as a current channel between the JFET and the HEMT. (d) By ion implantation, n-GaN layers are formed on both sides of the growing n-GaN layer. + -GaN layer, and then continue to form the first p-GaN layer behind the n-GaN layer, so that the first p-GaN layer presents a step shape. + -GaN layer is used for effective connection between HEMT source and JFET gate; (e) The MOCVD method is used to deposit the n-GaN layer and the n + -The UID-GaN layer continues to grow on the GaN layer; (f) growing an AlGaN layer on the UID-GaN layer by MOCVD; (g) growing a second p-GaN layer on the AlGaN layer by an MOCVD method; (h) etching away the two sides and the central portion of the second p-GaN layer using a photoresist mask etching method, thereby forming two rectangular regions in the center above the AlGaN layer; (i) etching a groove behind the AlGaN layer using a photoresist mask etching method, wherein the groove depth is equal to the thickness of the AlGaN layer; (j) growing an electrical isolation layer in the groove obtained in step (i) by a PECVD method; (k) etching a hole in the UID-GaN layer and the AlGaN layer to connect the JFET source metal layer and the JFET gate metal layer using a photoresist mask etching method; (l) forming a JFET source metal layer and a HEMT drain metal layer with ohmic contacts in the hole of step (k) by electron beam evaporation, forming a HEMT gate metal layer above the two rectangular regions in step (h), forming a HEMT source metal layer in the center of the two rectangular regions in step (h), forming a JFET gate metal layer on the back of the first p-GaN layer, and forming a HEMT gate metal layer on the n-type p-GaN layer. + A JFET drain metal layer is formed under the -GaN substrate to obtain a gallium nitride HJFET device with a cascode structure.

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