Semiconductor structure and forming method thereof
By designing the target graphics of interval arrangement on the substrate of the semiconductor structure, the problem of insufficient freedom of graphics in the prior art is solved, and higher flexibility and performance improvements are achieved, while saving structural area.
Patent Information
- Application Number
- CN202311534424.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-16
- Publication Date
- 2025-05-23
AI Technical Summary
After the existing semiconductor structures have reduced the graphic feature size, the degree of freedom and flexibility of the pattern are insufficient, making it difficult to meet the spacing requirements of semiconductor devices in different regions.
A semiconductor structure is designed, wherein the substrate is divided into a first region and a second region, the target patterns extend in the first direction and are spaced apart in the second direction, and the distance between adjacent first target patterns is smaller than the distance between adjacent second target patterns. The graphicization of the target pattern is achieved by forming a side wall layer on the side wall of the initial groove and removing the core layer, and forming a trench surrounded by the side wall layer and the target layer.
This structure can meet the requirements of different semiconductor devices for distances between adjacent devices, reduce parasitic capacitance, thereby improving the performance of semiconductor structures, and saving structural area under the conditions that meet the requirements.
Smart Images
Figure CN120035209A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.
[0003] Due to the continuous reduction of the critical dimension (CD), the self-aligned double patterning (SADP) process came into being. The density of the pattern formed on the substrate by the self-aligned double patterning method is twice that of the pattern formed on the substrate by the photolithography process, that is, 1 / 2 minimum pitch can be obtained, which can greatly improve the density of semiconductor integrated circuits, reduce the characteristic size of the pattern, and thus help improve the performance of the device.
[0004] Currently, the freedom and flexibility of patterning still need to be improved, making it a challenge to meet the requirements of semiconductor devices in different regions. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region; a target pattern located on the substrate, the target pattern comprising a first target pattern located in the first region, and a second target pattern located in the second region, the target patterns extending along a first direction and arranged at intervals along a second direction, and along the second direction, a distance between adjacent first target patterns is smaller than a distance between adjacent second target patterns.
[0007] Optionally, along the second direction, the width of the first region is smaller than the width of the second region.
[0008] Optionally, the semiconductor structure also includes: a dielectric layer located on the substrate; the target pattern is located in the dielectric layer, the first target pattern is a first interconnection groove, and the second target pattern is a second interconnection groove; the semiconductor structure also includes: a first interconnection layer located in the first interconnection groove; and a second interconnection layer located in the second interconnection groove.
[0009] Optionally, the dielectric layer is also located between adjacent first interconnection grooves in the first direction, and between adjacent second interconnection grooves in the first direction.
[0010] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, a target layer for forming a target pattern being formed on the substrate; forming a core layer on the target layer in the first region and the second region, the core layer having initial grooves extending along a first direction and arranged at intervals along a second direction, the initial grooves comprising a first initial groove located in the first region and a second initial groove located in the second region; forming a first spacer layer on the sidewalls of the initial grooves; removing the core layer; A second sidewall layer is formed on the sidewall of the sidewall layer, the second sidewall layer and the first sidewall layer constitute the sidewall layer, and a groove surrounded by the sidewall layer and the target layer is formed, the groove includes a first groove located in the first area, and a second groove located in the second area, and along the second direction, the distance between adjacent first grooves is smaller than the distance between adjacent second grooves; using the sidewall layer as a mask, the target layer is patterned along the first groove to form a first target pattern, and the target layer is patterned along the second groove to form a second target pattern, and the first target pattern and the second target pattern constitute a target pattern.
[0011] Optionally, in the step of forming the core layer, along the second direction, the width of the first initial groove is smaller than the width of the second initial groove.
[0012] Optionally, the step of forming the first spacer layer includes: forming a first spacer material layer on the sidewall and bottom of the initial groove and the core layer outside the initial groove; removing the first spacer material layer above the top of the core layer to expose the top of the core layer, and the remaining first spacer material layer serves as the first spacer layer.
[0013] Optionally, in the step of forming a first side wall material layer, the first side wall material layer forms a first groove; the step of forming the first side wall layer also includes: after forming the first side wall material layer, before removing the first side wall material layer above the top of the core layer, forming a sacrificial layer in the first groove; after forming the first side wall layer, the formation method also includes: removing the sacrificial layer.
[0014] Optionally, in the step of forming the sacrificial layer, the material of the sacrificial layer includes a high molecular organic polymer.
[0015] Optionally, in the step of removing the core layer, a gap is formed between adjacent first side wall layers at the position of the core layer; the step of forming a second side wall layer on the first side wall layer of the second initial groove includes: forming a filling layer on the side wall of the first side wall layer in the first initial groove and in the gap, the filling layer filling the remaining space in the first initial groove and the gap; under the filling action of the filling layer, a second side wall material layer is formed on the top of the filling layer and the top and side wall of the first side wall layer; the second side wall material layer on the top of the filling layer and the top of the first side wall layer is removed, and the remaining second side wall material layer is used as the second side wall layer; after forming the second side wall layer and before forming the groove, the formation method also includes: removing the filling layer to form the groove.
[0016] Optionally, the step of forming the filling layer includes: forming a filling material layer on the side walls of the first spacer layer in the first initial groove, the side walls and bottom of the first spacer layer in the second initial groove, the top of the first spacer layer outside the initial groove, and in the gap; removing the filling material layer above the top of the first spacer layer and the side walls and bottom of the first spacer layer in the second initial groove, and retaining the filling material layer on the side walls of the first spacer layer in the first initial groove and in the gap as the filling layer.
[0017] Optionally, the process of forming the filling material layer includes one or both of a chemical vapor deposition process and a physical vapor deposition process.
[0018] Optionally, in the step of forming the filling material layer, the material of the filling material layer includes silicon oxide.
[0019] Optionally, the process of removing the filling layer includes an isotropic etching process.
[0020] Optionally, the isotropic etching process includes an isotropic wet etching process, and the process parameters of the wet etching process include: the etching solution is a phosphoric acid solution, a hydrofluoric acid solution, an ammonia solution, a potassium hydroxide solution or a tetramethylammonium hydroxide solution; wherein the volume percent concentration of the phosphoric acid solution is 1:10 to 1:1, the volume percent concentration of the hydrofluoric acid solution is 1:1000 to 1:100, the volume percent concentration of the ammonia solution is 1:100 to 1:1, the volume percent concentration of the potassium hydroxide solution is 1:100 to 1:10, the volume percent concentration of the tetramethylammonium hydroxide solution is 1:1000 to 1:100, and the process temperature is room temperature.
[0021] Optionally, the process of forming the second spacer material layer includes one or both of a chemical vapor deposition process and a physical vapor deposition process.
[0022] Optionally, after forming the core layer and before forming the first sidewall layer, the formation method further includes: in the first region and the second region, along the first direction, removing the core layer of the first partial region between adjacent initial grooves to form a second groove, wherein the second groove divides the core layer in the first direction; in the step of forming the first sidewall layer, the first sidewall layer is also formed in the second groove; in the step of forming the groove, the first sidewall layer located in the second groove divides the groove across the first partial region along the first direction.
[0023] Optionally, after forming the second sidewall layer and before forming the groove, the formation method further includes: in the first region and the second region, along the first direction, forming a first barrier layer in the remaining space of the initial groove in the second partial region; in the step of forming the groove, along the first direction, the first barrier layer divides the groove across the second partial region.
[0024] Optionally, in the step of providing the substrate, the target layer is a dielectric layer; in the step of forming the target pattern, the dielectric layer is patterned, the first target pattern is a first interconnection groove, and the second target pattern is a second interconnection groove; after forming the first target pattern and the second target pattern, the forming method further includes: forming a filling conductive material in the first interconnection groove and the second interconnection groove, forming a first interconnection layer located in the first interconnection groove, and a second interconnection layer located in the second interconnection groove.
[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0026] The semiconductor structure provided by the embodiment of the present invention includes a target pattern located on the substrate, the target pattern includes a first target pattern located in the first area, and a second target pattern located in the second area, the target pattern extends along the first direction and is arranged at intervals along the second direction, and along the second direction, the distance between adjacent first target patterns is smaller than the distance between adjacent second target patterns. The distance between adjacent first target patterns is smaller than the distance between adjacent second target patterns, which can meet the requirements of semiconductor devices in different areas for the distance between adjacent devices, thereby meeting the requirements of different semiconductor devices for parasitic capacitance, and thus is conducive to improving the performance of the semiconductor structure.
[0027] In an optional solution, along the second direction, the width of the first region is smaller than the width of the second region, thereby saving the area of the first region and further saving the area of the semiconductor structure while meeting the requirements of different semiconductor devices for the distance between adjacent devices.
[0028] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a core layer is formed on a target layer in the first region and the second region, and initial grooves extending along the first direction and arranged at intervals along the second direction are formed in the core layer, and the initial grooves include a first initial groove located in the first region and a second initial groove located in the second region, a first sidewall layer is formed on the sidewall of the initial groove, a second sidewall layer is formed on the sidewall of the first sidewall layer located in the second initial groove, and a groove surrounded by the sidewall layer and the target layer is formed, the grooves include a first groove located in the first region and a second groove located in the second region, and along the second direction, the distance between adjacent first grooves is less than the distance between adjacent second grooves, the target layer is patterned along the first groove to form a first target pattern, and the target layer is patterned along the second groove to form a second target pattern. Since the distance between adjacent first grooves is smaller than the distance between adjacent second grooves, and the first target pattern is formed by patterning the target layer along the first grooves, and the second target pattern is formed by patterning the target layer along the second grooves, the distance between adjacent first target patterns is smaller than the distance between adjacent second target patterns, which can meet the requirements of different semiconductor devices for the distance between adjacent devices, thereby meeting the requirements of different semiconductor devices for parasitic capacitance, and is beneficial to improving the performance of the semiconductor structure.
[0029] In an optional scheme, the initial groove includes a first initial groove located in the first area and a second initial groove located in the second area. Along the second direction, the width of the first initial groove is smaller than the width of the second initial groove, so that in the second direction, the width of the first area is smaller than the width of the second area. This saves the area of the first area while meeting the requirements of different semiconductor devices for the distance between adjacent devices, thereby saving the area of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 is a top view of an embodiment of a semiconductor structure of the present invention;
[0031] Figure 2 yes Figure 3 Sectional view along AA1;
[0032] Figures 3 to 32 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0033] At present, since the density of the target pattern to be formed on the substrate is greater than the density of the target pattern formed on the substrate using the photolithography process, the target patterns are mostly combined with a minimum pitch as a cell. It is understandable that the target patterns formed on the substrate all have the same spacing, resulting in low freedom and flexibility in patterning, making it difficult to meet the spacing requirements of semiconductor devices in different regions.
[0034] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region; a target pattern located on the substrate, the target pattern including a first target pattern located in the first region, and a second target pattern located in the second region, the target patterns extending along a first direction and arranged at intervals along a second direction, and along the second direction, a distance between adjacent first target patterns is smaller than a distance between adjacent second target patterns.
[0035] The semiconductor structure provided by the embodiment of the present invention includes a target pattern located on the substrate, the target pattern includes a first target pattern located in the first area, and a second target pattern located in the second area, the target pattern extends along the first direction and is arranged at intervals along the second direction, and along the second direction, the distance between adjacent first target patterns is smaller than the distance between adjacent second target patterns. The distance between adjacent first target patterns is smaller than the distance between adjacent second target patterns, which can meet the requirements of semiconductor devices in different areas for the distance between adjacent devices, thereby meeting the requirements of different semiconductor devices for parasitic capacitance, and thus is conducive to improving the performance of the semiconductor structure.
[0036] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0037] Figure 1 is a top view of an embodiment of a semiconductor structure of the present invention; Figure 2 yes Figure 1 Cross-sectional view along AA1.
[0038] refer to Figure 1 to Figure 2 In this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 includes a first region i and a second region ii; a target pattern 160, located on the substrate 100, the target pattern 160 includes a first target pattern 161 located in the first region i, and a second target pattern 162 located in the second region ii, the target pattern 160 extends along the first direction y and is arranged at intervals along the second direction, and along the second direction x, the distance w1 between adjacent first target patterns 161 is less than the distance w2 between adjacent second target patterns 162.
[0039] The substrate 100 is used to provide a process platform for forming a semiconductor structure.
[0040] The distance w1 between adjacent first target patterns 161 is smaller than the distance w2 between adjacent second target patterns 162, which can meet the requirements of semiconductor devices in different regions for the distance between adjacent devices, thereby meeting the requirements of different semiconductor devices for parasitic capacitance, thereby facilitating improving the performance of the semiconductor structure.
[0041] In this embodiment, along the second direction x, the width of the first region i is smaller than the width of the second region ii.
[0042] Along the second direction y, the width of the first region i is smaller than the width of the second region ii, thereby saving the area of the first region i and further saving the area of the semiconductor structure while meeting the requirements of different semiconductor devices for the distance between adjacent devices.
[0043] In this embodiment, the semiconductor structure further includes: a dielectric layer 101, located on the substrate 100; a target pattern 160 located in the dielectric layer 101, the first target pattern 161 is a first interconnection groove, and the second target pattern 162 is a second interconnection groove. The semiconductor structure further includes: a first interconnection layer (not shown) located in the first interconnection groove; and a second interconnection layer (not shown) located in the second interconnection groove.
[0044] It can be understood that the first interconnect layer and the second interconnect layer constitute an interconnect layer.
[0045] The dielectric layer 101 is accordingly used to achieve isolation between adjacent interconnection layers.
[0046] Accordingly, the material of the dielectric layer is an insulating dielectric material, including one or more of a low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant less than 2.6), silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the dielectric layer is a low-k dielectric material.
[0047] The first interconnect layer and the second interconnect layer are used to realize electrical connection between devices or between different components in a device to meet circuit design requirements.
[0048] Specifically, the first interconnection layer and the second interconnection layer are made of the same material. Both the first interconnection layer and the second interconnection layer are made of conductive materials, such as copper, cobalt, and the like.
[0049] Correspondingly, in this embodiment, various semiconductor devices, such as MOS transistors, may be formed in the substrate 100 .
[0050] In other embodiments, based on actual process requirements, the target layer may also be other film layers, and the target pattern may also be other types.
[0051] In this embodiment, the dielectric layer 101 is also located between adjacent first interconnection grooves in the first direction y, and between adjacent second interconnection grooves in the first direction y.
[0052] The dielectric layer 101 is also located between adjacent first interconnection grooves in the first direction y, and between adjacent second interconnection grooves in the first direction y, so that the lengths of the first interconnection grooves and the second interconnection grooves can be adjusted in the first direction y, so that the lengths of the first interconnection grooves and the second interconnection grooves meet the design requirements, and thus the target pattern meets the design requirements.
[0053] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 32 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0054] refer to Figure 3 and Figure 4 , providing a substrate 500, the substrate 500 includes a first region I and a second region II, and a target layer 501 for forming a target pattern is formed on the substrate 500.
[0055] in, Figure 3 is a top view, Figure 4 for Figure 3 Cross-sectional view along AA1.
[0056] The substrate 500 is used to provide a platform for subsequent process steps.
[0057] The target layer 501 is a film layer to be patterned to form a target pattern. The target layer 501 in the first region I is used to provide a process basis for the subsequent formation of the first target pattern, and the target layer 501 in the second region II is used to provide a process basis for the subsequent formation of the second target pattern.
[0058] In this embodiment, in the step of providing the substrate 500 , the target layer 501 is a dielectric layer.
[0059] Specifically, after the dielectric layer is subsequently patterned to form the first interconnection trench and the second interconnection trench, a filling conductive material is formed in the first interconnection trench and the second interconnection trench, and the dielectric layer is correspondingly used to achieve isolation between adjacent conductive materials.
[0060] Accordingly, the material of the dielectric layer is an insulating dielectric material, including one or more of a low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant less than 2.6), silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the dielectric layer is a low-k dielectric material.
[0061] Correspondingly, in this embodiment, various semiconductor devices, such as MOS transistors, may be formed in the substrate 500 .
[0062] In other embodiments, based on actual process requirements, the target layer may also be other film layers, and the target pattern may also be other types.
[0063] In this embodiment, in the step of providing the substrate 500 , a hard mask layer 502 is formed on the target layer 501 .
[0064] The hard mask layer 502 is used as an initial stop position during the process of patterning the target layer 501 , thereby reducing the difficulty of patterning the target layer 501 and improving the uniformity of the depth of the target pattern.
[0065] Specifically, the material of the hard mask layer 502 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium nitride and titanium oxide.
[0066] refer to Figures 5 and 6 , and continue to refer to Figure 3 to Figure 4 A core layer 510 is formed on the target layer 501 in the first region I and the second region II, and initial grooves 600 extending along the first direction Y and arranged at intervals along the second direction X are formed in the core layer 510, and the initial grooves 600 include a first initial groove 601 located in the first region I and a second initial groove 602 located in the second region II.
[0067] in, Figure 5 is a top view, Figure 6 for Figure 5 Cross-sectional view along AA1.
[0068] The core layer 510 is used to provide support for the subsequent formation of the first sidewall layer.
[0069] The core layer 510 will be removed later, so the core layer 510 is a material that is easy to remove. In this embodiment, the material of the core layer 510 includes one or more of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. As an example, the material of the core layer 510 is amorphous silicon or amorphous carbon.
[0070] In this embodiment, in the step of forming the core layer 510 , along the second direction X, the width of the first preliminary trench 601 is smaller than the width of the second preliminary trench 602 .
[0071] The initial trench 600 includes a first initial trench 601 located in the first region I and a second initial trench 602 located in the second region II. Along the second direction X, the width of the first initial trench 601 is smaller than the width of the second initial trench 602. Accordingly, in the second direction X, the width of the first region I is smaller than the width of the second region II, thereby saving the area of the first region I and further saving the area of the semiconductor structure.
[0072] like Figures 5 and 6 As shown, in this embodiment, after forming the core layer 510 and before forming the first sidewall layer, the formation method also includes: in the first region I and the second region II, along the first direction Y, removing the core layer 510 in the first partial region between adjacent initial grooves 600 to form a second groove 604, and the second groove 604 divides the core layer 510 in the first direction Y.
[0073] In the subsequent step of forming the first sidewall layer, the first sidewall layer is also formed in the second groove 604, so that in the subsequent step of forming the groove, the first sidewall layer located in the second groove 604 divides the groove across the first partial area along the first direction Y, that is, the first sidewall layer located in the second groove 604 acts as a second barrier layer, cutting the groove across the first partial area, so that the length of the groove can be adjusted in the first direction Y, so that the length of the groove meets the design requirements, and further the target pattern of the first partial area meets the design requirements.
[0074] refer to Figure 7 and Fig.12 , a first spacer layer 520 is formed on the sidewall of the initial trench 600 .
[0075] in, Figure 7 is a top view, Figure 8 for Figure 7 Cross-sectional view along AA1, Fig. 9 is a top view, Fig.10 for Fig. 9 Cross-sectional view along AA1, Fig.11 is a top view, Fig.12 for Fig.11 Cross-sectional view along AA1.
[0076] The first spacer layer 520 and the subsequently formed second spacer layer constitute a spacer layer, and together serve as a mask for patterning the target layer. In addition, the first spacer layer 520 is also used to provide support for the subsequently formed second spacer layer.
[0077] Since the core layer 510 will be removed later, the first spacer layer 520 is selected from a material having an etching selectivity with the core layer 510. In this embodiment, the material of the first spacer layer 520 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon, aluminum oxide, titanium nitride and titanium oxide. As an example, the material of the first spacer layer 520 includes titanium oxide.
[0078] In this embodiment, the steps of forming the first spacer layer 520 include: Figures 7 and 8 As shown, a first spacer material layer 521 is formed on the sidewall and bottom of the initial trench 600 and the core layer 510 outside the initial trench 600; Figure 11 to Figure 12 As shown, the first spacer material layer 521 above the top of the core layer 510 is removed to expose the top of the core layer 510 , and the remaining first spacer material layer 521 serves as the first spacer layer 520 .
[0079] First, a first spacer material layer 521 is formed on the sidewall and bottom of the initial groove 600 and the core layer 510 outside the initial groove 600, and then the first spacer material layer 521 above the top of the core layer 510 is removed to expose the top of the core layer 510, which helps to reduce the difficulty of forming the first spacer layer 520. In addition, exposing the top of the core layer 510 also facilitates the subsequent removal of the core layer 510 through the top of the core layer 510.
[0080] Specifically, in the step of forming the first spacer material layer 521, the first spacer material layer 521 surrounds the first groove 603; the step of forming the first spacer layer 520 also includes: after forming the first spacer material layer 521, before removing the first spacer material layer 521 above the top of the core layer 510, forming a sacrificial layer 530 (such as Figures 9 and 10 After forming the first spacer layer 520, the forming method further includes: removing the sacrificial layer 530 (as shown in Figure 11 to Figure 12 shown).
[0081] A first sidewall material layer 521 is formed at the bottom of the initial groove 600, and a sacrificial layer 530 is formed in the first groove 603, so that in the process of removing the first sidewall material layer 521 on the top of the core layer 510, the first sidewall material layer 521 at the bottom of the initial groove 600 can be retained, that is, the first sidewall layer 520 is also formed at the bottom of the initial groove 600, so that the first sidewall layer 520 at the bottom of the initial groove 600 can support the first sidewall layer 520 on the side wall of the initial groove 600, thereby reducing the probability of collapse of the first sidewall layer 520 in subsequent processes.
[0082] More specifically, in the step of forming the sacrificial layer 530, the material of the sacrificial layer 530 includes a high molecular organic polymer. Accordingly, the process of removing the sacrificial layer 530 includes a wet treatment process. In other embodiments, a suitable removal process can also be selected according to the material of the sacrificial layer.
[0083] After forming the first spacer layer 520 , the sacrificial layer 530 is removed. The material of the sacrificial layer 530 includes a high molecular organic polymer, which reduces the probability of other film layers (eg, the first spacer layer 520 ) being damaged during the removal of the sacrificial layer 530 .
[0084] It should be noted that the process of removing the first spacer material layer 521 above the top of the core layer 510 to expose the top of the core layer 510 includes an anisotropic etching process. As an example, the anisotropic etching process is an anisotropic dry etching process.
[0085] In this embodiment, in the first region I and the second region II, the core layer 510 of the first partial region I between adjacent initial grooves 600 is removed along the first direction Y to form a second groove 604, which divides the core layer 510 in the first direction Y; accordingly, in the step of forming the first sidewall layer 520, the first sidewall layer 520 is also formed in the second groove 604.
[0086] refer to Figure 13 to Figure 14 , remove the core layer 510.
[0087] in, Fig.13 is a top view, Fig.14 for Fig.13 Cross-sectional view along AA1.
[0088] The core layer 510 is removed to expose the entire sidewall of the first spacer layer 520 , so that the target layer 501 can be patterned using the first spacer layer 520 as a mask to form a target pattern.
[0089] An initial groove 600 is formed in the core layer 510 , and a first spacer layer 520 is formed on the sidewall of the initial groove 600 ; accordingly, in this embodiment, in the step of removing the core layer 510 , a gap 605 is formed between adjacent first spacer layers 520 at the position of the core layer 510 .
[0090] In this embodiment, in the step of removing the core layer 510, a wet etching process is used to remove the core layer 510, and the etching selectivity ratio of the core layer 510 to the first spacer layer 520 is greater than 10. In other embodiments, other processes that are easy to achieve a larger etching selectivity ratio may also be used.
[0091] refer to Figures 15 to 26A second spacer layer 522 is formed on the side wall of the first spacer layer 520 located in the second initial groove 602. The second spacer layer 522 and the first spacer layer 520 constitute a spacer layer 525, and a groove 608 surrounded by the spacer layer 525 and the target layer 501 is formed. The groove 608 includes a first groove 606 located in the first area I, and a second groove 607 located in the second area II. Along the second direction X, the distance W1 between adjacent first grooves 606 is less than the distance W2 between adjacent second grooves 607.
[0092] in, Fig.15 is a top view, Fig.16 for Fig.15 Cross-sectional view along AA1, Fig.17 is a top view, Fig.18 for Fig.17 Cross-sectional view along AA1, Fig.19 is a top view, Fig. 20 for Fig.19 Cross-sectional view along AA1, Fig.21 is a top view, Fig. 22 for Fig.21 Cross-sectional view along AA1, Fig.23 is a top view, Fig.24 for Fig.23 Cross-sectional view along AA1, Fig.25 is a top view, Fig.26 for Fig.25 Cross-sectional view along AA1.
[0093] Since the distance W1 between adjacent first grooves 606 is smaller than the distance W2 between adjacent second grooves 607, the subsequent first target pattern is formed by patterning the target layer 501 along the first grooves 606, and the second target pattern is formed by patterning the target layer 501 along the second grooves 607. Therefore, the distance between adjacent first target patterns formed subsequently is smaller than the distance between adjacent second target patterns, which can meet the requirements of different semiconductor devices for the distance between adjacent devices, thereby meeting the requirements of different semiconductor devices for parasitic capacitance, and is beneficial to improving the performance of the semiconductor structure.
[0094] In this embodiment, the step of forming the second spacer layer 522 on the first spacer layer 520 of the second initial trench 602 includes: forming a filling layer 540 on the sidewall of the first spacer layer 520 located in the first initial trench 601 and in the gap 605, and the filling layer 540 fills the remaining space in the first initial trench 601 and the gap 605; under the filling effect of the filling layer 540, forming a second spacer material layer 523 (such as a second spacer material layer 524) on the top of the filling layer 540 and the top and sidewall of the first spacer layer 520. Figure 19 to Figure 20); remove the top of the filling layer 540 and the second spacer material layer 523 on the top of the first spacer layer 520, and the remaining second spacer material layer 523 is used as the second spacer layer 522 (as shown); Figure 21 to Figure 22 After forming the second spacer layer 522 and before forming the trench 608, the forming method further includes: removing the filling layer 540 (as shown in Figure 23 to Figure 24 As shown), to form a groove 608.
[0095] A filling layer 540 is formed on the side wall of the first spacer layer 520 located in the first initial groove 601 and in the gap 605, so that the filling layer 540 fills the remaining space in the first initial groove 601 and the gap 605. It can be understood that the filling layer 540 occupies part of the space between adjacent first spacer layers 520, thereby facilitating the formation of the second spacer layer 522 on the side wall of the first spacer layer 520 located in the second initial groove 602, thereby reducing the difficulty of forming the second spacer layer 522.
[0096] In this embodiment, the step of forming the filling layer 540 includes: forming a filling material layer 541 (such as a filler material layer 542) on the sidewall of the first spacer layer 520 in the first initial trench 601, on the sidewall and bottom of the first spacer layer 520 in the second initial trench 602, on the top of the first spacer layer 520 outside the initial trench 600, and in the gap 605. Figure 15 to Figure 16 ); remove the filling material layer 541 above the top of the first spacer layer 520 and the sidewall and bottom of the first spacer layer 520 located in the second initial trench 602, and retain the filling material layer 541 on the sidewall of the first spacer layer 520 in the first initial trench 601 and in the gap 605 as the filling layer 540 (as shown); Figure 17 to Figure 18 shown).
[0097] A filling material layer 541 is first formed on the side walls of the first spacer layer 520 in the first initial groove 601, on the side walls and bottom of the first spacer layer 520 in the second initial groove 602, on the top of the first spacer layer 520 outside the initial groove 600, and in the gap 605, and then the filling material layer 541 above the top of the first spacer layer 520 and on the side walls and bottom of the first spacer layer 520 located in the second initial groove 602 is removed to reduce the difficulty of forming the filling layer 540.
[0098] It should be noted that the process of forming the filling material layer 541 includes one or both of a chemical vapor deposition process and a physical vapor deposition process.
[0099] The chemical vapor deposition process has a high gap filling capability and high process stability, which is conducive to better quality of the filling material layer 541 formed on the sidewall of the first spacer layer 520 in the first initial trench 601 and the gap 605, and correspondingly also makes the quality of the filling layer 540 better. The physical vapor deposition process has the advantages of low deposition temperature, fast deposition speed, controllable composition and structure of the deposition layer, simple operation, high efficiency and low cost, and the physical vapor deposition process is highly compatible with existing machines and process flows, which is conducive to combining with existing process steps.
[0100] It should also be noted that, in the step of forming the filling material layer 541 , the material of the filling material layer 541 includes silicon oxide.
[0101] The material of the filling material layer 541 includes silicon oxide, which is beneficial to improving the adhesion between the filling material layer 541 and the first side wall layer 520, thereby further reducing the probability of forming the second side wall layer 522 on the side wall of the first side wall layer 520 in the first initial groove 601 and in the gap 605, and further improving the quality of the second side wall layer 522; moreover, silicon oxide can easily achieve a larger etching selectivity ratio with the material of the side wall layer 525 (such as silicon nitride).
[0102] It should be further explained that the process of removing the filling material layer 541 above the top of the first spacer layer 520 and the sidewall and bottom of the first spacer layer 520 located in the second initial trench 602 includes an isotropic etching process.
[0103] The isotropic etching process has the characteristic of isotropy, which makes it easy to remove the filling material layer 541 above the top of the first sidewall layer 520 and the sidewall and bottom of the first sidewall layer 520 located in the second initial groove 602, while retaining the filling material layer 541 on the sidewall of the first sidewall layer 520 in the first initial groove 601 and in the gap 605. It is also easy to achieve a higher etching selectivity between the etched object (that is, the filling material layer 541) and other film layers (such as the first sidewall layer 520), thereby reducing damage to other film layers.
[0104] As an example, the isotropic etching process includes an isotropic wet etching process.
[0105] In this embodiment, the process of forming the second spacer material layer 523 includes one or both of a chemical vapor deposition process and a physical vapor deposition process. As an example, the process of forming the second spacer material layer 523 includes a chemical vapor deposition process.
[0106] The chemical vapor deposition process has good step coverage, which is beneficial to improving the film continuity and formation quality of the second spacer material layer 523, and the chemical vapor deposition process has high process stability.
[0107] In this embodiment, the material of the second spacer 522 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon, aluminum oxide, titanium nitride and titanium oxide. As an example, the material of the second spacer 522 includes titanium oxide.
[0108] In this embodiment, the process of removing the top of the filling layer 540 and the second spacer material layer 523 on the top of the first spacer layer 520 includes an anisotropic etching process. As an example, the anisotropic etching process is an anisotropic dry etching process.
[0109] In this embodiment, the process of removing the filling layer 540 includes an isotropic etching process.
[0110] The isotropic etching process has the characteristic of isotropy, and it is easy to achieve a higher etching selectivity ratio between the etched object (ie, the filling layer 540 ) and other film layers (eg, the sidewall layer 525 ), thereby reducing damage to other film layers.
[0111] Specifically, the isotropic etching process includes an isotropic wet etching process, and the process parameters of the wet etching process include: the etching solution is a phosphoric acid solution, a hydrofluoric acid (HF) solution, an ammonia solution, a potassium hydroxide solution or a tetramethylammonium hydroxide (TMAH) solution; wherein the volume percentage concentration of the phosphoric acid solution is 1:10 to 1:1, the volume percentage concentration of the hydrofluoric acid solution is 1:1000 to 1:100, the volume percentage concentration of the ammonia solution is 1:100 to 1:1, the volume percentage concentration of the potassium hydroxide solution is 1:100 to 1:10, the volume percentage concentration of the tetramethylammonium hydroxide solution is 1:1000 to 1:100, and the process temperature is room temperature.
[0112] The cost of the wet etching process is relatively low and the operation steps are simple.
[0113] Phosphoric acid solution, hydrofluoric acid solution, ammonia solution, potassium hydroxide solution, and tetramethylammonium hydroxide solution are commonly used solutions in wet etching processes and are relatively easy to obtain.
[0114] It should be noted that by setting the volume percentage concentration of phosphoric acid solution, hydrofluoric acid solution, ammonia solution, potassium hydroxide solution or tetramethylammonium hydroxide solution, and the process temperature within the above range, it is beneficial to further improve the etching selectivity between the filling layer 540 and other film layers.
[0115] In this embodiment, after forming the second spacer layer 522 and before forming the trench 608, the forming method further includes: in the first region I and the second region II, along the first direction Y, forming a first barrier layer 550 (such as Figures 25 to 26 shown).
[0116] A first barrier layer 550 is formed in the remaining space of the initial groove 600 in the second partial area along the first direction Y, so that in the subsequent step of forming the groove, the first barrier layer 550 divides the groove across the second partial area along the first direction Y, that is, the first barrier layer 550 cuts off the groove across the second partial area, so that the length of the groove can be adjusted in the first direction Y, so that the length of the groove meets the design requirements, and further the target pattern of the second partial area meets the design requirements.
[0117] Specifically, in the step of forming the first barrier layer 550 , the sidewall layer 525 in the second partial region is also removed to increase the process window for forming the first barrier layer 550 and reduce the process difficulty of forming the first barrier layer 550 .
[0118] In this embodiment, the step of forming the trench 608 includes: using the hard mask layer 502 as the initial stop position, removing the first portion of the thickness of the sidewall layer 525 (eg, Figure 25 to Figure 26 ); then, the sidewall layer 525 is used as a mask to pattern the hard mask layer 502 to form a groove 608 surrounded by the sidewall layer 525 and the target layer 501. In the process of patterning the hard mask layer 502, the sidewall layer 525 of the second part thickness is also removed (as shown in FIG. Figure 27 to Figure 28 shown).
[0119] refer to Figure 29 to Figure 32 , using the sidewall layer 525 as a mask, the target layer 501 is patterned along the first groove 606 to form a first target pattern 561 , and the target layer 501 is patterned along the second groove 607 to form a second target pattern 562 . The first target pattern 561 and the second target pattern 562 constitute a target pattern 560 .
[0120] in, Fig.29 is a top view, Fig.30 for Fig.29 Cross-sectional view along AA1, Fig.31 is a top view, Fig.32 for Fig.31 Cross-sectional view along AA1.
[0121] Since the distance between adjacent first grooves 606 is smaller than the distance between adjacent second grooves 607, and the first target pattern 561 is formed by patterning the target layer 501 along the first grooves 606, and the second target pattern 562 is formed by patterning the target layer 501 along the second grooves 607, the distance W3 between adjacent first target patterns 561 is smaller than the distance W4 between adjacent second target patterns 562, which can meet the requirements of different semiconductor devices for the distance between adjacent devices, thereby meeting the requirements of different semiconductor devices for parasitic capacitance, and is beneficial to improving the performance of the semiconductor structure.
[0122] Accordingly, in this embodiment, in the step of forming the trench 608 , the first spacer layer 520 located in the second recess 604 divides the trench 608 across the first partial region along the first direction Y.
[0123] Accordingly, in this embodiment, in the step of forming the trench 608 , along the first direction Y, the first barrier layer 550 divides the trench 608 across the second partial region.
[0124] Accordingly, in this embodiment, in the step of forming the target pattern 560, the dielectric layer is patterned, the first target pattern 561 is the first interconnection groove, and the second target pattern 562 is the second interconnection groove.
[0125] In this embodiment, after forming the first target pattern 561 and the second target pattern 562, the forming method further includes: removing the sidewall layer 525, the first barrier layer 550, and the remaining hard mask layer 502 (such as Fig.31 and 32 shown).
[0126] In this embodiment, after forming the first target pattern 561 and the second target pattern 562, the forming method further includes: forming a filling conductive material in the first interconnection groove and the second interconnection groove, forming a first interconnection layer (not shown) located in the first interconnection groove, and a second interconnection layer (not shown) located in the second interconnection groove.
[0127] The first interconnect layer and the second interconnect layer are used to realize electrical connection between devices or between different components in a device to meet circuit design requirements.
[0128] Specifically, the first interconnection layer and the second interconnection layer are made of the same material. Both the first interconnection layer and the second interconnection layer are made of conductive materials, such as copper, cobalt, and the like.
[0129] It should be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.
[0130] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, It is characterized in that include: a substrate comprising a first region and a second region; A target pattern is located on the substrate, and the target pattern includes a first target pattern located in a first area and a second target pattern located in a second area. The target patterns extend along a first direction and are arranged at intervals along a second direction. Along the second direction, a distance between adjacent first target patterns is smaller than a distance between adjacent second target patterns.
2. The semiconductor structure according to claim 1, It is characterized in that Along the second direction, a width of the first region is smaller than a width of the second region.
3. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further includes: a dielectric layer located on the substrate; The target pattern is located in the dielectric layer, the first target pattern is a first interconnection groove, and the second target pattern is a second interconnection groove; The semiconductor structure further includes: a first interconnection layer located in the first interconnection groove; and a second interconnection layer located in the second interconnection groove.
4. The semiconductor structure according to claim 3, It is characterized in that The dielectric layer is also located between adjacent first interconnection grooves in the first direction and between adjacent second interconnection grooves in the first direction.
5. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, the substrate comprising a first area and a second area, and a target layer for forming a target pattern formed on the substrate; Forming a core layer on the target layer in the first region and the second region, wherein initial grooves extending along the first direction and arranged at intervals along the second direction are formed in the core layer, and the initial grooves include first initial grooves located in the first region and second initial grooves located in the second region; forming a first spacer layer on the sidewall of the initial trench; removing the core layer; forming a second spacer layer on the side wall of the first spacer layer in the second initial trench, wherein the second spacer layer and the first spacer layer constitute a spacer layer, and forming a trench surrounded by the spacer layer and the target layer, wherein the trench comprises a first trench located in the first region and a second trench located in the second region, and along the second direction, a distance between adjacent first trenches is smaller than a distance between adjacent second trenches; The target layer is patterned along the first groove using the sidewall layer as a mask to form a first target pattern, and the target layer is patterned along the second groove to form a second target pattern. The first target pattern and the second target pattern constitute a target pattern.
6. The method for forming a semiconductor structure according to claim 5, It is characterized in that In the step of forming the core layer, along the second direction, a width of the first preliminary trench is smaller than a width of the second preliminary trench.
7. The method for forming a semiconductor structure according to claim 5 or 6, It is characterized in that The step of forming the first spacer layer includes: forming a first spacer material layer on the sidewall and bottom of the initial trench and the core layer outside the initial trench; The first spacer material layer above the top of the core layer is removed to expose the top of the core layer, and the remaining first spacer material layer serves as the first spacer layer.
8. The method for forming a semiconductor structure according to claim 7, It is characterized in that In the step of forming the first spacer material layer, the first spacer material layer forms a first groove; the step of forming the first spacer layer further comprises: after forming the first spacer material layer, before removing the first spacer material layer above the top of the core layer, forming a sacrificial layer in the first groove; After forming the first spacer layer, the forming method further includes: removing the sacrificial layer.
9. The method for forming a semiconductor structure according to claim 8, It is characterized in that In the step of forming the sacrificial layer, the material of the sacrificial layer includes a high molecular organic polymer.
10. The method for forming a semiconductor structure according to claim 5, It is characterized in that In the step of removing the core layer, a gap is formed between adjacent first sidewall layers at the position of the core layer; The step of forming a second spacer layer on the first spacer layer of the second initial trench comprises: forming a filling layer on the sidewall of the first spacer layer in the first initial trench and in the gap, wherein the filling layer fills the remaining space in the first initial trench and the gap; Under the filling effect of the filling layer, a second spacer material layer is formed on the top of the filling layer and on the top and sidewall of the first spacer layer; Removing the second spacer material layer on the top of the filling layer and the top of the first spacer layer, and using the remaining second spacer material layer as the second spacer layer; After forming the second spacer layer and before forming the trench, the forming method further includes: removing the filling layer to form the trench.
11. The method for forming a semiconductor structure according to claim 10, It is characterized in that The steps of forming the filling layer include: forming a filling material layer on the sidewall of the first spacer layer in the first initial trench, on the sidewall and bottom of the first spacer layer in the second initial trench, on the top of the first spacer layer outside the initial trench, and in the gap; The filling material layer above the top of the first spacer layer and the sidewall and bottom of the first spacer layer in the second initial trench is removed, and the filling material layer on the sidewall of the first spacer layer in the first initial trench and in the gap is retained as a filling layer.
12. The method for forming a semiconductor structure according to claim 11, It is characterized in that The process of forming the filling material layer includes one or both of a chemical vapor deposition process and a physical vapor deposition process.
13. The method for forming a semiconductor structure according to claim 11, It is characterized in that In the step of forming the filling material layer, the material of the filling material layer includes silicon oxide.
14. The method for forming a semiconductor structure according to claim 10, It is characterized in that The process of removing the filling layer includes an isotropic etching process.
15. The method for forming a semiconductor structure according to claim 14, It is characterized in that The isotropic etching process includes an isotropic wet etching process, and the process parameters of the wet etching process include: the etching solution is a phosphoric acid solution, a hydrofluoric acid solution, an ammonia solution, a potassium hydroxide solution or a tetramethylammonium hydroxide solution; wherein the volume percentage concentration of the phosphoric acid solution is 1:10 to 1:1, the volume percentage concentration of the hydrofluoric acid solution is 1:1000 to 1:100, the volume percentage concentration of the ammonia solution is 1:100 to 1:1, the volume percentage concentration of the potassium hydroxide solution is 1:100 to 1:10, the volume percentage concentration of the tetramethylammonium hydroxide solution is 1:1000 to 1:100, and the process temperature is room temperature.
16. The method for forming a semiconductor structure according to claim 10, It is characterized in that The process of forming the second spacer material layer includes one or both of a chemical vapor deposition process and a physical vapor deposition process.
17. The method for forming a semiconductor structure according to claim 5 or 6, It is characterized in that After forming the core layer and before forming the first spacer layer, the forming method further comprises: removing the core layer in a first part of the region between adjacent initial grooves in the first region and the second region along the first direction to form a second groove, wherein the second groove divides the core layer in the first direction; In the step of forming the first spacer layer, the first spacer layer is also formed in the second groove; In the step of forming the trench, the first spacer layer located in the second groove divides the trench across the first partial area along the first direction.
18. The method for forming a semiconductor structure according to claim 5 or 6, It is characterized in that After forming the second spacer layer and before forming the trench, the forming method further comprises: forming a first barrier layer in the first region and the second region, along the first direction, in the remaining space of the initial trench in the second partial region; In the step of forming the trench, along the first direction, the first barrier layer divides the trench across the second partial region.
19. The method for forming a semiconductor structure according to claim 5 or 6, It is characterized in that In the step of providing the substrate, the target layer is a dielectric layer; In the step of forming the target pattern, the dielectric layer is patterned, the first target pattern is a first interconnection groove, and the second target pattern is a second interconnection groove; After forming the first target pattern and the second target pattern, the forming method further includes: forming a filling conductive material in the first interconnection groove and the second interconnection groove, forming a first interconnection layer located in the first interconnection groove, and a second interconnection layer located in the second interconnection groove.