Semiconductor device

Abstract

A semiconductor device includes a lower transistor and an upper transistor located at a higher vertical level than the lower transistor. The lower transistor includes a lower source / drain region, and a lower gate structure and a lower isolation insulating layer in contact with a side surface of the lower source / drain region. The upper transistor includes an upper source / drain region, and an upper gate structure and an upper isolation insulating layer in contact with a side surface of the upper source / drain region. A bottom surface of the lower isolation insulating layer is at the same vertical level as a bottom surface of the lower gate structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0161457 filed in the Korean Intellectual Property Office on November 20, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the inventive concept relate to a semiconductor device, and more particularly, to a semiconductor device including a three-dimensional stacked (3DS) field effect transistor (FET). Background Art

[0004] The scaling down of semiconductor devices has been rapidly developed. In addition, because semiconductor devices should have a fast operating speed and operate accurately, the structure of transistors in semiconductor devices is optimized. In particular, as semiconductor devices become highly integrated, semiconductor devices include three-dimensional transistors with multi-gate structures. Summary of the invention

[0005] Embodiments of the inventive concept provide a semiconductor device having improved structural reliability.

[0006] According to an embodiment of the present invention, a semiconductor device is provided, which includes a lower transistor and an upper transistor located at a vertical level higher than the lower transistor. The lower transistor includes a lower source / drain region and a lower gate structure and a lower isolation insulating layer in contact with the side surface of the lower source / drain region. The upper transistor includes an upper source / drain region and an upper gate structure and an upper isolation insulating layer in contact with the side surface of the upper source / drain region. The bottom surface of the lower isolation insulating layer is located at the same vertical level as the bottom surface of the lower gate structure.

[0007] According to another embodiment of the present invention, there is provided a semiconductor device including a lower transistor and an upper transistor located at a higher vertical level than the lower transistor. The lower transistor includes: a lower source / drain region; a lower gate structure and a lower isolation insulating layer in contact with the side surface of the lower source / drain region, wherein the lower gate and the lower nanosheet are alternately stacked in the lower gate structure; and a lower source / drain contact in contact with the lower source / drain region. The upper transistor includes: an upper source / drain region; an upper gate structure and an upper isolation insulating layer in contact with the side surface of the upper source / drain region, wherein the upper gate and the upper nanosheet are alternately stacked in the upper gate structure; and an upper source / drain contact in contact with the upper source / drain region. The bottom surface of the lower isolation insulating layer is located at the same vertical level as the bottom surface of the lower gate structure.

[0008] According to an embodiment of the present invention, there is provided a semiconductor device including a lower transistor and an upper transistor located at a vertical level higher than the lower transistor. The lower transistor includes a lower source / drain region and a lower gate in contact with a side surface of the lower source / drain region, a lower nanosheet, and a lower isolation insulating layer. The upper transistor includes an upper source / drain region, an upper gate in contact with a side surface of the upper source / drain region, an upper nanosheet and an upper isolation insulating layer, and an upper horizontal insulating layer disposed on the upper gate and at the uppermost end and extending in a horizontal direction. The lower gate and the lower nanosheet are alternately stacked, the upper gate and the upper nanosheet are alternately stacked, each of the lower gate and the lower nanosheet is spaced apart from the lower isolation insulating layer in a first horizontal direction, each of the upper gate and the upper nanosheet is spaced apart from the upper isolation insulating layer in a first horizontal direction, and the bottom surface of the lower isolation insulating layer is located at the same vertical level as the bottom surface of the lower gate at the lowermost end. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a plan layout diagram of a semiconductor device according to an embodiment.

[0010] Figure 2 According to the implementation method Figure 1 A cross-sectional view taken along line II'.

[0011] Figure 3 According to the implementation method Figure 2 An enlarged cross-sectional view of area A.

[0012] Figure 4 According to the implementation method Figure 2 An enlarged cross-sectional view of area A.

[0013] Figure 5 According to the implementation method Figure 1 A cross-sectional view taken along line II'.

[0014] Figures 6 to 17 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0015] Fig.18 is a circuit diagram of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like elements throughout. In this regard, the presented embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein.

[0017] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals may be used for the same components in the drawings, and redundant descriptions thereof may be omitted.

[0018] Figure 1 is a plan layout diagram of a semiconductor device according to an embodiment. Figure 2 According to the implementation method Figure 1 A cross-sectional view taken along line II'. Figure 3 According to the implementation method Figure 2 An enlarged cross-sectional view of area A.

[0019] Reference Figures 1 to 3 In an implementation, the semiconductor device 100 includes a first insulating layer 110 , a second insulating layer 180 , a third insulating layer 190 , an isolation insulating layer 300 , a lower transistor LTR, and an upper transistor UTR.

[0020] The semiconductor device 100 of the embodiment of the present inventive concept includes a field effect transistor (FET). For example, the semiconductor device 100 includes a complementary metal oxide semiconductor field effect transistor (cFET). The complementary metal oxide semiconductor field effect transistor includes a metal oxide semiconductor (MOS) transistor. For example, the complementary metal oxide semiconductor field effect transistor includes an N-channel metal oxide semiconductor (NMOS) transistor and a P-channel metal oxide semiconductor (PMOS) transistor.

[0021] In this specification, the horizontal direction (X direction and / or Y direction) refers to a direction parallel to the main surface (e.g., upper surface or lower surface) of the first insulating layer 110, and the vertical direction (Z direction) refers to a direction perpendicular to the horizontal direction (X direction and / or Y direction). The first horizontal direction (e.g., X direction) may be defined as crossing the second horizontal direction (e.g., Y direction). The first horizontal direction and the second horizontal direction may be perpendicular to each other.

[0022] Furthermore, the semiconductor device 100 has two surfaces spaced apart from each other in a vertical direction, wherein one surface closer to a back side wiring structure (BWS) may be referred to as a bottom surface and the other surface opposite to the bottom surface may be referred to as a top surface.

[0023] The first insulating layer 110 includes at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof. The lower transistor LTR and the upper transistor UTR are disposed on the first insulating layer 110 .

[0024] The lower transistor LTR and the upper transistor UTR are located at different vertical levels. For example, the upper transistor UTR is located at a higher vertical level than the lower transistor LTR.

[0025] The semiconductor device further includes a front wiring structure FWS disposed at a vertical level higher than the plurality of upper transistors UTR and a back wiring structure BWS disposed at a vertical level lower than the plurality of lower transistors LTR. Various vertical levels may represent relative positions along a vertical direction. In an embodiment, the front wiring structure FWS transmits a signal voltage to the plurality of lower transistors LTR and the plurality of upper transistors UTR, and the back wiring structure BWS transmits a power supply voltage and a ground voltage to the plurality of lower transistors LTR and the plurality of upper transistors UTR.

[0026] The lower transistor LTR includes a lower gate structure LGST, a lower source / drain region 130, and a lower isolation insulating layer 340. The lower gate structure LGST includes a lower gate 120 and a lower nanosheet structure LNS alternately stacked in a vertical direction (Z direction) on the first insulating layer 110. In addition, the lower gate structure LGST further includes a lower source / drain contact 220 contacting the lower source / drain region 130.

[0027] In addition, the upper transistor UTR includes an upper gate structure UGST, an upper source / drain region 160, and an upper isolation insulating layer 320. The upper gate structure UGST includes an upper gate 150 and an upper nanosheet structure UNS alternately stacked in a vertical direction (Z direction) on the lower gate structure LGST. In addition, the upper gate structure UGST further includes an upper horizontal insulating layer 170 and an upper source / drain contact 240 in contact with the upper source / drain region 160.

[0028] In an embodiment, the plurality of lower transistors LTR are PMOS transistors and the plurality of upper transistors UTR are NMOS transistors. In other embodiments, the plurality of lower transistors LTR are NMOS transistors and the plurality of upper transistors UTR are PMOS transistors. In other embodiments, the plurality of lower transistors LTR are NMOS transistors each having a first threshold voltage and the plurality of upper transistors UTR are NMOS transistors each having a second threshold voltage different from the first threshold voltage. In other embodiments, the plurality of lower transistors LTR are PMOS transistors each having a first threshold voltage and the plurality of upper transistors UTR are PMOS transistors each having a second threshold voltage different from the first threshold voltage.

[0029] Each of the lower nanosheet structure LNS and the upper nanosheet structure UNS extends in the second horizontal direction (Y direction). Each of the lower nanosheet structure LNS and the upper nanosheet structure UNS includes two nanosheets spaced apart in the vertical direction (Z direction). The lower nanosheet structure LNS includes a first lower nanosheet LNS1 and a second lower nanosheet LNS2. In addition, the upper nanosheet structure UNS includes a first upper nanosheet UNS1 and a second upper nanosheet UNS2. The number of nanosheets in each of the lower nanosheet structure LNS and / or the upper nanosheet structure UNS is not necessarily limited to the number shown, and may be modified in various ways in other embodiments. That is, various embodiments may include one or more nanosheets in each of the upper nanosheet structure UNS and the lower nanosheet structure LNS. The term "nanosheet" may refer to a layer having a thickness falling within the range of about 1 nm to about 100 nm.

[0030] Each of the first lower nanosheet LNS1 and the second lower nanosheet LNS2 in the lower nanosheet structure LNS and the first upper nanosheet UNS1 and the second upper nanosheet UNS2 in the upper nanosheet structure UNS is used as a channel region. In an embodiment, the first lower nanosheet LNS1, the second lower nanosheet LNS2, the first upper nanosheet UNS1 and the second upper nanosheet UNS2 each have substantially the same thickness in the vertical direction (Z direction). In other embodiments, at least some of the first lower nanosheet LNS1, the second lower nanosheet LNS2, the first upper nanosheet UNS1 and the second upper nanosheet UNS2 have different thicknesses in the vertical direction (Z direction).

[0031] like Figure 2 As shown, the first lower nanosheet LNS1, the second lower nanosheet LNS2, the first upper nanosheet UNS1, and the second upper nanosheet UNS2 each have the same or similar size in the first horizontal direction (X direction). In other embodiments, at least some of the first lower nanosheet LNS1, the second lower nanosheet LNS2, the first upper nanosheet UNS1, and the second upper nanosheet UNS2 have different sizes in the first horizontal direction (X direction).

[0032] Each of the lower and upper nanosheet structures LNS and UNS includes at least one of a Group IV semiconductor such as Si or Ge, a Group IV-IV compound semiconductor such as SiGe or SiC, and a Group III-V compound semiconductor such as GaAs, InAs, or InP.

[0033] Each of the lower gate 120 and the upper gate 150 surrounds the corresponding nanosheet structure and extends in the second horizontal direction (Y direction). For example, the lower gate 120 includes a series of layers stacked above and below each of the first lower nanosheet LNS1 and the second lower nanosheet LNS2, so that the lower gate 120 and the lower nanosheet structure LNS are alternately stacked in the vertical direction. Similarly, the upper gate 150 includes a series of layers stacked above and below each of the first upper nanosheet UNS1 and the second upper nanosheet UNS2, so that the upper gate 150 and the upper nanosheet structure UNS are alternately stacked in the vertical direction. Each of the lower gate 120 and the upper gate 150 is stacked in the vertical direction (Z direction) and spaced apart from each other.

[0034] The lower gate 120 includes a lower gate dielectric layer 122 and a lower gate electrode 124, and the upper gate 150 includes an upper gate dielectric layer 152 and an upper gate electrode 154. The lower gate dielectric layer 122 surrounds the lower gate electrode 124, and the upper gate dielectric layer 152 surrounds the upper gate electrode 154.

[0035] Each of the lower gate dielectric layer 122 and the upper gate dielectric layer 152 includes at least one of a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer, and a combination thereof. The high-k dielectric layer includes at least one of a metal oxide and a metal oxynitride. For example, the high-k dielectric layer that can be used as the lower gate dielectric layer 122 and the upper gate dielectric layer 152 includes HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 and at least one of a combination thereof, but is not necessarily limited thereto.

[0036] Each of the lower gate electrode 124 and the upper gate electrode 154 includes at least one of doped polysilicon, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, and combinations thereof, for example, including at least one of Ag, Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, and combinations thereof, but not necessarily limited thereto. In an embodiment, each of the lower gate electrode 124 and the upper gate electrode 154 includes a work function metal-containing layer and a gap filling metal layer. The work function metal-containing layer includes at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The gap filling metal layer includes one of a W layer and an Al layer. In an embodiment, each of the lower gate electrode 124 and the upper gate electrode 154 includes one of a stack structure of TiAlC / TiN / W, a stack structure of TiN / TaN / TiAlC / TiN / W, and a stack structure of TiN / TaN / TiN / TiAlC / TiN / W, but is not necessarily limited thereto.

[0037] The lower horizontal insulating layer 140 is respectively disposed between the lower gate structure LGST and the upper gate structure UGST, between the lower gate structure LGST and the upper isolation insulating layer 320, between the lower isolation insulating layer 340 and the upper gate structure UGST, and between the lower isolation insulating layer 340 and the upper isolation insulating layer 320. The lower horizontal insulating layer 140 contacts at least one of the lower gate 120 and the lower nanosheet LNS, and contacts at least one of the upper gate 150 and the upper nanosheet UNS. In addition, the upper horizontal insulating layer 170 is disposed in the upper region of the upper gate structure UGST. The lower horizontal insulating layer 140 protects the lower gate structure LGST and the upper gate structure UGST and electrically isolates them from each other, and the upper horizontal insulating layer 170 is disposed on the uppermost end of the upper gate electrode 154 and electrically isolates the uppermost end of the upper gate electrode 154 from other components of the semiconductor device 100. The lower horizontal insulating layer 140 and the upper horizontal insulating layer 170 each include at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof.

[0038] The upper isolation insulating layer 320 and the lower isolation insulating layer 340 extend in the second horizontal direction (Y direction) and the vertical direction (Z direction). The upper isolation insulating layer 320 extends from the vertical level of the top surface of the upper gate structure UGST to the vertical level of the bottom surface of the upper gate structure UGST, and the lower isolation insulating layer 340 extends from the vertical level of the top surface of the lower gate structure LGST to the vertical level of the bottom surface of the lower gate structure LGST. The top surface of the upper isolation insulating layer 320 may be located at the same vertical level as the top surface of the upper gate structure UGST, and the bottom surface of the upper isolation insulating layer 320 may be located at the same vertical level as the bottom surface of the upper gate structure UGST. The top surface of the lower isolation insulating layer 340 may be located at the same vertical level as the top surface of the lower gate structure LGST, and the bottom surface of the lower isolation insulating layer 340 may be located at the same vertical level as the bottom surface of the lower gate structure LGST. The upper isolation insulating layer 320 may be spaced apart from the upper gate structure UGST in the first horizontal direction. The lower isolation insulating layer 340 may be spaced apart from the lower gate structure LGST in the first horizontal direction.

[0039] The upper isolation insulating layer 320 includes a first seam seam1 therein, and the lower isolation insulating layer 340 includes a second seam seam2 therein. The first seam seam1 and the second seam seam2 are empty spaces generated during the formation of the isolation insulating layer 300.

[0040] When viewed in a plan view, the first seam seam1 is located in the center portion of the upper isolation insulating layer 320 in the first horizontal direction (X direction), and the second seam seam2 is located in the center portion of the lower isolation insulating layer 340 in the first horizontal direction (X direction). In addition, each of the first seam seam1 and the second seam seam2 is spaced apart from the lower horizontal insulating layer 140 in the vertical direction (Z direction).

[0041] In the cross section where the upper isolation insulating layer 320 and the lower isolation insulating layer 340 are in contact with the lower horizontal insulating layer 140, each of the upper isolation insulating layer 320 and the lower isolation insulating layer 340 has a rectangular shape. For example, the bottom surface of the upper isolation insulating layer 320 and the top surface of the lower isolation insulating layer 340 each have a flat shape. However, the shapes of the lower horizontal insulating layer 140, the upper isolation insulating layer 320, and the lower isolation insulating layer 340 may be modified in various ways. For example, in the process of forming the upper isolation insulating layer 320 and the lower isolation insulating layer 340, the shapes of the lower horizontal insulating layer 140, the upper isolation insulating layer 320, and the lower isolation insulating layer 340 may be changed according to the change of the etching profile.

[0042] Each of the upper isolation insulating layer 320 and the lower isolation insulating layer 340 includes at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof. For example, the upper isolation insulating layer 320 and the lower isolation insulating layer 340 may each include the same material. In another embodiment, the upper isolation insulating layer 320 and the lower isolation insulating layer 340 include different materials.

[0043] The bottom surfaces of the lower gate structure LGST and the lower isolation insulating layer 340 are located at the same vertical level, and the top surfaces of the upper gate structure UGST and the upper isolation insulating layer 320 are located at the same vertical level. For example, the bottom surface of the lower isolation insulating layer 340 is located at the same vertical level as the bottom surface of the lower gate 120 at the lowermost end. In other embodiments, the bottom surfaces of the lower gate structure LGST and the lower isolation insulating layer 340 are located at the same vertical level, and the top surfaces of the upper gate structure UGST and the upper isolation insulating layer 320 are located at different vertical levels. The term "vertical level" used in this specification refers to the distance from the back wiring structure (BWS) in the vertical direction (Z direction or -Z direction).

[0044] Since the semiconductor device 100 includes the upper isolation insulating layer 320 and the lower isolation insulating layer 340 , diversity in layouts of the lower transistor LTR and the upper transistor UTR may increase.

[0045] In addition, each of the lower gate structure LGST, the upper gate structure UGST, the upper isolation insulating layer 320, and the lower isolation insulating layer 340 further includes a spacer extending along the second horizontal direction (Y direction) and the vertical direction (Z direction) on its respective sidewalls. The spacer electrically isolates each of the lower gate structure LGST, the upper gate structure UGST, the upper isolation insulating layer 320, and the lower isolation insulating layer 340 from the source / drain region.

[0046] Each lower source / drain region 130 is disposed between a plurality of lower gate structures LGST, between the lower gate structure LGST and the lower isolation insulating layer 340, and between a plurality of lower isolation insulating layers 340. Each lower source / drain region 130 is located between one of the lower gate structures LGST and one of the lower isolation insulating layers 340, or between two lower isolation insulating layers 340. For example, for one or more lower source / drain regions 130, the lower gate structure LGST is in contact with a first sidewall of the lower source / drain region 130, and the lower isolation insulating layer 340 is in contact with an opposite sidewall of the lower source / drain region 130. Similarly, for one or more other lower source / drain regions 130, the lower isolation insulating layer 340 is in contact with opposite sidewalls of another lower source / drain region 130. In addition, each upper source / drain region 160 is interposed between a plurality of upper gate structures UGST, between the upper gate structure UGST and the upper isolation insulating layer 320, and between a plurality of upper isolation insulating layers 320. Each upper source / drain region 160 is located between one of the upper gate structures UGST and one of the upper isolation insulating layers 320, or between two upper isolation insulating layers 320. For example, for one or more upper source / drain regions 160, the upper gate structure UGST is in contact with a first sidewall of the upper source / drain region 160, and the upper isolation insulating layer 320 is in contact with an opposite sidewall of the upper source / drain region 160. Similarly, for one or more other upper source / drain regions 160, the upper isolation insulating layer 320 is in contact with the opposite sidewalls of another upper source / drain region 160.

[0047] The lower source / drain region 130 and the upper source / drain region 160 are located on both sides of the nanosheet structure. The lower source / drain region 130 and the upper source / drain region 160 are in contact with the sidewall of the nanosheet structure surrounded by the adjacent gate. The lower source / drain region 130 is in contact with the sidewall of each of the first lower nanosheet LNS1 and the second lower nanosheet LNS2 of the lower nanosheet structure LNS, and the upper source / drain region 160 is in contact with the sidewall of each of the first upper nanosheet UNS1 and the second upper nanosheet UNS2 of the upper nanosheet structure UNS.

[0048] The lower source / drain region 130 includes one of an epitaxially grown Si layer and an epitaxially grown SiC layer, and the upper source / drain region 160 includes a plurality of epitaxially grown SiGe layers. For example, each lower source / drain region 130 includes a Si layer doped with an n-type dopant, wherein the n-type dopant includes phosphorus (P), and each upper source / drain region 160 includes a Si layer doped with a p-type dopant. 1-x Ge x layer (here, x≠0), the p-type dopant includes at least one of boron (B), gallium (Ga), carbon (C), and a combination thereof, but is not necessarily limited thereto.

[0049] In other embodiments, the lower source / drain region 130 includes a plurality of epitaxially grown SiGe layers, and the upper source / drain region 160 includes one of an epitaxially grown Si layer and an epitaxially grown SiC layer. For example, each lower source / drain region 130 includes a Si layer doped with a p-type dopant. 1-x Ge x A layer (here, x≠0) layer, wherein the p-type dopant includes at least one of boron (B), gallium (Ga), carbon (C) and a combination thereof, and each upper source / drain region 160 includes a Si layer doped with an n-type dopant, and the n-type dopant includes phosphorus (P), but is not limited thereto.

[0050] The second insulating layer 180 is disposed between the lower source / drain region 130 and the upper source / drain region 160, and the third insulating layer 190 is disposed on the upper source / drain region 160. The second insulating layer 180 and the third insulating layer 190 each include at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof.

[0051] The semiconductor device 100 further includes a lower source / drain contact 220 on the lower source / drain region 130 and extending in a vertical direction (Z direction) toward the first insulating layer 110 and / or an upper source / drain contact 240 on the upper source / drain region 160 and extending in a vertical direction (Z direction) away from the first insulating layer 110. At least a portion of the lower source / drain contact 220 is surrounded by the lower source / drain region 130, and at least a portion of the upper source / drain contact 240 is surrounded by the upper source / drain region 160. In addition, at least a portion of the lower source / drain contact 220 is surrounded by the second insulating layer 180, and at least a portion of the upper source / drain contact 240 is surrounded by the third insulating layer 190.

[0052] In addition, a silicide layer may be further interposed between the lower source / drain region 130 and the lower source / drain contact 220 and / or between the upper source / drain region 160 and the upper source / drain contact 240. For example, the silicide layer includes titanium silicide, but is not necessarily limited thereto.

[0053] Each of the lower source / drain contact 220 and the upper source / drain contact 240 includes at least one of a metal, a conductive metal nitride, and a combination thereof. For example, each of the lower source / drain contact 220 and the upper source / drain contact 240 includes at least one of W, Cu, Al, Ti, Ta, TiN, TaN, an alloy thereof, and a combination thereof.

[0054] The backside wiring structure BWS is disposed below the lower source / drain contact 220. The backside wiring structure BWS includes a first wiring line BML and a first cover insulating layer BIL. The first wiring line BML includes a plurality of conductive patterns at different vertical levels and a plurality of conductive paths connecting the plurality of conductive patterns to each other, and the first cover insulating layer BIL includes a plurality of insulating layers surrounding the plurality of conductive patterns and the plurality of conductive paths.

[0055] The front wiring structure FWS is disposed on the upper source / drain contact 240. The front wiring structure FWS includes a second wiring line FML and a second cover insulating layer FIL. The second wiring line FML includes a plurality of conductive patterns located at different vertical levels and a plurality of conductive paths connecting the plurality of conductive patterns to each other, and the second cover insulating layer FIL includes a plurality of insulating layers surrounding the plurality of conductive patterns and the plurality of conductive paths.

[0056] Furthermore, a capping insulating layer and a via may be interposed between the lower source / drain contacts 220 and the backside wiring structure BWS and / or between the upper source / drain contacts 240 and the frontside wiring structure FWS.

[0057] In a general semiconductor device, an isolation insulating layer is formed by performing an etching process at the same vertical level as the top surface of the upper gate structure. Therefore, the arrangement of transistors of the semiconductor device may be limited. In addition, when etching is performed from the top surface of the upper gate structure to the bottom surface of the lower gate structure, the isolation insulating layer has a high aspect ratio structure, so the reliability of the isolation insulating layer is low.

[0058] However, the semiconductor device 100 according to the embodiment of the inventive concept includes an upper isolation insulating layer 320 formed by performing an etching process at the same vertical level as the top surface of the upper gate structure UGST, and a lower isolation insulating layer 340 formed by performing an etching process at the same vertical level as the bottom surface of the lower gate structure LGST. Therefore, the etching depth of the isolation insulating layer 300 is reduced, thereby improving the reliability of the process of forming the isolation insulating layer 300. In addition, because the upper isolation insulating layer 320 and the lower isolation insulating layer 340 are formed at different vertical levels, the arrangement of transistors in the semiconductor device 100 can be diversified.

[0059] Figure 4 According to the implementation method Figure 2 The enlarged cross-sectional view of area A of FIG. Figure 2 and Figure 4 Give a description.

[0060] Reference Figure 4In an embodiment, at least some of the corners where the upper isolation insulating layer 320a and the lower isolation insulating layer 340a face each other are rounded. Because at least some of the corners where the upper isolation insulating layer 320a and the lower isolation insulating layer 340a face each other are rounded, two surfaces of the lower horizontal insulating layer 140a spaced apart in the vertical direction (Z direction) are rounded. For example, each of the bottom surface of the upper isolation insulating layer 320a and the top surface of the lower isolation insulating layer 340a is rounded. For example, each of the bottom surface of the upper isolation insulating layer 320a and the top surface of the lower isolation insulating layer 340a may be concave (e.g., may have a concave profile). Figure 4 The shape of each of the lower horizontal insulating layer 140a, the upper isolation insulating layer 320a and the lower isolation insulating layer 340a is different from Figure 3 The shape of each of the lower horizontal insulating layer 140, the upper isolation insulating layer 320, and the lower isolation insulating layer 340 is changed. As described above, in the process of forming the upper isolation insulating layer 320a and the lower isolation insulating layer 340a, the shapes of the upper isolation insulating layer 320a and the lower isolation insulating layer 340a may be changed due to the etching profile. The method of forming the upper isolation insulating layer 320a and the lower isolation insulating layer 340a will be referred to Figures 6 to 17 is described in more detail.

[0061] Figure 5 According to the implementation method Figure 1 The cross-sectional view taken along the line II' of FIG. Figure 1 and Figure 5 Give a description.

[0062] Reference Figure 5 In an implementation, the semiconductor device 100 a includes a first insulating layer 110 , a second insulating layer 180 , a third insulating layer 190 , an isolation insulating layer 300 a , a lower transistor LTR, and an upper transistor UTR.

[0063] and Figure 2 Compared with the semiconductor device 100, Figure 5 The semiconductor device 100a does not include the lower horizontal insulating layer 140. Therefore, the lower gate structure LGST and the upper gate structure UGST are in contact with each other, the lower gate structure LGST and the upper isolation insulating layer 320 are in contact with each other, the upper gate structure UGST and the lower isolation insulating layer 340 are in contact with each other, and the semiconductor device 100a further includes a through isolation insulating layer (or through separation insulating layer) 360.

[0064] The through-isolating insulating layer 360 extends from the vertical level of the top surface of the upper gate structure UGST (e.g., the top surface of the upper source / drain contact 240) to the vertical level of the bottom surface of the lower gate structure LGST. The bottom surface of the through-isolating insulating layer 360 is located at the same vertical level as the bottom surface of the lower gate structure LGST, and the top surface of the through-isolating insulating layer 360 is located at the same vertical level as the top surface of the upper gate structure UGST.

[0065] The through isolation insulating layer 360 includes a first seam seam1 and a second seam seam2 spaced apart from each other in the vertical direction (Z direction). Two etching processes and two deposition processes are performed to form the through isolation insulating layer 360. Therefore, the through isolation insulating layer 360 includes a plurality of seams. At least two of the plurality of seams in the through isolation insulating layer 360 are spaced apart from each other in the vertical direction (Z direction).

[0066] Figures 6 to 17 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment. Figures 6 to 17 is shown in the order of process and along Figure 1 The cross-sectional view of the section corresponding to the section taken along the line II'. Figures 6 to 17 Give a description.

[0067] Reference Figure 6 In an embodiment, a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet layers NS are alternately stacked one after another on a substrate 102. The plurality of nanosheet layers NS include at least one of a group IV semiconductor (such as Si or Ge), a group IV-IV compound semiconductor (such as SiGe or SiC), and a group III-V compound semiconductor (such as GaAs, InAs, or InP). The plurality of sacrificial semiconductor layers 104 include a material having an etching selectivity relative to the plurality of nanosheet layers NS. In some embodiments, the plurality of nanosheet layers NS include silicon (Si), and the plurality of sacrificial semiconductor layers 104 include silicon germanium (SiGe). In an embodiment, the plurality of nanosheet layers NS and the plurality of sacrificial semiconductor layers 104 are formed by an epitaxial growth process, and the epitaxial growth process includes a chemical vapor deposition (CVD) process (such as one of vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), etc.), molecular beam epitaxy, or a combination thereof.

[0068] In addition, a preliminary insulating layer 140p is stacked between the two sacrificial semiconductor layers 104. The preliminary insulating layer 140p will later physically and / or electrically isolate the gate structure into a lower region (such as a lower gate structure LGST) and an upper region (such as an upper gate structure UGST). The preliminary insulating layer 140p includes at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof.

[0069] Reference Figure 7 In an embodiment, a dummy gate line 400 is formed on the uppermost sacrificial semiconductor layer 104, and the dummy gate line 400 is etched by using the dummy gate line 400 as an etching mask. Figure 6 At least a portion of each of the nanosheet layer NS, the sacrificial semiconductor layer 104, and the preliminary insulating layer 140p is removed. Figure 6 At least a portion of the preliminary insulating layer 140p is etched to form a lower horizontal insulating layer 140. The lower horizontal insulating layer 140 physically and / or electrically isolates the lower region and the upper region of the gate structure GST from each other. The etched portion on the substrate 102 is a portion where the lower source / drain region 130 and the upper source / drain region 160 are later formed.

[0070] The dummy gate lines 400 are spaced apart from each other at equal intervals in a first horizontal direction (X direction). In an embodiment, the plurality of dummy gate lines 400 include at least one of silicon nitride (SiN), silicon oxide (SiO), polysilicon, and a spin-on hard mask. Each of the plurality of dummy gate lines 400 has a double-layer structure made of different materials. In addition, dummy gate line spacers may be further formed on the sidewalls of the plurality of dummy gate lines 400.

[0071] Reference Figure 8 In an embodiment, by an epitaxial growth method Figure 7 A lower source / drain region 130 and an upper source / drain region 160 are formed in the etched portion of the structure. In addition, a second insulating layer 180 is formed between the lower source / drain region 130 and the upper source / drain region 160, and a preliminary third insulating layer 190p is formed on the upper source / drain region 160. The second insulating layer 180 and the preliminary third insulating layer 190p each include at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof.

[0072] Reference Fig. 9 , remove Figure 8 The dummy gate line 400 is removed Figure 8 At least a portion of the preliminary third insulating layer 190p is removed to form the third insulating layer 190. Thereafter, Figure 8 The sacrificial semiconductor layer 104 is formed to form a gate. The gate can be removed by a wet etching process based on the etching selectivity. Figure 8 The sacrificial semiconductor layer 104 is formed by a semiconductor layer having a plurality of semiconductor layers.

[0073] The gate formed in the lower region may be referred to as a lower gate 120, and the gate formed in the upper region may be referred to as an upper gate 150. The lower gate 120 includes a lower gate electrode 124 and a lower gate dielectric layer 122 surrounding the lower gate electrode 124. In addition, the upper gate 150 includes an upper gate electrode 154 and an upper gate dielectric layer 152 surrounding the upper gate electrode 154.

[0074] In addition, an upper horizontal insulating layer 170 extending in the second horizontal direction (Y direction) is formed on the uppermost upper gate electrode 150. The upper horizontal insulating layer 170 physically and / or electrically isolates the uppermost upper gate electrode 154 from different configurations of the semiconductor device 100. The upper horizontal insulating layer 170 includes at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof.

[0075] Through such a process, a lower gate structure LGST and an upper gate structure UGST are formed. The lower gate structure LGST includes a lower nanosheet structure LNS and a lower gate 120, and the upper gate structure UGST may include an upper nanosheet structure UNS, an upper gate 150, and an upper horizontal insulating layer 170. In addition, the lower horizontal insulating layer 140 is interposed between the lower gate structure LGST and the upper gate structure UGST. The upper horizontal insulating layer 170 includes at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof.

[0076] Then, an upper source / drain contact 240 is formed that penetrates at least a portion of each of the upper source / drain regions 160 and the third insulating layer 190. After forming a trench that penetrates at least a portion of each of the upper source / drain regions 160 and the third insulating layer 190, the trench is filled with a metal and / or a metal nitride to form the upper source / drain contact 240. For example, the upper source / drain contact 240 includes at least one of W, Cu, Al, Ti, Ta, TiN, TaN, alloys thereof, and combinations thereof.

[0077] Reference Fig.10In an embodiment, a first hard mask layer HM1 and a first photoresist pattern PR1 are formed on the upper gate structure UGST, the third insulating layer 190, and the upper source / drain contacts 240. An opening of the first photoresist pattern PR1 is aligned in a vertical direction (Z direction) with a portion in which an upper isolation insulating layer 320 will be formed later. The first hard mask layer HM1 includes at least one of an amorphous carbon layer (ACL), a silicon oxide layer, and a silicon nitride layer.

[0078] Reference Fig.11 In an embodiment, by using Fig.10 The first photoresist pattern PR1 is etched Fig.10 The first hard mask layer HM1 is removed to form a first hard mask pattern HM1P. Fig.10 The first photoresist pattern PR1 is formed by etching the first hard mask pattern HM1P as an etching mask to etch at least a portion of the upper gate structure UGST to form a plurality of first openings OP1. Each first opening OP1 is formed in a region where an upper isolation insulating layer 320 will be formed later. The lower horizontal insulating layer 140 is used as an etching stop layer. In other embodiments, at least a portion of the upper gate structure UGST is etched based on an etching process time.

[0079] Reference Fig.12 In an embodiment, when removing Fig.11 After the first hard mask pattern HM1P is formed, Fig.11 An insulating material is formed in the plurality of first openings OP1 of the upper gate structure UGST, and at least a portion of the insulating material is chemically mechanically polished (CMP) to form a plurality of upper isolation insulating layers 320. Each of the plurality of upper isolation insulating layers 320 includes a first seam seam1 therein. The first seam seam1 is spaced apart from the lower horizontal insulating layer 140 in the vertical direction Z. A top surface of the upper isolation insulating layer 320 is located at the same vertical level as a top surface of the upper gate structure UGST. The upper isolation insulating layer 320 includes at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof.

[0080] Reference Fig.13 In an embodiment, inverting Fig.12 The resulting product is then removed from substrate 102.

[0081] Reference Fig.14 In an embodiment, Fig.13A second hard mask layer HM2 and a second photoresist pattern PR2 are formed on the resultant product. An opening of the second photoresist pattern PR2 is aligned in the vertical direction (Z direction) with a portion where a lower isolation insulating layer 340 will be formed later. The second hard mask layer HM2 includes at least one of an amorphous carbon layer (ACL), a silicon oxide layer, and a silicon nitride layer.

[0082] Reference Fig.15 In an embodiment, by using Fig.14 The second photoresist pattern PR2 is etched Fig.14 The second hard mask layer HM2 is removed to form a second hard mask pattern HM2P. Fig.14 The second photoresist pattern PR2 is formed by etching the second hard mask pattern HM2P as an etching mask to etch at least a portion of the lower gate structure LGST to form a plurality of second openings OP2. Each second opening OP2 is formed in a region where a lower isolation insulating layer 340 will be formed later. The lower horizontal insulating layer 140 is used as an etching stop layer. In other embodiments, at least a portion of the lower gate structure LGST is etched based on the etching process time.

[0083] Reference Fig.16 In an embodiment, when removing Fig.15 After forming the second hard mask pattern HM2P, Fig.15 Insulating material is formed in the plurality of second openings OP2 of the lower horizontal insulating layer 140, and at least a portion of the insulating material is chemically mechanically polished to form a plurality of lower isolation insulating layers 340. Each of the plurality of lower isolation insulating layers 340 includes a second seam seam2 therein. The second seam seam2 is spaced apart from the lower horizontal insulating layer 140 in the vertical direction Z. The bottom surface ( Fig.16 The top surface of the lower gate structure LGST is located at the same level as the bottom surface of the lower gate structure LGST. Fig.16 The lower isolation insulating layer 340 includes at least one of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and combinations thereof.

[0084] Reference Fig.17In an embodiment, a first insulating layer 110 is formed on the lower gate structure LGST and the lower source / drain region 130, and a lower source / drain contact 220 is formed on the lower source / drain region 130. The lower source / drain contact 220 penetrates at least a portion of each of the lower source / drain regions 130 and the first insulating layer 110. After forming a trench penetrating at least a portion of each of the lower source / drain regions 130 and the first insulating layer 110, the lower source / drain contact 220 is formed by filling the trench with a metal and / or a metal nitride. For example, the lower source / drain contact 220 includes at least one of W, Cu, Al, Ti, Ta, TiN, TaN, alloys thereof, and combinations thereof.

[0085] Thereafter, a backside wiring structure BWS is formed on the lower source / drain contact 220, and a frontside wiring structure FWS is formed on the upper source / drain contact 240. The backside wiring structure BWS includes a first wiring line BML and a first cover insulating layer BIL. The frontside wiring structure FWS includes a second wiring line FML and a second cover insulating layer FIL. The first wiring line BML and the second wiring line FML each include a plurality of conductive patterns located at different vertical levels and a plurality of conductive paths connecting the plurality of conductive patterns to each other, and the first cover insulating layer BIL and the second cover insulating layer FIL each include a plurality of insulating layers surrounding the plurality of conductive patterns and the plurality of conductive paths.

[0086] As mentioned above, reference has been made Figures 6 to 17 Describes the manufacturing method according to the embodiment Figure 2 The method of the semiconductor device 100 is to form Figure 5 The semiconductor device 100a is formed Figure 6 In the process of forming the nanosheet layer NS and the sacrificial semiconductor layer 104, the preliminary insulating layer 140p is omitted. In addition, at least a portion of the upper isolation insulating layer 320 that has been generated in the process of forming the second opening OP2 is removed. Thereafter, because the lower isolation insulating layer 340 is formed inside the second opening OP2, the through isolation insulating layer 360 can be formed integrally.

[0087] The method of manufacturing the semiconductor device 100 according to the embodiment of the inventive concept includes a method of forming the isolation insulating layer 300 at the same vertical level as the lower surface of the lower gate structure LGST. Therefore, the etching depth for forming the isolation insulating layer 300 is reduced, thereby improving the reliability of the process of forming the isolation insulating layer 300. In addition, because the upper isolation insulating layer 320 and the lower isolation insulating layer 340 are formed at different vertical levels, the arrangement of the transistors in the semiconductor device 100 can be diversified.

[0088] Fig.18 is a circuit diagram of a semiconductor device according to an embodiment.

[0089] Reference Fig.18 In an embodiment, the semiconductor device 100 includes six transistors. For example, the semiconductor device 100 includes a first transmission transistor PT1, a second transmission transistor PT2, a first pull-up transistor PUT1, a second pull-up transistor PUT2, a first pull-down transistor PDT1, and a second pull-down transistor PDT2. The gate of the second pull-up transistor PUT2, the gate of the second pull-down transistor PDT2, and the bit line B / L are connected to the source / drain region of the first transmission transistor PT1. In addition, the gate of the first pull-up transistor PUT1, the gate of the first pull-down transistor PDT1, and the bit line B / L are connected to the source / drain region of the first transmission transistor PT1. Connected to the source / drain region of the second transfer transistor PT2.

[0090] In addition, each of the first transfer transistor PT1, the second transfer transistor PT2, the first pull-down transistor PDT1, and the second pull-down transistor PDT2 includes an NMOS FET, and each of the first pull-up transistor PUT1 and the second pull-up transistor PUT2 includes a PMOS FET. In addition, the first pull-up transistor PUT1 and the first pull-down transistor PDT1 constitute a complementary FET (cFET), and the second pull-up transistor PUT2 and the second pull-down transistor PDT2 constitute a complementary FET (cFET). In addition, the first pull-up transistor PUT1 and the first pull-down transistor PDT1 and the second pull-up transistor PUT2 and the second pull-down transistor PDT2 constitute a storage element of the semiconductor device 100.

[0091] In the semiconductor device 100 according to the embodiment, the first pull-up transistor PUT1, the first pull-down transistor PDT1, the second pull-up transistor PUT2 and the second pull-down transistor PDT2 include field effect transistors (FETs) having a three-dimensional stack (3DS) structure. In addition, the field effect transistors (FETs) having the 3DS structure include stacked nanosheet structures.

[0092] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: Lower transistor; as well as an upper transistor located at a higher vertical level than the lower transistor, wherein The lower transistor includes The lower source / drain region, and A lower gate structure and a lower isolation insulating layer are in contact with the side surface of the lower source / drain region, and the upper transistor includes upper source / drain regions, and An upper gate structure and an upper isolation insulating layer are in contact with side surfaces of the upper source / drain region, and a bottom surface of the lower isolation insulating layer is located at the same vertical level as a bottom surface of the lower gate structure.

2. The semiconductor device according to claim 1, wherein The lower gate structure includes lower gates and nanosheets stacked alternately, and The upper gate structure includes upper gates and nanosheets that are alternately stacked.

3. The semiconductor device according to claim 1, wherein The lower gate structure and the upper gate structure are spaced apart from each other in a vertical direction.

4. The semiconductor device according to claim 1, wherein The lower isolation insulating layer extends from the level of the upper surface of the lower gate structure to the level of the lower surface of the lower gate structure, and The upper isolation insulating layer extends from the level of the upper surface of the upper gate structure to the level of the lower surface of the upper gate structure.

5. The semiconductor device according to claim 1, wherein The upper isolation insulating layer includes a first seam therein, and The lower isolation insulating layer includes a second seam therein.

6. The semiconductor device according to claim 5, wherein: The first seam and the second seam are spaced apart from each other in a vertical direction.

7. The semiconductor device according to claim 1, wherein A top surface of the lower isolation insulating layer and a bottom surface of the upper isolation insulating layer are flat.

8. The semiconductor device according to claim 1, wherein A top surface of the lower isolation insulating layer and a bottom surface of the upper isolation insulating layer have rounded corners.

9. A semiconductor device comprising: Lower transistor; as well as an upper transistor located at a higher vertical level than the lower transistor, Wherein, the lower transistor comprises: Lower source / drain region, a lower gate structure and a lower isolation insulating layer in contact with the side surface of the lower source / drain region, wherein the lower gate and the lower nanosheet are alternately stacked in the lower gate structure, and a lower source / drain contact in contact with the lower source / drain region, Wherein, the upper transistor includes Upper source / drain region, an upper gate structure and an upper isolation insulating layer in contact with the side surface of the upper source / drain region, wherein the upper gate and the upper nanosheet are alternately stacked in the upper gate structure, and an upper source / drain contact in contact with the upper source / drain region, Wherein, a bottom surface of the lower isolation insulating layer is located at the same vertical level as a bottom surface of the lower gate structure. 10 . The semiconductor device according to claim 9 , further comprising a lower horizontal insulating layer disposed between the lower gate structure and the upper gate structure and extending in a horizontal direction.

11. The semiconductor device according to claim 10, wherein A top surface of the lower isolation insulating layer contacts the lower horizontal insulating layer, and A bottom surface of the upper isolating insulating layer contacts the lower horizontal insulating layer.

12. The semiconductor device according to claim 10, wherein The upper isolation insulating layer includes a first seam therein, the lower isolation insulating layer includes a second seam therein, and Each of the first seam and the second seam is spaced apart from the lower horizontal insulation layer in a vertical direction perpendicular to the horizontal direction.

13. The semiconductor device according to claim 9, further comprising: A through-isolating insulating layer extends from the level of the top surface of the upper source / drain contact to the level of the bottom surface of the lower gate structure, wherein A bottom surface of the through-isolating insulating layer is located at the same vertical level as the bottom surface of the lower gate structure.

14. The semiconductor device according to claim 13, wherein The through-isolating insulating layer includes a plurality of seams therein, and At least two of the plurality of seams are spaced apart from each other in a vertical direction.

15. The semiconductor device according to claim 9, wherein The lower transistor includes an NMOS transistor, and The upper transistor includes a PMOS transistor.

16. The semiconductor device according to claim 9, wherein The lower transistor includes a PMOS transistor, and The upper transistor includes an NMOS transistor.

17. A semiconductor device comprising: Lower transistor; as well as an upper transistor located at a higher vertical level than the lower transistor, wherein The lower transistor includes The lower source / drain region, and a lower gate, a lower nanosheet, and a lower isolation insulating layer, contacting the side surfaces of the lower source / drain region, and The upper transistor includes Upper source / drain region, an upper gate, an upper nanosheet, and an upper isolation insulating layer, contacting the side surfaces of the upper source / drain region, and an upper horizontal insulating layer, disposed on the upper gate and at the uppermost end, and extending in a horizontal direction, The lower gate and the lower nanosheet are stacked, The upper gate and the upper nanosheet are stacked, Each of the lower gate and the lower nanosheet is spaced apart from the lower isolation insulating layer in a first horizontal direction, Each of the upper gate and the upper nanosheet is spaced apart from the upper isolation insulating layer in the first horizontal direction, and A bottom surface of the lower isolation insulating layer is located at the same vertical level as a bottom surface of the lower gate at the lowermost end.

18. The semiconductor device according to claim 17, wherein: The lower isolation insulating layer and the upper isolation insulating layer are spaced apart from each other in a vertical direction perpendicular to the first horizontal direction.

19. The semiconductor device according to claim 17, further comprising a lower horizontal insulating layer, disposed between the lower isolation insulating layer and the upper isolation insulating layer and extending in a horizontal direction, wherein The lower horizontal insulating layer contacts at least one of the lower gate and the lower nanosheet, and contacts at least one of the upper gate and the upper nanosheet.

20. The semiconductor device according to claim 17, further comprising The insulating layer is penetrated and extends from the uppermost gate to the lowermost gate. The through-separating insulating layer includes a plurality of seams therein, and At least two of the plurality of seams are spaced apart from each other in a vertical direction perpendicular to the first horizontal direction.

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