Electrostatic discharge protection circuit

Abstract

The invention provides an electrostatic discharge protection circuit. The electrostatic discharge protection circuit comprises a main transistor, a resistor element and a control circuit, the first voltage end is coupled to the second end of the main transistor and the first end of the resistor element. The second voltage terminal is coupled to the first terminal of the main transistor. The control circuit is coupled between the second end of the resistor element and the control end of the main transistor. When an electrostatic discharge event occurs, the product of the capacitance value of the parasitic capacitor of the control circuit and the resistance value of the resistive element is greater than the duration of the electrostatic discharge event, and the control circuit turns on the main transistor so that the electrostatic discharge current flows through the main transistor.

Description

Technical Field

[0001] The invention relates to an integrated circuit, and in particular to an electrostatic discharge (ESD) protection circuit. Background Art

[0002] Among the many factors that damage integrated circuits due to electrical overstress (EOS), electrostatic discharge (ESD) may permanently damage semiconductor components within the integrated circuit, thereby affecting the function of the integrated circuit (or even making it unable to work properly). How to prevent ESD from damaging integrated circuits is one of the many technical issues in this field. Summary of the invention

[0003] The invention provides an electrostatic discharge protection circuit to prevent electrostatic discharge (ESD) from damaging an integrated circuit.

[0004] In one embodiment of the present invention, the electrostatic discharge protection circuit is coupled between the first voltage terminal and the second voltage terminal. The electrostatic discharge protection circuit includes a main transistor, a first resistor element and a control circuit. The first end of the main transistor is coupled to the second voltage terminal. The second end of the main transistor is coupled to the first voltage terminal. The first end of the first resistor element is coupled to the first voltage terminal. The first end of the control circuit is coupled to the first voltage terminal. The second end of the control circuit is coupled to the second voltage terminal. The input end of the control circuit is coupled to the second end of the first resistor element. The output end of the control circuit is coupled to the control end of the main transistor. The control circuit includes a first control transistor and a second control transistor. The first end of the first control transistor is coupled to the first end of the control circuit. The control end of the first control transistor is coupled to the input end of the control circuit. The first end of the second control transistor is coupled to the second end of the control circuit. The second end of the second control transistor is coupled to the second end of the first control transistor. The control end of the second control transistor is coupled to the input end of the control circuit. When an electrostatic discharge event occurs, the product of the capacitance of the parasitic capacitance of the second control transistor and the resistance of the first resistance element is greater than the duration of the electrostatic discharge event, and the control circuit is used to turn on the main transistor to allow the electrostatic discharge current to flow through the main transistor.

[0005] Based on the above, in the embodiments of the present invention, the product of the capacitance value of the parasitic capacitance of the second control transistor and the resistance value of the first resistor element is greater than the duration of the electrostatic discharge event, so the parasitic capacitance and the first resistor element can be used as an electrostatic discharge detector. When an electrostatic discharge event occurs, the parasitic capacitance and the first resistor element can trigger the control circuit to turn on the main transistor so that the electrostatic discharge current flows through the main transistor. Therefore, the electrostatic discharge protection circuit can prevent ESD from damaging the integrated circuit.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a circuit block diagram of an electrostatic discharge (ESD) protection circuit drawn according to an embodiment. Figure 2 is a circuit block diagram of an ESD protection circuit according to an embodiment of the present invention. Figure 3 is a circuit block diagram of an ESD protection circuit according to another embodiment of the present invention. Figure 4 is a circuit block diagram of an ESD protection circuit according to yet another embodiment of the present invention. Figure 5 FIG. 4 is a circuit block diagram of an ESD protection circuit according to yet another embodiment of the present invention. Figure 6 is a circuit block diagram of an ESD protection circuit according to another embodiment of the present invention. Figure 7 is a circuit block diagram of an ESD protection circuit according to another embodiment of the present invention. Figure 8 is a circuit block diagram of an ESD protection circuit 800 according to yet another embodiment of the present invention. Fig. 9 A circuit diagram of a pull-down circuit according to an embodiment of the present invention is drawn. Explanation of symbols: 100, 200, 300, 400, 500, 600, 700, 800: Electrostatic discharge (ESD) protection circuit 210, 310, 410, 510, 610, 710, 810, 910: Control circuit 620, 720, 820, 920: Pull-down circuit A6, A7, A8, A9: Input terminals B11, B21, B31, B41, B51, B61, B71, B81, B91: Main transistors C11: Capacitor Cgs, Cgd: parasitic capacitance M11, M12: transistors M21, M22, M31, M32, M41, M42, M45, M46, M51, M52, M61, M62, M71, M72, M81, M82, M85, M86, M91, M92, M93, M94: control transistor N9: Node PAD11, PAD12, PAD21, PAD22, PAD31, PAD32, PAD41, PAD42, PAD51, PAD52, PAD61, PAD62, PAD71, PAD72, PAD81, PAD82, PAD91, PAD92: Voltage terminal R11: Resistor R21, R31, R41, R51, R52, R61, R71, R81, R91, R92: resistor elements DETAILED DESCRIPTION

[0008] The term "coupled (or connected)" used in the entire specification of this case (including the scope of the patent application) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire specification of this case (including the scope of the patent application) are used to name the name of the element, or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor to limit the order of the elements. In addition, wherever possible, elements / components / steps with the same number in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same number or the same terminology in different embodiments can refer to the relevant descriptions of each other.

[0009] Figure 1 FIG. 1 is a circuit block diagram of an electrostatic discharge (ESD) protection circuit 100 according to an embodiment. The electrostatic discharge protection circuit 100 may be configured in an integrated circuit. Figure 1The ESD protection circuit 100 is coupled between a voltage terminal PAD11 and a voltage terminal PAD12. The voltage terminals PAD11 and PAD12 may be bonding pads or other types of connection pads. In some application examples, the voltage terminal PAD11 is used to transmit a system voltage (e.g., VDD), and the voltage terminal PAD12 is used to transmit a reference voltage (e.g., VSS). In other application examples, the voltage terminal PAD11 is used to transmit input / output data (or input / output signals) of an integrated circuit.

[0010] Figure 1 The ESD protection circuit 100 shown includes a resistor R11, a capacitor C11, a transistor M11, a transistor M12, and a main transistor B11. The voltage terminal PAD12 is coupled to the first end of the capacitor C11, the first end (e.g., source) of the transistor M12, and the first end (e.g., source) of the main transistor B11. The voltage terminal PAD11 is coupled to the first end of the resistor R11, the first end (e.g., source) of the transistor M11, and the second end (e.g., drain) of the main transistor B11. The second end of the resistor R11 and the second end of the capacitor C11 are coupled to the control end (e.g., gate) of the transistor M11 and the control end (e.g., gate) of the transistor M12. The second end (e.g., drain) of the transistor M11 and the second end (e.g., drain) of the transistor M12 are coupled to the control end (e.g., gate) of the main transistor B11.

[0011] In the normal operation mode of the integrated circuit, the resistor R11 and the capacitor C11 can provide a high logic voltage to the control end of the transistors M11 and M12, thereby turning the transistor M12 on and turning the transistor M11 and the main transistor B11 off. Therefore, the ESD protection circuit 100 will not affect the normal operation of the integrated circuit. When an ESD event (taking a positive pulse as an example) occurs at the voltage end PAD11, the resistor R11 and the capacitor C11 can provide a low voltage to the control end of the transistors M11 and M12, thereby turning the transistor M12 off and turning the transistor M11 and the main transistor B11 on. At this time, the main transistor B11 can transfer the ESD current of the voltage end PAD11 to the voltage end PAD12. Therefore, the ESD protection circuit 100 can prevent ESD from damaging the integrated circuit. Generally speaking, the capacitor C11 occupies a large area of ​​the integrated circuit.

[0012] Figure 21 is a circuit block diagram of an ESD protection circuit 200 according to an embodiment of the present invention. The ESD protection circuit 200 can be configured in an integrated circuit. The ESD protection circuit 200 is coupled between a voltage terminal PAD21 and a voltage terminal PAD22. The voltage terminals PAD21 and PAD22 can be pads or other types of connection pads. In some application examples, the voltage terminal PAD21 is used to transmit a system voltage (e.g., VDD), and the voltage terminal PAD22 is used to transmit a reference voltage (e.g., VSS). In other application examples, the voltage terminal PAD21 is used to transmit input / output data (or input / output signals) of the integrated circuit.

[0013] Figure 2 The ESD protection circuit 200 shown includes a resistor element R21 , a control circuit 210 , and a main transistor B21 . Figure 2 The main transistor B21 shown is, for example, an N-type transistor, that is, an N-channel Metal-Oxide-Semiconductor (NMOS) transistor, but is not limited thereto in other embodiments. The resistor element R21 is, for example, an actual resistor, or may be other elements equivalent to a resistor, such as an active element or an inductor, wherein the active element is, for example, a Metal-Oxide-Semiconductor (MOS) (which may be an N-channel or P-channel) transistor, a field-effect transistor (FET), a bipolar transistor (BJT), a heterojunction bipolar transistor (HBT) or a diode. The voltage terminal PAD22 is coupled to the second end of the control circuit 210 and the first end (e.g., source) of the main transistor B21. The voltage terminal PAD21 is coupled to the first end of the resistor element R21, the first end of the control circuit 210 and the second end (e.g., drain) of the main transistor B21. The input end of the control circuit 210 is coupled to the second end of the resistor element R21. The output end of the control circuit 210 is coupled to the control end (e.g., gate) of the main transistor B21. When an ESD event occurs, the control circuit 210 can turn on the main transistor B21 so that the ESD current flows through the main transistor B21. In the present embodiment, the ESD event takes a positive pulse as an example, and the ESD current, for example, flows from the voltage terminal PAD21 through the main transistor B21 and is directed to the voltage terminal PAD22. In other embodiments, for example, the ESD event takes a negative pulse as an example, and the ESD current may also flow from the voltage terminal PAD22 through the main transistor B21 and be directed to the voltage terminal PAD21.

[0014] exist Figure 2In the illustrated embodiment, the control circuit 210 includes a control transistor M21 and a control transistor M22 . Figure 2 The control transistor M21 shown is, for example, a P-type transistor, that is, a P-channel Metal-Oxide-Semiconductor (PMOS) transistor, and the control transistor M22 is, for example, an N-type transistor, that is, an N-channel Metal-Oxide-Semiconductor transistor, but is not limited thereto in other embodiments. The sizes of the main transistor B21, the control transistor M21, and the control transistor M22 can be determined according to actual design. For example, in some application examples, the size of the main transistor B21 is larger than the size of the control transistor M22. The first end (for example, source) of the control transistor M21 is coupled to the first end of the control circuit 210. The control end (for example, gate) of the control transistor M21 is coupled to the input end of the control circuit 210. The first end (for example, source) of the control transistor M22 is coupled to the second end of the control circuit 210. The second end (for example, drain) of the control transistor M22 is coupled to the second end (for example, drain) of the control transistor M21. The control end (for example, gate) of the control transistor M22 is coupled to the input end of the control circuit 210. The second terminals of the control transistors M22 and M21 are coupled to the output terminal of the control circuit 210 .

[0015] In the normal working mode of the integrated circuit, the resistor element R21 can provide a high logic voltage to the control end of the control transistor M22 and M21, thereby turning on the control transistor M22 and turning off the control transistor M21 and the main transistor B21. Therefore, the ESD protection circuit 200 will not affect the normal operation of the integrated circuit. When an ESD event (taking a positive pulse as an example) occurs at the voltage end PAD21, the product of the capacitance value of the parasitic capacitance Cgs (effective capacitance between the gate and the source) of the control transistor M22 and the resistance value of the resistor element R21 is greater than the duration of the ESD event, and the resistor element R21 and the parasitic capacitance Cgs of the control transistor M22 can provide a low voltage to the control end of the control transistor M22 and M21, thereby turning off the control transistor M22 and turning on the control transistor M21 and the main transistor B21 (the potential of the output end of the control circuit 210 is a high potential). At this time, the main transistor B21 can transmit the ESD current of the voltage end PAD21 to the voltage end PAD22. Therefore, the ESD protection circuit 200 can prevent ESD from damaging the integrated circuit. Figure 1 In the illustrated embodiment, the capacitor C11 may be omitted to save the area of ​​the integrated circuit. In addition, the resistance value of the resistor element R21 may be an equivalent resistance value of the resistor element R21 when an ESD event occurs.

[0016] Figure 3is a circuit block diagram of an ESD protection circuit 300 according to another embodiment of the present invention. Figure 3 The voltage terminal PAD31, the voltage terminal PAD32 and the ESD protection circuit 300 can refer to Figure 2 The voltage terminal PAD21 , the voltage terminal PAD22 and the ESD protection circuit 200 are described in detail and can be deduced by analogy. Figure 3 The ESD protection circuit 300 shown includes a resistor element R31 , a control circuit 310 , and a main transistor B31 . Figure 3 The main transistor B31 shown is, for example, a P-type transistor, that is, a P-channel metal oxide semiconductor transistor, but is not limited thereto in other embodiments. Figure 3 The resistor element R31, the control circuit 310 and the main transistor B31 can refer to Figure 2 The relevant descriptions of the resistor element R21, the control circuit 210, and the main transistor B21 are shown and can be deduced by analogy. When an ESD event occurs, the control circuit 310 can turn on the main transistor B31 to allow the ESD current to flow through the main transistor B31. In this embodiment, the ESD event takes a positive pulse as an example, and the ESD current, for example, flows from the voltage terminal PAD31 through the main transistor B31 and is directed to the voltage terminal PAD32. In other embodiments, for example, the ESD event takes a negative pulse as an example, and the ESD current may also flow from the voltage terminal PAD32 through the main transistor B31 and be directed to the voltage terminal PAD31.

[0017] exist Figure 3 In the illustrated embodiment, the control circuit 310 includes a control transistor M31 and a control transistor M32 . Figure 3 The control transistor M32 shown is, for example, a P-type transistor, that is, a P-channel metal oxide semiconductor transistor, and the control transistor M31 is, for example, an N-type transistor, that is, an N-channel metal oxide semiconductor transistor, but is not limited thereto in other embodiments. The sizes of the main transistor B31, the control transistor M32, and the control transistor M31 can be determined according to the actual design. For example, in some application examples, the size of the main transistor B31 is larger than the size of the control transistor M32. The first end (e.g., drain) of the control transistor M31 is coupled to the first end of the control circuit 310. The control end (e.g., gate) of the control transistor M31 is coupled to the input end of the control circuit 310. The first end (e.g., drain) of the control transistor M32 is coupled to the second end of the control circuit 310. The second end (e.g., source) of the control transistor M32 is coupled to the second end (e.g., source) of the control transistor M31. The control end (e.g., gate) of the control transistor M32 is coupled to the input end of the control circuit 310. The second terminals of the control transistors M32 and M31 are coupled to the output terminal of the control circuit 310 .

[0018] In the normal working mode of the integrated circuit, the resistor element R31 can provide a high logic voltage to the control terminals of the control transistors M31 and M32, thereby turning on the control transistor M31 and turning off the control transistor M32 and the main transistor B31. Therefore, the ESD protection circuit 300 will not affect the normal operation of the integrated circuit. When an ESD event (taking a positive pulse as an example) occurs at the voltage terminal PAD31, the product of the capacitance value of the parasitic capacitance Cgd (effective capacitance between the gate and the drain) of the control transistor M32 and the resistance value of the resistor element R31 is greater than the duration of the ESD event, and the resistor element R31 and the parasitic capacitance Cgd of the control transistor M32 can provide a low voltage to the control terminals of the control transistors M31 and M32, thereby turning off the control transistor M31 and turning on the control transistor M32 and the main transistor B31 (the potential of the output terminal of the control circuit 310 is a low potential). At this time, the main transistor B31 can transmit the ESD current of the voltage terminal PAD31 to the voltage terminal PAD32. Therefore, the ESD protection circuit 300 can prevent ESD from damaging the integrated circuit, and can also omit the capacitor C11, thereby saving the area of ​​the integrated circuit. In addition, the resistance value of the resistor element R31 can be the equivalent resistance value of the resistor element R31 when an ESD event occurs.

[0019] Figure 4 is a circuit block diagram of an ESD protection circuit 400 according to yet another embodiment of the present invention. Figure 4 The voltage terminal PAD41, the voltage terminal PAD42 and the ESD protection circuit 400 can refer to Figure 2 The descriptions of the voltage terminal PAD21 , the voltage terminal PAD22 and the ESD protection circuit 200 are similar and can be deduced by analogy. Figure 4 The illustrated ESD protection circuit 400 includes a resistor element R41 , a control circuit 410 , and a main transistor B41 . Figure 4 The resistor element R41, the control circuit 410 and the main transistor B41 can refer to Figure 2 The relevant descriptions of the resistor element R21, the control circuit 210, and the main transistor B21 are shown and can be deduced by analogy. When an ESD event occurs, the control circuit 410 can turn on the main transistor B41 to allow the ESD current to flow through the main transistor B41. In this embodiment, the ESD event takes a positive pulse as an example, and the ESD current, for example, flows from the voltage terminal PAD41 through the main transistor B41 and is directed to the voltage terminal PAD42. In other embodiments, for example, the ESD event takes a negative pulse as an example, and the ESD current may also flow from the voltage terminal PAD42 through the main transistor B41 and be directed to the voltage terminal PAD41.

[0020] exist Figure 4In the illustrated embodiment, the control circuit 410 includes a control transistor M41 , a control transistor M42 , a control transistor M45 , and a control transistor M46 . Figure 4 The main transistor B41 shown is, for example, a P-type transistor, that is, a P-channel metal oxide semiconductor transistor, the control transistors M41 and M45 are, for example, P-type transistors, that is, P-channel metal oxide semiconductor transistors, and the control transistors M42 and M46 are, for example, N-type transistors, that is, N-channel metal oxide semiconductor transistors, but in other embodiments, it is not limited thereto. The sizes of the main transistor B41, the control transistor M41, the control transistor M42, the control transistor M45, and the control transistor M46 can be determined according to actual design. For example, in some application examples, the size of the main transistor B41 is larger than the size of the control transistor M45. The first end (e.g., source) of the control transistor M41 and the first end (e.g., source) of the control transistor M45 are coupled to the first end of the control circuit 410. The control end (e.g., gate) of the control transistor M41 and the control end (e.g., gate) of the control transistor M42 are coupled to the input end of the control circuit 410. The first end (e.g., source) of the control transistor M42 and the first end (e.g., source) of the control transistor M46 are coupled to the second end of the control circuit 410. The second end (e.g., drain) of the control transistor M42 and the second end (e.g., drain) of the control transistor M41 are coupled to the control end (e.g., gate) of the control transistor M46 and the control end (e.g., gate) of the control transistor M45. The second ends of the control transistors M45 and M46 are coupled to the output end of the control circuit 410.

[0021] In the normal working mode of the integrated circuit, the resistor element R41 can provide a high logic voltage to the control terminals of the control transistors M42 and M41, thereby turning on the control transistors M42 and M45 and turning off the control transistors M41, M46 and the main transistor B41. Therefore, the ESD protection circuit 400 will not affect the normal operation of the integrated circuit. When an ESD event (taking a positive pulse as an example) occurs at the voltage terminal PAD41, the product of the capacitance value of the parasitic capacitance Cgs (effective capacitance between the gate and the source) of the control transistor M42 and the resistance value of the resistor element R41 is greater than the duration of the ESD event, and the resistor element R41 and the parasitic capacitance Cgs of the control transistor M42 can provide a low voltage to the control terminals of the control transistors M42 and M41, thereby turning off the control transistors M42 and M45 and turning on the control transistors M41, M46 and the main transistor B41 (the potential of the second terminals of the control transistors M41 and M42 is a high potential, so that the potential of the output terminal of the control circuit 410 is a low potential). At this time, the main transistor B41 can transmit the ESD current of the voltage terminal PAD41 to the voltage terminal PAD42. Therefore, the ESD protection circuit 400 can prevent ESD from damaging the integrated circuit, and the capacitor C11 can be omitted to save the area of ​​the integrated circuit. In addition, the resistance value of the resistor element R41 can be the equivalent resistance value of the resistor element R41 when the ESD event occurs.

[0022] Figure 5 FIG. 5 is a circuit block diagram of an ESD protection circuit 500 according to yet another embodiment of the present invention. Figure 5 The voltage terminal PAD51, the voltage terminal PAD52 and the ESD protection circuit 500 can refer to Figure 2 The descriptions of the voltage terminal PAD21 , the voltage terminal PAD22 and the ESD protection circuit 200 are similar and can be deduced by analogy. Figure 5 The ESD protection circuit 500 shown includes a resistor element R51, a control circuit 510 and a main transistor B51. The control circuit 510 includes a control transistor M51 and a control transistor M52. Figure 5 The resistor element R51, the control circuit 510, the control transistor M51, the control transistor M52, and the main transistor B51 can refer to Figure 2The related descriptions of the resistor element R21, the control circuit 210, the control transistor M21, the control transistor M22, and the main transistor B21 are shown and are analogized, so they are not repeated. When an ESD event occurs, the control circuit 510 can turn on the main transistor B51 to allow the ESD current to flow through the main transistor B51. In the present embodiment, the ESD event takes a positive pulse as an example, and the ESD current, for example, flows from the voltage terminal PAD51 through the main transistor B51 and is directed to the voltage terminal PAD52. In other embodiments, for example, the ESD event takes a negative pulse as an example, and the ESD current may also flow from the voltage terminal PAD52 through the main transistor B51 and be directed to the voltage terminal PAD51.

[0023] Different from Figure 2 The embodiment shown is that Figure 5 The ESD protection circuit 500 shown further includes a resistor element R52. A first end of the resistor element R52 is coupled to the control end of the main transistor B51. A second end of the resistor element R52 is coupled to the voltage end PAD52. In the normal working mode, during the initialization phase of the integrated circuit, the system voltage from the voltage end PAD51 gradually rises, but may not reach the turn-on voltage of the control transistor M52, so the transistor M52 cannot be turned on, thereby making the potential of the output end of the control circuit 510 high. In this case, it is easy to mislead the main transistor B51 (corresponding to the reference Figure 2 Embodiment, in the normal working mode, the output terminal of the control circuit 210 must be at a low potential in order to cut off the main transistor B21); and the addition of the resistor element R52 can maintain the output terminal of the control circuit 510 at a low potential in the normal working mode, thereby preventing the main transistor B51 from being mis-turned on. Among them, the resistance value of the resistor element R52 can be set according to the actual design. For example, in some application examples, the resistance value of the resistor element R52 is greater than or equal to 10KΩ, and less than or equal to 10MΩ. In a preferred embodiment, the resistor element R52 is less than or equal to 5MΩ. Furthermore, when an ESD event occurs, if the resistance value of the resistor element R52 is less than 10KΩ, the potential of the output terminal of the control circuit 510 may be zero, and the main transistor B51 cannot be turned on (corresponding to reference Figure 2 In the embodiment, when an ESD event occurs, the output terminal of the control circuit 210 must be at a high potential to turn on the main transistor B21). In the normal working mode, if the resistance value of the resistor element R52 is greater than 10MΩ, the output terminal of the control circuit 510 may be floating, that is, the resistor element R52 cannot function. Figure 5 The resistor element R52 can be configured in the same manner as shown in FIG. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 6, Figure 7 , Figure 8 or Fig. 9 The ESD protection circuit is shown in FIG.

[0024] Figure 6 FIG. 4 is a circuit block diagram of an ESD protection circuit 600 according to another embodiment of the present invention. Figure 6 The voltage terminal PAD61, the voltage terminal PAD62 and the ESD protection circuit 600 can refer to Figure 2 The voltage terminal PAD21 , the voltage terminal PAD22 and the ESD protection circuit 200 are described in detail and can be deduced by analogy. Figure 6 The ESD protection circuit 600 shown includes a resistor element R61, a control circuit 610 and a main transistor B61. The control circuit 610 includes a control transistor M61 and a control transistor M62. Figure 6 The resistor element R61, the control circuit 610, the control transistor M61, the control transistor M62, and the main transistor B61 can refer to Figure 2 The related descriptions of the resistor element R21, the control circuit 210, the control transistor M21, the control transistor M22, and the main transistor B21 are shown and are analogized, so they are not repeated. When an ESD event occurs, the control circuit 610 can turn on the main transistor B61 to allow the ESD current to flow through the main transistor B61. In the present embodiment, the ESD event takes a positive pulse as an example, and the ESD current, for example, flows from the voltage terminal PAD61 through the main transistor B61 and is directed to the voltage terminal PAD62. In other embodiments, for example, the ESD event takes a negative pulse as an example, and the ESD current may also flow from the voltage terminal PAD62 through the main transistor B61 and be directed to the voltage terminal PAD61.

[0025] Different from Figure 2 The embodiment shown is that Figure 6The ESD protection circuit 600 further includes a pull-down circuit 620. The pull-down circuit 620 is coupled between the input terminal A6 of the control circuit 610, the voltage terminal PAD61, and the voltage terminal PAD62. That is, the pull-down circuit 620 is coupled between the first terminal and the second terminal of the resistor element R61. When an ESD event occurs, the pull-down circuit 620 can pull down the potential of the input terminal A6 of the control circuit 610 and keep it at a low potential. The ESD energy from the voltage terminal PAD61 is gradually released until the potential difference between the input terminal A6 of the control circuit 610 and the voltage terminal PAD61 is lower than the critical voltage, indicating that the ESD event is over and the normal working mode can be returned. The pull-down circuit 620 can change the potential of the input terminal A6 of the control circuit 610 from a low potential to a high potential to cut off the main transistor B61. Thus, in this embodiment, the ESD protection circuit 600 utilizes the pull-down circuit 620 to assist in pulling current during an ESD event, so that the potential of the input terminal A6 of the control circuit 610 is pulled down and maintained at a low potential, thereby enabling the main transistor B61 to be smoothly turned on during the ESD event, thereby more effectively preventing ESD from damaging the integrated circuit.

[0026] Figure 7 is a circuit block diagram of an ESD protection circuit 700 according to another embodiment of the present invention. Figure 7 The voltage terminal PAD71, the voltage terminal PAD72 and the ESD protection circuit 700 can refer to Figure 2 The voltage terminal PAD21 , the voltage terminal PAD22 and the ESD protection circuit 200 are described in detail and can be deduced by analogy. Figure 7 The ESD protection circuit 700 shown includes a resistor element R71, a control circuit 710, and a main transistor B71. The control circuit 710 includes a control transistor M71 and a control transistor M72. Figure 7 The resistor element R71, the control circuit 710, the control transistor M71, the control transistor M72 and the main transistor B71 can refer to Figure 3 The related descriptions of the resistor element R31, the control circuit 310, the control transistor M31, the control transistor M32, and the main transistor B31 are shown and are analogized, so they are not repeated. When an ESD event occurs, the control circuit 710 can turn on the main transistor B71 to allow the ESD current to flow through the main transistor B71. In the present embodiment, the ESD event takes a positive pulse as an example, and the ESD current, for example, flows from the voltage terminal PAD71 through the main transistor B71 and is directed to the voltage terminal PAD72. In other embodiments, for example, the ESD event takes a negative pulse as an example, and the ESD current may also flow from the voltage terminal PAD72 through the main transistor B71 and be directed to the voltage terminal PAD71.

[0027] Different from Figure 3 The embodiment shown is that Figure 7 The ESD protection circuit 700 shown further includes a pull-down circuit 720. The pull-down circuit 720 is coupled between the input terminal A7 of the control circuit 710, the voltage terminal PAD71, and the voltage terminal PAD72. That is, the pull-down circuit 720 is coupled between the first terminal and the second terminal of the resistor element R71. When an ESD event occurs, the pull-down circuit 720 can pull down the potential of the input terminal A7 of the control circuit 710 and keep it at a low potential. The ESD energy from the voltage terminal PAD71 is gradually discharged until the potential difference between the input terminal A7 of the control circuit 710 and the voltage terminal PAD71 is lower than the critical voltage, indicating that the ESD event is over and the normal working mode can be returned. The pull-down circuit 720 can change the potential of the input terminal A7 of the control circuit 710 from a low potential to a high potential to cut off the main transistor B71. Thus, in this embodiment, the ESD protection circuit 700 utilizes the pull-down circuit 720 to assist in pulling current during an ESD event, so that the potential of the input terminal A6 of the control circuit 710 is pulled down and maintained at a low potential, thereby enabling the main transistor B71 to be smoothly turned on during the ESD event, thereby more effectively preventing ESD from damaging the integrated circuit.

[0028] Figure 8 is a circuit block diagram of an ESD protection circuit 800 according to yet another embodiment of the present invention. Figure 8 The voltage terminal PAD81, the voltage terminal PAD82 and the ESD protection circuit 800 can refer to Figure 2 The voltage terminal PAD21 , the voltage terminal PAD22 and the ESD protection circuit 200 are described in detail and can be deduced by analogy. Figure 8 The ESD protection circuit 800 shown includes a resistor element R81, a control circuit 810, and a main transistor B81. The control circuit 810 includes a control transistor M81, a control transistor M82, a control transistor M85, and a control transistor M86. Figure 8 The resistor element R81, the control circuit 810, the control transistor M81, the control transistor M82, the control transistor M85, the control transistor M86, and the main transistor B81 can refer to Figure 4The related descriptions of the resistor element R41, the control circuit 410, the control transistor M41, the control transistor M42, the control transistor M45, the control transistor M46, and the main transistor B41 are shown and are analogized, so they are not repeated. When an ESD event occurs, the control circuit 810 can turn on the main transistor B81 to allow the ESD current to flow through the main transistor B81. In the present embodiment, the ESD event takes a positive pulse as an example, and the ESD current, for example, flows from the voltage terminal PAD81 through the main transistor B81 and is directed to the voltage terminal PAD82. In other embodiments, for example, the ESD event takes a negative pulse as an example, and the ESD current may also flow from the voltage terminal PAD82 through the main transistor B81 and be directed to the voltage terminal PAD81.

[0029] Different from Figure 4 The embodiment shown is that Figure 8 The ESD protection circuit 800 shown further includes a pull-down circuit 820. The pull-down circuit 820 is coupled between the input terminal A8 of the control circuit 810, the voltage terminal PAD81, and the voltage terminal PAD82. That is, the pull-down circuit 820 is coupled between the first terminal and the second terminal of the resistor element R81. When an ESD event occurs, the pull-down circuit 820 can pull down the potential of the input terminal A8 of the control circuit 810 and keep it at a low potential. The ESD energy from the voltage terminal PAD81 is gradually discharged until the potential difference between the input terminal A8 of the control circuit 810 and the voltage terminal PAD81 is lower than the critical voltage, indicating that the ESD event is over and the normal working mode can be returned. The pull-down circuit 820 can change the potential of the input terminal A8 of the control circuit 810 from a low potential to a high potential to cut off the main transistor B81. Thus, in this embodiment, the ESD protection circuit 800 utilizes the pull-down circuit 820 to assist in pulling current during an ESD event, so that the potential of the input terminal A8 of the control circuit 810 is pulled down and maintained at a low potential, thereby enabling the main transistor B81 to be smoothly turned on during the ESD event, thereby more effectively preventing ESD from damaging the integrated circuit.

[0030] Fig. 9 A circuit diagram of a pull-down circuit 920 according to an embodiment of the present invention is drawn. Further explanation: Fig. 9 It shows a voltage terminal PAD91, a voltage terminal PAD92, a resistor element R91, a control circuit 910, a pull-down circuit 920 and a main transistor B91. Fig. 9 The voltage terminal PAD91, the voltage terminal PAD92, the resistor R91, the control circuit 910 (including the control transistor M91 and the control transistor M92), the pull-down circuit 920 and the main transistor B91 can refer to Figure 6The voltage terminal PAD61, the voltage terminal PAD62, the resistor R61, the control circuit 610, the pull-down circuit 620 and the main transistor B61 are described and deduced by analogy, or by reference to the related descriptions of the voltage terminal PAD61, the voltage terminal PAD62, the resistor R61, the control circuit 610, the pull-down circuit 620 and the main transistor B61. Figure 7 The voltage terminal PAD71, the voltage terminal PAD72, the resistor R71, the control circuit 710, the pull-down circuit 720 and the main transistor B71 are described and deduced by analogy, or by reference to Figure 8 The related descriptions of the voltage terminal PAD81, the voltage terminal PAD82, the resistor element R81, the control circuit 810, the pull-down circuit 820 and the main transistor B81 are described and can be deduced by analogy. Fig. 9 The pull-down circuit 920 shown can be used as Figure 6 One of many embodiments of the pull-down circuit 620 shown, or as Figure 7 One of many embodiments of the pull-down circuit 720 shown, or as Figure 8 One of many embodiments of pull-down circuit 820 is shown.

[0031] exist Fig. 9 In the illustrated embodiment, the pull-down circuit 920 includes a control transistor M93, a control transistor M94, and a resistor R92. The resistor R92 is, for example, an actual resistor, or may be other elements equivalent to a resistor, such as an active element or an inductor, wherein the active element is, for example, a metal oxide semiconductor (which may be an N-channel or P-channel) transistor, a field effect transistor, a bipolar junction transistor, a heterojunction bipolar transistor, or a diode. Fig. 9 The control transistor M93 shown is a P-type transistor, that is, a P-channel metal oxide semiconductor transistor, and the control transistor M94 is an N-type transistor, that is, an N-channel metal oxide semiconductor transistor, but it is not limited to this in other embodiments. The first end (e.g., source) of the control transistor M93 is coupled to the first end of the resistor element R91. The control end (e.g., gate) of the control transistor M93 is coupled to the input end A9 of the control circuit 910. The first end (e.g., source) of the control transistor M94 is coupled to the voltage end PAD92. The second end (e.g., drain) of the control transistor M94 is coupled to the input end A9 of the control circuit 910. The control end (e.g., gate) of the control transistor M94 is coupled to the second end (e.g., drain) of the control transistor M93. The first end of the resistor element R92 is coupled to the second end of the control transistor M93 and the control end of the control transistor M94. The second end of the resistor element R92 is coupled to the voltage end PAD92. In addition, it should be noted that, Figure 6 , Figure 7 , Figure 8The pull-down circuits 620, 720, and 820 are respectively drawn as examples to couple the voltage terminals PAD62, PAD72, and PAD82 through a node, but this drawing method only indicates that the pull-down circuits 620, 720, and 820 are respectively coupled to the voltage terminals PAD62, PAD72, and PAD82, and does not limit the coupling method to only one node. Fig. 9 Further, the exemplary components of the pull-down circuit 920 and the exemplary coupling relationship between the pull-down circuit 920 and the voltage terminal PAD92 are shown, where the resistor element R92 and the control transistor M94 are coupled to the voltage terminal PAD92 via two nodes respectively. Such a coupling method can be applied to Figure 6 , Figure 7 , Figure 8 In the embodiment of .

[0032] In the normal working mode of the integrated circuit, the potential difference between the input terminal A9 of the control circuit 910 and the voltage terminal PAD91 is quite small (lower than the critical voltage, or even 0), so the control transistor M93 is turned off. When the control transistor M93 is turned off, the resistor R92 can pull down the control terminal voltage of the control transistor M94 to a low logic level, so the control transistor M94 is turned off. At this time, the pull-down circuit 920 does not affect the input terminal A9 of the control circuit 910.

[0033] When an ESD event (taking a positive pulse as an example) occurs at the voltage terminal PAD91, the parasitic capacitance (Cgs) of the resistor element R21 and the control transistor M92 can provide a low voltage to the input terminal A9 of the control circuit 910, thereby turning on the control transistor M93. That is to say, at this time, the potential difference between the first end of the control transistor M93 and the input terminal A9 of the control circuit 910 is greater than the turn-on voltage of the control transistor M93. When the control transistor M93 is turned on, the control transistor M93 can pull up the control terminal voltage of the control transistor M94 to a high logic level, so the control transistor M94 is turned on. The turned-on control transistor M94 can pull down the potential of the input terminal A9 of the control circuit 910 and maintain it at a low potential, for example, the potential is pulled down to zero. At this time, the main transistor B91 can act as a small resistor in the turned-on state, and when the ESD current flows, the ESD voltage occurring at the voltage terminal PAD91 can be pulled down and fixed at the clamping voltage. When the potential difference between the input terminal A9 of the control circuit 910 and the voltage terminal PAD91 is lower than the critical voltage of the control transistor M93, it indicates that the ESD event is over and it is possible to return to the normal working mode. The control transistors M93 and M94 are cut off. Therefore, the pull-down circuit 920 can change the potential of the input terminal A9 of the control circuit 910 from a low potential to a high potential to cut off the main transistor B91.

[0034] The resistance value of the resistor R92 can be set according to the actual design. For example, in some application examples, the resistance value of the resistor R92 is greater than or equal to 10Ω and less than or equal to 10MΩ. In a preferred embodiment, the resistor R92 is less than or equal to 5MΩ. Further, when an ESD event occurs, if the resistance value of the resistor R92 is less than 10Ω, the potential of the node N9 between the first end of the resistor R92, the second end of the control transistor M93 and the control end of the control transistor M94 may be zero, and the control transistor M94 cannot be turned on, and the potential of the input terminal A9 of the control circuit 910 cannot be pulled down and maintained at a low potential. In the normal working mode, if the resistance value of the resistor R92 is greater than 10MΩ, the node N9 may be floating. In this way, the resistor R92 is easy to couple with other nearby wirings, so that the pull-down circuit 920 is easily affected by the signals on other wirings, which is an undesirable situation. In addition, the resistance value of the resistance element R92 may be an equivalent resistance value of the resistance element R92.

[0035] According to the above, in this embodiment, the control transistor M93, the control transistor M94 and the resistor R92 of the pull-down circuit 920 are used to assist in pulling current during the ESD event, so that the potential of the input terminal A9 of the control circuit 910 is pulled down and maintained at a low potential, thereby enabling the main transistor B81 to be smoothly turned on during the ESD event, which can more effectively prevent ESD from damaging the integrated circuit. The control transistor M93 and the control transistor M94 are active components that can be controlled by voltage; compared to Figure 1 The capacitor C11, control transistor M93 and control transistor M94 used in the embodiment can pull down the potential of the input terminal A9 of the control circuit 910 faster. In addition, in some embodiments, the resistor R92 can also be an active element, which can further speed up the speed of pulling down the potential of the input terminal A9 of the control circuit 910 by voltage control. Figure 6 , 7 , 8, the operation of the ESD protection circuits 600, 700, 800 can be performed more quickly and effectively.

[0036] In summary, the product of the capacitance value of the parasitic capacitor (such as Cgs or Cgd) and the resistance value of the resistor element (such as R21, R31, R41, R51, R61, R71, R81 or R91) in the above embodiments is greater than the duration of the ESD event, so the parasitic capacitor and the resistor element can be used as an ESD detector. When an ESD event occurs, the parasitic capacitor and the resistor element can trigger the control circuit (e.g., 210, 310, 410, 510, 610, 710, 810, or 910) to turn on the main transistor (e.g., B21, B31, B41, B51, B61, B71, B81, or B91) so that the ESD current is transmitted between the first voltage terminal (e.g., PAD21, PAD31, PAD41, PAD51, PAD61, PAD71, PAD81, or PAD91) and the second voltage terminal (e.g., PAD22, PAD32, PAD42, PAD52, PAD62, PAD72, PAD82, or PAD92). Therefore, the ESD protection circuits of the above embodiments can prevent ESD from damaging the integrated circuit, and because the above embodiments use parasitic capacitors to replace large capacitors, the area of ​​the integrated circuit can be saved.

[0037] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. An electrostatic discharge protection circuit, It is characterized in that Coupled between a first voltage terminal and a second voltage terminal, the electrostatic discharge protection circuit comprises: a main transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the main transistor is coupled to the second voltage terminal, and the second terminal of the main transistor is coupled to the first voltage terminal; a first resistor element having a first end and a second end, wherein the first end of the first resistor element is coupled to the first voltage end; and A control circuit having a first terminal, a second terminal, an input terminal and an output terminal, wherein the first terminal of the control circuit is coupled to the first voltage terminal, the second terminal of the control circuit is coupled to the second voltage terminal, the input terminal of the control circuit is coupled to the second terminal of the first resistor element, the output terminal of the control circuit is coupled to the control terminal of the main transistor, and the control circuit comprises: a first control transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first control transistor is coupled to the first terminal of the control circuit, and the control terminal of the first control transistor is coupled to the input terminal of the control circuit; and a second control transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second control transistor is coupled to the second terminal of the control circuit, the second terminal of the second control transistor is coupled to the second terminal of the first control transistor, and the control terminal of the second control transistor is coupled to the input terminal of the control circuit; When an electrostatic discharge event occurs, the product of a parasitic capacitance of the second control transistor and a resistance of the first resistor element is greater than a duration of the electrostatic discharge event, and the control circuit is used to turn on the main transistor to allow the electrostatic discharge current to flow through the main transistor.

2. The electrostatic discharge protection circuit according to claim 1, It is characterized in that The main transistor is an N-type transistor, and the size of the main transistor is larger than the size of the second control transistor.

3. The electrostatic discharge protection circuit according to claim 2, It is characterized in that When the electrostatic discharge event occurs, the first control transistor is turned on, the second control transistor is turned off, and the potential of the output end of the control circuit is a high potential to turn on the main transistor.

4. The electrostatic discharge protection circuit according to claim 3, It is characterized in that The first control transistor is a P-type transistor, and the second control transistor is an N-type transistor.

5. The electrostatic discharge protection circuit according to claim 1, It is characterized in that The main transistor is a P-type transistor, and the size of the main transistor is larger than the size of the second control transistor.

6. The electrostatic discharge protection circuit according to claim 5, It is characterized in that When the electrostatic discharge event occurs, the first control transistor is turned off, the second control transistor is turned on, and the potential of the output end of the control circuit is low to turn on the main transistor.

7. The electrostatic discharge protection circuit according to claim 6, It is characterized in that The first control transistor is an N-type transistor, and the second control transistor is a P-type transistor.

8. The electrostatic discharge protection circuit according to claim 1, It is characterized in that Also includes: a pull-down circuit coupled between the input terminal of the control circuit, the first voltage terminal and the second voltage terminal, When the electrostatic discharge event occurs, the potential of the input terminal of the control circuit is a low potential.

9. The electrostatic discharge protection circuit according to claim 8, It is characterized in that When the potential difference between the input terminal of the control circuit and the first voltage terminal is lower than a critical voltage, the potential of the input terminal of the control circuit changes from a low potential to a high potential to turn off the main transistor.

10. The electrostatic discharge protection circuit according to claim 8, It is characterized in that The pull-down circuit is coupled to the first end and the second end of the first resistor element.

11. The electrostatic discharge protection circuit according to claim 8, It is characterized in that The pull-down circuit includes: a third control transistor, wherein a first terminal of the third control transistor is coupled to the first terminal of the first resistance element, and a control terminal of the third control transistor is coupled to the input terminal of the control circuit; and A fourth control transistor, wherein a first terminal of the fourth control transistor is coupled to the second voltage terminal, a second terminal of the fourth control transistor is coupled to the input terminal of the control circuit, and a control terminal of the fourth control transistor is coupled to a second terminal of the three control transistors.

12. The electrostatic discharge protection circuit according to claim 11, It is characterized in that The pull-down circuit further includes: A second resistance element, wherein a first end of the second resistance element is coupled to the second end of the third control transistor and the control end of the fourth control transistor, and a second end of the second resistance element is coupled to the second voltage end.

13. The electrostatic discharge protection circuit according to claim 12, It is characterized in that The resistance value of the second resistor element is greater than or equal to 10Ω and less than or equal to 10MΩ.

14. The electrostatic discharge protection circuit according to claim 11, It is characterized in that When the electrostatic discharge event occurs, the third control transistor is turned on, and the fourth control transistor is turned on, so that the potential of the input terminal of the control circuit is maintained at a low potential.

15. The electrostatic discharge protection circuit according to claim 14, It is characterized in that The third control transistor is a P-type transistor, and the fourth control transistor is an N-type transistor.

16. The electrostatic discharge protection circuit according to claim 1, It is characterized in that Also includes a third resistance element, wherein a first end of the third resistance element is coupled to the control end of the main transistor, and a second end of the third resistance element is coupled to the second voltage end.

17. The electrostatic discharge protection circuit according to claim 16, It is characterized in that The resistance value of the third resistor element is greater than or equal to 10KΩ and less than or equal to 10MΩ.

18. The electrostatic discharge protection circuit according to claim 1, It is characterized in that The control circuit further includes: a fifth control transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fifth control transistor is coupled to the first terminal of the control circuit, the second terminal of the fifth control transistor is coupled to the output terminal of the control circuit, and the control terminal of the fifth control transistor is coupled to the second terminal of the first control transistor; and A sixth control transistor has a first end, a second end and a control end, wherein the first end of the sixth control transistor is coupled to the second end of the control circuit, the second end of the sixth control transistor is coupled to the second end of the fifth control transistor, and the control end of the sixth control transistor is coupled to the second end of the second control transistor.

19. The electrostatic discharge protection circuit according to claim 18, It is characterized in that When the electrostatic discharge event occurs, the first control transistor is turned on, the second control transistor is turned off, the fifth control transistor is turned off, the sixth control transistor is turned on, the potential of the second end of the first control transistor and the potential of the second end of the second control transistor are high potentials, and the potential of the output end of the control circuit is low potential to turn on the main transistor.

20. The electrostatic discharge protection circuit according to claim 19, It is characterized in that The main transistor is a P-type transistor, and the size of the main transistor is larger than the size of the first control transistor. The first control transistor and the fifth control transistor are P-type transistors, and the second control transistor and the sixth control transistor are N-type transistors.

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