MEMS sensor and preparation method thereof

Abstract

The invention relates to an MEMS sensor and a preparation method thereof. The method comprises the following steps: providing an electrode layer; the electrode layer comprises a bonding anchor point and a capacitor plate which is lower than the bonding anchor point; bonding the device wafer with the bonding anchor point, and etching the device wafer to form a through groove penetrating to the bonding anchor point; a connecting column for connecting the device wafer and the bonding anchor point is formed in the through groove through deposition; carrying out patterning etching on the device wafer to generate a movable structure and obtain a device layer; and bonding one side, deviating from the electrode layer, of the device wafer with the cover layer. The bonding reliability can be improved, and the device layer is prevented from falling off.

Description

Technical Field

[0001] The present application relates to the technical field of MEMS devices, and particularly to a MEMS sensor and a manufacturing method thereof. Background Art

[0002] MEMS (Micro-Electro Mechanical System) technology integrates a sensor structure and corresponding electronic circuits in a small housing. Compared with sensors manufactured by traditional processing methods, MEMS sensors are fabricated based on integrated circuit technology and micromachining technology, and have advantages such as small size, light weight, and low power consumption, and have broad application prospects in both military and civilian uses.

[0003] MEMS sensors, such as IMU (Inertial Measurement Unit), MEMS gyroscopes, MEMS accelerometers, etc., include a cover layer, a device layer, and a substrate layer. Among them, the device layer includes a device wafer on which a movable structure is formed, and the substrate layer includes capacitor plates. An induction capacitor is formed by the cooperation of the movable structure and the capacitor plates to sense corresponding physical quantities. The device layer and the substrate layer are fixed by fusion bonding. Fusion bonding has high requirements for flatness. If the bonding fails and the structure separates, it will cause contamination of the wafer surface and wafer processing tools / equipment, and may lead to wafer breakage, leakage, contamination, and tool / equipment damage. How to improve the bonding reliability of the device layer is an urgent problem to be solved. Summary of the Invention

[0004] Based on this, in view of the above problems, it is necessary to provide a MEMS sensor and a manufacturing method thereof that can improve bonding reliability.

[0005] A manufacturing method of a MEMS sensor includes:

[0006] Providing an electrode layer; the electrode layer includes bonding anchors and capacitor plates with a relatively lower height relative to the bonding anchors;

[0007] Bonding a device wafer to the bonding anchors, etching the device wafer to form a through groove leading to the bonding anchors;

[0008] Depositing in the through groove to form connection columns connecting the device wafer and the bonding anchors;

[0009] Performing patterned etching on the device wafer to generate a movable structure, obtaining a device layer;

[0010] Bonding one side of the device wafer facing away from the electrode layer to a cover layer.

[0011] In one embodiment, the providing of the electrode layer includes:

[0012] Generating a first oxide layer on a substrate wafer, patterning and etching the first oxide layer, and forming a first polysilicon layer on the patterned and etched first oxide layer;

[0013] Patterning and etching the first polysilicon layer to form a wiring, and depositing a second oxide layer on the first polysilicon layer;

[0014] After patterning and etching the second oxide layer, forming a second polysilicon layer;

[0015] Patterning and etching the second polysilicon layer to form a bonding anchor and a capacitor plate having a height lower than that of the bonding anchor.

[0016] In one embodiment, the forming of the first polysilicon layer on the patterned and etched first oxide layer includes: depositing polysilicon on the patterned and etched first oxide layer, and then depositing a refractory metal for high-temperature annealing to form a first polysilicon layer containing a high-temperature refractory metal silicide.

[0017] In one embodiment, the forming of the second polysilicon layer after patterning and etching the second oxide layer includes: depositing polysilicon after patterning and etching the second oxide layer, and then depositing a refractory metal for high-temperature annealing to form a second polysilicon layer containing a high-temperature refractory metal silicide.

[0018] In one embodiment, the patterning and etching of the second polysilicon layer to form a bonding anchor and a capacitor plate having a height lower than that of the bonding anchor includes:

[0019] Performing a planarization process on the second polysilicon layer, and forming a third oxide layer on the planarized second polysilicon layer;

[0020] Patterning and etching the third oxide layer and the second polysilicon layer to form a bonding anchor and a capacitor plate, and retaining a portion of the third oxide layer covering the bonding anchor;

[0021] Generating a fourth oxide layer covering the third oxide layer and the capacitor plate;

[0022] Patterning and etching the third oxide layer and the fourth oxide layer to expose the bonding anchor, and retaining the fourth oxide layer covering the capacitor plate;

[0023] After the patterning and etching of the device wafer to generate a movable structure and obtain a device layer, the method further includes: removing the fourth oxide layer covering the capacitor plate.

[0024] In one embodiment, the bonding of the device wafer to the bonding anchor and the etching of the device wafer to form a through groove leading to the bonding anchor include:

[0025] Bond the device wafer to the bonding anchor and perform planarization on the device wafer;

[0026] Etch from the device wafer to the second polysilicon layer where the bonding anchor is located, and stop etching at the second oxide layer to form a through groove penetrating the device wafer and the second polysilicon layer.

[0027] In one embodiment, the deposition of a connection column connecting the device wafer and the bonding anchor in the through groove includes: depositing polysilicon in the through groove to form a polysilicon connection column; the polysilicon connection column connects the device wafer and the second polysilicon layer where the bonding anchor is located.

[0028] In one embodiment, after depositing a connection column connecting the device wafer and the bonding anchor in the through groove and before patterning and etching the device wafer to generate a movable structure to obtain a device layer, the method further includes: depositing metal on the device wafer to obtain solder joints and a first bonding portion.

[0029] In one embodiment, before bonding the side of the device wafer facing away from the electrode layer to the cover layer, the method further includes:

[0030] Providing a cover layer wafer;

[0031] Deposit metal on the cover layer wafer and perform patterning and etching to obtain a second bonding portion; the side of the device wafer facing away from the electrode layer and the cover layer wafer are eutectically bonded through the first bonding portion and the second bonding portion.

[0032] A MEMS sensor includes an electrode layer, a device layer, and a cover layer, and the MEMS sensor is prepared by the above method.

[0033] The above MEMS sensor and its manufacturing method provide an electrode layer including a bonding anchor and a capacitor plate. After bonding the device wafer to the bonding anchor, the device wafer is etched to form a through groove leading to the bonding anchor, a connection column connecting the device wafer and the bonding anchor is deposited in the through groove, and then the device wafer is patterned and etched to generate a movable structure to obtain a device layer. This can improve the bonding reliability and prevent the device layer from falling off. Description of the Drawings

[0034] Figure 1 It is a flowchart of the manufacturing method of the MEMS sensor in one embodiment;

[0035] Figure 2 Flow chart for providing an electrode layer in one embodiment;

[0036] Figures 3 to 31 Structural schematic diagram of the preparation process of the MEMS sensor part in one embodiment; Specific embodiments

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0040] In one embodiment, as Figure 1 shown, a method for manufacturing a MEMS sensor is provided, including:

[0041] Step S110: Provide an electrode layer. Among them, the electrode layer includes bonding anchors and capacitor plates with a relatively lower height than the bonding anchors. The bonding anchors and the capacitor plates can be respectively etched from the same polysilicon layer of the electrode layer to make there be a height difference between the bonding anchors and the capacitor plates.

[0042] Specifically, as Figure 2 shown, step S110 may include step S111 to step S114.

[0043] Step S111: Generate a first oxide layer on a substrate wafer, and perform patterned etching on the first oxide layer to form a first polysilicon layer on the patterned-etched first oxide layer.

[0044] As Figure 3As shown, first, a substrate wafer 110 is provided. Specifically, a silicon wafer can be used. By doping boron or phosphorus, the resistance can be reduced and the conductivity can be improved. The sheet resistance of the substrate wafer 110 can be made 1 - 10 Ω / cm through doping. 2 . The thickness of the substrate wafer 110 is 150 - 800 μm. By designing a thicker substrate wafer 110, the capacitor plates of the subsequent formed MEMS sensor have better stability.

[0045] As Figure 4 and Figure 5 shown, by performing oxide deposition (e.g., thermal oxide deposition) on one or both sides of the substrate wafer 110, a first oxide layer 120 is generated. The first oxide layer 120 on one side is patterned and etched, and part of the oxide is etched away to form an etching groove, exposing part of the substrate wafer 110. Among them, the first oxide layer 120 can be any dielectric film. In this embodiment, the first oxide layer 120 is a silicon oxide layer. The first oxide layer 120 is used to shield and protect the substrate wafer 110 in subsequent process steps. The first oxide layer 120 can be deposited thicker, for example, 1 - 3 μm. A thick oxide layer can reduce the parasitic capacitance.

[0046] The first polysilicon layer can be formed by depositing and doping polysilicon. For example, after depositing polysilicon, it can be formed by doping phosphorus or boron, or after depositing polysilicon, refractory metal is deposited and then annealed at high temperature to form a first polysilicon layer containing high-temperature refractory metal silicide. In this embodiment, in step S111, forming the first polysilicon layer on the patterned and etched first oxide layer includes: depositing polysilicon on the patterned and etched first oxide layer, and then depositing refractory metal and performing high-temperature annealing to form a first polysilicon layer containing high-temperature refractory metal silicide.

[0047] As Figures 6 to 8 shown, after the patterning and etching of the first oxide layer 120 are completed, polysilicon is deposited to generate a first polysilicon 132 with a thickness of 0.25 - 0.75 μm. Then, the first refractory metal 134 is deposited by sputtering or evaporation. The first refractory metal 134 can be tantalum (Ta), tungsten (W), molybdenum (Mo), niobium (Nb), etc. The thickness of the first refractory metal 134 depends on the selected refractory metal, the thickness of the first polysilicon 132, and the desired resistance value. Then, in an N 2 environment, high-temperature annealing is performed at 800 - 1000 °C. The refractory metal is completely consumed by the polysilicon, forming high-temperature refractory metal silicide, and a first polysilicon layer 130 containing high-temperature refractory metal silicide is obtained. The first polysilicon layer 130 covers the patterned and etched first oxide layer 120 and fills the etching groove of the first oxide layer 120 to contact the substrate wafer 110.

[0048] The doping of polysilicon is limited to a resistance of about 10 - 20 Ω·cm. To achieve this resistance level, the cross-section of the polysilicon must be quite large, and the doping must be close to the solid solubility, increasing the space required for completing the wiring and restricting the doping method and dopant type. In this embodiment, by depositing a refractory metal onto the polysilicon and performing high-temperature annealing, the refractory metal diffuses into the polysilicon to form a high-temperature refractory metal silicide, which can reduce the resistance and increase the conductivity of the polysilicon layer. In this way, while obtaining the desired resistance, the polysilicon layer has a smaller cross-section, whereby the parasitic capacitance can be reduced. Additionally, the polysilicon layer can withstand high temperatures compared to metal wirings such as aluminum, enabling subsequent high-temperature processing steps, such as fusion bonding, to be realized.

[0049] Step S112: Pattern-etch the first polysilicon layer to form a wiring, and deposit a second oxide layer on the first polysilicon layer. As Figure 9 and Figure 10 shown, dry plasma etching can be used to pattern-etch the first polysilicon layer 130 to form a wiring, and the etching stops at the first oxide layer 120. Then, an oxide is deposited on the first polysilicon layer 130 through a plasma-enhanced chemical vapor deposition process to form a second oxide layer 140. Among them, the second oxide layer 140 can also be formed by vapor deposition using any dielectric material. For example, the second oxide layer 140 can also be a silicon oxide layer.

[0050] Step S113: After pattern-etching the second oxide layer, a second polysilicon layer is formed. Specifically, as Figure 11 and Figure 12 shown, the second oxide layer 140 can be first chemically mechanically polished. After completing the planarization process, the second oxide layer 140 is pattern-dry etched to etch away part of the oxide to form an etching groove, exposing part of the first polysilicon layer 130. The second oxide layer 140 after the planarization process can be relatively thick. For example, 1 - 5 μm. The thick oxide layer can reduce the parasitic capacitance.

[0051] Similarly, the second polysilicon layer can be formed by depositing and doping polysilicon. For example, after depositing polysilicon, it can be formed by doping phosphorus or boron, or after depositing polysilicon, a refractory metal can be deposited and then high-temperature annealing is performed to form a second polysilicon layer containing a high-temperature refractory metal silicide. In this embodiment, step S113 includes: depositing polysilicon after pattern-etching the second oxide layer, and then depositing a refractory metal and performing high-temperature annealing to form a second polysilicon layer containing a high-temperature refractory metal silicide.

[0052] As Figure 13As shown, after patterning and etching the second oxide layer 140, polysilicon is deposited to form the second polysilicon 152. The second polysilicon 152 covers the patterned and etched second oxide layer 140 and fills the etched trenches of the second oxide layer 140 to contact the first polysilicon layer 130. As Figure 14 shown, a second refractory metal 153 is deposited on the second polysilicon 152. The second refractory metal 153 can also be tantalum (Ta), tungsten (W), molybdenum (Mo), niobium (Nb), etc. If the second polysilicon 152 is relatively thick, a form of alternating stacking of multiple layers of polysilicon and refractory metals can also be adopted, which can not only achieve the desired thickness of the polysilicon layer but also finally obtain the desired resistance. Then in N 2 environment, high-temperature annealing is carried out at 800 - 1000 °C to completely consume the refractory metal by the polysilicon, forming a high-temperature refractory metal silicide, and obtaining the second polysilicon layer 150 containing the high-temperature refractory metal silicide, as Figure 15 shown.

[0053] Step S114: Pattern and etch the second polysilicon layer to form bonding anchors and capacitor plates with a height lower than that of the relative bonding anchors. Specifically, step S114 includes step S1141 and step S1142.

[0054] Step S1141: Planarize the second polysilicon layer and form a third oxide layer on the planarized second polysilicon layer. As Figure 16 and Figure 17 shown, the planarization process can be completed by chemical mechanical polishing of the second polysilicon layer 150 to achieve the desired flatness and overall thickness deviation for subsequent fusion bonding. Then, an oxide is deposited on the second polysilicon layer 150 by plasma-enhanced chemical vapor deposition process to generate the third oxide layer 160.

[0055] Step S1142: Pattern and etch the third oxide layer and the second polysilicon layer to form bonding anchors and capacitor plates, and retain the part of the third oxide layer covering the bonding anchors. Specifically, the patterning and etching of the third oxide layer 160 and the second polysilicon layer 150 can be completed in two steps. As Figure 18 shown, in the first step of etching, the third oxide layer 160 and the second polysilicon layer 150 are simultaneously patterned and dry-etched, and the etching time is limited so that multiple bonding anchors are formed on the second polysilicon layer 150. For the third oxide layer 160, only the part of the third oxide layer 160 covering the bonding anchors is retained to protect the surface of the bonding anchors before bonding in subsequent steps. The etching depth of the second polysilicon layer 150 in the first step of etching determines the gap between the subsequent generated capacitor plate and the device layer. As Figure 19As shown, in the second etching step, on the basis of the first etching region, part of the region is further masked, and the second polysilicon layer 150 is continuously dry-etched until the etching stops at the second oxide layer 140, forming a capacitor electrode plate 154 on the second polysilicon layer 150. Thus, the electrode layer is formed.

[0056] In this embodiment, by performing patterned etching on the same polysilicon layer (the second polysilicon layer 150) to obtain the bonding anchor and the capacitor electrode plate 154, it is beneficial to reduce the process steps and simplify the preparation process. In addition, by arranging the capacitor electrode plate 154 and the wiring on different polysilicon layers, specifically, the capacitor electrode plate 154 is arranged on the second polysilicon layer 150 and the wiring is arranged on the first polysilicon layer 130, the design of the inductive capacitance and the wiring can be made more flexible. In addition, the first polysilicon layer 130 and the second polysilicon layer 150 are in electrical connection through step S113, and this electrical connection method makes the design more compact.

[0057] In one embodiment, as Figures 20 - 22 shown, in order to avoid adverse effects on the capacitor electrode plate 154 during the process of patterning and etching the device wafer when performing the subsequent step S140, and in order to enable the etching to stop in time after the movable structure is formed and avoid over-etching, after performing step S1142, an oxide patch protection process needs to be performed. Step S114 may further include step S1143 and step S1144.

[0058] Step S1143: Generate a fourth oxide layer covering the third oxide layer and the capacitor electrode plate. As Figure 20 shown, after etching to obtain the capacitor electrode plate 154, a plasma-enhanced chemical vapor deposition process is used to deposit an oxide to form a fourth oxide layer 170. The fourth oxide layer 170 covers the capacitor electrode plate 154 and the remaining third oxide layer 160. The material of the fourth oxide layer 170 is not unique. Specifically, the fourth oxide layer 170 can be made of any dielectric film that can be removed by gaseous hydrogen fluoride, so as to remove the fourth oxide layer 170 after the movable structure is formed. In this embodiment, the fourth oxide layer 170 is a silicon oxide layer.

[0059] Step S1144: Pattern and etch the third oxide layer and the fourth oxide layer to expose the bonding anchor and retain the fourth oxide layer covering the capacitor electrode plate. As Figure 21 shown, first, the fourth oxide layer 170 is pattern dry-etched until the etching stops at the third oxide layer 160, exposing the third oxide layer 160 covering the bonding anchor and retaining the fourth oxide layer 170 covering the capacitor electrode plate 154. As Figure 22As shown, the third oxide layer 160 is wet-etched to remove the third oxide layer 160 covering the bonding anchor points, exposing the bonding anchor points for subsequent fusion bonding. The remaining fourth oxide layer 170 is used to protect the capacitor plate 154 from unwanted etching during the subsequent fabrication of the movable structure and to provide endpoint detection for the device wafer etching, i.e., the etching stops when the fourth oxide layer 170 is encountered.

[0060] Step S120: Bond the device wafer to the bonding anchor points and etch the device wafer to form a through-hole reaching the bonding anchor points. Specifically, the device wafer is fusion-bonded to the bonding anchor points at a bonding temperature of 900 - 1050 °C. The device wafer can be a silicon wafer. Since a complete wafer that has not been etched to form specific structures and / or patterns is bonded to the second polysilicon layer 150, there is no need to consider bonding tolerances during bonding, and no specific point-to-point alignment bonding is required. Precise alignment can be based on image tolerances rather than bonding tolerances. Further, the bonding anchor points on the second polysilicon layer do not need to increase the anchor point size to consider bonding tolerances, that is, the anchor point size can be reduced, thereby enabling a more compact device structure.

[0061] Specifically, in one embodiment, step S120 includes step S121 and step S122.

[0062] Step S121: Bond the device wafer to the bonding anchor points and planarize the device wafer. As Figure 23 shown, the device wafer 210 is fusion-bonded to the exposed bonding anchor points. In steps S1141 and S1142, the second polysilicon layer is first planarized and then the bonding anchor points are formed. That is, the bonding anchor points have a flat surface, which is beneficial for fusion bonding. In addition, there is no temperature limit for fusion bonding, and a higher temperature can be used for fusion bonding to obtain a higher bonding strength, making the connection between the electrode layer and the device layer firm. As Figure 24 shown, after bonding, the device wafer 210 is polished to complete the planarization process.

[0063] Step S122: Etch from the device wafer to the second polysilicon layer where the bonding anchor points are located, and the etching stops at the second oxide layer to form a through-hole penetrating the device wafer and the second polysilicon layer. As Figure 25 shown, deep reactive ion etching is performed corresponding to the position where the bonding anchor points are located, etching from the device wafer 210 to the second oxide layer 140 to form a through-hole 211 penetrating the device wafer 210 and the second polysilicon layer 150.

[0064] Step S130: Deposit connection columns in the through-holes to connect the device wafer and the bonding anchor points.

[0065] Reliable and repeatable fusion bonding is crucial for MEMS processes. Fusion bonding requires a nearly perfect surface, free of particles, flat, and without excessive roughness. As the number of bonds per chip increases, fusion bonding becomes more challenging. If the surface of the bonding anchor is not completely clean, tiny voids may form between the device wafer 210 and the bonding anchor. After the subsequent formation of movable structures, the voids may cause the device layer to peel off. If the bonding fails and the structure separates, it will result in contamination of the wafer surface and wafer processing tools / equipment, which may lead to wafer breakage, leakage, contamination, and damage to the tools / equipment. Therefore, the device wafer 210 is etched to form through-holes leading to the bonding anchor, and then connection posts are deposited. The connection posts are used to connect the device wafer to the bonding anchor, playing a fixing role, which can improve the bonding reliability and prevent the device layer from peeling off.

[0066] The specific material of the connection post is not unique. In one embodiment, step S130 includes: depositing polysilicon in the through-hole to form a polysilicon connection post. As Figure 26 shown, the third polysilicon 222 can be deposited on the device wafer 210. The third polysilicon 222 can be doped or undoped. For example, if the third polysilicon 222 needs to be electrically connected, it needs to be doped. Alternatively, the third polysilicon 222 can be made conductive by forming a high-temperature metal refractory silicide. As Figure 27 shown, the excess polysilicon on the surface of the device wafer 210 is removed to obtain the polysilicon connection post 220 in the through-hole. The polysilicon connection post 220 connects the device wafer 210 to the second polysilicon layer 150 where the bonding anchor is located.

[0067] Furthermore, after step S130 and before step S140, the method further includes: depositing metal on the device wafer to obtain solder joints and the first bonding part. First, the first bonding metal layer can be deposited on the device wafer, and then the first bonding metal layer is patterned and etched to obtain the solder joints and the first bonding part.

[0068] Specifically, as Figure 28As shown, metal deposition is performed on the device wafer 210 to obtain the first bonding metal layer. The material of the first bonding metal layer can be any eutectic metal capable of wire bonding, such as aluminum. Then, the first bonding metal layer is patterned and etched to form solder joints 232 and the first bonding portion 234. By depositing and etching the first bonding metal layer, the solder joints 232 for wire bonding and the first bonding portion 234 for eutectic bonding can be formed, which is beneficial to reducing process steps and simplifying the preparation process. It can be understood that the third polysilicon 222 can be doped to obtain the conductive polysilicon connection column 220, or the polysilicon connection column 220 can be made conductive by generating high-temperature refractory metal silicides. The solder joints 232 are at least partially in contact with the polysilicon connection column 220. In this way, the solder joints 232 are electrically connected through the polysilicon connection column 220, the second polysilicon layer 150, and the wiring formed by the first polysilicon layer 130.

[0069] Step S140: Pattern and etch the device wafer to generate a movable structure and obtain a device layer.

[0070] The traditional method for fabricating the device layer of a MEMS sensor includes a sacrificial release process. Specifically, an oxide layer is provided between the capacitor plate and the device wafer. After the device wafer is patterned and etched to form a movable structure, the movable structure is in a state locked by the oxide layer. It is necessary to drill holes in the device wafer to allow the etching gas to pass through, and the etching gas is used to etch and remove at least part of the oxide layer to release the movable structure. The sensing capacitor formed by the movable structure and the capacitor plate is used to sense changes in external physical quantities, such as acceleration or angular velocity. Drilling holes in the device wafer will affect the sensing capacitor of the sensor. In this application, a non-sacrificial release process is adopted. The bonding anchor points and the capacitor plate 154 are both formed on the second polysilicon layer 150. After the device wafer is bonded to the bonding anchor points, since the height of the capacitor plate 154 is relatively lower than that of the bonding anchor points, a cavity is formed between the device wafer and the capacitor plate 154. Therefore, after the device wafer is patterned and etched to generate a movable structure, there is no need to etch holes to release the movable structure, and the cavity provides a moving space for the movable structure. Compared with the sacrificial release process, since there is no need to etch holes to release the movable structure, the sensing capacitor for out-of-plane sensing is higher. In addition, since there is no need to etch holes, compared with the sacrificial release process, the Q value of out-of-plane sensing is lower - reducing the ringing phenomenon and the influence during impact or drop events, and the drift and stability changes caused by impact or drop are lower, and the use reliability is higher.

[0071] As Figure 29As shown, the device wafer 210 is patterned and etched through the device wafer 210 to generate the movable structure 212. Specifically, deep reactive ion etching is used. After etching through the device wafer 210 and until reaching the fourth oxide layer 170, the etching terminates. The fourth oxide layer 170 provides endpoint detection for the etching to prevent over-etching. The fourth oxide layer 170 covering the capacitor plate 154 provides a protective effect for the capacitor plate 154 to avoid unwanted etching of the capacitor plate 154. The plurality of movable structures 212 formed by etching are used for cooperation with the capacitor plate 154 for detection.

[0072] In addition, the thickness of the movable structure 212 fabricated in this embodiment is jointly determined by the initial thickness of the device wafer 210 and the thickness of grinding and polishing, and the thickness of grinding and polishing can be selected according to actual needs. It can be understood that the maximum thickness of the movable structure 212 can be the initial thickness of the device wafer 210. Thus, a relatively thick movable structure 212 can be fabricated to achieve a higher planar capacitance. Compared with the device layer generated by the traditional thin film deposition process, in this application, the thickness of the movable structure 212 is determined by grinding and polishing on the basis of the initial device wafer 210, which is more convenient to fabricate and has higher accuracy.

[0073] In addition, after step S140, the method may further include: removing the fourth oxide layer covering the capacitor plate. As Figure 30 shown, after completing the patterned etching of the device wafer 210 to form the movable structure 212, the remaining fourth oxide layer 170 can be etched off by vapor phase hydrogen fluoride to expose the capacitor plate 154.

[0074] Step S150: Bond the side of the device wafer facing away from the electrode layer to the cover layer. As Figure 31 shown, the side of the device wafer 210 facing away from the substrate wafer 110 is eutectically bonded to the cover layer.

[0075] In one embodiment, before step S150, the method further includes a preparation step for the cover layer. The preparation step of the cover layer specifically includes: providing a cover layer wafer; depositing and patterning metal on the cover layer wafer to obtain a second bonding portion.

[0076] Specifically, as Figure 31As shown, the capping wafer 310 can also be a silicon wafer. Metal deposition is performed on the capping wafer 310 to obtain a second bonding metal layer, and then the second bonding metal layer is patterned and etched to obtain a second bonding portion 320. The material of the second bonding metal layer can be any eutectic metal, such as germanium or gold. The side of the device wafer 210 facing away from the substrate wafer 110 and the capping wafer 310 are eutectically bonded through the first bonding portion 234 and the second bonding portion 320. It can be understood that the bonding method can be any type of eutectic bonding, or other types of bonding methods can be used, such as thermocompression bonding, transient liquid phase bonding, soldering bonding, glass frit bonding, etc.

[0077] Further, the preparation steps of the capping layer may further include: patterning and etching the capping wafer to generate a capping chamber. The capping chamber provides an activity space for the movable structure 212.

[0078] Further, the preparation steps of the capping layer may further include: generating a getter in the capping chamber of the capping wafer. Specifically, the MEMS sensor is an IMU (Inertial Measurement Unit), which includes a gyroscope and an accelerometer. As Figure 31 shown, wherein, region X is used to fabricate the gyroscope, region Y is used to fabricate the accelerometer, and a getter 330 is provided in the capping chamber corresponding to region X on the capping wafer 310. The getter 330 provided in the capping chamber is used to maintain a vacuum in the gyroscope.

[0079] In one embodiment, after step S150, the method may further include: patterning and etching the capping layer to expose part of the device layer. After the bonding is completed, the capping wafer 310 is ground and polished to reduce the thickness of the capping wafer 310 and improve the flatness of the capping wafer 310. The part of the capping wafer 310 that blocks the solder joints 232 is patterned and etched to expose the solder joints 232. On the one hand, it is convenient to connect wires after the solder joints 232 are exposed. On the other hand, the position of the solder joints 232 is lower than that of the capping wafer 310. After the solder joints 232 are connected to the leads, the height of the leads can be lower than that of the capping wafer 310. In this way, the package size can be reduced during subsequent packaging of the housing.

[0080] In one embodiment, there is also provided a MEMS sensor, including an electrode layer, a device layer, and a capping layer. The electrode layer includes a substrate wafer, a first oxide layer, a first polysilicon layer, a second oxide layer, and a second polysilicon layer. The MEMS sensor may further include a getter, etc. The MEMS sensor is prepared by the above method.

[0081] For the above MEMS sensor and its manufacturing method, after the device wafer is bonded to the bonding anchor, the device wafer is etched to form a through groove that penetrates to the bonding anchor, and a connection column connecting the device wafer and the bonding anchor is deposited in the through groove, which can improve the bonding reliability and prevent the device layer from falling off. Since the height of the capacitor plate is relatively lower than that of the bonding anchor, a cavity is formed between the device wafer and the capacitor plate. Therefore, after patterning and etching the device wafer to generate a movable structure, there is no need to etch holes to release the movable structure, and the sensing capacitance for out-of-plane sensing is higher. In addition, by depositing a refractory metal onto polysilicon and performing high-temperature annealing, the refractory metal diffuses into the polysilicon to form a high-temperature refractory metal silicide, which can reduce the resistance and increase the conductivity of the polysilicon.

[0082] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0083] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a MEMS sensor, characterized in that: include: Providing an electrode layer; the electrode layer includes a bonding anchor point and a capacitor plate with a lower height relative to the bonding anchor point; Bonding the device wafer to the bonding anchor point, and etching the device wafer to form a through groove penetrating to the bonding anchor point; Depositing a connection column in the through groove to connect the device wafer and the bonding anchor point; Performing patterned etching on the device wafer to generate a movable structure and obtain a device layer; The side of the device wafer facing away from the electrode layer is bonded to the cap layer.

2. The method according to claim 1, characterized in that The providing of the electrode layer comprises: Generating a first oxide layer on a substrate wafer, and pattern-etching the first oxide layer, so as to form a first polysilicon layer on the first oxide layer after pattern-etching; Performing patterned etching on the first polysilicon layer to form wiring, and depositing a second oxide layer on the first polysilicon layer; After patterning and etching the second oxide layer, a second polysilicon layer is formed; The second polysilicon layer is pattern-etched to form a bonding anchor point and a capacitor plate with a lower height than the bonding anchor point.

3. The method according to claim 2, characterized in that The first oxide layer after patterned etching forms a first polysilicon layer, comprising: depositing polysilicon on the first oxide layer after patterned etching, and then depositing a refractory metal for high temperature annealing to form a first polysilicon layer containing high temperature refractory metal silicide.

4. The method according to claim 2, characterized in that: The second polysilicon layer is formed after patterning and etching the second oxide layer, comprising: depositing polysilicon after patterning and etching the second oxide layer, and then depositing a refractory metal for high temperature annealing to form a second polysilicon layer containing a high temperature refractory metal silicide.

5. The method according to claim 2, characterized in that: The patterning and etching of the second polysilicon layer to form a bonding anchor point and a capacitor plate with a lower height relative to the bonding anchor point includes: performing a planarization process on the second polysilicon layer, and forming a third oxide layer on the second polysilicon layer after the planarization process; Performing patterned etching on the third oxide layer and the second polysilicon layer to form a bonding anchor point and a capacitor plate, and retaining a portion of the third oxide layer covering the bonding anchor point; generating a fourth oxide layer covering the third oxide layer and the capacitor plate; Patterning and etching the third oxide layer and the fourth oxide layer to expose the bonding anchor point and retain the fourth oxide layer covering the capacitor plate; After patterning and etching the device wafer to generate a movable structure and obtain a device layer, the method further includes: removing the fourth oxide layer covering the capacitor plate.

6. The method according to claim 2, characterized in that The step of bonding the device wafer to the bonding anchor point and etching the device wafer to form a through groove penetrating to the bonding anchor point comprises: Bonding the device wafer to the bonding anchor point, and performing a planarization process on the device wafer; Etching is performed from the device wafer to the second polysilicon layer where the bonding anchor point is located, and the etching stops at the second oxide layer to form a through groove penetrating the device wafer and the second polysilicon layer.

7. The method according to claim 2, characterized in that The step of depositing a connection column connecting the device wafer and the bonding anchor point in the through groove comprises: depositing polysilicon in the through groove to form a polysilicon connection column; the polysilicon connection column connects the device wafer and a second polysilicon layer where the bonding anchor point is located.

8. The method according to claim 1, characterized in that: After depositing in the through groove to form a connecting column connecting the device wafer and the bonding anchor point, patterning and etching the device wafer to generate a movable structure, and before obtaining the device layer, the method also includes: depositing metal on the device wafer to obtain a solder joint and a first bonding portion.

9. The method according to claim 8, characterized in that Before bonding the side of the device wafer facing away from the electrode layer to the cap layer, the method further comprises: providing a cap layer wafer; Metal is deposited on the cover layer wafer and patterned and etched to obtain a second bonding portion; a side of the device wafer facing away from the electrode layer is eutectically bonded to the cover layer wafer through the first bonding portion and the second bonding portion.

10. A MEMS sensor, characterized in that: The MEMS sensor comprises an electrode layer, a device layer and a cover layer, and is prepared by the method according to any one of claims 1 to 9.

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