Processing circuit applied to vehicle-mounted rotating speed sensor

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By designing a vehicle-mounted speed sensor processing circuit with multiple circuit functions, the problem of high cost and poor adaptability of the magnetic link speed sensor signal processing circuit in the prior art is solved, and higher adaptability and cost-effectiveness are achieved.

CN120044261APending Publication Date: 2025-05-27NANJING WEIFU JINNING

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Patent Information

Application Number: CN202510330382.2
Authority / Receiving Office: CN · China
Patent Type: Applications(China)
Current Assignee / Owner
Filing Date: 2025-03-20
Publication Date: 2025-05-27

AI Technical Summary

Technical Problem

The existing magnetic link speed sensor signal processing circuit is costly and has poor adaptability. It requires peripheral circuits to cooperate and adjust environmental parameters to match the electrical characteristics of the chip, which increases the difficulty of development and debugging.

Method used

Design a vehicle-mounted speed sensor processing circuit, including bias circuit, straight blocking circuit, clamping circuit, amplifying circuit, proportional integral circuit, filtering circuit and logic inversion circuit, and dynamically adjust the circuit parameters to adapt to special operating conditions in different application scenarios.

Benefits of technology

It significantly improves adaptability, reduces costs, has high cost performance, and simplifies the use of system interface resources.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention relates to a processing circuit applied to a vehicle-mounted rotating speed sensor. The input end of the biasing circuit is connected to an input signal from a vehicle-mounted rotating speed sensor; the input end of the blocking circuit is connected with the output end of the biasing circuit; the input end of the clamping circuit is connected with the output end of the blocking circuit; the input end of the amplifying circuit is connected with the output end of the clamping circuit; the input end of the proportional-integral circuit is connected to the output end of the amplifying circuit; the input end of the filter circuit is connected to the output end of the proportional-integral circuit; and the input end of the logic negation circuit is connected to the output end of the filter circuit, and the logic negation circuit is used for inverting the filtered PWM square wave signal so as to reduce the rising edge and falling edge time of the square wave, and outputting the signal to a control chip for rotating speed data analysis. The circuit reduces the cost.

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Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a processing circuit applied to an on-vehicle rotational speed sensor. Background Art

[0002] In modern automotive electronic systems, the rotational speeds of generators, motors, or oil pumps need to be collected in many application scenarios. There are various methods for rotational speed collection. Among them, magnetic chain rotational speed sensors are recognized and adopted by most manufacturers due to their strong anti-interference ability and low cost.

[0003] Generally, an integrated IC is selected for signal processing in the signal processing circuit of a magnetic chain rotational speed sensor, such as CY30B of Bosch and NCV1124 of ON Semiconductor. Although the integrated IC solution makes the chip design itself more concise, its cost is high, and it requires the cooperation of peripheral circuits. In addition, the integrated IC solution has many constraints on the application environment and poor adaptability. Usually, external environmental parameters need to be adjusted to match the electrical characteristics of the chip, which often requires extra time to optimize the adaptability during the vehicle integration process, thus increasing the difficulty of development and debugging. Summary of the Invention

[0004] Therefore, the present invention provides a processing circuit applied to an on-vehicle rotational speed sensor. This circuit can dynamically adjust circuit parameters according to the actual application environment of the vehicle to adapt to special working conditions in different application scenarios. By providing appropriate circuit parameters specifically, this solution significantly improves the adaptability, and compared with the integrated IC solution, it has a lower cost and extremely high cost performance.

[0005] To solve the above technical problems, the present invention provides a processing circuit applied to an on-vehicle rotational speed sensor, including:

[0006] A bias circuit, whose input end is connected to an input signal from an on-vehicle rotational speed sensor. The bias circuit is used to apply a bias voltage to the input signal to enhance its signal strength;

[0007] A DC blocking circuit, whose input end is connected to the output end of the bias circuit. The DC blocking circuit is used to convert the input signal from a DC quantity to an AC quantity;

[0008] A clamping circuit, whose input end is connected to the output end of the DC blocking circuit. The clamping circuit is used to clamp and control the signal amplitude of the input signal converted to an AC quantity within a required range;

[0009] An amplifying circuit, whose input end is connected to the output end of the clamping circuit. The amplifying circuit is used to perform gain amplification on the input signal after clamping;

[0010] A proportional-integral circuit, whose input terminal is connected to the output terminal of the amplifier circuit. The proportional-integral circuit is used to convert the input signal after gain amplification into a PWM square-wave signal. Among them, the input signal after gain amplification is the sine signal output by the amplifier circuit;

[0011] A filter circuit, whose input terminal is connected to the output terminal of the proportional-integral circuit. The filter circuit is used to filter out high-frequency interference signals in the PWM square-wave signal;

[0012] A logic inversion circuit, whose input terminal is connected to the output terminal of the filter circuit. The logic inversion circuit is used to invert the filtered PWM square-wave signal to reduce the rise and fall times of the square wave, and output the signal to the control chip for rotational speed data analysis.

[0013] In an embodiment of the present invention, the bias circuit includes a VCC power supply, a first resistor R1, a second resistor R2, a first capacitor C1, and a first diode D1;

[0014] The first end of the first resistor R1 is connected to the input port of the vehicle speed sensor, and the second end of the first resistor R1 is connected to the ground terminal GND;

[0015] The first end of the first capacitor C1 is connected to the first end of the first resistor R1, and the second end of the first capacitor C1 is connected to the ground terminal GND;

[0016] The negative terminal of the first diode D1 is connected to the first end of the first resistor R1, and the positive terminal of the first diode D1 is connected to the first end of the second resistor R2;

[0017] The second end of the second resistor R2 is connected to the positive pole of the VCC power supply, and the negative pole of the VCC power supply is connected to the ground terminal GND.

[0018] In an embodiment of the present invention, the DC-blocking circuit includes a third resistor R3 and a second capacitor C2;

[0019] The first end of the third resistor R3 is connected to one end of the first resistor R1, and the second end of the third resistor R3 is connected to the first end of the second capacitor C2.

[0020] In an embodiment of the present invention, the clamping circuit includes a second diode D2 and a third diode D3:

[0021] The positive terminal of the second diode D2 is connected to the second end of the second capacitor C2, and the negative terminal of the second diode D2 is connected to the ground terminal GND;

[0022] The positive terminal of the third diode D3 is connected to the ground terminal GND, and the negative terminal of the third diode D3 is connected to the positive terminal of the second diode D2.

[0023] In an embodiment of the present invention, both the second diode D2 and the third diode D3 are clamping diodes.

[0024] In an embodiment of the present invention, the amplifier circuit further includes a first operational amplifier U1, a fourth resistor R4, and a fifth resistor R5;

[0025] The first end of the fourth resistor R4 is connected to the ground terminal GND, and the second end of the fourth resistor R4 is connected to the negative pole of the first operational amplifier U1;

[0026] The first end of the fifth resistor R5 is connected to the negative pole of the first operational amplifier U1, and the second end of the fifth resistor R5 is connected to the output terminal of the first operational amplifier U1;

[0027] The positive pole of the first operational amplifier U1 is connected to the negative terminal of the third diode D3.

[0028] In an embodiment of the present invention, the proportional-integral circuit includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a second operational amplifier U2;

[0029] The first end of the sixth resistor R6 is connected to the output terminal of the first operational amplifier U1, and the second end of the sixth resistor R6 is connected to the first end of the third capacitor C3;

[0030] The second end of the third capacitor C3 is connected to the ground terminal GND;

[0031] The first end of the seventh resistor R7 is connected to the second end of the sixth resistor R6, and the second end of the seventh resistor R7 is connected to the positive pole of the second operational amplifier U2;

[0032] The first end of the eighth resistor R8 is connected to the ground terminal GND, and the second end of the eighth resistor R8 is connected to the negative pole of the second operational amplifier U2;

[0033] The first end of the fourth capacitor C4 is connected to the ground terminal GND, and the second end of the fourth capacitor C4 is connected to the negative pole of the second operational amplifier U2;

[0034] The first end of the ninth resistor R9 is connected to the negative pole of the second operational amplifier U2, and the second end of the ninth resistor R9 is connected to the positive pole of the power supply VCC;

[0035] The first end of the tenth resistor R10 is connected to the positive pole of the second operational amplifier U2, and the second end of the tenth resistor R10 is connected to the output end of the second operational amplifier U2;

[0036] The first end of the fifth capacitor C5 is connected to the positive pole of the second operational amplifier U2, and the second end of the fifth capacitor C5 is connected to the output end of the second operational amplifier U2;

[0037] The first end of the sixth capacitor C6 is connected to the positive pole of the power supply VCC, and the second end of the sixth capacitor C6 is connected to the ground terminal GND.

[0038] In an embodiment of the present invention, the filtering circuit includes an eleventh resistor R11 and a seventh capacitor C7;

[0039] The first end of the eleventh resistor R11 is connected to the output end of the second operational amplifier U2, and the second end of the eleventh resistor R11 is connected to the first end of the seventh capacitor C7;

[0040] The second end of the seventh capacitor C7 is connected to the ground terminal GND.

[0041] In an embodiment of the present invention, the inverting circuit includes a logic inverter U3. The input end of the logic inverter U3 is connected to the first end of the seventh capacitor C7, and the output end of the logic inverter U3 is connected to the PWM capture port of the control chip.

[0042] The above technical solution of the present invention has the following advantages compared with the prior art:

[0043] A processing circuit applied to a vehicle speed sensor of the present invention does not need to use an integrated chip, and only uses a general operational amplifier, a diode and resistive-capacitive elements to complete signal conditioning and analysis. Therefore, it has stronger versatility and lower cost. By flexibly adjusting circuit parameters such as amplification and filtering, it can adapt to different application environments and has lower requirements for the quality of the original input signal; at the same time, this circuit only needs a single signal pin and a ground wire to realize the collection of the speed signal, which is more concise than the dual-pin input method required by the existing integrated chip solution and effectively saves system interface resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to make the content of the present invention easier to be clearly understood, the following further details the present invention according to specific embodiments of the present invention in conjunction with the drawings.

[0045] Figure 1 It is a schematic diagram of the processing circuit applied to the vehicle speed sensor of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the exemplified embodiments are not intended to limit the present invention.

[0047] In the present invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of the present invention, rather than indicating or implying that the technical features referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0048] In the present invention, the meaning of "several" is one or more, the meaning of "multiple" is two or more, and "greater than", "less than", "exceeding", etc. are understood not to include the recited number; "above", "below", "within", etc. are understood to include the recited number. In the description of the present invention, if "first" and "second" are described, they are only used to distinguish technical features and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0049] In the present invention, unless otherwise clearly defined, terms such as "arranged", "installed", "connected", etc. should be understood in a broad sense. For example, they can be directly connected, or indirectly connected through an intermediate medium; they can be fixedly connected, or detachably connected, or integrally formed; they can be mechanically connected, or electrically connected or capable of communicating with each other; they can be the communication inside two components or the interaction relationship between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in the present invention in combination with the specific content of the technical solution.

[0050] Refer to Figure 1 As shown, an in-vehicle rotational speed sensor processing circuit of the present invention includes:

[0051] A bias circuit, whose input terminal is connected to an input signal from an in-vehicle rotational speed sensor, and the bias circuit is used to apply a bias voltage to the input signal to enhance its signal strength; wherein, when the amplitude of the input signal is small, the bias circuit is loaded onto the original input signal, enhancing the signal strength of the original input signal and increasing the EMS capability;

[0052] A DC blocking circuit, whose input terminal is connected to the output terminal of the bias circuit, and the DC blocking circuit is used to convert the input signal from a DC quantity to an AC quantity;

[0053] A clamping circuit, whose input terminal is connected to the output terminal of the DC blocking circuit, and the clamping circuit is used to clamp and control the signal amplitude of the input signal converted to an AC quantity within a required range;

[0054] An amplifier circuit, whose input terminal is connected to the output terminal of the clamping circuit, and the amplifier circuit is used to perform gain amplification on the input signal after clamping;

[0055] A proportional-integral circuit, whose input terminal is connected to the output terminal of the amplifier circuit, and the proportional-integral circuit is used to convert the input signal after gain amplification into a PWM square-wave signal, where the input signal after gain amplification is a sine signal output by the amplifier circuit;

[0056] A filter circuit, whose input terminal is connected to the output terminal of the proportional-integral circuit, and the filter circuit is used to filter out high-frequency interference signals in the PWM square-wave signal;

[0057] A logic inversion circuit, whose input terminal is connected to the output terminal of the filter circuit, and the logic inversion circuit is used to invert the filtered PWM square-wave signal to reduce the rise and fall times of the square wave, and output this signal to a control chip (MCU) for rotational speed data analysis.

[0058] In one embodiment, the bias circuit includes a VCC power supply, a first resistor R1, a second resistor R2, a first capacitor C1, and a first diode D1;

[0059] The first end of the first resistor R1 is connected to the input port (SPIN-sin) of the vehicle speed sensor, and the second end of the first resistor R1 is connected to the ground terminal GND;

[0060] The first end of the first capacitor C1 is connected to the first end of the first resistor R1, and the second end of the first capacitor C1 is connected to the ground terminal GND;

[0061] The negative terminal of the first diode D1 is connected to the first end of the first resistor R1, and the positive terminal of the first diode D1 is connected to the first end of the second resistor R2;

[0062] The second end of the second resistor R2 is connected to the positive pole of the VCC power supply, and the negative pole of the VCC power supply is connected to the ground terminal GND.

[0063] In one embodiment, the DC-blocking circuit includes a third resistor R3 and a second capacitor C2;

[0064] The first end of the third resistor R3 is connected to one end of the first resistor R1, and the second end of the third resistor R3 is connected to the first end of the second capacitor C2.

[0065] Specifically, for the VCC power supply, it is required to be output by an automotive-grade LDO, with an accuracy of 2%;

[0066] In one embodiment, the clamping circuit includes a second diode D2 and a third diode D3:

[0067] The positive terminal of the second diode D2 is connected to the second terminal of the second capacitor C2, and the negative terminal of the second diode D2 is connected to the ground terminal GND;

[0068] The positive terminal of the third diode D3 is connected to the ground terminal GND, and the negative terminal of the third diode D3 is connected to the positive terminal of the second diode D2.

[0069] In one embodiment, both the second diode D2 and the third diode D3 are clamping diodes, and the clamping voltage is 0.7V.

[0070] In one embodiment, the amplifier circuit further includes a first operational amplifier U1, a fourth resistor R4, and a fifth resistor R5;

[0071] The first terminal of the fourth resistor R4 is connected to the ground terminal GND, and the second terminal of the fourth resistor R4 is connected to the negative electrode of the first operational amplifier U1;

[0072] The first terminal of the fifth resistor R5 is connected to the negative electrode of the first operational amplifier U1, and the second terminal of the fifth resistor R5 is connected to the output terminal of the first operational amplifier U1;

[0073] The positive electrode of the first operational amplifier U1 is connected to the negative terminal of the third diode D3.

[0074] In one embodiment, the proportional-integral circuit includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a second operational amplifier U2;

[0075] The first terminal of the sixth resistor R6 is connected to the output terminal of the first operational amplifier U1, and the second terminal of the sixth resistor R6 is connected to the first terminal of the third capacitor C3;

[0076] The second terminal of the third capacitor C3 is connected to the ground terminal GND;

[0077] The first terminal of the seventh resistor R7 is connected to the second terminal of the sixth resistor R6, and the second terminal of the seventh resistor R7 is connected to the positive electrode of the second operational amplifier U2;

[0078] The first terminal of the eighth resistor R8 is connected to the ground terminal GND, and the second terminal of the eighth resistor R8 is connected to the negative electrode of the second operational amplifier U2;

[0079] The first terminal of the fourth capacitor C4 is connected to the ground terminal GND, and the second terminal of the fourth capacitor C4 is connected to the negative electrode of the second operational amplifier U2;

[0080] The first end of the ninth resistor R9 is connected to the negative pole of the second operational amplifier U2, and the second end of the ninth resistor R9 is connected to the positive pole of the power supply VCC;

[0081] The first end of the tenth resistor R10 is connected to the positive pole of the second operational amplifier U2, and the second end of the tenth resistor R10 is connected to the output end of the second operational amplifier U2;

[0082] The first end of the fifth capacitor C5 is connected to the positive pole of the second operational amplifier U2, and the second end of the fifth capacitor C5 is connected to the output end of the second operational amplifier U2;

[0083] The first end of the sixth capacitor C6 is connected to the positive pole of the power supply VCC, and the second end of the sixth capacitor C6 is connected to the ground terminal GND.

[0084] In one embodiment, the filtering circuit includes an eleventh resistor R11 and a seventh capacitor C7;

[0085] The first end of the eleventh resistor R11 is connected to the output end of the second operational amplifier U2, and the second end of the eleventh resistor R11 is connected to the first end of the seventh capacitor C7;

[0086] The second end of the seventh capacitor C7 is connected to the ground terminal GND.

[0087] Specifically, the first operational amplifier U1 and the second operational amplifier U2 have a maximum supply voltage of 32V.

[0088] In one embodiment, the inverting circuit includes a logic inverter U3. The input end of the logic inverter U3 is connected to the first end of the seventh capacitor C7, and the output end of the logic inverter U3 is connected to the PWM capture port (SPIN-pwm) of the control chip MCU. The MCU analyzes the signal to obtain the rotational speed signal. The response time of the logic inverter U3 reaches the microsecond level.

[0089] It should be noted that this vehicle-mounted rotational speed sensor processing circuit is applied to the acquisition and analysis of magnetic chain rotational speed signals. When the signal amplitude is small, the bias circuit is loaded onto the original signal to enhance the signal strength of the original input signal and increase the EMS capability; the capacitive isolation circuit converts the signal from a direct current quantity to an alternating current quantity;

[0090] The clamping circuit clamps a voltage with a large amplitude to a range that the subsequent circuit can withstand, protecting the circuit from damage due to too large a signal amplitude; the amplification circuit amplifies the signal, and the maximum voltage will not exceed the supply voltage of the first operational amplifier U1; the proportional-integral circuit converts the sine signal into a PWM square-wave signal; the filtering circuit is an RC low-pass filter that can filter out high-frequency signals; the inversion circuit inverts the conditioned signal to reduce the rise and fall times of the square wave, and the output signal is given to the MCU for sampling.

[0091] The working principle of the present invention is specifically described as follows:

[0092] When an input signal is input, the bias circuit superimposes a bias voltage on the input signal, and the bias ≈ (VCC - VF D1 ) * R2 / (R1 + R2), so as to increase the signal strength of the input signal;

[0093] Then the signal passes through the Jung and clamping circuits to control the signal amplitude within: -VF D3 ~+VF D2 , and the amplitude < the input amplitude of U1;

[0094] The signal is amplified by the amplification circuit, and the amplification factor = -R5 / R4. By adjusting the ratio of R5 and R4, the output amplitude of the amplification circuit can be adjusted, and the maximum value < VCC;

[0095] The output of the amplification circuit is integrated by the proportional-integral circuit to convert the signal into a PWM square-wave signal;

[0096] The high-frequency interference signals are filtered out by the filtering circuit, and the cut-off frequency is related to R11 and C7;

[0097] The signal quality is further optimized by the inversion circuit to reduce the rise and fall times.

[0098] Finally, the processed PWM square-wave signal is given to the MCU for parsing to obtain the rotational speed signal data.

[0099] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A processing circuit for a vehicle speed sensor, characterized in that: include: A bias circuit, whose input end is connected to an input signal from an on-vehicle speed sensor, and the bias circuit is used to apply a bias voltage to the input signal to enhance its signal strength; A DC isolation circuit, whose input end is connected to the output end of the bias circuit, and the DC isolation circuit is used to convert the input signal from a DC quantity to an AC quantity; A clamping circuit, whose input end is connected to the output end of the DC blocking circuit, and the clamping circuit is used to clamp the signal amplitude of the input signal converted into an AC quantity to a desired range; an amplifier circuit, whose input end is connected to the output end of the clamping circuit, and the amplifier circuit is used to perform gain amplification on the input signal after clamping; A proportional-integral circuit, whose input end is connected to the output end of the amplifier circuit, and the proportional-integral circuit is used to convert the input signal after gain amplification into a PWM square wave signal, wherein the input signal after gain amplification is a sinusoidal signal output by the amplifier circuit; A filter circuit, whose input end is connected to the output end of the proportional integral circuit, and the filter circuit is used to filter out high-frequency interference signals in the PWM square wave signal; A logic inversion circuit, whose input end is connected to the output end of the filtering circuit, is used to invert the filtered PWM square wave signal to reduce the rising and falling edge time of the square wave, and output the signal to the control chip for speed data analysis.

2. The processing circuit for a vehicle speed sensor according to claim 1, characterized in that: The bias circuit includes a VCC power supply, a first resistor R1, a second resistor R2, a first capacitor C1, and a first diode D1; The first end of the first resistor R1 is connected to the input port of the vehicle speed sensor, and the second end of the first resistor R1 is connected to the ground terminal GND; A first end of the first capacitor C1 is connected to a first end of the first resistor R1, and a second end of the first capacitor C1 is connected to a ground terminal GND; The cathode terminal of the first diode D1 is connected to the first end of the first resistor R1, and the anode terminal of the first diode D1 is connected to the first end of the second resistor R2; The second end of the second resistor R2 is connected to the positive electrode of the VCC power supply, and the negative electrode of the VCC power supply is connected to the ground terminal GND.

3. The processing circuit for a vehicle speed sensor according to claim 2, characterized in that: The DC blocking circuit includes a third resistor R3 and a second capacitor C2; A first end of the third resistor R3 is connected to one end of the first resistor R1 , and a second end of the third resistor R3 is connected to a first end of the second capacitor C2 .

4. The processing circuit for a vehicle speed sensor according to claim 3, characterized in that: The clamping circuit includes a second diode D2 and a third diode D3: The positive terminal of the second diode D2 is connected to the second terminal of the second capacitor C2, and the negative terminal of the second diode D2 is connected to the ground terminal GND; An anode terminal of the third diode D3 is connected to the ground terminal GND, and a cathode terminal of the third diode D3 is connected to an anode terminal of the second diode D2.

5. The processing circuit for a vehicle speed sensor according to claim 4, characterized in that: The second diode D2 and the third diode D3 are both clamping diodes.

6. The processing circuit for a vehicle speed sensor according to claim 4, characterized in that: The amplifying circuit also includes a first operational amplifier U1, a fourth resistor R4, and a fifth resistor R5; A first end of the fourth resistor R4 is connected to the ground terminal GND, and a second end of the fourth resistor R4 is connected to the negative electrode of the first operational amplifier U1; A first end of the fifth resistor R5 is connected to the negative electrode of the first operational amplifier U1, and a second end of the fifth resistor R5 is connected to the output end of the first operational amplifier U1; The anode of the first operational amplifier U1 is connected to the cathode of the third diode D3.

7. The processing circuit for a vehicle speed sensor according to claim 6, characterized in that: The proportional integral circuit includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a second operational amplifier U2; The first end of the sixth resistor R6 is connected to the output end of the first operational amplifier U1, and the second end of the sixth resistor R6 is connected to the first end of the third capacitor C3; The second end of the third capacitor C3 is connected to the ground GND; The first end of the seventh resistor R7 is connected to the second end of the sixth resistor R6, and the second end of the seventh resistor R7 is connected to the positive electrode of the second operational amplifier U2; A first end of the eighth resistor R8 is connected to the ground terminal GND, and a second end of the eighth resistor R8 is connected to the negative electrode of the second operational amplifier U2; A first terminal of the fourth capacitor C4 is connected to the ground terminal GND, and a second terminal of the fourth capacitor C4 is connected to the negative electrode of the second operational amplifier U2; A first end of the ninth resistor R9 is connected to the negative electrode of the second operational amplifier U2, and a second end of the ninth resistor R9 is connected to the positive electrode of the power supply VCC; A first end of the tenth resistor R10 is connected to the positive electrode of the second operational amplifier U2, and a second end of the tenth resistor R10 is connected to the output end of the second operational amplifier U2; A first end of the fifth capacitor C5 is connected to the positive electrode of the second operational amplifier U2, and a second end of the fifth capacitor C5 is connected to the output end of the second operational amplifier U2; A first terminal of the sixth capacitor C6 is connected to the positive electrode of the power source VCC, and a second terminal of the sixth capacitor C6 is connected to the ground terminal GND.

8. The processing circuit for a vehicle speed sensor according to claim 7, characterized in that: The filter circuit includes an eleventh resistor R11 and a seventh capacitor C7; A first end of the eleventh resistor R11 is connected to the output end of the second operational amplifier U2, and a second end of the eleventh resistor R11 is connected to a first end of the seventh capacitor C7; A second terminal of the seventh capacitor C7 is connected to the ground terminal GND.

9. The processing circuit for a vehicle speed sensor according to claim 8, characterized in that: The inversion circuit includes a logic inverter U3, an input end of the logic inverter U3 is connected to the first end of the seventh capacitor C7, and an output end of the logic inverter U3 is connected to the PWM capture port of the control chip.