FPGA debugging system, method, equipment and medium
By designing an FPGA debugging system including probe module, message resolution module and timestamp module, the problems of low FPGA debugging efficiency and limited data storage capacity in the prior art are solved, and real-time monitoring and efficient debugging of FPGA are realized.
Patent Information
- Application Number
- CN202510110628.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-27
AI Technical Summary
The existing FPGA debugging methods need to be implemented repeatedly, resulting in low debugging efficiency and the test data is stored in RAM, with limited capacity, making it difficult to perform comprehensive bug positioning.
An FPGA debugging system is designed, including multiple probe modules, message analysis modules, probe analysis modules, timestamp modules and message packaging modules. Through these modules, real-time monitoring and efficient debugging of FPGAs are realized, and the debugging data is stored in the onboard DDR.
Real-time monitoring and efficient debugging of FPGAs are realized, debugging efficiency is improved, and the problems of repeated comprehensive implementation and limited data storage capacity are overcome.
Smart Images
Figure CN120044377A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic device testing, and particularly to an FPGA debugging system, method, device and medium. Background Art
[0002] FPGA (Field Programmable Gate Array) is an integrated circuit with programmable characteristics pre-designed and implemented on a silicon chip. It can be configured into a specified circuit structure according to the needs of designers, enabling customers not to rely on ASIC (Application Specific Integrated Circuit) chips designed and manufactured by chip manufacturers. It is widely used in fields such as prototype verification, communication, automotive electronics, industrial control, aerospace, and data centers.
[0003] Currently, systems using FPGAs face complex debugging problems. The common method for FPGA debugging is to add an Integrated Logic Analyzer (ILA). However, each time a new ILA is added, the module needs to be synthesized and implemented, which is an essential process in FPGA design. If the project is large, a single synthesis and implementation can take several hours. At the same time, when debugging by adding an ILA, the test data is stored in the RAM. At this time, only a small amount of test data can be stored. When locating bugs, only a small amount of test data can be used for positioning. If the positioning is not successful, it is necessary to add a new ILA to replace the collected test data. Summary of the Invention
[0004] To solve the above problems, this application proposes an FPGA debugging system, method, device and medium. An FPGA debugging system includes:
[0005] Multiple probe modules, each connected to a respective module within the FPGA under test, for caching debugging data and sending the debugging data to a message packing module; a message parsing module for parsing a debugging instruction sent by a host computer to obtain a control command; the control command includes the name of the module to be debugged and a debugging trigger condition; a probe analysis module for activating the corresponding probe module according to the control command and loading the debugging data of the module to be debugged into the corresponding probe module after the debugging trigger condition is satisfied; a timestamp module that starts timing when a command for the host computer to debug the module under test is obtained, for adding a timestamp to the debugging data; a message packing module for packing the debugging data of the module to be debugged into a data message in a preset format and sending the data message to the on-board DDR.
[0006] In one example, the FPGA debugging system further includes: an exception monitoring module, connected to the probe module and the probe analysis module, for monitoring exceptions of the probe module and the probe analysis module; a statistical extraction module, connected to the exception monitoring module, for counting the exception data monitored by the exception monitoring module and feeding back the exception data to the host computer.
[0007] In one example, the FPGA debugging system further includes: a high-speed Ethernet module, for transmitting debugging commands and debugging data between the host computer and the FPGA.
[0008] In one example, the FPGA debugging system further includes: a status extraction module, for extracting status data of each module in the to-be-tested FPGA, where the status data is data for indicating the control status of each module in the to-be-tested FPGA.
[0009] This application also provides an FPGA debugging method, including: receiving and parsing a debugging instruction from a host computer to obtain a control command; the control command includes the name of the to-be-debugged module and a debugging trigger condition; determining the to-be-debugged module according to the control command, and enabling the corresponding probe module of the to-be-debugged module; after the debugging trigger condition is satisfied, loading the hierarchical debugging data of the to-be-debugged module into the corresponding probe module; starting timing when receiving the host computer's command to debug the to-be-tested module, and adding a timestamp to the debugging data; packing the debugging data with the added timestamp into a data packet in a preset format to obtain a data message, and sending the data message back to the host computer and storing it in the format of a waveform file.
[0010] In one example, before sending the data message back to the host computer and storing it in the format of a waveform file, the method further includes: extracting the status data of all state machines in the to-be-tested FPGA, and monitoring the probe module and the probe analysis module to obtain exception data; packing the status data and the exception data into the data message.
[0011] In one example, after sending the data message back to the host computer and storing it in the format of a waveform file, the method further includes: analyzing the waveform file through a preset analysis software to determine the status of the to-be-debugged module, all state machines, the probe module, and the probe analysis module in the to-be-tested FPGA, and generating log information; if there is a status exception in the to-be-tested FPGA, intercepting the waveform data corresponding to a specific time period in the waveform file according to the log information and the timestamp for code exception location; after repairing the abnormal code, sending a debugging instruction to the to-be-tested FPGA again.
[0012] In one example, the data packet includes: a packet header, a timestamp, and a checksum; the abnormal data includes at least one of probe module storage abnormality and instruction abnormality; the status data includes at least one of state machine data and internal buffer abnormality of the FPGA under test.
[0013] The present application also provides an FPGA debugging device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to: receive and parse a debugging instruction from a host computer to obtain a control command; the control command includes the name of the module to be debugged and a debugging trigger condition; determine the module to be debugged according to the control command, and activate the probe module corresponding to the module to be debugged; after the debugging trigger condition is satisfied, load the hierarchical debugging data of the module to be debugged into the corresponding probe module; start timing when receiving a host computer command to debug the module under test, add a timestamp to the debugging data; packetize the debugging data with the added timestamp according to a preset format to obtain a data packet, and send the data packet back to the host computer and store it in the format of a waveform file.
[0014] The present application also provides a non-volatile computer storage medium storing computer-executable instructions, which are set to: receive and parse a debugging instruction from a host computer to obtain a control command; the control command includes the name of the module to be debugged and a debugging trigger condition; determine the module to be debugged according to the control command, and activate the probe module corresponding to the module to be debugged; after the debugging trigger condition is satisfied, load the hierarchical debugging data of the module to be debugged into the corresponding probe module; start timing when receiving a host computer command to debug the module under test, add a timestamp to the debugging data; packetize the debugging data with the added timestamp according to a preset format to obtain a data packet, and send the data packet back to the host computer and store it in the format of a waveform file.
[0015] The method proposed by the present application can bring the following beneficial effects: by storing the debugging data in the on-board DDR instead of the relatively small RAM, the problem of repeated synthesis implementation in FPGA debugging is overcome, real-time monitoring of the FPGA is achieved, the debugging efficiency of the FPGA is improved, and efficient debugging of the FPGA is realized. Description of the Drawings
[0016] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:
[0017] Figure 1 It is a schematic structural diagram of an FPGA debugging system in an embodiment of the present application;
[0018] Figure 2 It is a schematic flow diagram of an FPGA debugging method in an embodiment of the present application;
[0019] Figure 3 It is a schematic structural diagram of an FPGA debugging device in an embodiment of the present application. Detailed implementation manners
[0020] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below in conjunction with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0021] The following will describe in detail the technical solutions provided by the embodiments of the present application in conjunction with the drawings.
[0022] As Figure 1 shown, the FPGA debugging system provided by the present application includes multiple probe modules, which are represented as probe FIFO1 - probe FIFO1n in Figure 1 and are respectively connected to each module in the FPGA to be tested, used to cache debugging data and send the debugging data to the message packing module.
[0023] A message parsing module, used to parse the debugging instructions sent by the host computer to obtain control commands, where the control commands include the names of the modules to be debugged and the debugging trigger conditions. The module to be debugged here can be one or multiple, that is, multiple modules in the FPGA system are debugged simultaneously. In Figure 1 it, the module to be debugged is represented as DUT, and at this time the debugging trigger condition can also be one or multiple.
[0024] A probe analysis module connected to the probe module, which is used to activate the corresponding probe module according to a control command, and after the debugging trigger condition is satisfied, load the debugging data of the module to be debugged into the corresponding probe module. A timestamp module, which is a counter that starts timing when receiving a command from the host computer to debug the module to be tested, and is used to add timestamps to the debugging data. A message packaging module, which is used to package the debugging data of the module to be debugged in a preset format to obtain a data message, and send the data message to the on-board DDR.
[0025] In one embodiment, the FPGA debugging system further includes an anomaly monitoring module and a statistical extraction module. The anomaly monitoring module is connected to the probe module and the probe analysis module, and is used to monitor anomalies in the probe module and the probe analysis module. When monitoring anomalies in the probe module, it mainly monitors anomalies in the FIFO of the probe module. When monitoring anomalies in the probe analysis module, it is mainly used to monitor whether the control command is an illegal instruction. The statistical extraction module is connected to the anomaly monitoring module, and is used to count the anomaly data monitored by the anomaly monitoring module and feedback the anomaly data to the host computer.
[0026] In one embodiment, the FPGA debugging system further includes a high-speed Ethernet module, which is used to transmit debugging commands and debugging data between the host computer and the FPGA.
[0027] In one embodiment, the FPGA debugging system further includes a status extraction module, which is used to extract the status data of each module in the FPGA to be tested. The status data is data used to indicate the control status of each module in the FPGA to be tested. These status data are usually used to indicate the data or control status of each module in the FPGA to be tested, such as the status of the state machine, the empty / full status of the internal FIFO, etc.
[0028] Figure 2 It is a schematic flowchart of an FPGA debugging method provided by one or more embodiments of this specification. This process can be executed by a computing device in the relevant field. Some input parameters or intermediate results in the process allow manual intervention and adjustment to help improve accuracy.
[0029] The implementation of the analysis method involved in the embodiments of this application can be a terminal device or a server. This application does not make special restrictions on this. For the convenience of understanding and description, the following embodiments will be described in detail using a server as an example.
[0030] It should be noted that this server can be a single device or a system composed of multiple devices, that is, a distributed server. This application does not make specific limitations on this.
[0031] As Figure 2 shown, the embodiments of this application provide an FPGA debugging method, including:
[0032] S201: Receive and parse the debugging instruction from the host computer to obtain a control command; the control command includes the name of the module to be debugged and the debugging trigger condition.
[0033] After the server receives the debugging instruction from the host computer, it parses the debugging instruction through the message parsing module to obtain a control instruction. Here, the control command includes the name of the module to be debugged and the debugging trigger condition. When the debugging trigger condition is met, the data output by the module to be debugged is the debugging data to be measured.
[0034] S202: Determine the module to be debugged according to the control command, and activate the probe module corresponding to the module to be debugged.
[0035] After obtaining the control command, one or more modules to be debugged can be determined according to the name of the module to be debugged in the control command, and the probe module corresponding to the module to be debugged is activated. It should be noted that one probe module may correspond to one or more FPGA modules.
[0036] S203: After the debugging trigger condition is met, load the hierarchical debugging data of the module to be debugged into the corresponding probe module.
[0037] When the debugging trigger condition is met, through the round-robin arbiter in the probe analysis module, the hierarchical debugging data of the module to be debugged is cyclically loaded into the corresponding probe module for caching. It should be noted that in this probe module, the module to be debugged is mostly hierarchical because most designs are module-based designs, conforming to the top-down model structure.
[0038] S204: Start timing when receiving the command from the host computer to debug the module to be tested, and add a timestamp to the debugging data.
[0039] After the message parsing module finishes parsing the control instruction, the timestamp module will start timing and add a timestamp to the debugging data obtained by the probe module.
[0040] S205: Pack the debugging data with the added timestamp into a message according to a preset format to obtain a data message, and send the data message back to the host computer and store it in the format of a waveform file.
[0041] In the message packing module, the timestamp is placed in front of the debugging data as the time mark of the debugging data, which is convenient for selecting the debugging data of a certain period through the command of the host computer in the subsequent process. When packing, the debugging data is packed into a message in the format of a packet header, timestamp, and checksum, and the message is sent to the on-board DDR.
[0042] In one embodiment, before sending the data packet back to the host computer and storing it in the format of a waveform file, the method further includes: extracting the status data of all state machines in the FPGA under test, and monitoring the probe module and the probe analysis module to obtain abnormal data; and packing the status data and the abnormal data into the data packet.
[0043] In one embodiment, after sending the data packet back to the host computer and storing it in the format of a waveform file, the method further includes: analyzing the waveform file through a preset analysis software to determine the status of the module to be debugged, all state machines, the probe module, and the probe analysis module in the FPGA under test, and generating log information; if there is an abnormal status in the FPGA under test, intercepting the waveform data corresponding to a specific time period in the waveform file according to the log information and the timestamp for code anomaly location; after repairing the abnormal code, reissuing a debugging instruction to the FPGA under test. The abnormal monitoring module here has two major functions: First, if there is an error in the data or command, the host computer needs to know in time and reload the correct command. Second, ensure that each module in the debugging system proposed in this application is problem-free. If there is a problem with the debugging system, a reset of the whole is required.
[0044] In one embodiment, the data packet includes: a packet header, a timestamp, and a checksum; the abnormal data includes at least one of abnormal storage in the probe module and instruction anomaly; the status data includes at least one of state machine data and internal cache anomaly in the FPGA under test.
[0045] As Figure 3 shown, this application also provides an FPGA debugging device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute:
[0046] Receiving and parsing a debugging instruction from the host computer to obtain a control command; the control command includes the name of the module to be debugged and a debugging trigger condition; determining the module to be debugged according to the control command, and enabling the corresponding probe module of the module to be debugged; after the debugging trigger condition is satisfied, loading the hierarchical debugging data of the module to be debugged into the corresponding probe module; starting timing when receiving the host computer's command to debug the module under test, adding a timestamp to the debugging data; packing the debugging data with the added timestamp into a data packet in a preset format to obtain a data packet, and sending the data packet back to the host computer and storing it in the format of a waveform file.
[0047] The embodiment of the present application also provides a non-volatile computer storage medium, storing computer-executable instructions, and the computer-executable instructions are configured to:
[0048] Receive and parse the debugging instructions from the host computer to obtain control commands; the control commands include the name of the module to be debugged and the debugging trigger condition; determine the module to be debugged according to the control commands, and activate the corresponding probe module of the module to be debugged; after the debugging trigger condition is satisfied, load the hierarchical debugging data of the module to be debugged into the corresponding probe module; start timing when receiving the host computer's command to debug the module to be tested, add a timestamp to the debugging data; packetize the debugging data with the timestamp added in a preset format to obtain a data packet, and send the data packet back to the host computer and store it in the format of a waveform file.
[0049] The embodiments in the present application are all described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiments.
[0050] The devices and media provided by the embodiments of the present application correspond one by one to the methods. Therefore, the devices and media also have beneficial technical effects similar to those of their corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be elaborated here.
[0051] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can be implemented in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be implemented in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.
[0052] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be realized by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to generate a machine, so that the instructions executed by the processors of the computer or other programmable data processing devices generate for realizing in the process Figure 1 one process or multiple processes and / or blocksFigure 1 means for the functions specified in one or more boxes.
[0053] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction means that implements the functions specified in one Figure 1 process or more processes and / or boxes Figure 1 or more boxes.
[0054] These computer program instructions may also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are performed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one Figure 1 process or more processes and / or boxes Figure 1 or more boxes.
[0055] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.
[0056] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM) and / or non-volatile memory such as read-only memory (ROM) or flash RAM. The memory is an example of computer-readable media.
[0057] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media such as modulated data signals and carrier waves.
[0058] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements not only includes those elements but also other elements not expressly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, commodity or device comprising the element.
[0059] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.
Claims
1. An FPGA debugging system, characterized in that: include: A plurality of probe modules are respectively connected to each module in the FPGA to be tested, and are used to cache debug data and send the debug data to the message packaging module; The message parsing module is used to parse the debugging instructions sent by the host computer to obtain the control commands; The control command includes the name of the module to be debugged and the debugging trigger condition; A probe analysis module, used to start the corresponding probe module according to the control command, and load the debugging data of the module to be debugged into the corresponding probe module after the debugging trigger condition is met; A timestamp module, which starts timing when receiving a command from the host computer to debug the module under test, and is used to add a timestamp to the debugging data; The message packing module is used to pack the debugging data of the module to be debugged into messages according to a preset format to obtain data messages, and send the data messages to the onboard DDR.
2. The FPGA debugging system according to claim 1, characterized in that: The FPGA debugging system also includes: An abnormality monitoring module, connected to the probe module and the probe analysis module, and used to monitor abnormalities of the probe module and the probe analysis module; The statistical extraction module is connected to the abnormality monitoring module and is used to collect statistics of abnormal data detected by the abnormality monitoring module and feed back the abnormal data to the host computer.
3. The FPGA debugging system according to claim 1, characterized in that: The FPGA debugging system also includes: a high-speed Ethernet module, which is used for transmitting debugging commands and debugging data between the host computer and the FPGA.
4. The FPGA debugging system according to claim 1, characterized in that: The FPGA debugging system further includes: a state extraction module, which is used to extract state data of each module in the FPGA to be tested, wherein the state data is data used to indicate the control state of each module in the FPGA to be tested.
5. An FPGA debugging method, characterized in that: include: Receive and parse debugging instructions from the host computer to obtain control commands; The control command includes the name of the module to be debugged and the debugging trigger condition; According to the control command, determine the module to be debugged, and start the probe module corresponding to the module to be debugged; After the debugging trigger condition is met, the hierarchical debugging data of the module to be debugged is loaded into the corresponding probe module; When receiving a command from the host computer to debug the module under test, the timing starts, and a timestamp is added to the debugging data; The debugging data with the timestamp added is packaged into messages according to a preset format to obtain data messages, and the data messages are sent back to the host computer and stored in the format of a waveform file.
6. The FPGA debugging method according to claim 5, characterized in that: Before sending the data message back to the host computer and storing it in the format of the waveform file, the method further includes: Extract the state data of all state machines in the FPGA to be tested, and monitor the probe module and the probe analysis module to obtain abnormal data; The state data and the abnormal data are packaged into the data message.
7. The FPGA debugging method according to claim 6, characterized in that: After sending the data message back to the host computer and storing it in the format of the waveform file, the method further includes: Analyze the waveform file by using preset analysis software to determine the status of the module to be debugged, all state machines, probe modules and probe analysis modules in the FPGA to be tested, and generate log information; If there is an abnormal state in the FPGA to be tested, the waveform data corresponding to a specific time period is intercepted in the waveform file according to the log information and the timestamp to locate the code abnormality; After the abnormal code is repaired, the debugging instruction is reissued to the FPGA to be tested.
8. The FPGA debugging method according to claim 7, characterized in that: The data message includes: a packet header, a timestamp and a checksum; The abnormal data includes at least one of a probe module storage abnormality and an instruction abnormality; The state data includes state machine data and at least one of anomalies in the internal cache of the FPGA to be tested.
9. An FPGA debugging device, characterized in that: include: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute: Receive and parse the debugging instructions from the host computer to obtain a control command; the control command includes the name of the module to be debugged and the debugging trigger condition; According to the control command, determine the module to be debugged, and start the probe module corresponding to the module to be debugged; After the debugging trigger condition is met, the hierarchical debugging data of the module to be debugged is loaded into the corresponding probe module; When receiving a command from the host computer to debug the module under test, the timing starts, and a timestamp is added to the debugging data; The debugging data with the timestamp added is packaged into messages according to a preset format to obtain data messages, and the data messages are sent back to the host computer and stored in the format of a waveform file.
10. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured to: Receive and parse the debugging instructions from the host computer to obtain a control command; the control command includes the name of the module to be debugged and the debugging trigger condition; According to the control command, determine the module to be debugged, and start the probe module corresponding to the module to be debugged; After the debugging trigger condition is met, the hierarchical debugging data of the module to be debugged is loaded into the corresponding probe module; When receiving a command from the host computer to debug the module under test, the timing starts, and a timestamp is added to the debugging data; The debugging data with the timestamp added is packaged into messages according to a preset format to obtain data messages, and the data messages are sent back to the host computer and stored in the format of a waveform file.