Display substrate and display panel

Abstract

The invention relates to a display substrate and a display panel. The display substrate comprises a plurality of pixel regions, and a spacer region is arranged between every two adjacent pixel regions. The display substrate comprises a substrate body, a plurality of grid lines, a plurality of data lines, a common electrode and at least one conducting layer. The conductive layer is located between the substrate and a layer where the grid lines are located or located between the layer where the grid lines are located and a layer where the common electrodes are located and electrically connected with the common electrodes, the conductive layer is located in the spacer region, and the conductive layer comprises at least one first conductive wire extending in the extending direction of the data lines and / or at least one second conductive wire extending in the extending direction of the grid lines. The orthographic projection of the first conductive wire and the orthographic projection of the grid lines on the substrate body are overlapped. According to the invention, the transmission resistance of the voltage signal of the common electrode can be reduced, or the coupling capacitance between the common electrode and the grid line can be reduced, and crosstalk can be avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display panel. Background Art

[0002] In the information society, the importance of displays as a medium for visual information transmission is further strengthened. In order to occupy a dominant position in the future, displays are developing towards lighter, thinner, lower energy consumption, lower cost and better image quality. Among them, liquid crystal display panels (LCD) have been widely used in mobile phones, digital cameras, PDAs (Personal Digital Assistants, also known as handheld computers) and other electronic products due to their ability to achieve lighter and thinner, faster display response and other characteristics. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate and a display panel.

[0004] In order to achieve the above object, the present disclosure provides a display substrate, wherein the display substrate comprises a plurality of pixel areas, and a spacing area is provided between two adjacent pixel areas, and the display substrate comprises:

[0005] substrate substrate;

[0006] A plurality of gate lines and a plurality of data lines are located on one side of the base substrate and in the spacing area, and the gate lines and the data lines cross each other;

[0007] A common electrode is located at a side of the gate line and the data line away from the base substrate, and at least a part of the common electrode is located in the pixel area;

[0008] At least one conductive layer, the conductive layer is located between the substrate and the layer where the gate line is located, or between the layer where the gate line is located and the layer where the common electrode is located, and is electrically connected to the common electrode, the conductive layer is located in the spacer area, and the conductive layer includes:

[0009] At least one first conductive line extending along the extending direction of the data line, the first conductive line and the orthographic projections of the plurality of gate lines on the base substrate overlap;

[0010] and / or, at least one second conductive line extending along the gate line extension direction.

[0011] In some embodiments, the data line is located on a side of the gate line away from the substrate;

[0012] The display substrate further includes a first planarization layer located between the common electrode and the data line;

[0013] The conductive layer includes at least one first conductive line, which is disposed in the same layer as the data line and is electrically insulated from the data line;

[0014] The common electrode is electrically connected to the first conductive line through a via hole penetrating the first planarization layer.

[0015] In some embodiments, the data line is located on a side of the gate line away from the substrate;

[0016] The display substrate further comprises:

[0017] A first planarization layer, located between the common electrode and the data line;

[0018] An interlayer dielectric layer, located between the data line and the gate line;

[0019] A buffer layer and a gate insulating layer are located between the gate line and the substrate, and the gate insulating layer is located on a side of the buffer layer away from the substrate;

[0020] The conductive layer is located between the buffer layer and the base substrate, and the common electrode is electrically connected to the conductive layer through a via hole penetrating the first planarization layer, the interlayer dielectric layer, the gate insulating layer and the buffer layer.

[0021] In some embodiments, the display substrate further comprises:

[0022] A plurality of thin film transistors, each thin film transistor comprising a gate, wherein the gate and the gate line are arranged in the same layer;

[0023] A light-blocking layer, located between the buffer layer and the base substrate, wherein the orthographic projection of the light-blocking layer on the base substrate covers the orthographic projection of the gate on the base substrate;

[0024] The conductive layer is arranged on the same layer as the light blocking layer.

[0025] In some embodiments, the conductive layer includes at least one second conductive line, and an orthographic projection of the second conductive line on the base substrate does not overlap with an orthographic projection of the light blocking layer on the base substrate;

[0026] The thin film transistor further comprises:

[0027] an active layer, located between the buffer layer and the gate insulating layer, wherein the active layer comprises a source connecting portion, a drain connecting portion and a channel portion located between the source connecting portion and the drain connecting portion, and an orthographic projection of the channel portion on the base substrate overlaps with an orthographic projection of the data line on the base substrate;

[0028] A source-drain electrode layer, wherein the source-drain electrode layer and the data line are arranged in the same layer, the source-drain electrode layer includes a source and a drain, the source and the data line are connected as an integral structure, and the source is electrically connected to the source connecting portion through a via hole penetrating the gate insulating layer and the interlayer dielectric layer, and the orthographic projection of the source connecting portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0029] In some embodiments, the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the light blocking layer on the base substrate, and the conductive layer includes at least one first conductive line, or the conductive layer includes at least one first conductive line and at least one second conductive line;

[0030] The thin film transistor further comprises:

[0031] an active layer, located between the buffer layer and the gate insulating layer, the active layer comprising a source connecting portion, a drain connecting portion and a channel portion located between the source connecting portion and the drain connecting portion, wherein an orthographic projection of the channel portion on the base substrate does not overlap with an orthographic projection of the data line on the base substrate;

[0032] A source-drain electrode layer, wherein the source-drain electrode layer and the data line are arranged in the same layer, the source-drain electrode layer includes a source and a drain, the source and the data line are connected as an integral structure, and the source is electrically connected to the source connecting portion through a via hole penetrating the gate insulating layer and the interlayer dielectric layer, and the orthographic projection of the source connecting portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0033] In some embodiments, the display substrate further comprises:

[0034] An interlayer dielectric layer, located between the gate line and the data line;

[0035] A first planarization layer, located between the data line and the common electrode;

[0036] at least one third conductive line extending along the extending direction of the gate line, the third conductive line being arranged in the same layer as the gate line and being electrically insulated from the gate line, and the third conductive line being located in the spacing area;

[0037] At least one first conductive part, the first conductive part is arranged in the same layer as the data line and is electrically insulated from the data line, and the first conductive part is located in the spacing area, the conductive layer is electrically connected to the first conductive part, the first conductive part is electrically connected to the third conductive line through a via hole penetrating the interlayer dielectric layer, and the common electrode is electrically connected to the first conductive part through a via hole penetrating the first planarization layer.

[0038] In some embodiments, the data line is located on a side of the gate line away from the substrate;

[0039] The display substrate further comprises:

[0040] A first planarization layer and a second passivation layer are located between the data line and the common electrode, and the second passivation layer is located on a side of the first planarization layer away from the base substrate;

[0041] A first passivation layer is located on a side of the common electrode away from the substrate;

[0042] A pixel electrode, located on a side of the first passivation layer away from the base substrate;

[0043] at least one second conductive portion, the second conductive portion is disposed in the same layer as the pixel electrode and is electrically insulated, and the second conductive portion is located in the spacing area;

[0044] A plurality of thin film transistors are located between the base substrate and the first planarization layer, and the pixel electrode is electrically connected to the thin film transistor through a first via hole penetrating the first passivation layer, the second passivation layer and the first planarization layer;

[0045] The conductive layer is located between the first planarization layer and the second passivation layer, and an orthographic projection of the conductive layer on the base substrate does not overlap with an orthographic projection of the first via hole on the base substrate;

[0046] The second conductive portion is electrically connected to the common electrode through a via hole penetrating the first passivation layer, and is electrically connected to the conductive layer through a via hole penetrating the first passivation layer and the second passivation layer.

[0047] In some embodiments, the display substrate further includes a touch electrode layer located between the first planarization layer and the second passivation layer, and the conductive layer is disposed on the same layer as the touch electrode layer and is electrically insulated.

[0048] In some embodiments, the data line is located on a side of the gate line away from the substrate;

[0049] The display substrate further comprises:

[0050] A first planarization layer and a second planarization layer are located between the data line and the common electrode, and the second planarization layer is located on a side of the first planarization layer away from the base substrate;

[0051] A plurality of third conductive portions, located between the first planarization layer and the second planarization layer and located in the spacing area;

[0052] A first passivation layer is located on a side of the common electrode away from the substrate;

[0053] A pixel electrode, located on a side of the first passivation layer away from the base substrate;

[0054] A plurality of thin film transistors, wherein the thin film transistors include an active layer, a gate and a source-drain electrode layer, wherein the active layer is located between the substrate and the gate line, the gate and the gate line are arranged in the same layer, the source-drain electrode layer and the data line are arranged in the same layer, and the source-drain electrode layer includes a source electrode and a drain electrode;

[0055] Wherein, the conductive layer is located between the first planarization layer and the second planarization layer, and the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the third conductive portion on the base substrate;

[0056] The pixel electrode is electrically connected to the third conductive portion through a via hole penetrating the first passivation layer and the second planarization layer, the third conductive portion is electrically connected to the drain through a via hole penetrating the first planarization layer, and the common electrode is electrically connected to the conductive layer through a via hole penetrating the second planarization layer.

[0057] In some embodiments, the third conductive portion is disposed on the same layer as the conductive layer;

[0058] And / or, the display substrate further includes a touch electrode layer located between the first planarization layer and the second planarization layer, and the conductive layer is disposed in the same layer as the touch electrode layer and is electrically insulated from the touch electrode layer.

[0059] In some embodiments, the display substrate further comprises:

[0060] An interlayer dielectric layer, located between the gate line and the data line;

[0061] At least one third conductive line extending along the extending direction of the gate line, wherein the third conductive line is disposed in the same layer as the gate line and is electrically insulated from the gate line;

[0062] At least one first conductive portion, the first conductive portion is disposed in the same layer as the data line and is electrically insulated;

[0063] The conductive layer is electrically connected to the first conductive part through a via hole penetrating the first planarization layer, and the first conductive part is electrically connected to the third conductive line through a via hole penetrating the interlayer dielectric layer.

[0064] In some embodiments, the conductive layer includes at least one first conductive line and at least one second conductive line, and the first conductive line and the second conductive line are connected to form an integral structure.

[0065] In some embodiments, the conductive layer includes at least one first conductive line, the first conductive line includes a main portion extending along an extension direction of the data line and at least one protruding portion electrically connected to the main portion, the orthographic projection of the main portion on the substrate overlaps with the orthographic projection of the data line on the substrate, and the common electrode is electrically connected to the protruding portion.

[0066] The present disclosure also provides a display panel, comprising the display substrate as described in any one of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0068] Figure 1 is a schematic diagram showing a cross-sectional structure of a substrate in some embodiments;

[0069] Figure 2A yes Figure 1 A schematic diagram of a planar structure of a display substrate is shown;

[0070] Figure 2B yes Figure 2A Schematic diagram of the planar structure of the common electrode;

[0071] Figure 2C yes Figure 2A A schematic diagram of the planar structure of the middle gate and the third conductive line;

[0072] Figure 2D yes Figure 2A Schematic diagram of the planar structure of the active layer;

[0073] Figure 2E yes Figure 2A A schematic diagram of the planar structure of the data line, the first conductive portion, and the source-drain electrode layer;

[0074] Figure 2F yes Figure 2A Schematic diagram of the planar structure of the middle light-blocking layer;

[0075] Figure 2G yes Figure 2ASchematic diagram of the planar structure of the pixel electrode;

[0076] Figure 3 is a schematic diagram of a cross-sectional structure of a display substrate in some embodiments of the present disclosure;

[0077] Figure 4A yes Figure 3 A schematic diagram of a planar structure of a display substrate is shown;

[0078] Figure 4B yes Figure 4A A schematic diagram of the planar structure of the data line, the conductive layer, the first conductive portion and the source-drain electrode layer;

[0079] Figure 5 is a schematic diagram of a cross-sectional structure of a substrate in other embodiments of the present disclosure;

[0080] Fig. 6A yes Figure 5 A schematic diagram of a planar structure of a display substrate is shown;

[0081] Figure 6B yes Fig. 6A A schematic diagram of the planar structure of the data line, the first conductive part and;

[0082] Figure 6C is a schematic diagram of the planar structure of the second conductive line and the light blocking layer;

[0083] Fig. 7A yes Figure 5 Another schematic diagram of the planar structure of the display substrate is shown;

[0084] Figure 7B yes Fig. 7A Schematic diagram of the planar structure of the active layer;

[0085] Figure 7C yes Fig. 7A Schematic diagram of the planar structure of the conductive layer and the light-blocking layer;

[0086] Fig. 8A yes Figure 5 A schematic diagram of another planar structure of the display substrate is shown;

[0087] Figure 8B yes Fig. 8A Schematic diagram of the planar structure of the conductive layer and the light-blocking layer;

[0088] Fig. 9 is a schematic diagram of a cross-sectional structure of a substrate in other embodiments of the present disclosure;

[0089] Fig. 10A yes Fig. 9 A schematic diagram of a planar structure of a display substrate is shown;

[0090] Fig. 10B yes Fig. 10A Schematic diagram of the planar structure of the light-blocking layer and the conductive layer;

[0091] Fig.11 is a schematic diagram of a cross-sectional structure of a substrate in other embodiments of the present disclosure;

[0092] Fig. 12A yes Fig.11 A schematic diagram of a planar structure of a display substrate is shown;

[0093] Fig. 12B yes Fig. 12A A schematic diagram of the planar structure of the pixel electrode and the second conductive portion;

[0094] Fig. 12C yes Fig. 12A Schematic diagram of the planar structure of the conductive layer;

[0095] Fig.13A yes Fig.11 Another schematic diagram of the planar structure of the display substrate is shown;

[0096] Fig. 13B yes Fig.13A Schematic diagram of the planar structure of the conductive layer;

[0097] Fig.14A yes Fig.11 A schematic diagram of another planar structure of the display substrate is shown;

[0098] Fig. 14B yes Fig.14A Schematic diagram of the planar structure of the conductive layer;

[0099] Fig.15 is a schematic diagram of a cross-sectional structure of a substrate in other embodiments of the present disclosure;

[0100] Fig.16A yes Fig.15 A schematic diagram of a planar structure of a display substrate is shown;

[0101] Fig. 16B yes Fig.16A Schematic diagram of the plane structure of the middle grid line;

[0102] Fig. 16C yes Fig.16A A schematic diagram of the planar structure of the data line and the source-drain electrode layer;

[0103] Fig.16D yes Fig.16A Schematic diagram of the planar structure of the pixel electrode;

[0104] Fig.16E yes Fig.16A A schematic diagram of the planar structure of the middle conductive layer and the third conductive portion;

[0105] Fig.17A yes Fig.15 Another schematic diagram of the planar structure of the display substrate is shown;

[0106] Fig. 17B yes Fig.17A A schematic diagram of the planar structure of the middle conductive layer and the third conductive portion;

[0107] Fig.18A yes Fig.15 A schematic diagram of another planar structure of the display substrate is shown;

[0108] Fig.18B yes Fig.18A A schematic diagram of the planar structure of the middle conductive layer and the third conductive portion;

[0109] Fig.19 is a schematic diagram of a cross-sectional structure of a substrate in other embodiments of the present disclosure;

[0110] Fig. 20A yes Fig.19 A schematic diagram of a planar structure of a display substrate is shown;

[0111] Fig. 20B yes Fig. 20A A schematic diagram of the planar structure of the middle conductive layer and the third conductive portion;

[0112] Fig.21A yes Fig.19 Another schematic diagram of the planar structure of the display substrate is shown;

[0113] Fig. 21B yes Fig.21A A schematic diagram of the planar structure of the middle conductive layer and the third conductive portion;

[0114] Fig.22A yes Fig.19 A schematic diagram of another planar structure of the display substrate is shown;

[0115] Fig. 22B yes Fig.22A Schematic diagram of the planar structure of the middle conductive layer and the third conductive part. DETAILED DESCRIPTION

[0116] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0117] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0118] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0119] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.

[0120] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0121] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0122] At present, liquid crystal display panels have been widely used in display fields such as mobile phones, tablets, laptops, car displays, and desktop displays.

[0123] Since a higher refresh rate can make the image changes in the LCD panel smoother and allow users to have a smoother visual experience, the consumer market has a great demand for LCD panels with high refresh rates. However, for LCD panels in modes such as IPS (In-Plane Switching), FFS (Fringe Field Switching) or ADS (Advanced Super Dimension Switching), horizontal crosstalk is prone to occur at high refresh rates, causing display abnormalities. In the field of display technology, crosstalk generally refers to a display abnormality in which the display of a certain area in the LCD panel is affected by another area, causing picture distortion. For example, in one example, the display of the peripheral area is affected by the display of the central area, resulting in obvious uneven brightness in the peripheral area visible to the naked eye. LCD panels whose brightness unevenness exceeds the allowable range are considered defective.

[0124] The cause of crosstalk is usually capacitive coupling. For example, if there is capacitive coupling between the data line or gate and the common electrode, when the voltage signal in the data line or gate changes during the display process of the LCD panel, it will affect the voltage of the common electrode, making the actual voltage applied to the liquid crystal different from the set voltage, thus causing the brightness of the display panel to deviate.

[0125] Further, the specific reason for the capacitive coupling between the data line or the gate and the common electrode is that in the liquid crystal display panel of the mode of IPS, FFS or ADS, the common electrode and the data line or the gate line are all arranged in the display substrate, and the film layer distance is relatively close, so a large capacitive coupling will be generated. Specifically, when the voltage signal in the data line or the gate line changes, the voltage change of the common electrode will be caused by coupling, but the common electrode is electrically connected to the external power supply, so the voltage change of the common electrode will recover within a certain period of time. When the refresh rate is low, the voltage in the common electrode has enough time to recover, so the coupling effect will not cause the change of the driving voltage. But when the refresh rate is high, the voltage of the common electrode is too late to recover, so it will cause the driving voltage to be low, so that the brightness of the surrounding area is low, causing the display of the liquid crystal display panel to be abnormal. The structure of the display panel in the specific embodiment is further understood below.

[0126] A liquid crystal display panel generally includes a display substrate, a color filter substrate, and a liquid crystal layer located between the color filter substrates.

[0127] Figure 1 Schematic diagram of the cross-sectional structure of a display substrate in some embodiments. Figure 2A yes Figure 1 The following is a schematic diagram of a planar structure of a display substrate. Figure 2B to Figure 2G Given Figure 2A Schematic diagram of the planar structure of each membrane layer. Specifically, Figure 2B yes Figure 2A A schematic diagram of the planar structure of the common electrode 40, Figure 2C yes Figure 2A A schematic diagram of the planar structure of the middle gate Gate and the third conductive line 20, Figure 2D yes Figure 2A Schematic diagram of the planar structure of the active layer 14, Figure 2E yes Figure 2A Schematic diagram of the planar structure of the data line data, the first conductive portion 30, and the source-drain electrode layer (source 11, drain 13), Figure 2F yes Figure 2A A schematic diagram of the planar structure of the middle light blocking layer 60, Figure 2G yes Figure 2A Schematic diagram of the planar structure of the pixel electrode 50.

[0128] The display substrate generally includes a plurality of pixel regions, and a spacing region is provided between two adjacent pixel regions. Figure 1As shown, the display substrate includes a base substrate SUB and a light blocking layer 60, a buffer layer BUF, a gate insulating layer GI, an interlayer dielectric layer ILD, a first planarization layer PLN1, a first passivation layer PVX1 and an orientation layer PI, which are located on one side of the base substrate SUB and are stacked in sequence in a direction away from the base substrate SUB. Optionally, the material of the orientation layer PI may include polyimide.

[0129] The display substrate further includes a plurality of gate lines Gate, a plurality of data lines data, a plurality of thin film transistors 10, a plurality of pixel electrodes 50 and a common electrode 40 located on one side of the base substrate SUB. The gate lines Gate, the data lines data, and the thin film transistors 10 are generally located in the spacing area, and the plurality of gate lines Gate and the plurality of data lines data intersect each other. At least a portion of the pixel electrode 50 and at least a portion of the common electrode 40 are both located in the pixel area.

[0130] Among them, the gate line Gate is located between the gate insulating layer GI and the interlayer dielectric layer ILD, and the data line data is located between the interlayer dielectric layer ILD and the first planarization layer PLN1. The thin film transistor 10 includes an active layer 14, a source-drain electrode layer and a gate 12, wherein the active layer 14 is located between the buffer layer BUF and the gate insulating layer GI, the source-drain electrode layer is arranged in the same layer as the data line data, and the gate 12 is arranged in the same layer as the gate line Gate. The source-drain electrode layer includes a source electrode 11 and a drain electrode 13, and the source electrode 11 and the drain electrode 13 are electrically connected to the active layer 14 respectively. The pixel electrode 50 is electrically connected to the drain electrode 13 through a via hole penetrating the first planarization layer PLN1 and the first passivation layer PVX1.

[0131] In addition, the active layer 14 may include a source connection portion, a drain connection portion, and a channel region located between the source connection portion and the drain connection portion, and the channel region is directly opposite to the gate 12 of the thin film transistor 10. Among them, the source 11 is electrically connected to the source connection portion, and the drain 13 is electrically connected to the drain connection portion. Optionally, the active layer 14 also includes a low-doped region LDD located between the source connection portion and the channel region, and a high-doped region located between the low-doped regions LDD. Optionally, the active layer 14 can be a polycrystalline silicon (poly-Si) layer.

[0132] Optionally, the source electrode 11 is connected to the data line data as an integral structure, and the source electrode 11 is electrically connected to the source connection portion through a via hole penetrating the gate insulating layer GI and the interlayer dielectric layer ILD. The gate 12 is connected to the gate line Gate as an integral structure.

[0133] Among them, the gate line Gate is used to provide a driving signal for the thin film transistor 10, the data line data is used to provide a data signal for the thin film transistor 10, the common electrode 40 and the pixel electrode 50 are used to provide a driving voltage for the liquid crystal layer to control the liquid crystal molecules in the liquid crystal layer to change direction, so that the liquid crystal display panel can display.

[0134] In addition, the display substrate further includes a first conductive portion 30 disposed in the same layer as the data line data and electrically insulated, and a third conductive line 20 disposed in the same layer as the gate line Gate and electrically insulated. The first conductive portion 30 and the third conductive line 20 are located in the spacing area.

[0135] The third conductive line 20 extends in the same direction as the gate line Gate. The common electrode 40 is electrically connected to the first conductive part 30 through a via hole penetrating the first planarization layer PLN1, and the first conductive part 30 is electrically connected to the third conductive line 20 through a via hole penetrating the interlayer dielectric layer ILD. Obviously, the third conductive line 20 is electrically connected to the common electrode 40 through the first conductive part 30, thereby reducing the transmission resistance of the voltage signal of the common electrode 40.

[0136] For including Figure 1 and Figure 2A The liquid crystal display panel of the structure shown, at a high refresh rate, due to the large coupling capacitance and the fact that the setting of the third conductive line 20 cannot meet the voltage transmission resistance of the common electrode 40, that is, the transmission resistance is still large, etc., the voltage signal of the common electrode 40 cannot be recovered within the charging time of a row of pixels, that is, the driving time of a row of thin film transistors 10, thereby causing obvious horizontal crosstalk problems.

[0137] In order to at least alleviate or solve one of the above-mentioned technical problems, the present disclosure provides a display substrate and a display panel.

[0138] Figure 3 It is a schematic diagram of the cross-sectional structure of a display substrate in some embodiments of the present disclosure. Figure 4A yes Figure 3 A schematic diagram of a planar structure of a display substrate is shown. Figure 4B yes Figure 4A Schematic diagram of the planar structure of the data line, conductive layer, first conductive part and source-drain electrode layer. Figure 4A The planar structure of other film layers Figure 2A The same as in, specific can be combined Figure 2B to Figure 2G To understand.

[0139] like Figure 3 As shown, the present disclosure provides a display substrate, including: a base substrate SUB, a plurality of gate lines Gate and a plurality of data lines data, a common electrode 40 and at least one conductive layer 90 .

[0140] The gate line Gate is located on one side of the substrate SUB, and the data line Data is located on a side of the gate line Gate away from the substrate SUB. The common electrode 40 is located on a side of the gate line Gate and the data line Data away from the substrate SUB.

[0141] The conductive layer 90 is located between the layer where the gate line Gate is located and the layer where the common electrode 40 is located, or between the layer where the gate line Gate is located and the layer where the common electrode 40 is located, and is electrically connected to the common electrode 40. Figure 3 In the illustrated embodiment, the conductive layer 90 is located between the layer where the gate 12 is located and the layer where the common electrode 40 is located. Specifically, the conductive layer 90 is located between the interlayer dielectric layer ILD and the planarization layer. In addition, the common electrode 40 is electrically connected to the conductive layer 90 through a via hole penetrating the first planarization layer PLN1. Optionally, the material of the conductive layer 90 may include metal.

[0142] Furthermore, the conductive layer 90 is located in the spacing region.

[0143] Specifically, Figure 4A As shown, the conductive layer 90 includes at least one first conductive line 91 extending along the extension direction of the data line data and / or at least one second conductive line 92 extending along the extension direction of the gate line Gate. Figure 4A In the illustrated embodiment, the conductive layer 90 includes a first conductive line 91 .

[0144] The first conductive line 91 is located in the spacing area and overlaps with the orthographic projections of the plurality of gate lines Gate on the substrate SUB. The second conductive line 92 is located in the spacing area.

[0145] The disclosed embodiment can reduce the transmission resistance of the voltage signal in the common electrode 40, accelerate the recovery of the voltage signal of the common electrode 40, and avoid the phenomenon of uneven brightness of the liquid crystal display panel caused by crosstalk due to capacitive coupling by arranging at least one first conductive line 91 and / or at least one second conductive line 92 between the layer where the gate line Gate is located and the layer where the common electrode 40 is located or between the layer where the gate line Gate is located and the layer where the common electrode 40 is located and in the spacing area.

[0146] In some embodiments, Figure 3 As shown, the first conductive line 91 is disposed in the same layer as the data line data and is electrically insulated from the data line data. Specifically, the common electrode 40 is electrically connected to the first conductive line 91 through a via hole penetrating the first planarization layer PLN1.

[0147] In the embodiment of the present disclosure, the first conductive line 91 and the data line data are arranged in the same layer so that the first conductive line 91, the data line data and the gate 12 of the thin film transistor 10 can be formed simultaneously in the same preparation process, thereby simplifying the preparation process, reducing the preparation difficulty and reducing the preparation cost.

[0148] Figure 5 It is a schematic diagram of the cross-sectional structure of a display substrate in other embodiments of the present disclosure. Fig. 6A yes Figure 5A schematic diagram of a planar structure of a display substrate is shown. Figure 6B yes Fig. 6A A schematic diagram of the planar structure of the data line, the first conductive part and the Figure 6C yes Fig. 6A Schematic diagram of the planar structure of the second conductive line 92 and the light blocking layer 60. Fig. 7A yes Figure 5 Another schematic diagram of the planar structure of the display substrate is shown. Figure 7B yes Fig. 7A Schematic diagram of the planar structure of the active layer, Figure 7C yes Fig. 7A Schematic diagram of the planar structure of the conductive layer and the light-blocking layer.

[0149] Fig. 8A yes Figure 5 Another schematic diagram of a planar structure of a display substrate is shown. Figure 8B yes Fig. 8A Schematic diagram of the planar structure of the conductive layer and the light-blocking layer.

[0150] In some embodiments, Figure 5 As shown, the conductive layer 90 is located between the layer where the gate line Gate is located and the base substrate SUB, specifically between the buffer layer BUF and the base substrate SUB, and the common electrode 40 is electrically connected to the conductive layer 90 through a via that penetrates the first planarization layer PLN1, the interlayer dielectric layer ILD, the gate insulation layer GI and the buffer layer BUF.

[0151] The conductive layer 90 may include at least one second conductive line 92, and the second conductive line 92 is located between the layer where the gate line Gate is located and the substrate SUB, specifically between the first conductive line 91 located in the buffer layer BUF and the substrate SUB. In this case, the common electrode 40 is electrically connected to the second conductive line 92 through a via hole penetrating the first planarization layer PLN1, the interlayer dielectric layer ILD, the gate insulating layer GI and the buffer layer BUF.

[0152] Alternatively, the conductive layer 90 may include at least one first conductive line 91, and the first conductive line 91 is located between the layer where the gate line Gate is located and the substrate SUB, specifically between the buffer layer BUF and the substrate SUB. Similarly, the common electrode 40 is electrically connected to the first conductive line 91 through a via hole that penetrates the first planarization layer PLN1, the interlayer dielectric layer ILD, the gate insulating layer GI and the buffer layer BUF.

[0153] Alternatively, the conductive layer 90 may include at least one first conductive line 91 and at least one second conductive line 92. The common electrode 40 is electrically connected to the conductive layer 90 through a via hole penetrating the first planarization layer PLN1, the interlayer dielectric layer ILD, the gate insulating layer GI, and the buffer layer BUF. Specifically, the common electrode 40 is electrically connected to at least one of the first conductive line 91 and the second conductive line 92 through a via hole penetrating the first planarization layer PLN1, the interlayer dielectric layer ILD, the gate insulating layer GI, and the buffer layer BUF.

[0154] The disclosed embodiment can reduce the transmission resistance of the voltage signal in the common electrode 40 and accelerate the recovery of the voltage signal in the common electrode 40 by setting at least one first conductive line 91 and / or at least one second conductive line 92 between the buffer layer BUF and the base substrate SUB, thereby avoiding the phenomenon of uneven brightness of the liquid crystal display panel caused by crosstalk due to capacitive coupling.

[0155] In some embodiments, Figure 5 As shown, the display substrate further includes a light blocking layer 60 located between the buffer layer BUF and the base substrate SUB. Optionally, the orthographic projection of the light blocking layer 60 on the base substrate SUB can cover the orthographic projection of the gate 12 on the base substrate SUB. Optionally, the orthographic projection of the light blocking layer 60 on the base substrate SUB can cover the orthographic projection of the channel region on the base substrate SUB. In this case, the conductive layer 90 is disposed on the same layer as the light blocking layer 60.

[0156] For example, in Fig. 6A In the embodiment shown, the conductive layer 90 includes: at least one second conductive line 92, and the second conductive line 92 is disposed in the same layer as the light blocking layer 60. Fig. 7A In the embodiment shown, the conductive layer 90 includes: at least one first conductive line 91, and the first conductive line 91 is disposed in the same layer as the light blocking layer 60. Fig. 8A In the illustrated embodiment, the conductive layer 90 includes: at least one first conductive line 91 and at least one second conductive line 92 , wherein the first conductive line 91 and the second conductive line 92 are both disposed in the same layer as the light blocking layer 60 .

[0157] In the embodiment of the present disclosure, the conductive layer 90 and the light blocking layer 60 are arranged in the same layer, so that the conductive layer 90 and the light blocking layer 60 can be formed simultaneously in the same preparation process, thereby simplifying the preparation process, reducing the preparation difficulty, and reducing the preparation cost.

[0158] In some embodiments, Figure 5 , Fig. 6A , Figure 6C , Fig. 7A , Figure 7C , Fig. 8A and Figure 8BAs shown, the orthographic projection of the conductive layer 90 on the base substrate SUB does not overlap with the orthographic projection of the light blocking layer 60 on the base substrate SUB.

[0159] Among them, in Fig. 6A , Figure 6C , Fig. 8A and Figure 8B In the illustrated embodiment, the conductive layer 90 is provided with a first opening. Specifically, the conductive layer 90 includes a second conductive line 92. The second conductive line 92 is provided with a first opening. At least a portion of the light blocking layer 60 is located in the first opening.

[0160] In the disclosed embodiment, the orthographic projection of the conductive layer 90 on the base substrate SUB and the orthographic projection of the light blocking layer 60 on the base substrate SUB do not overlap, which can prevent electrical signals from being present in the light blocking layer 60, thereby affecting the function of the light blocking layer 60. Moreover, the orthographic projection of the light blocking layer 60 on the base substrate SUB covers the channel portion, which is directly opposite to the gate 12. Therefore, it can also prevent the electrical signals between the light blocking layer 60 and the gate 12 from affecting each other, thereby affecting the display effect of the display panel.

[0161] In some embodiments, Fig. 6A As shown, the conductive layer 90 only includes at least one second conductive line 92 , and the orthographic projection of the second conductive line 92 on the base substrate SUB does not overlap with the orthographic projection of the light blocking layer 60 on the base substrate SUB.

[0162] In this case, the orthographic projection of the channel portion on the base substrate SUB overlaps with the orthographic projection of the data line data on the base substrate SUB. The orthographic projection of the source connection portion on the base substrate SUB overlaps with the orthographic projection of the data line data on the base substrate SUB.

[0163] In some embodiments, Fig. 7A As shown, the conductive layer 90 includes at least one first conductive line 91, or Fig. 8A As shown, the conductive layer 90 includes at least one first conductive line 91 and at least one second conductive line 92. In order to satisfy that the orthographic projection of the conductive layer 90 on the substrate SUB does not overlap with the orthographic projection of the light blocking layer 60 on the substrate SUB, the orthographic projection of the channel portion on the substrate SUB does not overlap with the orthographic projection of the data line data on the substrate SUB, and the orthographic projection of the source connection portion on the substrate SUB overlaps with the orthographic projection of the data line data on the substrate SUB. In this embodiment, as Fig. 7A and Figure 7B As shown, the shape and laying position of the active layer 14 are similar to Fig. 6A The shape and laying position of the active layer 14 in Figure 2D), etc., it is necessary to avoid the laying position of the first conductive line 91. Further, in the embodiment of the present disclosure, the position of the first conductive line 91 can refer to the position of the data line data, that is, the orthographic projection of the first conductive line 91 on the substrate SUB covers the orthographic projection of the data line data on the substrate SUB, therefore, Fig. 7A and Figure 7B The channel portion of the active layer 14 needs to avoid the position of the data line data.

[0164] Fig. 9 is a schematic diagram showing the cross-sectional structure of a substrate in other embodiments of the present disclosure, Fig. 10A yes Fig. 9 A schematic diagram of a planar structure of a display substrate is shown. Fig. 10B yes Fig. 10A Schematic diagram of the planar structure of the light-blocking layer and the conductive layer.

[0165] In some embodiments, Fig. 9 and Fig. 10A As shown, the conductive layer 90 and the light blocking layer 60 are connected to form an integral structure.

[0166] For example, in Fig. 10A In the illustrated embodiment, the conductive layer 90 includes at least one second conductive line 92 , and the second conductive line 92 is connected to the light blocking layer 60 as an integral structure.

[0167] Of course, combined Fig. 7A It can be understood that in another embodiment, the conductive layer 90 includes at least one first conductive line 91, and the first conductive line 91 is connected to the light blocking layer 60 as an integral structure. Fig. 8A It can be understood that in another embodiment, the conductive layer 90 includes at least one first conductive line 91 and at least one second conductive line 92 , and the first conductive line 91 , the second conductive line 92 and the light blocking layer 60 are connected to form an integrated structure.

[0168] In the embodiment of the present disclosure, the conductive layer 90 and the light blocking layer 60 are connected as an integral structure. Figures 5 to 8A The display substrate in the can simplify the process.

[0169] In some embodiments, Figure 3 , Figure 5 and Fig. 9 As shown, the first conductive part 30 is electrically connected to the common electrode 40. Specifically, the common electrode 40 is electrically connected to the first conductive part 30 through a via hole penetrating the first planarization layer PLN1. The conductive layer 90 is electrically connected to the first conductive part 30. Specifically, Figure 3 In the embodiment shown, the conductive layer 90 is disposed on the same layer as the first conductive portion 30 and is electrically connected to the first conductive portion 30. Figure 5 and Fig. 9In the illustrated embodiment, the first conductive portion 30 is electrically connected to the conductive layer 90 through a via hole penetrating the interlayer dielectric layer ILD, the gate insulating layer GI and the buffer layer BUF.

[0170] Among them, Figure 3 In the embodiment shown, the first conductive part 30 and the conductive layer 90 are arranged in the same layer and can be connected as an integral structure. Therefore, the first conductive part 30 only needs to be electrically connected to the third conductive line 20 through a via hole, and no longer needs to be electrically connected to other film layers through other via holes. Figure 5 He Ru Fig. 9 In the embodiment shown, the conductive layer 90 and the first conductive part 30 are not in the same layer. In addition to being electrically connected to the third conductive line 20 through the via hole, the first conductive part 30 also needs to be electrically connected to the conductive layer 90 through another via hole. Figure 6B and Figure 4B , Figure 6B yes Figure 5 and Fig. 9 Schematic diagram of the first conductive part 30, Figure 4B yes Figure 3 The schematic diagram of the first conductive part 30 in FIG. Figure 5 He Ru Fig. 9 In the embodiment shown in the figure, the width of the first conductive portion 30 in the extending direction of the gate line Gate is greater than that in the extending direction of the gate line Gate. Figure 3 In the illustrated embodiment, the width of the first conductive portion 30 in the extending direction of the gate line Gate is large.

[0171] Fig.11 It is a schematic diagram of the cross-sectional structure of a display substrate in other embodiments of the present disclosure. Fig. 12A yes Fig.11 A schematic diagram of a planar structure of a display substrate is shown. Fig. 12B yes Fig. 12A Schematic diagram of the planar structure of the pixel electrode and the second conductive part. Fig. 12C yes Fig. 12A Schematic diagram of the planar structure of the conductive layer. Fig.13A yes Fig.11 Another schematic diagram of the planar structure of the display substrate is shown. Fig. 13B yes Fig.13A Schematic diagram of the planar structure of the conductive layer. Fig.14A yes Fig.11 A schematic diagram of another planar structure of a display substrate is shown. Fig. 14B yes Fig.14A Schematic diagram of the planar structure of the conductive layer.

[0172] In some embodiments, Fig.11As shown, the display substrate further includes: a second passivation layer PVX2 and at least one second conductive portion 70. The second passivation layer PVX2 is located between the first planarization layer PLN1 and the common electrode 40, and the second conductive portion 70 is disposed in the same layer as the pixel electrode 50 and is electrically insulated. Furthermore, the second conductive portion 70 is located in the spacing area.

[0173] The pixel electrode 50 is electrically connected to the thin film transistor 10 through a first via hole penetrating the first passivation layer PVX1, the second passivation layer PVX2 and the first planarization layer PLN1. Specifically, the pixel electrode 50 is electrically connected to the drain 13 through a first via hole penetrating the first passivation layer PVX1, the second passivation layer PVX2 and the first planarization layer PLN1. The conductive layer 90 is located between the first planarization layer PLN1 and the second passivation layer PVX2, and the orthographic projection of the conductive layer 90 on the base substrate SUB does not overlap with the orthographic projection of the first via hole on the base substrate SUB.

[0174] For example, in Fig. 12A In the embodiment shown, the conductive layer 90 includes at least one second conductive line 92. Fig. 12C As shown, the second conductive line 92 has a second opening, combined with Fig.11 , Fig. 12A and Fig. 12C It can be known that the orthographic projection of the first opening on the base substrate SUB is located within the orthographic projection range of the second opening on the base substrate SUB.

[0175] In such Fig.13A and Fig. 13B In the illustrated embodiment, the conductive layer 90 includes at least one first conductive line 91. The orthographic projection of the first conductive line 91 on the substrate SUB does not overlap with the orthographic projection of the first opening on the substrate SUB.

[0176] In the embodiment shown in FIG. 14 , the conductive layer 90 includes at least one first conductive line 91 and at least one second conductive line 92. Fig. 14B As shown in the figure, the second conductive line 92 has a second opening. Fig.11 , Fig.14A and Fig. 14B It can be known that the orthographic projection of the first opening on the base substrate SUB is located within the orthographic projection range of the second opening on the base substrate SUB.

[0177] The second conductive portion 70 is electrically connected to the common electrode 40 through a via hole penetrating the first passivation layer PVX1 , and is electrically connected to the conductive layer 90 through a via hole penetrating the first passivation layer PVX1 and the second passivation layer PVX2 .

[0178] The embodiment of the present disclosure can reduce the transmission resistance of the voltage signal in the common electrode 40 and accelerate the recovery of the voltage signal of the common electrode 40 by setting at least one first conductive line 91 and / or at least one second conductive line 92 between the first planarization layer PLN1 and the second passivation layer PVX2, thereby avoiding the phenomenon of uneven brightness of the liquid crystal display panel caused by crosstalk due to capacitive coupling.

[0179] Specifically, in Fig. 12A In the illustrated embodiment, the conductive layer 90 includes at least one second conductive line 92. Fig.13A In the illustrated embodiment, the conductive layer 90 includes at least one first conductive line 91. Fig.14A In the illustrated embodiment, the conductive layer 90 includes at least one first conductive line 91 and at least one second conductive line 92 .

[0180] At the same time, the embodiment of the present disclosure can achieve electrical connection between the conductive layer 90 and the common electrode 40 by setting the second conductive part 70 to be electrically connected to the common electrode 40 through a via hole penetrating the first passivation layer PVX1, and to be electrically connected to the conductive layer 90 through a via hole penetrating the first passivation layer PVX1 and the second passivation layer PVX2.

[0181] In other embodiments, the display substrate further includes a touch electrode layer between the first planarization layer PLN1 and the second passivation layer PVX2, and the conductive layer 90 is disposed in the same layer as the touch electrode layer and is electrically insulated. The touch electrode layer is used to realize the touch function of the display substrate of the embodiment of the present disclosure.

[0182] In the embodiment of the present disclosure, the conductive layer 90 and the touch electrode layer are disposed in the same layer so that the conductive layer 90 and the touch electrode layer can be formed in the same preparation process, which can simplify the preparation process, reduce the preparation difficulty, and save costs.

[0183] Fig.15 It is a schematic diagram of the cross-sectional structure of a display substrate in other embodiments of the present disclosure. Fig.16A yes Fig.15 A schematic diagram of a planar structure of a display substrate is shown. Fig. 16B yes Fig.16A Schematic diagram of the planar structure of the middle grid line. Fig. 16C yes Fig.16A Schematic diagram of the planar structure of the data line and source-drain electrode layer. Fig.16D yes Fig.16A Schematic diagram of the planar structure of the pixel electrode. Fig.16E yes Fig.16A Schematic diagram of the planar structure of the middle conductive layer and the third conductive part. Fig.17A yes Fig.15 Another schematic diagram of the planar structure of the display substrate is shown. Fig. 17B yes Fig.17ASchematic diagram of the planar structure of the middle conductive layer and the third conductive part. Fig.18A yes Fig.15 A schematic diagram of another planar structure of a display substrate is shown. Fig. 17B yes Fig.18A Schematic diagram of the planar structure of the middle conductive layer and the third conductive part.

[0184] In some embodiments, Fig.15 As shown, the display substrate further includes a second planarization layer PLN2 and a third conductive portion 80, wherein the second planarization layer PLN2 is located between the first planarization layer PLN1 and the common electrode 40. The third conductive portion 80 is located between the first planarization layer PLN1 and the second planarization layer PLN2. The conductive layer 90 is located between the first planarization layer PLN1 and the second planarization layer PLN2. Furthermore, the third conductive portion 80 is located in the spacing area.

[0185] And, if FIG. 16A to FIG. 18A As shown, the orthographic projection of the conductive layer 90 on the base substrate SUB does not overlap with the orthographic projection of the third conductive portion 80 on the base substrate SUB, that is, the third conductive portion 80 is electrically insulated from the conductive layer 90 .

[0186] For example, in Fig.16A In the illustrated embodiment, the conductive layer 90 includes at least one second conductive line 92, and the orthographic projection of the second conductive line 92 on the substrate SUB does not overlap with the orthographic projection of the third conductive portion 80 on the substrate SUB. Fig.16E As shown, the second conductive line 92 is provided with a second opening, and at least a portion of the third conductive portion 80 is located in the second opening.

[0187] In such Fig.17AIn the illustrated embodiment, the conductive layer 90 includes at least one first conductive line 91, and the orthographic projection of the first conductive line 91 on the substrate SUB does not overlap with the orthographic projection of the third conductive portion 80 on the substrate SUB. Specifically, the orthographic projection of the first conductive line 91 on the substrate SUB covers the orthographic projection of the data line data on the substrate SUB. Further, the orthographic projection of the first conductive line 91 on the substrate SUB can exceed the orthographic projection of the data line data on the substrate SUB on both sides in the extension direction of the gate line Gate. In addition, in order to ensure the size of the pixel opening, when the width of the gate line Gate in the extension direction of the first conductive line 91 is the widest, the width of the part of the orthographic projection of the first conductive line 91 on the substrate SUB on both sides in the extension direction of the gate line Gate that exceeds the orthographic projection of the data line data on the substrate SUB can not exceed 1 μm. Of course, in the case where the transmission resistance requirement of the voltage signal of the common electrode 40 can be met, the orthographic projection of the first conductive line 91 on the substrate SUB can be located within the orthographic projection range of the data line data on the substrate SUB.

[0188] In such Fig.18A In the illustrated embodiment, the conductive layer 90 includes at least one first conductive line 91 and at least one second conductive line 92, and the orthographic projection of the first conductive line 91 on the substrate SUB does not overlap with the orthographic projection of the third conductive portion 80 on the substrate SUB, and the orthographic projection of the second conductive line 92 on the substrate SUB does not overlap with the orthographic projection of the third conductive portion 80 on the substrate SUB. Specifically, as Fig.18B As shown, the second conductive line 92 is provided with a second opening, and at least a portion of the third conductive portion 80 is located in the second opening.

[0189] like Fig.15 As shown, the pixel electrode 50 is electrically connected to the third conductive part 80 through a via hole penetrating the first passivation layer PVX1 and the second planarization layer PLN2, the third conductive part 80 is electrically connected to the drain 13 through a via hole penetrating the first planarization layer PLN1, and the common electrode 40 is electrically connected to the conductive layer 90 through a via hole penetrating the second planarization layer PLN2.

[0190] The embodiment of the present disclosure can reduce the transmission resistance of the voltage signal of the common electrode 40 through the conductive layer 90, thereby improving the voltage recovery speed of the common electrode 40. At the same time, the embodiment of the present disclosure can also increase the thickness between the common electrode 40 and the data line data by adopting a double planarization layer structure, thereby further reducing the size of the coupling capacitance and reducing the crosstalk between the common electrode 40 and the data line data.

[0191] In addition, in the embodiment of the present disclosure, the electrical connection between the pixel electrode 50 and the drain electrode 13 is no longer as Figure 1 In the embodiment, the electrical connection is not directly achieved through the via hole penetrating the film layer between the pixel electrode 50 and the drain electrode 13, but the switching is achieved through the third conductive part 80. Fig.15 , Fig.16A , Fig.17A and Fig.18A In the embodiment of FIG. 1 , the shape of the pixel electrode 50 electrically connected to the drain electrode 14 is changed. Figure 1 , Figure 2G , Fig.15 , Fig.16D It can be seen that the pixel electrode 50 has an extended connection portion, wherein Figure 1 and Figure 2G In the embodiment shown, the extended connection portion is electrically connected to the drain electrode 14, and the orthographic projection of the extended connection portion on the base substrate SUB overlaps with the orthographic projection of the drain electrode 12 on the base substrate SUB. Fig.15 , Fig.16D In the embodiment shown, the orthographic projection of the extended connection part on the substrate SUB overlaps with the orthographic projection of the third connection part 80 on the substrate SUB, but does not overlap with the orthographic projection of the drain 14 on the substrate SUB. This is to achieve that the extended connection part can be electrically connected to the third connection part 80 through a via hole penetrating the first passivation layer PVX1 and the second planarization layer PLN2PLN, and the third connection part 80 is electrically connected to the drain 14 through a via hole penetrating the first planarization layer PLN1.

[0192] In some embodiments, the third conductive portion 80 is disposed on the same layer as the conductive layer 90 .

[0193] In the embodiment of the present disclosure, the third conductive part 80 and the conductive layer 90 are arranged in the same layer, which can simplify the process and reduce the difficulty of preparation.

[0194] In some other embodiments, the display substrate further includes a touch electrode layer located between the first planarization layer PLN1 and the second planarization layer PLN2 , and the conductive layer 90 is disposed on the same layer as the touch electrode layer and is electrically insulated.

[0195] In the embodiment of the present disclosure, the conductive layer 90 and the touch electrode layer are disposed in the same layer so that the conductive layer 90 and the touch electrode layer can be formed in the same preparation process, which can simplify the preparation process, reduce the preparation difficulty, and save costs.

[0196] Fig.19 It is a schematic diagram of the cross-sectional structure of a display substrate in other embodiments of the present disclosure. Fig. 20A yes Fig.19 A schematic diagram of a planar structure of a display substrate is shown. Fig. 20B yes Fig. 20A Schematic diagram of the planar structure of the middle conductive layer and the third conductive part. Fig.21A yes Fig.19 Another schematic diagram of the planar structure of the display substrate is shown. Fig. 21B yes Fig.21A Schematic diagram of the planar structure of the middle conductive layer and the third conductive part. Fig.22A yes Fig.19 A schematic diagram of another planar structure of a display substrate is shown. Fig. 22B yes Fig.22A Schematic diagram of the planar structure of the middle conductive layer and the third conductive part.

[0197] In some embodiments, Fig.19 As shown, the conductive layer 90 is electrically connected to the first conductive portion 30 through a via hole penetrating the first planarization layer PLN1 , and the first conductive portion 30 is electrically connected to the third conductive line 20 through a via hole penetrating the interlayer dielectric layer ILD.

[0198] like FIG. 20A to FIG. 22A The display substrate shown is compared to Figures 15 to 18A The display substrate shown in the figure has a first conductive portion 30 and a third conductive line 20 added thereto. Therefore, the embodiment of the present disclosure can further reduce the transmission resistance of the voltage signal of the common electrode 40, thereby improving the recovery speed of the voltage signal of the common electrode 40. Figures 15 to 18A The display substrate shown in FIG. 1 does not need to be provided with the first conductive portion 30 and the third conductive line 20 in the spacing area. FIG. 20A to FIG. 22A The display substrate shown can increase the pixel area, that is, increase the pixel aperture ratio. Figures 3 to 14A In the embodiment shown, the first conductive part 30 and the third conductive line 20 may not be provided, and the embodiments of the present disclosure will not be described in detail.

[0199] Therefore, the embodiments of the present disclosure support that in a specific display substrate, the pixel aperture ratio and the design of the common electrode 40 voltage signal transmission resistance can be comprehensively considered for selection. For example, the embodiments of the present disclosure can be provided with a multi-layer conductive layer 90, and the first conductive part 30 and the third conductive line 20 are not provided, which can reduce the transmission resistance of the common electrode 40 voltage signal while ensuring the pixel aperture ratio. Therefore, the display substrate in the embodiments of the present disclosure can meet the different needs of various products.

[0200] In some embodiments, Fig.19 , Fig. 20A as well as Fig. 20B , or Fig.19 , Fig.22A and Fig. 22BAs shown in FIG. 1 , due to the arrangement of the third conductive line 20, the width of the spacing area in the extending direction of the data line data is relatively large, so the width of the second conductive line 92 in the extending direction of the data line data can also be set larger. Accordingly, the second opening can be opened in the middle area of ​​the second conductive line 92, and the third conductive portion 80 is located in the second opening. Fig.15 , Fig.16A and Fig.16E As shown, or as Fig.15 , Fig.18A and Fig.18B As shown, since the third conductive line 20 is not set, the width of the spacing area in the extension direction of the data line data is relatively small. At this time, in order to prevent the conductive layer 90 from affecting the size of the spacing area or the pixel area, the width of the second conductive line 92 in the extension direction of the data line data needs to be set smaller. Accordingly, the second opening can be opened in the edge area of ​​the second conductive line 92, and at least part of the third conductive portion 80 is located in the second opening.

[0201] In some embodiments, Fig. 8A and Figure 8B , Fig.14A and Fig. 14B , Fig.18A and Fig.18B , Fig.22A and Fig. 22B As shown, the conductive layer 90 includes at least one first conductive line 91 and at least one second conductive line 92 , and the first conductive line 91 and the second conductive line 92 are connected to form an integral structure.

[0202] In the disclosed embodiment, the first conductive line 91 and the second conductive line 92 are connected as an integrated structure to form a "mesh" structure, which can not only reduce the transmission resistance of the voltage signal of the common electrode 40, but also further simplify the process and reduce the difficulty of preparation.

[0203] In some embodiments, Figure 7C , Fig. 13B and Fig. 21B As shown, the first conductive line 91 includes a main body 912 extending along the extension direction of the data line data and at least one protruding portion 911 electrically connected to the main body 912, the orthographic projection of the main body 912 on the substrate SUB overlaps with the orthographic projection of the data line data on the substrate, and the common electrode 40 is electrically connected to the protruding portion 911.

[0204] For example, in Figure 7C In the embodiment shown, Figure 5 As shown, the common electrode 40 is electrically connected to the extension portion 911 through a via hole penetrating the first planarization layer PLN1 , the interlayer dielectric layer ILD, the gate insulating layer GI and the buffer layer BUF.

[0205] In such Fig. 13B In the embodiment shown, Fig.11 As shown, the second conductive portion 70 is electrically connected to the common electrode 40 through a via hole penetrating the first passivation layer PVX1 , and is electrically connected to the extension portion 911 through a via hole penetrating the first passivation layer PVX1 and the second passivation layer PVX2 .

[0206] In such Fig. 21B In the embodiment shown, Fig.19 As shown, the common electrode 40 is electrically connected to the protruding portion 911 through a via hole penetrating the second planarization layer PLN2.

[0207] In the embodiment of the present disclosure, on the basis of only the first conductive layer 90, the embodiment of the present disclosure realizes electrical connection with the common electrode 40 by providing the extension portion 911. In this case, the width of the main body portion 912 in the extension direction of the gate line Gate can be adjusted according to actual needs, which can meet the needs of different display panels. At the same time, the width of the main body portion 912 in the extension direction of the gate line Gate can be further controlled within an appropriate width range, thereby avoiding affecting the size of the pixel opening.

[0208] Specifically, in order to ensure that the first conductive line 91 can reduce the transmission resistance of the common voltage signal, the embodiment of the present disclosure can widen the width of the main body 912 in the extension direction of the gate line Gate, for example, the orthographic projection of the main body 912 on the base substrate SUB covers the orthographic projection of the data line data on the base substrate SUB. Further, the orthographic projection of the main body 912 on the base substrate SUB can exceed the orthographic projection of the data line data on the base substrate SUB on both sides in the extension direction of the gate line Gate.

[0209] In addition, in Figure 7C , Fig. 13B and Fig. 21B In the illustrated embodiment, in order to ensure the size of the pixel opening, when the main body 912 of the first conductive layer 90 is the widest, the widths of the parts of the main body 912 on both sides of the projection of the main body 912 on the substrate SUB in the extension direction of the gate line Gate that exceed the projection of the data line data on the substrate SUB may not exceed 1 μm.

[0210] Of course, under the condition that the transmission resistance requirement of the voltage signal of the common electrode 40 can be met, the orthographic projection of the main body 912 on the base substrate SUB can be located within the orthographic projection range of the data line data on the base substrate SUB.

[0211] In summary, the embodiment of the present disclosure can set at least one conductive layer 90 at different film layer positions to reduce the transmission resistance of the voltage signal of the common electrode 40, thereby reducing the recovery speed of the voltage of the common electrode 40. Furthermore, the specific shape of each conductive layer 90 can be laid by setting the first conductive line 91 and / or the second conductive line 92, thereby further reducing the transmission resistance of the voltage signal of the common electrode 40. The number of layers and specific patterns of the conductive layer 90 of the embodiment of the present disclosure can be set as needed, which can meet the requirements of the transmission resistance of the voltage signal of the common electrode 40 in different products.

[0212] The present disclosure also provides a display panel, comprising a display substrate as described in any embodiment of the present disclosure.

[0213] In some embodiments, the display panel further includes a light shielding layer located on one side of the display substrate, and the light shielding layer may be, for example, a black matrix layer (BM). The black matrix layer includes a plurality of black matrix strips arranged along the extension direction of the data lines data. The extension direction of the black matrix strips is the same as the extension direction of the gate lines Gate.

[0214] In the embodiment where the conductive layer 90 includes the second conductive line 92, the orthographic projection of the second conductive line 92 on the substrate SUB can cover the orthographic projection of the black matrix strip on the substrate SUB. When the width of the second conductive line 92 in the extension direction of the data line data is the largest, the orthographic projection of the second conductive line 92 on the substrate SUB can exceed the orthographic projection of the black matrix strip on the substrate SUB on both opposite sides in the extension direction of the data line data, and in order to ensure the pixel aperture ratio, the exceeding distance on both sides does not exceed 2μm. Of course, in the case of satisfying the transmission resistance required for the voltage signal of the common electrode 40, the orthographic projection of the second conductive line 92 on the substrate SUB can also be within the range of the orthographic projection of the black matrix strip on the substrate SUB.

[0215] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a plurality of pixel regions, wherein a spacer region is provided between two adjacent pixel regions, wherein: The display substrate comprises: substrate substrate; A plurality of gate lines and a plurality of data lines are located on one side of the base substrate and in the spacing area, and the gate lines and the data lines cross each other; A common electrode is located at a side of the gate line and the data line away from the base substrate, and at least a part of the common electrode is located in the pixel area; At least one conductive layer, the conductive layer is located between the substrate and the layer where the gate line is located, or between the layer where the gate line is located and the layer where the common electrode is located, and is electrically connected to the common electrode, the conductive layer is located in the spacer area, and the conductive layer includes: At least one first conductive line extending along the extending direction of the data line, the first conductive line and the orthographic projections of the plurality of gate lines on the base substrate overlap; and / or, at least one second conductive line extending along the gate line extension direction.

2. The display substrate according to claim 1, characterized in that: The data line is located at a side of the gate line away from the substrate; The display substrate further includes a first planarization layer located between the common electrode and the data line; The conductive layer comprises at least one first conductive line, the first conductive line is arranged in the same layer as the data line and is electrically insulated from the data line; The common electrode is electrically connected to the first conductive line through a via hole penetrating the first planarization layer.

3. The display substrate according to claim 1, characterized in that: The data line is located at a side of the gate line away from the substrate; The display substrate further comprises: A first planarization layer, located between the common electrode and the data line; An interlayer dielectric layer, located between the data line and the gate line; A buffer layer and a gate insulating layer are located between the gate line and the substrate, and the gate insulating layer is located on a side of the buffer layer away from the substrate; The conductive layer is located between the buffer layer and the base substrate, and the common electrode is electrically connected to the conductive layer through a via hole penetrating the first planarization layer, the interlayer dielectric layer, the gate insulating layer and the buffer layer.

4. The display substrate according to claim 3, characterized in that: The display substrate further comprises: A plurality of thin film transistors, each thin film transistor comprising a gate, wherein the gate and the gate line are arranged in the same layer; a light-blocking layer, located between the buffer layer and the base substrate, wherein the orthographic projection of the light-blocking layer on the base substrate covers the orthographic projection of the gate on the base substrate; The conductive layer is arranged on the same layer as the light blocking layer.

5. The display substrate according to claim 4, characterized in that: The conductive layer comprises at least one second conductive line, and an orthographic projection of the second conductive line on the base substrate does not overlap with an orthographic projection of the light blocking layer on the base substrate; The thin film transistor further comprises: an active layer, located between the buffer layer and the gate insulating layer, wherein the active layer comprises a source connecting portion, a drain connecting portion and a channel portion located between the source connecting portion and the drain connecting portion, and an orthographic projection of the channel portion on the base substrate overlaps with an orthographic projection of the data line on the base substrate; A source-drain electrode layer, wherein the source-drain electrode layer and the data line are arranged in the same layer, the source-drain electrode layer includes a source and a drain, the source and the data line are connected as an integral structure, and the source is electrically connected to the source connecting portion through a via hole penetrating the gate insulating layer and the interlayer dielectric layer, and the orthographic projection of the source connecting portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

6. The display substrate according to claim 4, characterized in that: The orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the light blocking layer on the base substrate, and the conductive layer includes at least one first conductive line, or the conductive layer includes at least one first conductive line and at least one second conductive line; The thin film transistor further comprises: an active layer, located between the buffer layer and the gate insulating layer, the active layer comprising a source connecting portion, a drain connecting portion and a channel portion located between the source connecting portion and the drain connecting portion, wherein an orthographic projection of the channel portion on the base substrate does not overlap with an orthographic projection of the data line on the base substrate; A source-drain electrode layer, wherein the source-drain electrode layer and the data line are arranged in the same layer, the source-drain electrode layer includes a source and a drain, the source and the data line are connected as an integral structure, and the source is electrically connected to the source connecting portion through a via hole penetrating the gate insulating layer and the interlayer dielectric layer, and the orthographic projection of the source connecting portion on the substrate overlaps with the orthographic projection of the data line on the substrate.

7. The display substrate according to any one of claims 2 to 6, characterized in that: The display substrate further comprises: An interlayer dielectric layer, located between the gate line and the data line; A first planarization layer, located between the data line and the common electrode; at least one third conductive line extending along the extending direction of the gate line, the third conductive line being arranged in the same layer as the gate line and being electrically insulated from the gate line, and the third conductive line being located in the spacing area; At least one first conductive part, the first conductive part is arranged in the same layer as the data line and is electrically insulated from the data line, and the first conductive part is located in the spacing area, the conductive layer is electrically connected to the first conductive part, the first conductive part is electrically connected to the third conductive line through a via hole penetrating the interlayer dielectric layer, and the common electrode is electrically connected to the first conductive part through a via hole penetrating the first planarization layer.

8. The display substrate according to claim 1, characterized in that: The data line is located at a side of the gate line away from the substrate; The display substrate further comprises: A first planarization layer and a second passivation layer are located between the data line and the common electrode, and the second passivation layer is located on a side of the first planarization layer away from the base substrate; A first passivation layer is located on a side of the common electrode away from the substrate; A pixel electrode, located on a side of the first passivation layer away from the base substrate; at least one second conductive portion, the second conductive portion is disposed in the same layer as the pixel electrode and is electrically insulated, and the second conductive portion is located in the spacing area; A plurality of thin film transistors are located between the base substrate and the first planarization layer, and the pixel electrode is electrically connected to the thin film transistor through a first via hole penetrating the first passivation layer, the second passivation layer and the first planarization layer; The conductive layer is located between the first planarization layer and the second passivation layer, and an orthographic projection of the conductive layer on the base substrate does not overlap with an orthographic projection of the first via hole on the base substrate; The second conductive portion is electrically connected to the common electrode through a via hole penetrating the first passivation layer, and is electrically connected to the conductive layer through a via hole penetrating the first passivation layer and the second passivation layer.

9. The display substrate according to claim 8, characterized in that: The display substrate further includes a touch electrode layer located between the first planarization layer and the second passivation layer, and the conductive layer is disposed in the same layer as the touch electrode layer and is electrically insulated.

10. The display substrate according to claim 1, characterized in that: The data line is located at a side of the gate line away from the substrate; The display substrate further comprises: A first planarization layer and a second planarization layer are located between the data line and the common electrode, and the second planarization layer is located on a side of the first planarization layer away from the base substrate; A plurality of third conductive portions, located between the first planarization layer and the second planarization layer and located in the spacing area; A first passivation layer is located on a side of the common electrode away from the substrate; A pixel electrode, located on a side of the first passivation layer away from the base substrate; A plurality of thin film transistors, wherein the thin film transistors include an active layer, a gate and a source-drain electrode layer, wherein the active layer is located between the substrate and the gate line, the gate and the gate line are arranged in the same layer, the source-drain electrode layer and the data line are arranged in the same layer, and the source-drain electrode layer includes a source electrode and a drain electrode; Wherein, the conductive layer is located between the first planarization layer and the second planarization layer, and the orthographic projection of the conductive layer on the base substrate does not overlap with the orthographic projection of the third conductive portion on the base substrate; The pixel electrode is electrically connected to the third conductive portion through a via hole penetrating the first passivation layer and the second planarization layer, the third conductive portion is electrically connected to the drain through a via hole penetrating the first planarization layer, and the common electrode is electrically connected to the conductive layer through a via hole penetrating the second planarization layer.

11. The display substrate according to claim 10, characterized in that: The third conductive part is arranged on the same layer as the conductive layer; And / or, the display substrate further includes a touch electrode layer located between the first planarization layer and the second planarization layer, and the conductive layer is disposed in the same layer as the touch electrode layer and is electrically insulated from the touch electrode layer.

12. The display substrate according to any one of claims 8 to 11, characterized in that: The display substrate further comprises: An interlayer dielectric layer, located between the gate line and the data line; At least one third conductive line extending along the extending direction of the gate line, wherein the third conductive line is disposed in the same layer as the gate line and is electrically insulated from the gate line; At least one first conductive portion, the first conductive portion is disposed in the same layer as the data line and is electrically insulated; The conductive layer is electrically connected to the first conductive part through a via hole penetrating the first planarization layer, and the first conductive part is electrically connected to the third conductive line through a via hole penetrating the interlayer dielectric layer.

13. The display substrate according to any one of claims 2 to 6 and 8 to 11, characterized in that: The conductive layer includes at least one first conductive line and at least one second conductive line, and the first conductive line and the second conductive line are connected to form an integral structure.

14. The display substrate according to any one of claims 2 to 6 and 8 to 11, characterized in that: The conductive layer includes at least one first conductive line, the first conductive line includes a main body extending along the extension direction of the data line and at least one protruding part electrically connected to the main body, the orthographic projection of the main body on the substrate overlaps with the orthographic projection of the data line on the substrate, and the common electrode is electrically connected to the protruding part.

15. A display panel, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 14.

Images