Time-to-digital converter and its calibration method

Abstract

An embodiment of the present application provides a time-to-digital converter and its calibration method. The time-to-digital converter includes: a measurement delay module including a first delay chain and a register array, a storage module for storing the correspondence between temperature and candidate compensation coefficients, and a correction module. The correction module is configured to compensate the first count value of the register array according to the compensation coefficient when an echo signal is injected into the first delay chain, so as to obtain a compensated count value. By using the pre-stored information on the relationship between temperature and compensation coefficient, the time-to-digital converter can determine the compensation coefficient corresponding to the current operating temperature of the time-to-digital converter, and thereby achieve real-time compensation of the count value, significantly improving the measurement accuracy and reliability of the time-to-digital converter.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and particularly to a time-to-digital converter and its calibration method. Background Art

[0002] In lidar, a time-to-digital converter that converts the time of flight (TOF) of a laser from emission to reception into a digital count value is a key module for achieving accurate ranging, and its measurement accuracy is closely related to the distance resolution of the lidar.

[0003] The time-to-digital converter is mainly implemented through a delay chain structure. The echo signal obtained based on the photoelectric conversion of the reflected light signal will sequentially pass through multiple cascaded delay units in the delay chain. The time of flight corresponding to the echo signal (which refers to the entire time of flight of the laser signal, not the time from the target object to the lidar after reflection, that is, from the emission signal moment to the echo signal reception moment) is often not an integer number of clock cycles. After counting the integer number of clock cycles, it is also necessary to calculate the position of the pulse front edge of the echo signal in the last clock cycle, which can be obtained by using a time-to-digital converter. Each delay unit of the time-to-digital converter will generate a certain time delay. The delay chain structure can further compare the delayed signal with a threshold and output a response value (0 or 1, 0 indicates that the echo signal is lower than the threshold, and 1 indicates that the echo signal is higher than the threshold). Since the moment when the response value changes from 1 to 0 means that the delayed echo signal is phase-aligned with the clock signal, by counting the number of response values before the response value changes from 1 to 0, the exact moment where the pulse front edge of the echo signal is located can be determined, and thus the time of flight corresponding to the echo signal can be obtained. Summary of the Invention

[0004] Ideally, the delay time of the delay chain structure is accurately determined by the high-frequency clock cycle. However, in practical applications, the delay time of each delay unit will be affected by factors such as temperature, power supply fluctuations, and process deviations, resulting in errors in the count value corresponding to the time interval of the echo signal.

[0005] The time-to-digital converter and its calibration method provided by the embodiments of this application aim to reduce the defect that the delay time of the time-to-digital converter in related technologies is affected, resulting in errors in digital count values.

[0006] In a first aspect, embodiments of the present application provide the following technical solution: A time-to-digital converter. The time-to-digital converter includes: a measurement delay module, including a first delay chain and a register array. The first delay chain includes a first preset number of cascaded first delay units, and the first delay unit is used to access a first preset voltage. The register array includes a plurality of registers, and each register corresponds to one of the first delay units. A first input terminal of the register is connected to the corresponding first delay unit, and a second input terminal of the register is used to access a clock signal; a storage module, configured to store a plurality of candidate compensation coefficients corresponding to different temperatures, or configured to store an association relationship between temperature and candidate compensation coefficients; and a correction module, configured to, when an echo signal is injected into the first delay chain, compensate a first count value of the register array according to a compensation coefficient to obtain a compensated count value, where the compensation coefficient is obtained based on the current temperature of the time-to-digital converter and the plurality of candidate compensation coefficients, or the compensation coefficient is obtained based on the current temperature and the association relationship.

[0007] In a second aspect, embodiments of the present application provide the following technical solution: A calibration method for a time-to-digital converter. The calibration method includes: when an echo signal is injected into a first delay chain, obtaining a first count value of a register array; the first delay chain includes a first preset number of cascaded first delay units, and the register array includes a plurality of registers, and each register corresponds to one of the first delay units; determining a target compensation coefficient according to the current temperature and pre-stored reference data; and compensating the first count value according to the target compensation coefficient to obtain a compensated count value.

[0008] The advantages of the time-to-digital converter and its calibration method provided by embodiments of the present application are: Through the pre-stored relevant information of temperature and compensation coefficients, during the actual measurement process, according to the current working temperature of the time-to-digital converter, a suitable compensation coefficient can be quickly obtained to achieve real-time compensation of the count value, significantly improving the measurement accuracy and reliability of the time-to-digital converter. Description of the Drawings

[0009] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the figures do not constitute a proportional limitation.

[0010] Figure 1 Schematic diagram of a typical time-to-digital converter;

[0011] Figure 2 Schematic diagram of the time-to-digital converter provided by embodiments of the present application;

[0012] Figure 3 Schematic diagram of a time-to-digital converter provided in another embodiment of the present application;

[0013] Figure 4 Method flowchart of the calibration method according to an embodiment of the present application;

[0014] Figure 5 Method flowchart of the calibration method according to another embodiment of the present application;

[0015] Figure 6 Circuit schematic diagram of the time-to-digital converter according to an embodiment of the present application. Detailed implementation manners

[0016] For ease of understanding the present application, the present application will be described in more detail below with reference to the accompanying drawings and specific embodiments.

[0017] It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time, or it may also refer to two elements being interconnected through signals. When an element is considered to be "coupled" / "coupled to" another element, it can be directly coupled to the other element or there may be an intermediate element at the same time, or it may also refer to two elements being interactive through signals.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific implementation manners and are not intended to limit the present application.

[0019] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0020] Figure 1 It is a schematic diagram of a typical time-to-digital converter. As Figure 1 shown, the time-to-digital converter mainly consists of a delay-locked module 10 for generating a reference voltage and a time measurement module 20 for measuring a count value.

[0021] Among them, the delay-locked module 10 includes: a delay chain 11, a phase detector 12, a charge pump 13, and a low-pass filter 14.

[0022] Among them, the delay chain 11 is composed of a plurality of cascaded delay units D11 to D1n. The first delay unit D11 in the delay chain 11 is used to access a clock signal, and this clock signal is output from the output terminal of the last delay unit D1n after passing through the plurality of delay units of the delay chain 11 in sequence.

[0023] The phase detector 12 is a functional circuit for detecting the phase difference between an input signal and a reference signal and outputting a corresponding error signal. One input port of the phase detector 12 is connected to the output terminal of the last delay unit D1n in the delay chain 11, and the other port is used to access a clock signal, and a corresponding error signal is generated according to the phase difference between the delayed clock signal and the non-delayed clock signal.

[0024] The charge pump 13 is a voltage regulating circuit, which is connected to the output terminal of the phase detector 12, and can generate a source current or an absorption current according to the error signal output by the phase detector 12, so as to generate a corresponding control voltage at the output terminal.

[0025] The low-pass filter 14 is an RC filter network composed of a resistor R and a capacitor C. It is connected to the output terminal of the charge pump and is used to filter out the high-frequency noise in the control voltage generated by the charge pump 13, and form a stable reference voltage at the reference voltage node Vbias. This reference voltage node Vbias is also connected to the delay chain 11 to control the delay time of each delay unit in the delay chain 11.

[0026] During the actual operation process, the clock signal is input to the first delay unit D11 of the delay chain 11 and is transmitted through each stage of the delay unit in sequence to the last delay unit D1n for output. The clock signal is also directly input to the phase detector 12 as a reference clock signal.

[0027] The delay time of each delay unit in the delay chain 11 is determined by the reference voltage of the reference voltage node Vbias, and there is a negative correlation between the two. (That is, the higher the reference voltage, the shorter the delay time of the delay unit, and the shorter the total delay time of the delay chain 11. On the contrary, the lower the reference voltage, the longer the total delay time of the delay chain 11.)

[0028] When the total delay time of the delay chain 11 is greater than one clock cycle, the phase of the clock signal delayed by the delay chain 11 will lag behind the reference clock signal. When the phase detector 12 detects this phase lag, it outputs a corresponding error signal to make the charge pump 13 generate a source current. Correspondingly, the output voltage of the charge pump 13 increases, and the reference voltage of the reference voltage node Vbias increases accordingly, so that the signal transmission speed of the delay unit is accelerated, achieving the effect of reducing the total delay time of the delay chain 11.

[0029] On the contrary, when the total delay time of the delay chain 11 is less than one clock cycle, the phase of the clock signal delayed by the delay chain 11 is advanced with respect to the reference clock signal. When the phase detector 12 detects this phase advance, it outputs a corresponding error signal to cause the charge pump 13 to generate an absorption current. Accordingly, the output voltage of the charge pump 13 decreases, and the reference voltage of the reference voltage node Vbias decreases accordingly, causing the signal transmission speed of the delay unit to slow down, achieving the effect of increasing the total delay time of the delay chain 11.

[0030] Through the closed-loop action of the above-mentioned phase detection, voltage regulation, and delay time adjustment, a negative feedback regulation loop is formed, enabling the reference voltage Vbias to finally stabilize at the target value. At this time, the total delay time of the delay chain 11 is equivalent to one clock cycle T of the clock signal, and the delay time of each delay unit is T / n.

[0031] Please continue to refer to Figure 1 , the time measurement module 20 includes: a measurement delay chain 21 and a status register 22.

[0032] Among them, the measurement delay chain 21 is composed of a plurality of cascaded delay units D21 to D2n. The first delay unit D21 in the measurement delay chain 21 is used to receive the echo signal (detection process), and the echo signal can propagate along the measurement delay chain 21 through each delay unit in turn.

[0033] The reference voltage Vbias generated by the aforementioned delay locking module 10 is provided to the measurement delay chain 21 through physical metal transmission, so that the delay time of the delay units in the measurement delay chain 21 is equal to that of the delay units in the delay chain 11.

[0034] The status register 22 is correspondingly set with the delay units in the measurement delay chain 21. The set terminal D of a status register 22 is connected to a delay unit in the measurement delay chain 21 for sampling and recording whether the echo signal has propagated to this delay unit. The sampling control terminal CLK of each status register 22 is used to access the clock signal, and when the rising edge of the clock signal arrives, it triggers the sampling and recording actions.

[0035] During actual operation, when the echo signal is input from the input end of the first delay unit, the signal will propagate along the measurement delay chain 21. When the rising edge of the clock signal arrives, it triggers each status register 22 to perform sampling, and records whether the amplitude of the echo signal is higher than the threshold through the change of the register status. For example, when the response value output by the status output terminal of the status register 22 is 1, it indicates that the amplitude of the echo signal is higher than the threshold, that is, the echo signal corresponds at this time, and vice versa, it indicates that the amplitude of the echo signal is lower than the threshold, that is, the echo signal does not correspond at this time.

[0036] As described in the background art, since the flight time corresponding to the echo signal does not exactly correspond to an integer number of clock cycles, the rising edge (i.e., the leading edge) of the echo signal in the last clock cycle can be determined from the count value before the response value output by each register changes from 1 to 0, that is, the flight time can be determined.

[0037] In the process of implementing the present application, the applicant noticed that: the accuracy of the count value obtained by the measurement delay module is determined by the reference voltage provided by the delay lock module 10 to the measurement delay chain 21. It is always desired that the reference voltage received by the measurement delay chain 21 is equal to the reference voltage generated by the delay lock module 10 to ensure that there is a comparable delay time between the measurement delay chain 21 and the delay chain 11.

[0038] However, when the reference voltage is provided to the time measurement module 20 through physical metal transmission, it is affected by inevitable factors such as voltage drop during transmission and physical differences introduced during the manufacturing process, and cannot be accurately transmitted to the delay units of the measurement delay chain 21. This results in a deviation in the delay time of the measurement delay chain 21, causing an inaccurate problem with the digital count value.

[0039] In the process of implementing the present application, the applicant found through research that: based on some pre-stored and detected deviation information related to temperature, during the actual measurement process, according to the current operating temperature of the time-to-digital converter, the digital count value obtained by conversion can be quickly compensated in real time through a suitable compensation coefficient, so as to improve the measurement accuracy and reliability of the time-to-digital converter.

[0040] Figure 2 Schematic diagram of the time-to-digital converter provided by the embodiment of the present application. As Figure 2 shown, the time-to-digital converter includes: a measurement delay module 30, a storage module 40, and a correction module 50.

[0041] Among them, the measurement delay module 30 is a functional circuit for measuring and obtaining the original count value. It adopts Figure 1 a principle similar to that of the time measurement module 20 shown, and includes a first delay chain 31 and a register array 32.

[0042] The first delay chain 31 includes N first delay units D31 connected in cascade, where N is a first preset number. Each first delay unit D31 is connected to a first preset voltage V1, and the specific delay time is controlled by the first preset voltage.

[0043] The register array 32 includes a plurality of registers R32. Each register R32 corresponds to a first delay unit D31, and its first input terminal is connected to the corresponding first delay unit D31 for sampling and detecting the echo signal.

[0044] The second input terminal In_2 of each register R32 is used to access the clock signal Clock, which serves as a sampling trigger terminal to trigger the sampling and recording operations when the clock signal arrives.

[0045] When an echo signal is injected into the input terminal In_1 of the first delay chain 31, the register array 32 performs sampling and recording operations to generate a corresponding first count value. The first count value refers to the number of registers recorded by the register array before the echo signal is delayed to the same phase as the clock signal (i.e., when the echo signal passes through the first count value of the first delay units D31 in the first delay chain 31, the echo signal is phase-aligned with the clock signal).

[0046] The storage module 40 is a functional module that can record and hold data information in the form of charge, voltage, or other physical quantities, and can perform read and / or update operations on the data information according to requirements. It stores the mapping relationship between the temperature and the compensation coefficient obtained through pre-measurement operations, providing basic data support for the compensation and correction of the count value.

[0047] This mapping relationship is stored or represented by various different data information. For example, the storage module 40 stores a set of discrete data points formed by multiple candidate compensation coefficients corresponding to different temperatures. Alternatively, the storage module 40 stores the association relationship between the temperature and the candidate compensation coefficient, providing a calculation function that can be used to calculate the compensation coefficient at any temperature point.

[0048] The correction module 50 is a functional module for performing count value compensation processing. It is respectively connected to the storage module 40 and the register array 32, and is used to read the mapping relationship between the temperature and the compensation coefficient in the storage module 40, obtain the compensation coefficient, and compensate the first count value accordingly to obtain the compensated count value.

[0049] Specifically, the correction module 50 determines a specific compensation coefficient according to the current temperature of the time-to-digital converter and multiple candidate compensation coefficients, or calculates the corresponding compensation coefficient according to the current temperature and the above association relationship.

[0050] Through the pre-stored relevant information of the temperature and the compensation coefficient, during the actual measurement process, according to the current working temperature of the time-to-digital converter, the appropriate compensation coefficient can be quickly obtained to achieve real-time compensation of the count value, significantly improving the measurement accuracy and reliability of the time-to-digital converter.

[0051] In some other embodiments, as Figure 3 shown, the time-to-digital converter further includes: a calibration module 60.

[0052] Among them, the calibration module 60 is a functional module for measuring and acquiring data information on the mapping relationship between temperature and compensation coefficient. When a clock signal is injected into the input end In_1 of the first delay chain 31, it can acquire the second count value of the register array 32, and determine a candidate compensation coefficient according to the second count value and the expected count value corresponding to the first preset voltage.

[0053] In this application, similar to the above-mentioned first count value, this "second count value" refers to the number of registers recorded by the register array 32 when a clock signal is injected into the first delay chain 31 before the phases of the clock signal delayed by the measurement delay module and the non-delayed clock signal are the same (that is, when the clock signal passes through the second count value of the first delay units D31 in the first delay chain 31, the phases of the two clock signals are aligned).

[0054] This "expected count value" refers to the count value corresponding to the first delay chain 31 when receiving the first preset voltage and injecting the clock signal under ideal conditions, that is, the count value used as a reference.

[0055] As mentioned above, the first preset voltage V1 is generated by the delay lock module 10 based on the clock signal. Under ideal conditions, when the time measurement module 30 of the time-to-digital converter receives the same clock signal, based on the same delay time, the expected count value should be the same as the number of registers of the delay lock module 10; correspondingly, under ideal conditions, the measurement delay module 30 should generate a second count value that is the same as the expected count value.

[0056] However, in actual usage scenarios, there are often differences from the ideal state, that is, the second count value will be different from the expected count value; based on such a premise, the calibration module 60 combines the second count value and the expected count value, and can determine the deviation of the count value generated by the time-to-digital converter at the current temperature, so as to determine the corresponding candidate compensation coefficient to represent this deviation.

[0057] Specifically, the candidate compensation coefficient can be determined by the ratio between the second count value and the expected count value. For example, the ratio of the second count value to the expected count value, or the ratio of the expected count value to the second count value.

[0058] Please continue to refer to Figure 1 , in a typical time-to-digital converter, the delay chain 11 and the measurement delay chain 21 are designed to have the same number of delay units. However, in actual applications, for example, under different temperature conditions, the delay time of the delay units may be too small, resulting in the second count value being greater than the expected count value. At this time, if the number of delay units of the measurement delay chain 21 still remains the same as that of the delay chain 11, it will cause the second count value to overflow the measurement range, and an accurate second count value cannot be obtained for calculating the candidate compensation coefficient.

[0059] In some embodiments, please continue to refer to Figure 3 , several registers and corresponding delay units are appropriately added to the measurement delay module, so that the number of registers is greater than the expected count value, providing a sufficient time measurement range to avoid the problem of overflow of the second count value. Among Figure 3 , the registers and corresponding delay units that provide the additional added time measurement range are referred to as the "Tail of the measurement delay module".

[0060] In some embodiments, please continue to refer to Figure 3 , the time-to-digital converter further includes: a reference delay module 70 for providing a first preset voltage V1. The reference delay module 70 includes: a second delay chain 71, a phase detector 72, and a voltage control module 73.

[0061] Among them, the second delay chain 71 includes M second delay units D71 connected in cascade, where M is a second preset number. The second delay unit D71 is a delay unit having the same designed delay amount as the first delay unit D31, and its delay time is determined by a second preset voltage V2 generated by the voltage control module 73.

[0062] As described above, the second preset number M is equal to the aforementioned expected count value. That is, the total delay time after passing through M second delay units D72 connected in cascade is equal to the clock period of a clock signal.

[0063] Specifically, the ratio between the first preset number N and the second preset number M is controlled between 1.1 and 2.0 to ensure a sufficiently wide time measurement range while not excessively increasing the cost. Preferably, the ratio between the first preset number and the second preset number is 1.5.

[0064] The phase detector 72 is a functional circuit for comparing the phase differences of two input signals. Its first input terminal is connected to the output terminal of the second delay chain 71 for receiving the delayed clock signal, and its second input terminal is directly connected to the clock signal receiving terminal In_3 to receive the undelayed clock signal as a reference signal. Based on the phase comparison circuit in practical applications, the phase detector 72 represents the phase difference between the detected clock signal and the delayed clock signal in the form of a suitable control signal (for example, the level of the voltage).

[0065] The voltage control module 73 is a functional circuit that can adaptively adjust the output voltage according to the input control signal; it is connected to the phase detector 72 and is used to feedback-adjust the output second preset voltage according to the control signal provided by the phase detector 72 until the phases of the clock signal and the delayed clock signal are the same to reach the steady state of the feedback adjustment, and determine the second preset voltage V2 at this time as the first preset voltage V1.

[0066] The first preset voltage V1 output by the voltage control module 73 can be transmitted to the measurement delay module 30 through one or more physical transmission paths and applied to the first delay chain 31, so that the delay unit D31 of the first delay chain 31 has a delay time roughly equivalent to that of the delay unit D71 of the second delay chain 71.

[0067] Specifically, please continue to refer to Figure 3 , the voltage control module 73 includes: a charge pump 731 and a filter 732.

[0068] Among them, the input end of the charge pump 731 is connected to the output end of the phase detector 72, and is used to receive the output control signal and adjust the voltage level of the output voltage according to the control signal. The output end of the charge pump 731 is connected to the filter 732, and the high-frequency noise after the output voltage is filtered by the filter 732 to form the required second preset voltage. The output end of the filter 732 is respectively connected to each second delay unit D32 to apply the second preset voltage to the second delay unit D32.

[0069] In some embodiments, please continue to refer to Figure 3 , the time-to-digital converter further includes: a temperature sensor 80 for sensing temperature information.

[0070] Among them, the temperature sensor 80 is connected to the calibration module 60 and is used to provide the current temperature of the time-to-digital converter for the calibration module 60. The calibration module 60 stores the measured candidate compensation coefficient and the temperature as a set of corresponding data information into the storage module 40 for subsequent use.

[0071] During the actual measurement process, by changing the current temperature at which the time-to-digital converter is located, the calibration module 60 repeats the measurement operation of the candidate compensation coefficient multiple times to obtain multiple sets of data information and stores them into the storage module 40.

[0072] In some embodiments, the temperature corresponding to the candidate compensation coefficient specifically measured by the calibration module 60 is appropriately set and determined so that the data information stored in the storage module 40 has better representativeness and can better reflect the deviation situation of the time-to-digital converter in the actual application scenario.

[0073] For example, when used in a vehicle scenario (for example, when applied to a lidar of a vehicle), the candidate compensation coefficients measured by the calibration module 60 include: the candidate compensation coefficient corresponding to the low-temperature value within the vehicle temperature range, the candidate compensation coefficient of the normal temperature value, and the candidate compensation coefficient corresponding to the high-temperature value.

[0074] Specifically, the low-temperature value is in the range of [-40°C to 0°C), the normal-temperature value is in the range of [0°C to 40°C), and the high-temperature value is in the range of [40°C to 125°C). Through such a temperature distribution range, the conventional operating temperature range of the time-to-digital converter can be well covered, reflecting the deviation of the time-to-digital converter in the actual application scenario.

[0075] In some other embodiments, please continue to refer to Figure 2 and Figure 3 , the correction module 50 is also connected to the temperature sensor 80. The current temperature of the time-to-digital converter is collected through the temperature sensor 80, and based on the data information stored in the storage module 40, the first count value is compensated to obtain a compensated count value to ensure the accuracy of the time-to-digital converter.

[0076] Specifically, when the storage module 40 stores a discrete data set of multiple candidate compensation coefficients corresponding to different temperatures, the correction module 50 can use the current temperature, the corresponding relationship between the candidate compensation coefficients and the temperature, and a preset fitting scheme to determine the compensation coefficient corresponding to the current temperature, and compensate the first count value according to the compensation coefficient corresponding to the current temperature to obtain a compensated count value to compensate the first count value.

[0077] Based on the needs of actual applications, technicians can configure any suitable type of fitting scheme for the correction module 50 to obtain the compensation coefficient corresponding to the current temperature. For example, when the storage module 40 stores candidate compensation coefficients corresponding to three different temperatures, linear fitting is performed using these three candidate compensation coefficients to obtain a linear function relationship between the temperature and the compensation coefficient. Subsequently, the compensation coefficient corresponding to the current temperature is calculated through this fitted linear function relationship.

[0078] Based on the time-to-digital converter provided in the foregoing one or more embodiments, the present application further provides a calibration method. It can be applied to the time-to-digital converter provided in the foregoing one or more embodiments to help calibrate the output result of the time-to-digital converter and improve the accuracy of the count value.

[0079] In some embodiments, as Figure 4 shown, the calibration method of the time-to-digital converter includes the following steps:

[0080] S410. When an echo signal is injected into the first delay chain, obtain the first count value of the register array.

[0081] Among them, the first delay chain includes a first preset number of cascaded first delay units. The injected echo signal propagates through each of the first delay units in the first delay chain in sequence. The register array includes a plurality of registers, and each register corresponds to a first delay unit for sampling and detecting the echo signal. When receiving a clock signal, the register array samples and records, and outputs a corresponding first count value. The first count value refers to the number of registers recorded by the register array before the echo signal is delayed to the same phase as the clock signal (that is, when the echo signal passes through the first count value of the first delay units in the first delay chain, the echo signal is aligned with the clock signal in phase).

[0082] S420. Determine a target compensation coefficient according to the current temperature and pre-stored reference data.

[0083] Among them, the "reference data" is data information representing the correlation between the compensation coefficient and the temperature. Combining the reference data, the target compensation coefficient at the current temperature can be estimated and determined.

[0084] Specifically, the reference data includes: a plurality of candidate compensation coefficients corresponding to different temperatures. Alternatively, the reference data includes: the correlation between the temperature and the candidate compensation coefficients.

[0085] S430. Compensate the first count value according to the target compensation coefficient to obtain a compensated count value.

[0086] Among them, the target compensation coefficient represents the deviation situation of the time-to-digital converter at the current temperature. Using this target compensation coefficient, the first count value can be compensated and corrected to obtain a compensated count value, achieving the effect of eliminating the deviation and improving the accuracy of the count value.

[0087] Specifically, when the reference data includes a plurality of candidate compensation coefficients corresponding to different temperatures, the target compensation coefficient is determined according to the current temperature and the plurality of candidate compensation coefficients. Alternatively, when the reference data includes the correlation between the temperature and the candidate compensation coefficients, the target compensation coefficient is determined according to the correlation and the current temperature.

[0088] More specifically, based on a fitting method, the target compensation coefficient is determined according to a plurality of candidate compensation coefficients corresponding to different temperatures and the current temperature. First, according to the correspondence between the candidate compensation coefficients and the temperature, with a preset fitting scheme, the correlation between the compensation coefficient and the temperature is obtained by fitting. Subsequently, according to the current temperature, the target compensation coefficient is calculated and determined through the correlation between the compensation coefficient and the temperature.

[0089] For example, the preset fitting scheme is linear fitting, and the linear correlation between the temperature and the compensation coefficient is obtained by fitting.

[0090] The method of quickly determining a suitable target compensation coefficient based on pre-stored reference data and the current operating temperature of the time-to-digital converter to perform real-time compensation on the count value significantly improves the measurement accuracy and reliability of the time-to-digital converter during the actual measurement process.

[0091] In some other embodiments, the calibration method further includes the step of measuring and obtaining the foregoing reference data. For ease of description, hereinafter Figure 4 The method steps shown for implementing real-time compensation of the count value are referred to as the "operating mode", while Figure 5 The steps shown for measuring and obtaining the reference data are referred to as the "calibration mode". As Figure 5 shown, the steps of this calibration mode include:

[0092] S510. Obtain the current temperature of the time-to-digital converter.

[0093] Among them, the "current temperature" is detected and obtained through the temperature sensor of the time-to-digital converter.

[0094] S520. When a clock signal is injected into the first delay chain, obtain the second count value of the register array.

[0095] Among them, the "second count value" refers to the number of registers recorded by the register array before the phase of the clock signal delayed by the measurement delay module is the same as that of the non-delayed clock signal when a clock signal is injected into the first delay chain (that is, when the clock signal passes through the second count value of the first delay units in the first delay chain, the phases of the two clock signals are aligned).

[0096] S530. Determine a candidate compensation coefficient according to the second count value and the expected count value, and store and record it.

[0097] Among them, the expected count value refers to the count value corresponding to the first delay chain 31 when receiving the first preset voltage and injecting a clock signal under ideal conditions. It is used as a reference and benchmark for the count value.

[0098] Specifically, the candidate compensation coefficient is the ratio between the second count value and the expected count value. It can be the ratio of the second count value to the expected count value, or the ratio of the expected count value to the second count value, which is not specifically limited herein.

[0099] S540. Change the temperature at which the time-to-digital converter is located and return to step S501 again.

[0100] Among them, the reference data needs to include multiple candidate compensation coefficients corresponding to different temperatures to comprehensively cover the possible application environments of the time-to-digital converter. Thus, after changing the temperature, steps S510 to S530 are repeatedly executed until multiple candidate compensation coefficients corresponding to different temperatures required are obtained and stored, and then the calibration mode ends.

[0101] For example, the candidate compensation coefficients corresponding to the low-temperature values within the automotive temperature range, the candidate compensation coefficients for room-temperature values, and the candidate compensation coefficients for high-temperature values.

[0102] To fully describe the embodiments of the present application, the following combines Figure 6 the time-to-digital converter shown to detail the specific operation process and switching method of its calibration mode and working mode.

[0103] 1) Calibration mode:

[0104] In the calibration mode, the selector is configured to output "0", and a clock signal is injected into the echo input terminal In_1 of the measurement delay module 30. When the rising edge of the clock signal is received at the clock signal input terminal In_2 of the measurement delay module 30, the register array samples to determine the second count value. The calibration module 60 obtains the second count value determined by the register array sampling through the selector, and obtains the current temperature information through the temperature sensor 80.

[0105] The calibration module 60 calculates and obtains the candidate compensation coefficient at the current temperature based on the ratio between the second count value and the expected count value, and stores the candidate compensation coefficient and the corresponding temperature as a set of data into the storage module 40.

[0106] After changing the current temperature of the time-to-digital converter, the above operations are repeated multiple times until multiple candidate compensation coefficients at different temperatures required are obtained.

[0107] 2) Working mode:

[0108] In the working mode, the selector is configured to output "1". At this time, an echo signal is injected into the echo signal input terminal In_1 of the measurement delay module 30. When the rising edge of the clock signal is received at the clock signal input terminal In_2 of the measurement delay module 30, the register array samples to determine the first count value. The correction module 50 obtains the first count value determined by the register array sampling through the selector. Subsequently, the correction module 50 obtains the current temperature information through the temperature sensor 80, and calls the data information stored in the storage module 40 to determine the target compensation coefficient corresponding to the current temperature information. Finally, the first count value is compensated in real time using the target compensation coefficient, and the compensated count value is output through the count value output terminal Cnt.

[0109] In some embodiments, the time-to-digital converter has the ability to switch modes. After working in the operating mode for a period of time, it can be switched back to the calibration mode to update the reference data. Alternatively, the time-to-digital converter can also be configured not to have the switching ability, and after switching to the operating mode, it no longer has the ability to resume the calibration mode.

[0110] In other embodiments, the time-to-digital converter can also be directly configured or store pre-determined reference data in the storage module and directly operate in the operating mode without entering the calibration mode.

[0111] It should be noted that one or more method steps in the calibration method provided by the embodiments of the present application can be implemented or executed by electronic hardware, computer software programs, or a combination of the two. Whether these method steps are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0112] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other changes in different aspects of the present application as described above. For the sake of brevity, they are not provided in detail; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A time-to-digital converter, characterized in that, Comprising: A measurement delay module, including a first delay chain and a register array. The first delay chain includes a first preset number of cascaded first delay units. The first delay units are used to access a first preset voltage. The register array includes multiple registers. Each register corresponds to one of the first delay units. The first input terminal of the register is connected to the corresponding first delay unit. The second input terminal of the register is used to access a clock signal; A storage module, which is used to store multiple candidate compensation coefficients corresponding to different temperatures, or to store the association relationship between temperature and candidate compensation coefficients; A calibration module, which is used to determine the candidate compensation coefficient according to the second count value of the register array and the expected count value corresponding to the first preset voltage when the clock signal is injected into the first delay chain. The expected count value is less than the number of registers; And A correction module, which is used to compensate the first count value of the register array according to the compensation coefficient when an echo signal is injected into the first delay chain to obtain a compensated count value. The compensation coefficient is obtained according to the current temperature of the time-to-digital converter and the multiple candidate compensation coefficients, or the compensation coefficient is obtained according to the current temperature and the association relationship.

2. The time-to-digital converter according to claim 1, wherein The second count value is: when the clock signal is injected into the first delay chain, the number of registers recorded by the register array before the phase of the clock signal delayed by the measurement delay module is the same as that of the non-delayed clock signal.

3. The time-to-digital converter according to claim 2, wherein The candidate compensation coefficient is the ratio of one of the second count value and the expected count value to the other.

4. The time-to-digital converter according to claim 2, wherein It further includes a reference delay module, and the reference delay module includes: A second delay chain, including a second preset number of cascaded second delay units. The designed delay amount of the second delay units is the same as that of the first delay units. The second delay units are used to access a second preset voltage. The second delay chain is used to access the clock signal and perform delay to output a delayed clock signal, where the second preset number is equal to the expected count value; A phase detector, the first input terminal of the phase detector is connected to the output terminal of the second delay chain, the second input terminal of the phase detector is used to receive the clock signal, and the phase detector is used to compare the phase difference between the clock signal and the delayed clock signal; A voltage control module, connected to the phase detector, which is used to adjust the second preset voltage according to the phase difference until the phases of the clock signal and the delayed clock signal are the same, so as to obtain the adjusted second preset voltage, and determine the adjusted second preset voltage as the first preset voltage.

5. The time-to-digital converter according to claim 4, wherein The voltage control module includes a charge pump and a filter; The input terminal of the charge pump is connected to the output terminal of the phase detector, the output terminal of the charge pump is connected to the filter, and the filter is connected to each of the second delay units.

6. The time-to-digital converter according to claim 4, wherein The ratio of the first preset number to the second preset number is between 1.1 and 2.

0.

7. The time-to-digital converter according to claim 2, wherein It further includes a temperature sensor, which is used to obtain the current temperature of the time-to-digital converter; The calibration module is connected to the temperature sensor. The calibration module is used to measure candidate compensation coefficients corresponding to different temperatures and store the corresponding relationship between the compensation coefficients and temperatures in the storage module.

8. The time-to-digital converter according to claim 7, wherein, The different temperatures include low-temperature values, normal-temperature values, and high-temperature values within the vehicle specification temperature range; Among them, the low-temperature value is in the range of [-40°C to 0°C), the normal-temperature value is in the range of [0°C to 40°C), and the high-temperature value is in the range of [40°C to 125°C).

9. The time-to-digital converter according to claim 7, wherein The correction module is connected to the temperature sensor; The storage module is used to store multiple candidate compensation coefficients corresponding to different temperatures; The correction module is used to determine the compensation coefficient corresponding to the current temperature according to the current temperature, the corresponding relationship between the candidate compensation coefficients and temperatures, and a preset fitting scheme, and compensate the first count value according to the compensation coefficient corresponding to the current temperature to obtain a compensated count value.

10. A calibration method, applied to the time-to-digital converter as described in claim 1, characterized in that The method includes: When injecting an echo signal into the first delay chain, obtaining a first count value of the register array; the first delay chain includes a first preset number of cascaded first delay units, and the register array includes multiple registers, and each register corresponds to one of the first delay units; Determining a target compensation coefficient according to the current temperature and pre-stored reference data; Compensating the first count value according to the target compensation coefficient to obtain a compensated count value.

11. The calibration method according to claim 10, characterized in that, The pre-stored reference data includes: multiple candidate compensation coefficients corresponding to different temperatures. Specifically, determining the target compensation coefficient according to the current temperature includes: determining the target compensation coefficient according to the current temperature and the multiple candidate compensation coefficients; or The pre-stored reference data includes: the correlation relationship between temperature and candidate compensation coefficients. Specifically, determining the target compensation coefficient according to the current temperature includes: determining the target compensation coefficient according to the correlation relationship and the current temperature.

12. The calibration method according to claim 11, wherein The method further includes: Obtaining the current temperature of the time-to-digital converter; When injecting a clock signal into the first delay chain, obtaining a second count value of the register array; Determining the candidate compensation coefficient corresponding to the current temperature according to the second count value and the expected count value; Among them, the expected count value is the standard count value obtained after time-to-digital conversion of the clock signal; the candidate compensation coefficient is the ratio of one of the second count value and the expected count value to the other.

13. The calibration method according to claim 11, wherein, Specifically, determining the target compensation coefficient according to the current temperature and pre-stored reference data includes: According to the corresponding relationship between the candidate compensation coefficients and temperatures, fitting the correlation relationship between the compensation coefficient and temperature with a preset fitting scheme; Calculating and determining the target compensation coefficient according to the current temperature through the correlation relationship between the compensation coefficient and temperature.

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