Integrated current and voltage reference source circuit with process compensation

Abstract

The invention provides an integrated current and voltage reference source circuit with process compensation. The integrated current and voltage reference source circuit can be applied to the technical field of circuit design. The circuit comprises a current reference source sub-circuit which comprises at least one current transistor group, each current transistor group comprises a plurality of current transistors connected in parallel, and the current reference source sub-circuit is configured to output reference current according to the number of the current transistors connected in parallel in each current transistor group and the sizes of the current transistors; the voltage reference source sub-circuit comprises at least one voltage transistor group, and each voltage transistor group comprises a plurality of voltage transistors connected in parallel and is configured to obtain input current of the voltage reference source sub-circuit according to the reference current; the reference voltage is output according to the input current, the number of the voltage transistors connected in parallel in each voltage transistor group and the sizes of the voltage transistors; and the temperature compensation sub-circuit is connected with the output end of the current reference source sub-circuit and is configured to output compensation current, and the compensation current is used for reducing the temperature coefficient of the reference current.

Description

Technical Field

[0001] The present disclosure relates to the technical field of circuit design, and particularly to the scenario of battery-powered Internet of Things devices. More specifically, it relates to an integrated current and voltage reference source circuit with process compensation. Background Art

[0002] In recent years, the widespread application of portable electronic devices and wearable devices has prompted people to put forward higher requirements for these devices, including low power consumption to extend battery life and service life, and high precision to ensure the accuracy of data acquisition and measurement. The reference source plays a crucial role in analog integrated circuits, and the reference source includes a current reference source and a voltage reference source. The current reference source can provide a reference current for circuits such as operational amplifiers and oscillators; the voltage reference source can provide a reference voltage for circuits such as analog-to-digital converters and temperature sensors.

[0003] In the process of implementing the concept of the present disclosure, the inventors found that there are at least the following problems in the related art: The reference source circuit in the related art is difficult to ensure high process accuracy and low temperature coefficient while achieving low power consumption. Summary of the Invention

[0004] In view of this, the present disclosure provides an integrated current and voltage reference source circuit with process compensation.

[0005] One aspect of the present disclosure provides an integrated current and voltage reference source circuit with process compensation, including:

[0006] A current reference source sub-circuit, including at least one current transistor group, each of the above current transistor groups includes a plurality of parallel-connected current transistors, configured to output a reference current according to the number of the above parallel-connected current transistors in each of the above current transistor groups and the size of the above current transistors;

[0007] A voltage reference source sub-circuit, connected to the above current reference source sub-circuit, the above voltage reference source sub-circuit includes at least one voltage transistor group, each of the above voltage transistor groups includes a plurality of parallel-connected voltage transistors, configured to obtain the input current of the above voltage reference source sub-circuit according to the above reference current, and output a reference voltage according to the above input current, the number of the above parallel-connected voltage transistors in each of the above voltage transistor groups, and the size of the above voltage transistors;

[0008] A temperature compensation sub-circuit, connected to the output end of the above current reference source sub-circuit, configured to output a compensation current, and the above compensation current is used to reduce the temperature coefficient of the above reference current.

[0009] According to an embodiment of the present disclosure, the above-mentioned current reference source sub-circuit is configured to: in a first temperature range, output the above-mentioned reference current that decreases as the temperature increases; in a second temperature range, output the above-mentioned reference current that increases as the temperature increases;

[0010] The above-mentioned voltage reference source sub-circuit is configured to: in the above-mentioned first temperature range, output the above-mentioned reference voltage that increases as the temperature increases; in the above-mentioned second temperature range, output the above-mentioned reference voltage that decreases as the temperature increases;

[0011] The above-mentioned temperature compensation sub-circuit is configured to: in the above-mentioned first temperature range, output the above-mentioned compensation current that decreases as the temperature increases; in the above-mentioned second temperature range, output the above-mentioned compensation current that increases as the temperature increases;

[0012] Wherein, the temperature in the above-mentioned first temperature range is less than the temperature in the above-mentioned second temperature range.

[0013] According to an embodiment of the present disclosure, the above-mentioned circuit further includes:

[0014] A current output sub-circuit configured to output a current proportional to the absolute temperature;

[0015] Wherein, the above-mentioned temperature compensation sub-circuit is configured to output the above-mentioned compensation current according to the above-mentioned reference current and the current proportional to the absolute temperature to reduce the temperature coefficient of the above-mentioned reference current.

[0016] According to an embodiment of the present disclosure, the above-mentioned temperature compensation sub-circuit includes:

[0017] A first current mirror circuit configured to output a zero temperature coefficient current according to the above-mentioned reference current;

[0018] A temperature trigger control sub-circuit configured to adjust the magnitude of the above-mentioned zero temperature coefficient current;

[0019] A slope adjustment sub-circuit configured to adjust the magnitude of the above-mentioned compensation current according to the adjusted zero temperature coefficient current and the above-mentioned current proportional to the absolute temperature.

[0020] According to an embodiment of the present disclosure, the above-mentioned first current mirror circuit includes a first current mirror transistor group, a second current mirror transistor group, a third current mirror transistor group, and a fourth current mirror transistor group;

[0021] The above-mentioned temperature trigger control sub-circuit includes a first temperature trigger transistor group and a second temperature trigger transistor group. Wherein, the above-mentioned temperature trigger control sub-circuit adjusts the magnitude of the above-mentioned zero temperature coefficient current by controlling the aspect ratio between the above-mentioned first temperature trigger transistor group and the second temperature trigger transistor group;

[0022] The above-mentioned slope adjustment sub-circuit includes a first slope adjustment transistor group and a second slope adjustment transistor group. Among them, the above-mentioned slope adjustment sub-circuit adjusts the magnitude of the compensation current by controlling the aspect ratios of the above-mentioned first slope adjustment transistor group and the above-mentioned second slope adjustment transistor group.

[0023] According to an embodiment of the present disclosure, the source of the above-mentioned first current mirror transistor group is connected to the above-mentioned power supply voltage, the drain of the above-mentioned first current mirror transistor group is connected to the drain of the above-mentioned first temperature trigger transistor group, the source of the above-mentioned second current mirror transistor group is connected to the above-mentioned power supply voltage, the drain of the above-mentioned second current mirror transistor group is connected to the drain of the above-mentioned second temperature trigger transistor group and the drain of the above-mentioned third current mirror transistor group, the source of the above-mentioned third current mirror transistor group is connected to the above-mentioned power supply voltage, the gate of the above-mentioned third current mirror transistor group is connected to the gate of the above-mentioned fourth current mirror transistor group, the source of the above-mentioned fourth current mirror transistor group is connected to the above-mentioned power supply voltage, and the drain of the above-mentioned fourth current mirror transistor group is connected to the drain of the above-mentioned first slope adjustment transistor group;

[0024] The gate of the above-mentioned first temperature trigger transistor group is connected to the gate of the second temperature trigger transistor group, and the sources of the above-mentioned first temperature trigger transistor group and the second temperature trigger transistor group are grounded; the gate of the above-mentioned first slope adjustment transistor group is connected to the gate of the second slope adjustment transistor group, and the sources of the above-mentioned first slope adjustment transistor group and the second slope adjustment transistor group are grounded.

[0025] According to an embodiment of the present disclosure, the multiple above-mentioned current transistor groups include a first current transistor group, a second current transistor group, a third current transistor group, a fourth current transistor group, a fifth current transistor group, and a sixth current transistor group. The above-mentioned first current transistor group is arranged in the first branch of the above-mentioned current reference source sub-circuit, the above-mentioned second current transistor group and the third current transistor group are arranged in the second branch of the above-mentioned current reference source sub-circuit, the above-mentioned fourth current transistor group is arranged in the third branch of the above-mentioned current reference source sub-circuit, and the above-mentioned fifth current transistor group and the above-mentioned sixth current transistor group are arranged in the fourth branch of the above-mentioned current reference source sub-circuit.

[0026] According to an embodiment of the present disclosure, the drain of the first current transistor group is connected to the first branch of the current reference source sub-circuit, the gate of the first current transistor group is connected to the gate of the second current transistor group, the source of the first current transistor group is connected to the source of the third current transistor group and the source of the sixth current transistor group, the drain of the second current transistor group is connected to the second branch of the current reference source sub-circuit, the source of the second current transistor group is connected to the drain of the third current transistor group, the gate of the third current transistor group is connected to the gate and drain of the fourth current transistor group, the drain of the fourth current transistor group is connected to the third branch of the current reference source sub-circuit, the source of the fourth current transistor group is connected to the source of the fifth current transistor group and the drain of the sixth current transistor group, the drain of the fifth current transistor group is connected to the fourth branch of the current reference source sub-circuit, and the gate of the fifth current transistor group is connected to the gate of the sixth current transistor group.

[0027] According to an embodiment of the present disclosure, the multiple voltage transistor groups include a seventh voltage transistor group, an eighth voltage transistor group, a ninth voltage transistor group, a tenth voltage transistor group, and an eleventh voltage transistor group. The seventh voltage transistor group and the ninth voltage transistor group are disposed on the first branch of the voltage reference source sub-circuit, the eighth voltage transistor group and the tenth voltage transistor group are disposed on the second branch of the voltage reference source sub-circuit, and the eleventh voltage transistor group is disposed on the third branch of the voltage reference source sub-circuit.

[0028] According to an embodiment of the present disclosure, the drain of the seventh voltage transistor group is connected to the first branch of the voltage reference source sub-circuit, the gate of the seventh voltage transistor group is connected to the gate of the ninth voltage transistor group, the source of the seventh voltage transistor group is connected to the drain of the ninth voltage transistor group, the source of the ninth voltage transistor group is grounded, the drain of the eighth voltage transistor group is connected to the second branch of the voltage reference source sub-circuit, the gate of the eighth voltage transistor group is connected to the gate of the tenth voltage transistor group, the source of the eighth voltage transistor group is connected to the drain of the tenth voltage transistor group, the source of the tenth voltage transistor group is connected to the source of the seventh voltage transistor group, the drain of the eleventh voltage transistor group is connected to the third branch of the voltage reference source sub-circuit, the source of the eleventh voltage transistor group is connected to the source of the eighth voltage transistor group, and the gate of the eleventh voltage transistor group is connected to the drain of the eleventh voltage transistor group.

[0029] According to an embodiment of the present disclosure, the integrated current and voltage reference source circuit with process compensation in the present disclosure can provide a reference current and a reference voltage simultaneously. Moreover, by the number of current transistors connected in parallel in the current reference source sub-circuit and the number of voltage transistors connected in parallel in the voltage reference source sub-circuit, the overall aspect ratio of the current transistor group and the voltage transistor group can be adjusted, thereby controlling the magnitudes of the positive and negative temperature terms in the current reference source sub-circuit and the voltage reference source sub-circuit, obtaining a reference current and a reference voltage that are substantially independent of temperature, and outputting a compensation current through the temperature compensation circuit to act on the reference current to reduce the temperature coefficient of the reference current. By reasonably selecting the unit current transistor size of each current transistor group and reasonably selecting the unit current transistor size of each voltage transistor group, the process compensation effect can be achieved to improve the process accuracy of the output reference current and the output reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0031] Figure 1 Schematically shows an integrated current / voltage reference source circuit in the related art;

[0032] Figure 2 Schematically shows a schematic diagram of the principle of an integrated current and voltage reference source circuit with process compensation according to an embodiment of the present disclosure;

[0033] Figure 3 Schematically shows a circuit diagram of a current reference source sub-circuit according to an embodiment of the present disclosure;

[0034] Figure 4 Schematically shows a circuit diagram of a voltage reference source sub-circuit according to an embodiment of the present disclosure;

[0035] Figure 5 Schematically shows a temperature curve diagram of a reference current and a reference voltage according to an embodiment of the present disclosure;

[0036] Figure 6 Schematically shows a schematic diagram of the relationship between transistor size and process skew of threshold voltage;

[0037] Figure 7 Schematically shows a process compensation schematic diagram of a reference voltage according to an embodiment of the present disclosure;

[0038] Figure 8 Schematically shows a process compensation simulation comparison result according to an embodiment of the present disclosure;

[0039] Figure 9Schematically shows a circuit diagram of a current output sub - circuit according to an embodiment of the present disclosure;

[0040] Figure 10 Schematically shows a circuit diagram of a temperature compensation sub - circuit according to an embodiment of the present disclosure;

[0041] Figure 11 Schematically shows a diagram of the compensation result of a compensation current for a reference current according to an embodiment of the present disclosure;

[0042] Figure 12 Schematically shows a circuit diagram of an integrated current and voltage reference source circuit with process compensation according to an embodiment of the present disclosure; and

[0043] Figure 13 Schematically shows a simulation diagram of the temperature curves of the reference current and reference voltage output by an integrated current and voltage reference source circuit with process compensation according to an embodiment of the present disclosure. Detailed implementation manners

[0044] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well - known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0045] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0046] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0047] In the case of using expressions such as "at least one of A, B, and C, etc.", generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0048] Among existing reference sources, there is a reference source that is a complementary metal oxide semiconductor (CMOS) reference source. It achieves a temperature-independent reference output by operating a metal-oxide-semiconductor field-effect transistor (MOSFET) in the subthreshold region. Since this type of reference source does not require resistors, it has a smaller area compared to traditional bandgap reference sources while achieving low power consumption. However, since its output is generated based on the threshold voltage (V TH ), and V TH has a high process dependence, the CMOS reference source is very sensitive to process variations. And the reference source implemented based on MOSFET usually has a poor temperature coefficient (TC). Therefore, it is difficult for the existing technology to ensure high process accuracy and low temperature coefficient while achieving low power consumption.

[0049] Figure 1 Schematically shows an integrated current / voltage reference source circuit in the related art.

[0050] As Figure 1 shown, the startup circuit consists of M S1 ∼M S3 and its function is to make the VCR deviate from the zero bias point and enter the normal working state during the power-on process of the power supply. The transistor M S2 is used as a capacitor. When the power supply is powered on, at this time the V ref01 voltage has not been established and is 0V, and the gate-source voltage (V GS3 ) of M S3 increases as the power supply increases. When V GS3 is greater than the threshold voltage (V THS3 ) of M S3 , M S3 turns on, and then the gate voltages of M 3 and M 4 are reduced, so that the currents I 3 and I 4 flow through the VCR core circuit respectively, making it enter the normal working state. When V ref01 enters the normal working state, the gate voltage of M S3 is pulled low and the startup circuit is turned off. The transistor M 01 is a MOS transistor with a high threshold voltage, and the transistor M 02 is a MOS transistor with a low threshold voltage. Make M 01 and M 02Operating in the subthreshold region, since the currents flowing through the two MOS transistors are the same, both being I 3 , thus according to the current-voltage formula in the subthreshold region , it can be deduced that its output reference voltage is composed of the thermal voltage (V T ) and the threshold voltage (V TH ). V T has a temperature characteristic proportional to the absolute temperature (Proportional to Absolute Temperature, PTAT), and V TH has a temperature characteristic inversely proportional to the absolute temperature (Complementary to Absolute Temperature, CTAT). By appropriately adjusting the ratio of the PTAT term and the CTAT term, an output reference voltage independent of temperature can be obtained. The formula for the output reference voltage of this structure is:

[0051] (1)

[0052] Wherein, is the subthreshold slope factor, K 1 , K 2 are the width-to-length ratios of transistors M 01 and M 02 , V T is the thermal voltage, V TH01 and V TH02 are the threshold voltages of M 01 and M 02 respectively, C ox01 and C ox02 are the gate oxide capacitances.

[0053] Resistors R 1 and R 2 are different types of resistors with opposite TCs, that is, R 1 is a poly resistor with a negative TC, while R 2 is an NWELL resistor with a positive TC. The two are in series. By controlling the ratio relationship between R 1 and R 2 , a resistor insensitive to temperature is obtained. Through the clamping effect of the operational amplifier OPA, the voltage V A at point A is made equal to V ref01 , so V A is a voltage independent of temperature. Dividing by a resistor independent of temperature, a current independent of temperature is obtained, and then through the current mirror M 05 mirror replication, I ref01 is obtained.

[0054] Figure 1The integrated current / voltage reference source circuit shown generates a temperature-independent V T by combining the thermal voltage (V TH ) and the threshold voltage (V ref01 ) with different weights. Then, V ref01 is divided by a temperature-insensitive resistor to generate I ref01 . Since V TH and the resistor are greatly affected by the process, the circuit does not adopt corresponding optimization means to handle the process fluctuations of V TH and the resistor. Therefore, the process accuracy of the circuit is relatively poor. And because the circuit does not adopt corresponding technologies to optimize the temperature coefficient, the temperature coefficients of the output V ref01 and I ref01 of the circuit are both very high.

[0055] In view of this, the present disclosure provides an integrated current and voltage reference source circuit with process compensation, including: a current reference source sub-circuit, including at least one current transistor group, each of the current transistor groups including a plurality of parallel-connected current transistors, configured to output a reference current according to the number of the parallel-connected current transistors in each current transistor group and the size of the current transistors; a voltage reference source sub-circuit, connected to the current reference source sub-circuit, the voltage reference source sub-circuit including at least one voltage transistor group, each of the voltage transistor groups including a plurality of parallel-connected voltage transistors, configured to obtain the input current of the voltage reference source sub-circuit according to the reference current, and output a reference voltage according to the input current, the number of the parallel-connected voltage transistors in each voltage transistor group, and the size of the voltage transistors; a temperature compensation sub-circuit, connected to the output end of the current reference source sub-circuit, configured to output a compensation current, and the compensation current is used to reduce the temperature coefficient of the reference current.

[0056] Figure 2 Schematically shows a block diagram of an integrated current and voltage reference source circuit with process compensation according to an embodiment of the present disclosure.

[0057] As Figure 2 shown, the integrated current and voltage reference source circuit 200 with process compensation includes:

[0058] A current reference source sub-circuit 210, including at least one current transistor group, each of the current transistor groups including a plurality of parallel-connected current transistors, configured to output a reference current according to the number of the parallel-connected current transistors in each current transistor group and the size of the current transistors;

[0059] The voltage reference sub - circuit 220 is connected to the current reference sub - circuit 210. The voltage reference sub - circuit includes at least one voltage transistor group. Each voltage transistor group includes a plurality of parallel - connected voltage transistors, configured to obtain the input current of the voltage reference sub - circuit according to the reference current, and output a reference voltage according to the input current, the number of parallel - connected voltage transistors in each voltage transistor group, and the size of the voltage transistors.

[0060] The temperature compensation sub - circuit 230 is connected to the output end of the current reference sub - circuit 210, configured to output a compensation current, and the compensation current is used to reduce the temperature coefficient of the reference current.

[0061] According to an embodiment of the present disclosure, the integrated current and voltage reference source circuit with process compensation in the present disclosure can provide a reference current and a reference voltage simultaneously. Moreover, through the number of parallel - connected current transistors in the current reference sub - circuit and the number of parallel - connected voltage transistors in the voltage reference sub - circuit, the overall aspect ratio of the current transistor group and the voltage transistor group can be adjusted, thereby controlling the magnitudes of the positive and negative temperature terms in the current reference sub - circuit and the voltage reference sub - circuit, obtaining a reference current and a reference voltage that basically do not change with temperature, and outputting a compensation current through the temperature compensation circuit to act on the reference current to reduce the temperature coefficient of the reference current. By reasonably selecting the unit current transistor size of each current transistor group and reasonably selecting the unit current transistor size of each voltage transistor group, the process compensation effect can be achieved to improve the process accuracy of the output reference current and the output reference voltage.

[0062] Figure 3 The circuit schematic diagram of the current reference sub - circuit according to an embodiment of the present disclosure is schematically shown.

[0063] As Figure 3 shown, the current reference sub - circuit has a total of 4 branches, and the current in each branch is I REF , and the multiple current transistor groups include the first current transistor group M 1 , the second current transistor group M 2 , the third current transistor group M 3 , the fourth current transistor group M 4 , the fifth current transistor group M 5 , and the sixth current transistor group M 6 .

[0064] As Figure 3 shown, the first current transistor group M 1 is arranged in the first branch of the current reference sub - circuit, the second current transistor group M 2 and the third current transistor group M 3The fourth current transistor group M is disposed on the second branch of the current reference source sub-circuit 4 The fifth current transistor group M is disposed on the third branch of the current reference source sub-circuit 5 and the sixth current transistor group M 6 is disposed on the fourth branch of the current reference source sub-circuit

[0065] According to an embodiment of the present disclosure, the drain of the first current transistor group M 1 is connected to the first branch of the current reference source sub-circuit, the gate of the first current transistor group M 1 is connected to the gate of the second current transistor group M 2 the source of the first current transistor group M 1 is connected to the source of the third current transistor group M 3 and the source of the sixth current transistor group M 6 the drain of the second current transistor group M 2 is connected to the second branch of the current reference source sub-circuit, the source of the second current transistor group M 2 is connected to the drain of the third current transistor group M 3 the gate of the third current transistor group M 3 is connected to the gate and drain of the fourth current transistor group M 4 the drain of the fourth current transistor group M 4 is connected to the third branch of the current reference source sub-circuit, the source of the fourth current transistor group M 4 is connected to the source of the fifth current transistor group M 5 and the drain of the sixth current transistor group M 6 the drain of the fifth current transistor group M 5 is connected to the fourth branch of the current reference source sub-circuit, the gate of the fifth current transistor group M 5 is connected to the gate of the sixth current transistor group M 6

[0066] According to an embodiment of the present disclosure, the current transistor groups can all be NMOS transistors, M 1 、M 2 、M 4 and M 5 operate in the subthreshold region, M 3 operates in the linear region, M 6 operates in the saturation region

[0067] Wherein, the source-drain current of the MOS transistor in the subthreshold region can be expressed as:

[0068] (2)

[0069] The source-drain current of the MOS transistor in the saturation region can be expressed as: ​

[0070] (3)

[0071] The source-drain equivalent resistance of the MOS transistor in the linear region can be expressed as:

[0072] (4)

[0073] According to the above current formulas in the saturation region and subthreshold region and the expression of the equivalent resistance of the transistor in the linear region, we can derive the expression of I REF :

[0074] (5)

[0075] (6)

[0076] Among them, k i (i = 1~6) is the width-to-length ratio of the i-th current transistor group, and V THi (i = 1~6) is the threshold voltage of the i-th current transistor group. is the electron mobility, is the subthreshold slope factor, V T is the thermal voltage, is for M 4 , M 6 , M 5 , M 3 The difference relationship of the threshold voltages.

[0077] Among these, several parameters are temperature-related. The thermal voltage V T = KT / q has a positive temperature characteristic (K is the Boltzmann constant, q is the elementary charge, and T is the temperature); the threshold voltage V TH = V th0 + kT has a negative temperature characteristic (V th0 is the threshold voltage at a temperature of 0K, and k is the temperature coefficient of the threshold voltage); the mobility has a negative temperature characteristic ( is the mobility at temperature T 0 , and m is the temperature exponent of the mobility, generally considered to be 1.5). From the expression of I REF , it can be seen that by adjusting the number of current transistors connected in parallel in each current transistor group, the equivalent width-to-length ratio of the current transistor group can be controlled, thereby controlling the magnitudes of the positive and negative temperature terms. When the positive and negative temperature terms can exactly cancel each other out, a reference current that is basically independent of temperature can be obtained.

[0078] Figure 4 FIG. schematically shows a circuit diagram of a voltage reference source sub-circuit according to an embodiment of the present disclosure.

[0079] As shown Figure 4 , the voltage reference sub - circuit has a total of three branches, and the input current I of each branch BIAS is the same. The branch - current mirroring comes from I of the current reference sub - circuit REF . Since the current I REF is relatively large, considering low power consumption, I BIAS is not an exact one - to - one copy of I REF , and 3 / 10I REF can be selected. Among them, the multiple voltage transistor groups include the seventh voltage transistor group M 7 , the eighth voltage transistor group M 8 , the ninth voltage transistor group M 9 , the tenth voltage transistor group M 10 and the eleventh voltage transistor group M 11 . Among them, M 7 ~M 11 can be NMOS transistors and all operate in the sub - threshold region.

[0080] As shown Figure 4 , the seventh voltage transistor group M 7 and the ninth voltage transistor group M 9 are arranged in the first branch of the voltage reference sub - circuit, the eighth voltage transistor group M 8 and the tenth voltage transistor group M 10 are arranged in the second branch of the voltage reference sub - circuit, and the eleventh voltage transistor group M 11 is arranged in the third branch of the voltage reference sub - circuit.

[0081] According to an embodiment of the present disclosure, the drain of the seventh voltage transistor group M 7 is connected to the first branch of the voltage reference sub - circuit, the gate of the seventh voltage transistor group M 7 is connected to the gate of the ninth voltage transistor group M 9 , the source of the seventh voltage transistor group M 7 is connected to the drain of the ninth voltage transistor group M 9 , the source of the ninth voltage transistor group M 9 is grounded, the drain of the eighth voltage transistor group M 8 is connected to the second branch of the voltage reference sub - circuit, the gate of the eighth voltage transistor group M 8 is connected to the gate of the tenth voltage transistor group M 10 , the source of the eighth voltage transistor group M 8 is connected to the drain of the tenth voltage transistor group M 10 , and the source of the tenth voltage transistor group M 10 is connected to the seventh voltage transistor group M 7The source of, the eleventh voltage transistor group M 11 The drain of is connected to the third branch of the voltage reference source sub-circuit, the eleventh voltage transistor group M 11 The source of is connected to the source of the eighth voltage transistor group, the eleventh voltage transistor group M 11 The gate of is connected to the eleventh voltage transistor group M 11 The drain of.

[0082] As can be seen from the figure, V REF Can be expressed as M 9 、M 10 The source-drain voltage of and the sum of the gate-source voltages of M 11 : V REF =V DS9 +V DS10 +V DS11 ,while V DS9 Can be expressed as the gate-source voltage V 9 of M GS9 minus the gate-source voltage V 7 of M GS7 . According to the subthreshold region current formula, the expression of V GS can be obtained, and then the expression of V DS9 is as follows:

[0083] (7)

[0084] Similarly, the expression of V DS10 can be obtained as follows:

[0085] (8)

[0086] According to the subthreshold region current formula, the expression of V GS11 is as follows:

[0087] (9)

[0088] Substituting the above three expressions into the expression of V REF , we can obtain the relationship expression between V REF and the temperature-related quantity:

[0089] (10)

[0090] where, k i (i = 7~11)is the width-to-length ratio of the i-th voltage transistor group, V THi (i = 7~11)is the threshold voltage of the i-th voltage transistor group,

[0091] From the expression, we can see that V REF is composed of the thermal voltage VT and the threshold voltage V TH are combined to generate. Since the thermal voltage has a positive temperature characteristic and the threshold voltage has a negative temperature characteristic, the equivalent aspect ratio of the voltage transistor group is controlled by adjusting the number of voltage transistors connected in parallel in each voltage transistor group, thereby controlling the magnitude of the negative temperature term. When the positive temperature term and the negative temperature term can exactly cancel each other out, a reference voltage independent of temperature can be obtained.

[0092] Figure 5 Schematically shows the temperature curves of the reference current and the reference voltage according to an embodiment of the present disclosure.

[0093] As Figure 5 shown, by taking bias currents with different temperature shapes as the bias current of the voltage reference source sub-circuit, the obtained optimal temperature coefficients are different. The simulation results show that: Figure 5 When a zero temperature coefficient current is used as the bias in a, the optimal temperature coefficient of the reference voltage is about 3.1 ppm / °C; Figure 5 When a current with a concave temperature curve is used as the bias in b, the optimal temperature coefficient of the voltage reference is about 1.3 ppm / °C; Figure 5 When a current with a convex temperature shape is used as the bias in c, the optimal temperature coefficient of the reference voltage is about 4.1 ppm / °C. Therefore, for a reference voltage with a convex temperature curve, if a current with a concave temperature curve is used as the bias, the temperature coefficient of the reference voltage will be greatly optimized.

[0094] According to an embodiment of the present disclosure, as can be seen from Figure 5 d, when I BIAS is a concave curve, it is exactly opposite to the temperature curve shape of V REF (convex curve). And, as can be seen from Equation (10), the first term in the expression of V REF contains I BIAS , and I BIAS can be replicated through a current mirror from I REF . Therefore, the temperature curve of I BIAS is the same as the temperature curve of I REF . Therefore, when I REF is at a low temperature, it increases as the temperature decreases, thus compensating for the amount by which V REF decreases as the temperature decreases at a low temperature. When I REF is at a high temperature, it increases as the temperature increases, thus compensating for the amount by which V REF decreases as the temperature increases at a high temperature.

[0095] Thus, the current reference source sub-circuit can be configured to: output a reference current that decreases as the temperature increases in the first temperature range; output a reference current that increases as the temperature increases in the second temperature range; the voltage reference source sub-circuit can be configured to: output a reference voltage that increases as the temperature increases in the first temperature range; output a reference voltage that decreases as the temperature increases in the second temperature range; wherein, the temperature in the first temperature range is less than the temperature in the second temperature range.

[0096] Since the process variation of the threshold voltage V TH is very large, the output of the CMOS reference circuit is greatly affected by the process. From the expressions of the reference current and the reference voltage, they are both expressions related to the threshold voltage V TH .

[0097] (11)

[0098] (12)

[0099] I REF The V TH term in is , and the V REF The V TH term in is . Therefore, process compensation needs to be performed on the V TH term so that the V TH term does not change with the change of the process corner.

[0100] Figure 6 Schematically shows the relationship diagram between the transistor size and the process skew of the threshold voltage.

[0101] As Figure 6 shown, the difference between V TH at the slow process corner and the fast process corner (i.e., V TH，SS-FF ) is a function of the transistor size, and the transistor size is the channel width and channel length of the transistor. V TH，SS-FF decreases as the channel width of the transistor ( Figure 6 a in) and the channel length ( Figure 6 b in) increase. In addition, the process skew of V TH is only determined by the channel width of the transistor and is not affected by the number of parallel transistors in the transistor group ( Figure 6 c in). For I REF and V REF , this means that we can control the process skew of the V TH term by adjusting the channel length and channel width of the transistor corresponding to the threshold voltage appearing in their expressions. If the adjustment is appropriate, it will make VTH The value of the item does not change with the process. Taking V REF as an example, the schematic diagram of process compensation is as Figure 7 shown.

[0102] Figure 7 Schematically shows the schematic diagram of process compensation for the reference voltage according to an embodiment of the present disclosure.

[0103] As Figure 7 shown, when the channel widths and unit channel lengths of the parallel voltage transistors in M 9 are greater than those of the parallel voltage transistors in M 7 , it will cause V TH9 - V TH7 to have a positive process characteristic (a positive process characteristic means that from the SS process corner to the FF process corner, the value of V TH gradually increases; a negative process characteristic means that from the SS process corner to the FF process corner, the value of V TH gradually decreases); when the channel widths and channel lengths of the parallel voltage transistors in M 10 are greater than those of the parallel voltage transistors in M 8 , it will cause V TH10 - V TH8 to have a positive process characteristic, while V TH11 has a negative process characteristic. By adding appropriate weights, the V TH item that does not change with the process can be obtained. Similarly, the same method is adopted to reduce the process deviation of the V REF item in I TH .

[0104] Figure 8 Schematically shows the process compensation simulation comparison results according to an embodiment of the present disclosure.

[0105] As Figure 8 shown, the process deviation of V REF is measured by Monte Carlo simulation. At room temperature, a total of 200 Monte Carlo simulations are run, and the output results are as Figure 8 shown. Figure 8 In it, a is the Monte Carlo simulation result obtained by using large-size MOS transistors without process compensation. The average value ( REF ) of V is 1.133 V, and the standard deviation ( ) is 21.5 mV. Thus, the process deviation ( REF ) of V can be obtained as 1.89%. Figure 8 In it, b is the Monte Carlo simulation result obtained from the MOS transistor size with process compensation. V REFThe average value of ( ) is 1.081 V, and the standard deviation ( ) is 8.4 mV. Thus, the process deviation of V REF ( ) can be obtained as 0.78%. From the data comparison, we can see that the process deviation of V REF with process compensation is significantly smaller than that without process compensation, and the process accuracy is improved.

[0106] To further reduce its temperature coefficient, we compensate for the high-order non-linear terms in the current reference source through a segmented compensation circuit to continuously reduce the temperature coefficient of the reference current. Since the segmented compensation circuit requires two currents with different slopes to be compared with each other to generate the compensation current. One of the currents can be copied from the current reference, and the remaining current needs to be generated by other circuits.

[0107] First, we generate a PTAT current through the current output sub-circuit, as Figure 9 shown.

[0108] Figure 9 Schematically shows a circuit schematic diagram of the current output sub-circuit according to an embodiment of the present disclosure.

[0109] As Figure 9 shown, the generation of the PTAT current uses a resistor to make the NMOS transistors M a ~ M b operate in the sub-threshold region, and a resistor R 1 with a negative temperature characteristic is selected. Then, we can derive the expression of the PTAT current:

[0110] (13)

[0111] Where, I PTAT represents the PTAT current, and R 0 represents the resistance value of the resistor R 0 at temperature T 1 ; is the temperature coefficient of the resistor and is negative.

[0112] It can be seen from the expression that the numerator term has a positive temperature characteristic and the denominator term has a negative temperature characteristic. Therefore, the final I PTAT has a positive temperature characteristic.

[0113] After having the zero-temperature coefficient current and the PTAT current, the temperature compensation sub-circuit can be configured to output a compensation current according to the reference current and the current proportional to the absolute temperature to reduce the temperature coefficient of the reference current.

[0114] Figure 10A circuit schematic diagram of a temperature compensation sub - circuit according to an embodiment of the present disclosure is schematically shown.

[0115] As Figure 10 shown in a, the temperature compensation sub - circuit includes a first current mirror circuit 1010 configured to output a zero - temperature - coefficient current according to a reference current; a temperature - trigger control sub - circuit 1020 configured to adjust the magnitude of the zero - temperature - coefficient current; and a slope - adjustment sub - circuit 1030 configured to adjust the magnitude of the compensation current according to the adjusted zero - temperature - coefficient current and the current proportional to the absolute temperature.

[0116] According to an embodiment of the present disclosure, the first current mirror circuit 1010 includes a first current - mirror transistor group M p1 , a second current - mirror transistor group M p2 , a third current - mirror transistor group M p3 and a fourth current - mirror transistor group M p4 .

[0117] The temperature - trigger control sub - circuit 1020 includes a first temperature - trigger transistor group M n1 and a second temperature - trigger transistor group M n2 , wherein the temperature - trigger control sub - circuit 1032 adjusts the magnitude of the zero - temperature - coefficient current by controlling the aspect ratio between the first temperature - trigger transistor group M n1 and the second temperature - trigger transistor group M n2 .

[0118] The slope - adjustment sub - circuit 1030 includes a first slope - adjustment transistor group M n3 and a second slope - adjustment transistor group M n4 , wherein the slope - adjustment sub - circuit adjusts the magnitude of the compensation current by controlling the aspect ratio of the first slope - adjustment transistor group M n3 and the second slope - adjustment transistor group M n4 .

[0119] According to an embodiment of the present disclosure, the source of the first current - mirror transistor group M p1 is connected to the power supply voltage, the drain of the first current - mirror transistor group M p1 is connected to the drain of the first temperature - trigger transistor group M n1 , the source of the second current - mirror transistor group M p2 is connected to the power supply voltage, the drain of the second current - mirror transistor group M p2 is connected to the drain of the second temperature - trigger transistor group M n2 and the drain of the third current - mirror transistor group M p3 , the source of the third current - mirror transistor group M p3 is connected to the power supply voltage, and the gate of the third current - mirror transistor group M p3 is connected to the fourth current - mirror transistor group Mp4 The gate of the fourth current mirror transistor group M p4 The source of the fourth current mirror transistor group M is connected to the power supply voltage. p4 The drain of the fourth current mirror transistor group M is connected to the drain of the first slope adjustment transistor group M n3 ;

[0120] The gate of the first temperature trigger transistor group M n1 is connected to the gate of the second temperature trigger transistor group M n2 The source of the first temperature trigger transistor group M and the source of the second temperature trigger transistor group M are grounded. n1 The source of the first temperature trigger transistor group M and the source of the second temperature trigger transistor group M are grounded; n2 The gate of the first slope adjustment transistor group M n3 is connected to the gate of the second slope adjustment transistor group M n4 The source of the first slope adjustment transistor group M and the source of the second slope adjustment transistor group M are grounded. n3 The source of the first slope adjustment transistor group M and the source of the second slope adjustment transistor group M are grounded. n4

[0121] The PMOS transistors M p1 ~M p4 are of a current mirror structure. M p1 copies I REF from the current reference source sub-circuit, and the copied current is denoted as the zero temperature coefficient current I ZERO , M p2 copies I PTAT from the current output sub-circuit, and the copied current is denoted as I PTAT . n1 The PMOS transistors M n4 ~M n1 are also of a current mirror structure, where M n2 and M n3 are responsible for controlling the temperature trigger point of the compensation current, and M n4 and M

[0122] M n1 and M n2 have a width-to-length ratio of m:n. I ZERO is copied to M n1 and M n2 through the current mirror, and the current magnitude is n / mI n2 . As shown in b of ZERO . Figure 10 When this current is compared with the I p2 copied by M PTAT , when the current copied by M n2 is less than the current copied by M p2 , no current will be generated in M p3 and M p4 , and thus no ICOMP Current generation. When M n2 the replicated current is greater than M p2 the replicated current, M p3 and M p4 will generate a current, and the magnitude of the current is n / mI ZERO -I PTAT . By controlling the proportional relationship between m and n, the magnitude of I ZERO current can be controlled, and then the I ZERO current temperature curve and the intersection point of the I PTAT current temperature curve can be changed, so that the temperature trigger point of the compensation current can be changed. Then, by controlling M n3 and M n4 the aspect ratio, the slope of the compensation current can be controlled, that is, the magnitude of the compensation current can be controlled. The magnitude of the final compensation current is:

[0123] (14)

[0124] Since the temperature curve of the reference current is a concave curve, in the actual circuit, 2 such compensation branches are designed, each branch has a different temperature trigger threshold, one path corrects low temperature and the other path corrects high temperature. Therefore, the temperature compensation sub-circuit is configured to: output a compensation current that decreases as the temperature increases in the first temperature range; output a compensation current that increases as the temperature increases in the second temperature range.

[0125] Figure 11 Schematically shows a schematic diagram of the compensation result of the compensation current for the reference current according to an embodiment of the present disclosure.

[0126] As Figure 11 shown, subtracting the I REF before compensation from the compensation current I COMP finally obtains an I REF with a smaller temperature coefficient.

[0127] Figure 12 Schematically shows a circuit schematic diagram of an integrated current and voltage reference source circuit with process compensation according to an embodiment of the present disclosure.

[0128] As Figure 12 shown, M 1 ~M 6 are the core transistors of the current reference source sub-circuit 1210, and process compensation technology is required to reduce the process skew of V TH ; M 7 ~M 11 are the core transistors of the voltage reference source sub-circuit 1220, and process compensation technology is also required to reduce V THProcess skew. By appropriately adjusting the number of current transistors connected in parallel in the current reference core transistor, a current I that is substantially independent of temperature is generated. REF , and I is mirrored to the voltage reference source sub-circuit through a current mirror REF to provide a bias current for the voltage reference source sub-circuit. The bias current I BIAS = 3 / 10I REF . A PTAT current I is generated through the current output sub-circuit PTAT , and 3 / 10I is mirrored through a current mirror REF to obtain I ZERO . These two are used as the input currents of the segmented compensation circuit to generate two paths of temperature compensation currents (I COMP1 , I COMP2 ) to correct the temperature curve of the reference current. Finally, the output of the integrated current / voltage reference source is I OUT and V REF .

[0129] Figure 13 Schematically shows a simulation diagram of the temperature curves of the reference current and reference voltage output by the integrated current and voltage reference source circuit with process compensation according to an embodiment of the present disclosure.

[0130] As Figure 13 shown, through simulation verification, the temperature curve of the current output by the current reference source sub-circuit is as shown in Figure 13 a, and the temperature curve of the voltage output by the voltage reference source sub-circuit is as shown in Figure 13 b. It can be seen from the figure that the temperature coefficient of V REF is 1.3 ppm / °C. Before segmented correction, the temperature coefficient of the output I REF of the current reference source is 24.1 ppm / °C; after segmented curvature correction, the temperature coefficient of the output I OUT of the current reference source is 4.9 ppm / °C.

[0131] According to an embodiment of the present disclosure, the integrated current and voltage reference source circuit with process compensation provided by the embodiment of the present disclosure integrates the current reference source and the voltage reference source, uses the temperature curve characteristic of the reference current to perform temperature compensation on the reference voltage, and further reduces the temperature coefficient of the reference current by using the segmented curvature temperature compensation sub-circuit. With process compensation technology, the process influence of the threshold voltage in the current reference source and the voltage reference source is reduced, effectively improving the output process accuracy of the voltage reference source. At the same time, this reference source structure that generates the reference current and the reference voltage simultaneously (first generates the current reference source, and the current reference source then acts as the bias of the voltage reference source) saves power consumption.

[0132] The integrated current and voltage reference source circuit with process compensation of the present disclosure is implemented based on the CMOS process and can operate normally within the temperature range of -40~125°C. The current reference source sub-circuit serves as the bias circuit of the voltage reference source sub-circuit, which can not only reduce the consumed current but also lower the temperature coefficient of the voltage reference source sub-circuit. The temperature coefficient of the reference current can be reduced through the temperature compensation sub-circuit with segmented curvature, and the process accuracy of the voltage reference source sub-circuit can be improved through the process compensation technology. Compared with other integrated current / voltage references, ultimately, a reference current with a lower temperature coefficient, a reference voltage with a lower temperature coefficient, and a reference voltage with a higher process accuracy are achieved.

[0133] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art can understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0134] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. An integrated current and voltage reference source circuit with process compensation, comprising: A current reference source subcircuit, comprising at least one current transistor group, each of the current transistor groups comprising a plurality of current transistors connected in parallel, configured to output a reference current according to the number of the current transistors connected in parallel in each of the current transistor groups and the size of the current transistors; a voltage reference source subcircuit connected to the current reference source subcircuit, the voltage reference source subcircuit comprising at least one voltage transistor group, each of the voltage transistor groups comprising a plurality of voltage transistors connected in parallel, configured to obtain an input current of the voltage reference source subcircuit according to the reference current, and output a reference voltage according to the input current and the number of the voltage transistors connected in parallel in each of the voltage transistor groups and the size of the voltage transistors; The temperature compensation subcircuit is connected to the output end of the current reference source subcircuit and is configured to output a compensation current, wherein the compensation current is used to reduce the temperature coefficient of the reference current.

2. The circuit according to claim 1, wherein The current reference source subcircuit is configured to: in a first temperature range, output the reference current that decreases as the temperature increases; in a second temperature range, output the reference current that increases as the temperature increases; The voltage reference source subcircuit is configured to: in the first temperature range, output the reference voltage that increases with increasing temperature; in the second temperature range, output the reference voltage that decreases with increasing temperature; The temperature compensation subcircuit is configured to: in the first temperature range, output the compensation current that decreases as the temperature increases; in the second temperature range, output the compensation current that increases as the temperature increases; The temperature in the first temperature range is lower than the temperature in the second temperature range.

3. The circuit according to claim 2, further comprising: a current output subcircuit configured to output a current proportional to absolute temperature; The temperature compensation subcircuit is configured to output the compensation current according to the reference current and the current proportional to absolute temperature, so as to reduce the temperature coefficient of the reference current.

4. The circuit according to claim 3, wherein: The temperature compensation subcircuit comprises: A first current mirror circuit configured to output a zero temperature coefficient current according to the reference current; a temperature-triggered control subcircuit configured to adjust the magnitude of the zero temperature coefficient current; The slope adjustment subcircuit is configured to adjust the magnitude of the compensation current according to the zero temperature coefficient current after the magnitude adjustment and the current proportional to the absolute temperature.

5. The circuit according to claim 4, wherein: The first current mirror circuit includes a first current mirror transistor group, a second current mirror transistor group, a third current mirror transistor group and a fourth current mirror transistor group; The temperature-triggered control subcircuit comprises a first temperature-triggered transistor group and a second temperature-triggered transistor group, wherein the temperature-triggered control subcircuit adjusts the magnitude of the zero temperature coefficient current by controlling the width-to-length ratio between the first temperature-triggered transistor group and the second temperature-triggered transistor group; The slope adjustment subcircuit includes a first slope adjustment transistor group and a second slope adjustment transistor group, wherein the slope adjustment subcircuit adjusts the magnitude of the compensation current by controlling the width-to-length ratio of the first slope adjustment transistor group and the second slope adjustment transistor group.

6. The circuit according to claim 5, wherein: The source of the first current mirror transistor group is connected to the power supply voltage, the drain of the first current mirror transistor group is connected to the drain of the first temperature-triggered transistor group, the source of the second current mirror transistor group is connected to the power supply voltage, the drain of the second current mirror transistor group is connected to the drain of the second temperature-triggered transistor group and the drain of the third current mirror transistor group, the source of the third current mirror transistor group is connected to the power supply voltage, the gate of the third current mirror transistor group is connected to the gate of the fourth current mirror transistor group, the source of the fourth current mirror transistor group is connected to the power supply voltage, and the drain of the fourth current mirror transistor group is connected to the drain of the first slope adjustment transistor group; The gate of the first temperature-triggered transistor group is connected to the gate of the second temperature-triggered transistor group, and the source of the first temperature-triggered transistor group and the source of the second temperature-triggered transistor group are grounded; the gate of the first slope-adjusting transistor group is connected to the gate of the second slope-adjusting transistor group, and the source of the first slope-adjusting transistor group and the source of the second slope-adjusting transistor group are grounded.

7. The circuit according to any one of claims 1 to 6, wherein: The multiple current transistor groups include a first current transistor group, a second current transistor group, a third current transistor group, a fourth current transistor group, a fifth current transistor group and a sixth current transistor group. The first current transistor group is arranged in the first branch of the current reference source sub-circuit, the second current transistor group and the third current transistor group are arranged in the second branch of the current reference source sub-circuit, the fourth current transistor group is arranged in the third branch of the current reference source sub-circuit, and the fifth current transistor group and the sixth current transistor group are arranged in the fourth branch of the current reference source sub-circuit.

8. The circuit according to claim 7, wherein: The drain of the first current transistor group is connected to the first branch of the current reference source sub-circuit, the gate of the first current transistor group is connected to the gate of the second current transistor group, the source of the first current transistor group is connected to the source of the third current transistor group and the source of the sixth current transistor group, the drain of the second current transistor group is connected to the second branch of the current reference source sub-circuit, the source of the second current transistor group is connected to the drain of the third current transistor group, the gate of the third current transistor group is connected to the gate and drain of the fourth current transistor group, the drain of the fourth current transistor group is connected to the third branch of the current reference source sub-circuit, the source of the fourth current transistor group is connected to the source of the fifth current transistor group and the drain of the sixth current transistor group, the drain of the fifth current transistor group is connected to the fourth branch of the current reference source sub-circuit, and the gate of the fifth current transistor group is connected to the gate of the sixth current transistor group.

9. The circuit according to any one of claims 1 to 6, wherein: The multiple voltage transistor groups include a seventh voltage transistor group, an eighth voltage transistor group, a ninth voltage transistor group, a tenth voltage transistor group and an eleventh voltage transistor group, the seventh voltage transistor group and the ninth voltage transistor group are arranged in the first branch of the voltage reference source sub-circuit, the eighth voltage transistor group and the tenth voltage transistor group are arranged in the second branch of the voltage reference source sub-circuit, and the eleventh voltage transistor group is arranged in the third branch of the voltage reference source sub-circuit.

10. The circuit according to claim 9, wherein: The drain of the seventh voltage transistor group is connected to the first branch of the voltage reference source sub-circuit, the gate of the seventh voltage transistor group is connected to the gate of the ninth voltage transistor group, the source of the seventh voltage transistor group is connected to the drain of the ninth voltage transistor group, the source of the ninth voltage transistor group is grounded, the drain of the eighth voltage transistor group is connected to the second branch of the voltage reference source sub-circuit, the gate of the eighth voltage transistor group is connected to the gate of the tenth voltage transistor group, the source of the eighth voltage transistor group is connected to the drain of the tenth voltage transistor group, the source of the tenth voltage transistor group is connected to the source of the seventh voltage transistor group, the drain of the eleventh voltage transistor group is connected to the third branch of the voltage reference source sub-circuit, the source of the eleventh voltage transistor group is connected to the source of the eighth voltage transistor group, and the gate of the eleventh voltage transistor group is connected to the drain of the eleventh voltage transistor group.

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