Method for adjusting power consumption of chip and related device

Abstract

The invention provides a method for adjusting chip power consumption and a related device, and the method comprises the steps: increasing the array read-write duration of a first cell based on the data input / output duration of the first cell when the current value of the chip is greater than a first current threshold value in the process of carrying out read-write operation on the first cell of a first data channel in the chip; and the current value in the chip is reduced. By monitoring the chip current value in the read-write operation process of each cell in each data channel in real time, the array read-write duration of the cell can be adjusted in real time according to the data input / output duration of the corresponding cell, real-time adjustment of power consumption is achieved, and the purpose of reducing power consumption is achieved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular, to a method for adjusting chip power consumption and related devices. Background Art

[0002] In the prior art, power consumption is one of the main indicators for evaluating products such as mobile terminals and large storage devices. Taking the NAND Flash memory chip as an example, NAND Flash manufacturers have developed a peak power management (PPM) function based on NAND itself to meet the requirements of peak power consumption. The PPM function uses the NAND internal control logic designed by the manufacturer. In the concurrent scenario of multiple cells (represented by Dies) in any data channel, by staggering the peak currents of each cell through communication between cells, the peak power consumption is reduced to meet the application requirements. However, this is only a simple peak staggering, without real-time current feedback, and can only achieve adjustment at the software package level. In various different configuration parameter cases for different application scenarios, using this method will cause deterioration of read and write performance to a certain extent.

[0003] In addition, based on the NAND Die limit concurrency technology of the manufacturer's firmware (FW), through the cooperation of the controller in the NAND Flash and the FW software, the number of NAND Dies in progress at any moment can be directly limited. However, only when the number of Dies in progress is less than the allowed concurrent Die number, will a new Die be activated for business operations to reduce the peak power consumption. In the scenario of sequential reading and writing, the reduction of the NAND Die concurrency number will directly reduce the bandwidth performance in proportion. Summary of the Invention

[0004] Embodiments of this application provide a method for adjusting chip power consumption and related devices, which can adjust the power consumption of the chip in real time.

[0005] In a first aspect, this application provides a method for adjusting chip power consumption, the method includes: during the process of reading and writing the first cell of the first data channel in the chip, when the current value of the chip is greater than the first current threshold, the chip increases the array read / write duration of the first cell based on the data input / output duration of the first cell, so that the current value in the chip decreases; wherein, the first data channel is any one of the data channels in the chip, and the first cell is any one of the cells in the first data channel.

[0006] Compared with the prior art, the present application monitors the chip current value during the read and write operations of each cell in each data channel in real time, so as to adjust the array read and write duration of the cell in real time according to the data input / output duration of the corresponding cell, realize real-time adjustment of power consumption, and achieve the purpose of reducing power consumption.

[0007] In a possible embodiment of the present application, when the current value of the chip is greater than the first current threshold during the normal read stage or the normal program stage of the read and write operation, the value of the increased array read and write duration is less than or equal to n - 1 times the data input / output duration, where n is a positive integer and n is determined according to the number of cells in the first data channel.

[0008] The present application monitors the current value of the chip in real time during the normal read stage or the normal program stage of the read and write operation, and when the current value of the chip is greater than the first current threshold, the array read and write duration can be adjusted in time to achieve the purpose of reducing the chip current value. Since the data input / output duration remains unchanged, the performance of the chip will not decline. Then, the space saved by reducing the chip current value can further increase the cell concurrency, thereby improving the performance of the chip.

[0009] In a possible embodiment of the present application, when the current value of the chip is greater than the first current threshold and less than or equal to the second current threshold during the normal read stage or the normal program stage of the read and write operation, the value of the increased array read and write duration is less than or equal to the first duration; where the first duration is the difference between n - 1 times the data input / output duration and the second duration, and the second duration is the first target multiple of the current difference between the second current threshold and the first current threshold; n is a positive integer and n is determined according to the number of cells in the first data channel; the second current threshold is greater than the first current threshold.

[0010] The present application monitors the current value of the chip in real time during the normal read stage or the normal program stage of the read and write operation, and when the current value of the chip is greater than the first current threshold and less than or equal to the second current threshold, the array read and write duration can be adjusted in time to achieve the purpose of reducing the chip current value. Since the data input / output duration remains unchanged, the performance of the chip will not decline. Then, the space saved by reducing the chip current value can further increase the cell concurrency, thereby improving the performance of the chip. In addition, by further comparing the current value of the chip with the second current threshold, the chip can adapt to more application scenarios. At the same time, the chip can also be in a suitable operation mode to achieve the purpose of reducing the chip power consumption.

[0011] In a possible embodiment of the present application, when the current value of the chip is greater than the first current threshold during the cache reading stage or the cache programming stage of the read-write operation, the array read-write duration increases and then takes a value less than or equal to n times the data input / output duration, where n is a positive integer and n is determined according to the number of cells in the first data channel.

[0012] In the present application, by monitoring the current value of the chip in real time during the cache reading stage or the cache programming stage of the read-write operation, and when the current value of the chip is greater than the first current threshold, the array read-write duration can be adjusted in a timely manner to achieve the purpose of reducing the current value of the chip. Since the data input / output duration remains unchanged, the performance of the chip will not decline. Then, the space saved by reducing the current value of the chip can further increase the cell concurrency, thereby improving the performance of the chip.

[0013] In a possible embodiment of the present application, when the current value of the chip is greater than the first current threshold and less than or equal to the third current threshold during the cache reading stage or the cache programming stage of the read-write operation, the value of the array read-write duration after increasing is less than or equal to the third duration; where the third duration is the difference between n times the data input / output duration and the fourth duration, and the fourth duration is the second target multiple of the current difference between the third current threshold and the first current threshold; n is a positive integer and n is determined according to the number of cells in the first data channel, and the third current threshold is greater than the first current threshold.

[0014] In the present application, by monitoring the current value of the chip in real time during the cache reading stage or the cache programming stage of the read-write operation, and when the current value of the chip is greater than the first current threshold and less than or equal to the third current threshold, the array read-write duration can be adjusted in a timely manner to achieve the purpose of reducing the current value of the chip. Since the data input / output duration remains unchanged, the performance of the chip will not decline. Then, the space saved by reducing the current value of the chip can further increase the cell concurrency, thereby improving the performance of the chip. In addition, by further comparing the current value of the chip with the third current threshold, the chip can adapt to more application scenarios. At the same time, the chip can also be in a suitable operation mode to achieve the purpose of reducing the chip power consumption.

[0015] In a possible embodiment of the present application, during the process of performing read-write operations on the first cell in the first data channel of the chip, when the current value of the chip is less than the first current threshold, the array read-write duration of the first cell is reduced, so that the current value in the chip increases.

[0016] In the present application, during the read and write operations, the current value of the chip is monitored in real time. When the current value of the chip is less than the first current threshold, the read and write duration of the array can be adjusted in a timely manner to achieve the purpose of improving the energy efficiency ratio of the chip.

[0017] In a possible embodiment of the present application, when the current value of the chip is less than the first current threshold and greater than the fourth current threshold, the reduction ratio of the read and write duration of the array is determined according to the difference between the first current threshold and the fourth current threshold; wherein, the fourth current threshold is less than the first current threshold.

[0018] In the present application, during the read and write operations, the current value of the chip is monitored in real time. When the current value of the chip is less than the first current threshold and greater than the fourth current threshold, the read and write duration of the array can be adjusted in a timely manner to achieve the purpose of improving the energy efficiency ratio of the chip. Additionally, by further comparing the current value of the chip with the fourth current threshold, the chip can adapt to more application scenarios. At the same time, the chip can also be in a suitable operation mode to achieve the purpose of improving the energy efficiency ratio.

[0019] In a second aspect, the present application provides a power consumption adjustment device applied to a chip. The device includes: a storage unit and a duration adjustment unit; the storage unit is used for storing data; the duration adjustment unit is used for monitoring the current value of the chip in real time during the process of reading and writing the first cell of the first data channel in the storage unit; when the current value of the chip is greater than the first current threshold, based on the data input / output duration of the first cell, increasing the read and write duration of the array of the first cell to reduce the current value in the chip; wherein, the first data channel is any one of the data channels in the storage unit, and the first cell is any one of the cells in the first data channel.

[0020] In a possible embodiment of the present application, when, during the normal read stage or the normal program stage of the read and write operation, the current value of the chip is greater than the first current threshold, the value after the increase of the read and write duration of the array is less than or equal to n - 1 times the data input / output duration, where n is a positive integer and n is determined according to the number of cells in the first data channel.

[0021] In a possible embodiment of the present application, when, during the normal read phase or normal programming phase of the read / write operation, the current value of the chip is greater than the first current threshold and less than or equal to the second current threshold, the value of the array read / write duration after increase is less than or equal to the first duration; wherein, the first duration is the difference between n - 1 times the data input / output duration and the second duration, the second duration is the first target multiple of the current difference between the second current threshold and the first current threshold; n is a positive integer and n is determined according to the number of cells in the first data channel; the second current threshold is greater than the first current threshold.

[0022] In a possible embodiment of the present application, when, during the cache read phase or cache programming phase of the read / write operation, the current value of the chip is greater than the first current threshold, the value of the array read / write duration after increase is less than or equal to n times the data input / output duration, where n is a positive integer and n is determined according to the number of cells in the first data channel.

[0023] In a possible embodiment of the present application, when, during the cache read phase or cache programming phase of the read / write operation, the current value of the chip is greater than the first current threshold and less than or equal to the third current threshold, the value of the array read / write duration after increase is less than or equal to the third duration; wherein, the third duration is the difference between n times the data input / output duration and the fourth duration, the fourth duration is the second target multiple of the current difference between the third current threshold and the first current threshold; n is a positive integer and n is determined according to the number of cells in the first data channel, and the third current threshold is greater than the first current threshold.

[0024] In a possible embodiment of the present application, the duration adjustment unit is further configured to, during the process of performing a read / write operation on the first cell of the first data channel in the storage unit, when the current value of the chip is less than the first current threshold, reduce the array read / write duration of the first cell, so as to increase the current value in the chip.

[0025] In a possible embodiment of the present application, the duration adjustment unit is further configured to: when the current value of the chip is less than the first current threshold and greater than the fourth current threshold, the reduction ratio of the array read / write duration is determined according to the difference between the first current threshold and the fourth current threshold; wherein, the fourth current threshold is less than the first current threshold.

[0026] In a possible embodiment of the present application, the device further includes: a control unit; the control unit is connected to the duration adjustment unit; the control unit is configured to generate a first adjustment instruction and send the first adjustment instruction to the duration adjustment unit when the current value of the chip is greater than the first current threshold during the process of reading and writing the first cell in the first data channel of the chip; wherein, the first adjustment instruction indicates to increase the array read / write duration of the first cell based on the data input / output duration of the first cell; the duration adjustment unit is configured to increase the array read / write duration of the first cell based on the first adjustment instruction after receiving the first adjustment instruction.

[0027] Through the interaction between the control unit and the duration adjustment unit in the power consumption adjustment device of the present application, the current value of the chip is reduced, and the cell concurrency is increased, thereby improving the performance of the chip.

[0028] In a possible embodiment of the present application, the control unit is further configured to generate a second adjustment instruction and send the second adjustment instruction to the duration adjustment unit when the current value of the chip is less than the first current threshold; wherein, the second adjustment instruction indicates to reduce the array read / write duration of the first cell; the duration adjustment unit is further configured to reduce the array read / write duration of the first cell based on the second adjustment instruction after receiving the second adjustment instruction.

[0029] Through the interaction between the control unit and the duration adjustment unit in the power consumption adjustment device of the present application, the purpose of improving the energy efficiency ratio of the chip is achieved.

[0030] In a third aspect, the present application provides a chip, which includes: a storage area and a controller; the storage area is used to store data, and the controller is used to execute the method provided in any one of the above first aspects or any possible implementation manner in the first aspect.

[0031] In a fourth aspect, the present application provides a storage device, which includes: a circuit board and the chip provided in the above third aspect, and the chip is disposed on the circuit board. Description of the Drawings

[0032] Figure 1a A schematic diagram for adjusting the power consumption of a chip provided by the prior art;

[0033] Figure 1b A schematic diagram for adjusting the power consumption of a chip provided by the prior art;

[0034] Figure 2 A schematic flowchart of a method for adjusting the power consumption of a chip provided by an embodiment of the present application;

[0035] Figure 3Schematic diagram of current change in chip read operation provided by an embodiment of the present application;

[0036] Figure 4 Schematic diagram of adjusting chip power consumption in the normal read stage / normal program stage of the read operation provided by an embodiment of the present application;

[0037] Figure 5 Schematic diagram of adjusting chip power consumption in the cache read stage / cache program stage of the read operation provided by an embodiment of the present application;

[0038] Figure 6 Schematic diagram of adjusting chip power consumption in the read operation stage provided by an embodiment of the present application;

[0039] Figure 7 Schematic diagram of a method flow for adjusting chip power consumption provided by an embodiment of the present application;

[0040] Figure 8 Schematic diagram of a method flow for adjusting chip power consumption provided by an embodiment of the present application;

[0041] Figure 9 Schematic diagram of a power consumption adjustment device flow provided by an embodiment of the present application. Detailed implementation manners

[0042] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

[0043] In various embodiments of the present application, if there is no special description and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be mutually referred to, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0044] In the present application, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural.

[0045] It can be understood that in the embodiments of the present application, the various numerical numbers involved are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. The magnitude of the serial numbers of the above processes does not mean the sequence of execution, and the execution sequence of each process should be determined according to its function and internal logic.

[0046] Hereinafter, some terms in the embodiments of the present application will be explained to facilitate the understanding of those skilled in the art.

[0047] (1) The data channel of a chip refers to the physical path inside the chip for data transmission, usually composed of wires, transistors, etc. The data channel is used to transmit data. The wider the data channel, the faster the data transmission speed. Multiple data channel transmission methods can be adopted to improve the performance of the chip channels.

[0048] (2) A cell, which can be represented by Die, refers to the die of the chip before packaging, containing a complete functional unit or a group of related functional units of the chip. Each data channel of the chip can include multiple cells.

[0049] (3) Direct memory access (DMA) operation, that is, a working mode in which data input / output exchange is completely executed by hardware. In this mode, data exchange does not go through the central processing unit (CPU) and is directly carried out between the memory and the device. The DMA operation can include three main steps: the preprocessing stage before data transfer, the formal data transfer stage, and the post-processing stage after data transfer.

[0050] (4) An array Array is an ordered sequence of elements, used to store a collection of multiple data of the same type. Naming the collection of a finite number of variables of the same type is the array name. In programming, for the convenience of processing, an array is a form that organizes several elements of the same type in an ordered manner. This collection of ordered and homogeneous data elements is called an array.

[0051] In the prior art, a large number of universal flash storage (UFS), solid-state drives (SSD), etc. are widely used in mobile terminals and large storage devices. Power consumption is one of the main indicators for evaluating products such as mobile terminals and large storage devices. Taking the NAND Flash memory chip as an example, to ensure the availability of NAND Flash, in the system environment where NAND Flash is applied, the current value of NAND Flash needs to be within the power supply capacity range of the power management unit (PMU) of the system environment. At the same time, a higher energy efficiency ratio and lower power consumption will enable NAND Flash to have a longer battery life or lower electricity costs.

[0052] NAND Flash manufacturers have developed the PPM function based on NAND itself to meet the requirements of peak power consumption. As Figure 1a shown, the PPM function uses the NAND internal control logic designed by the manufacturer. In the case of multiple Die concurrency in any data channel, through the communication between Dies to stagger their respective peak currents, that is,Figure 1a The peak current I of Die x and Die y cc There is a certain time delay, thereby achieving a reduction in peak power consumption to meet the application requirements. However, this is only a simple peak shifting, without real-time current feedback and can only achieve regulation at the software package level. In the case of various different configuration parameters for different application scenarios, using this method will deteriorate the read and write performance to a certain extent.

[0053] In addition, for the NAND Die limit concurrency technology based on the manufacturer's firmware (FW), through the controller in the flash chip cooperating with the FW software, the number of NAND Dies in progress at any moment can be directly restricted. However, only when the number of Dies in business is less than the allowable concurrent Die number, will a new Die be activated for business operations to achieve a reduction in peak power consumption. As Figure 1b shown, in the scenario of sequential read and write in order, the DMA operations of Die-0, Die-1, Die-2, and Die-3 can be carried out synchronously. However, it is necessary to perform array read and write operations on Die-0 and Die-1 respectively first, and then perform array read and write operations on Die-2 and Die-3 respectively. Here, the reduction of the NAND Die concurrency number will directly reduce the bandwidth performance in proportion.

[0054] The controller of the storage product generally has multiple data channels, and each data channel mounts multiple NAND Dies to increase the system capacity. At the same time, through multi-Die concurrent operations, the system read and write bandwidth performance is improved. Taking the NAND chip as an example, in the scenario of heavy-load sequential read and write of the chip, when multiple Dies in a single channel perform pipelining operations, the delay of the NAND array read and write duration can be buried within the DMA operation time, that is, the delay of the NAND array read and write duration can be buried within the data IO transmission operation time. However, this is prone to the problem of high chip power consumption.

[0055] As Figure 2 shown, the present application provides a method for adjusting the power consumption of a chip, and the method includes:

[0056] S201, the chip performs a read operation on the first cell of the first data channel;

[0057] S202, when the current value of the chip is greater than the first current threshold, the chip increases the array read and write duration of the first cell based on the data input / output duration of the first cell, so that the current value in the chip decreases.

[0058] Here, the first data channel is any one of the data channels in the chip, and the first cell is any one of the cells in the first data channel.

[0059] Exemplarily, taking a NAND chip as an example, the NAND chip can be equivalent to a large capacitor network. It can be seen from Equation (1) below that the current I(t) in the NAND chip is proportional to the voltage change rate dU(t) / dt in the NAND chip within the target time. The slower the voltage change in the NAND chip, the smaller the current in the NAND chip. Therefore, by adjusting the time, the magnitude of the current in the NAND chip can be adjusted.

[0060] I(t) = dq(t) / dt = C * dU(t) / dt Equation (1)

[0061] Where t represents time, q(t) represents power, and C is a positive integer.

[0062] As Figure 3 shown, the read operation of the chip includes a pre-charge stage, a sensing stage, and a discharge stage. When the peak current of the chip appears in the pre-charge stage, by slowing down the boost speed and increasing the duration of the pre-charge stage, the peak current of the chip can be reduced, thereby reducing the power consumption of the chip.

[0063] In a possible embodiment of the present application, when the current value of the chip is greater than the first current threshold during the normal read or normal program stage of the read operation, the value of the array read / write duration after increase is less than or equal to n - 1 times the data input / output duration, where n is a positive integer and n is determined according to the number of cells in the first data channel. For example, for the topology of n Dies in the first data channel CH1, by satisfying the condition t_array ≤ (n - 1) * t_DMA, the purpose of reducing the current value in the chip is achieved. Here, the array read / write duration is represented by t_array, and the data input / output duration is represented by t_DMA.

[0064] Furthermore, as Figure 4 shown, during the normal read or normal program stage of the read operation in a large bandwidth scenario, the DMA operation can be performed simultaneously with the Array operation. Assume that the chip includes four channels CH0, CH1, CH2, CH3, and each channel includes 2 Dies, that is, CH0 includes Die 0 and Die 1, CH1 includes Die 2 and Die 3, CH2 includes Die 4 and Die 5, and CH3 includes Die 6 and Die 7. When the current value of the chip is greater than the first current threshold, by increasing t_array, the current value of the chip is reduced, that is, from Figure 4 (a) to Figure 4 (b) and then to Figure 4It can be seen from (c) that the t_array of each Die in each channel is gradually increasing. At the same time, the t_DMA in each channel remains unchanged. The current space saved by increasing the t_array can be further used to increase the concurrency of the Dies, thereby improving the performance of the chip.

[0065] Optionally, when the current value of the chip is greater than the first current threshold and less than or equal to the second current threshold during the normal read phase or the normal program phase of the read operation, the value of the t_array after the increase is less than or equal to the first duration. Wherein, the first duration is the difference between n - 1 times of the t_DMA and the second duration, the second duration is the first target multiple of the current difference between the second current threshold and the first current threshold, the second current threshold is greater than the first current threshold, n is a positive integer, and n is determined according to the number of cells in the first data channel. For example, if the first current threshold is Icc_peak and the array read / write duration corresponding to the first current threshold is t_array, then the second current threshold is Icc_peak + Δ I1 When it is, the increased array read / write duration can be t_array - Δ t1 , where Δ t1 and Δ I1 have a mapping relationship. For example, Δ t1 = K * Δ I1 , and K is the first target multiple. Here, the value of the first target multiple K can be determined according to the historical change experience data between the current and time. Optionally, K can be 0.4 or 1, and the specific value of K is not limited here.

[0066] Similarly, when the second current threshold is Icc_peak + Δ I2 the increased array read / write duration can be t_array - Δ t2 , where Δ t2 and Δ I2 also have a mapping relationship. For example, Δ t2 = K' * Δ I2 , and K' can also be the first target multiple. Here, the value of the first target multiple K' can be determined according to the historical change experience data between the current and time. Optionally, K' can be 0.5 or 2, and the specific value of K' is not limited here. It should be noted that the configuration values of the internal registers of the chip corresponding to different current threshold situations and different array read / write durations are also different, as shown in Table 1 below:

[0067] Table 1

[0068] Internal register configuration value of the chip Array read / write duration Current threshold a1 t_array Icc_peak a2 <![CDATA[t_array-Δ t1 > <![CDATA[Icc_peak+Δ I1 > a3 <![CDATA[t_array-Δ t2 > <![CDATA[Icc_peak+Δ I2 > … … …

[0069] In a possible embodiment of the present application, when the current value of the chip is greater than the first current threshold value in the cache read (Cache Read) phase or the cache program (Cache Program) phase of the read operation, t_array increases to a value less than or equal to n times t_DMA, where n is a positive integer and n is determined according to the number of cells in the first data channel. For example, for the topology of n Dies of the first data channel CH1, the purpose of reducing the current value in the chip is achieved by satisfying the condition of t_array≤n*t_DMA.

[0070] Further, such as Figure 5 As shown in the figure, in the cache read phase or cache program phase of the read operation in the large bandwidth scenario, the DMA operation is not performed simultaneously with the Array operation. Assume that the chip includes four channels CH0, CH1, CH2, and CH3, and each channel includes 2 Dies, that is, CH0 includes Die 0 and Die 1, CH1 includes Die 2 and Die 3, CH2 includes Die 4 and Die 5, and CH3 includes Die 6 and Die 7. When the current value of the chip is greater than the first current threshold, the current value of the chip is reduced by increasing t_array, that is, by Figure 5 (a) to Figure 5 (b) It can be seen that the t_array of each Die in each channel is gradually increasing.

[0071] Optionally, when the current value of the chip is greater than the first current threshold and less than or equal to the third current threshold in the cache read phase or the cache program phase of the read operation, the value of t_array after the increase is less than or equal to the third duration. The third duration is the difference between n times t_DMA and the fourth duration, and the fourth duration is the second target multiple of the current difference between the third current threshold and the first current threshold; the third current threshold is greater than the first current threshold, n is a positive integer, and n is determined according to the number of cells in the first data channel. For example, the first current threshold is Icc_peak, and the array read and write duration corresponding to the first current threshold is t_array, then the third current threshold is Icc_peak+Δ' I1 When the increased array read and write time is t_array-Δ' t1 , where Δ' t1 With Δ' I1 There is a mapping relationship, for example, Δ' t1 =K1*Δ' I1 , K1 is the second target multiple. Here, the value of the second target multiple K1 can be determined according to the historical current and time variation empirical data. Optionally, K1 can be 0.4 or 1, and the specific value of K1 is not limited here.

[0072] Similarly, the third current threshold is Icc_peak + Δ' I2 When it is I2 , the increased array read / write duration can be t_array - Δ' t2 , where Δ' t2 and Δ' I2 also have a mapping relationship. For example, Δ' t2 = K1' * Δ' I2 , and K1' can also be the second target multiple. Here, the value of the second target multiple K1' can be determined according to the historical change empirical data between current and time. Optionally, K1' can be 0.5 or 2, and the specific value of K1' is not limited here. It should be known that the chip internal register configuration values corresponding to different current threshold situations and different array read / write durations can also be different, as shown in Table 2 below:

[0073] Table 2

[0074] Internal register configuration value of the chip Array read / write duration Current threshold a1 t_array Icc_peak a2 <![CDATA[t_array-Δ’ t1 > <![CDATA[Icc_peak+Δ’ I1 > a3 <![CDATA[t_array-Δ’ t2 > <![CDATA[Icc_peak+Δ’ I2 > … … …

[0075] In the case of the chip in the light load sequential read / write scenario, it is difficult for multiple Dies in a single channel to perform continuous pipelining operations, and the magnitude of the current value of the chip in this scenario will not affect the chip. Considering the chip performance and energy efficiency ratio, the smaller t_array of NAND is, the better.

[0076] In a possible embodiment of the present application, during the process of reading the first cell in the first data channel of the chip, when the current value of the chip is less than the first current threshold, the array read / write duration of the first cell is reduced, so that the current value in the chip increases. As Figure 6 shown, the DMA operation can be performed simultaneously with the Array operation. Assume that the chip includes four channels CH0, CH1, CH2, CH3, and each channel includes 2 Dies, that is, CH0 includes Die 0 and Die 1, CH1 includes Die 2 and Die 3, CH2 includes Die 4 and Die 5, and CH3 includes Die 6 and Die 7. When the current value of the chip is less than the first current threshold, by reducing t_array, the current value of the chip is increased, that is, from Figure 6 (a) to Figure 6 (b) and then to Figure 6 (c), it can be seen that the t_array of each Die in each channel is gradually decreasing.

[0077] Exemplarily, the average power consumption of the peak current of the chip = the number of data pages (page) processed per second * the energy consumption consumed by one page operation. The energy efficiency ratio = page size / [Vcc * (Icc_array * t_array + Icc_DMA * t_DMA)], that is, the energy efficiency ratio = bandwidth / average power consumption, and the energy efficiency ratio characterizes the amount of data that can be processed per unit of energy. Among them, page size represents the bandwidth of the chip at the current moment, Vcc represents the voltage value provided by the power supply connected to the chip, Icc_array represents the current value of the chip under array operation, and Icc_DMA represents the current value of the chip under DMA operation. When reducing t_array, the average value of Icc_array may increase slightly, but the overall energy efficiency ratio is still improved.

[0078] Furthermore, when the current value of the chip is less than the first current threshold and greater than the fourth current threshold, the reduction ratio of the array read / write duration is determined according to the difference between the first current threshold and the fourth current threshold, and the fourth current threshold is less than the first current threshold. For example, the first current threshold is Icc_peak, and the array read / write duration corresponding to the first current threshold is t_array, then the fourth current threshold is Icc_peak - Δ” I1 At this time, the reduced array read / write duration can be t_array + Δ” t1 , where Δ” t1 has a mapping relationship with Δ” I1 , for example, Δ” t1 = K2 * Δ” I1 , and K2 is the third target multiple. Here, the value of the third target multiple K2 can be determined according to the historical change empirical data between current and time. Optionally, K2 can be 0.4 or 1, and the specific value of K2 is not limited here.

[0079] Similarly, when the fourth current threshold is Icc_peak - Δ” I2 , the reduced array read / write duration can be t_array - Δ” t2 , where Δ” t2 also has a mapping relationship with Δ” I2 , for example, Δ” t2 = K2’ * Δ” I2, K2' can also be the third target multiple. Here, the value of the third target multiple K2' can be determined according to the historical change experience data between the current and time. Optionally, K2' can be 0.5 or 2, and the specific value of K2' is not limited here. It should be known that the chip internal register configuration values corresponding to different current threshold situations and different array read / write durations are also different, as shown in Table 3 below. By reducing t_array, the energy consumption of a single page operation is reduced, and thus the energy efficiency ratio can be improved.

[0080] Table 3

[0081] Internal register configuration value of the chip Array read / write duration Current threshold a1 t_array Icc_peak a2 <![CDATA[t_array+Δ” t1 > <![CDATA[Icc_peak-Δ” I1 > a3 <![CDATA[t_array+Δ” t2 > <![CDATA[Icc_peak-Δ” I2 > … … …

[0082] In a possible embodiment of the present application, a power consumption adjustment device can also be provided, which is applied to a chip. The power consumption adjustment device can include a control unit and a duration adjustment unit, and the control unit and the duration adjustment unit are connected. As Figure 7 shown, the specific execution process of the power consumption adjustment device for adjusting the chip power consumption includes:

[0083] S701, during the process of the control unit reading the first cell of the first data channel in the chip, the control unit monitors the current value Icc of the chip in real time;

[0084] S702, the control unit determines whether Icc is greater than the first current threshold; if so, execute step S703, if not, execute step S704;

[0085] S703, the control unit sends a first adjustment instruction to the duration adjustment unit, and the duration adjustment unit increases t_array to t_array + Δ based on the first adjustment instruction t ;

[0086] S704, the control unit sends a non-switching operation instruction to the duration adjustment unit, and the duration adjustment unit maintains the original operation mode;

[0087] S705, end.

[0088] Here, the control unit can feedback the first adjustment instruction carrying n-bit to the duration adjustment unit in any one of the following ways:

[0089] Way 1, through the parameter feature set feature, parameter setting set parameter or a specific command in cooperation with the NAND self-service copyright agreement (SCA);

[0090] Way 2, through designing a separate port hardware in the port manner.

[0091] Optionally, in this embodiment, the control unit can also configure the duration adjustment unit to monitor the chip's Icc value in real time through the duration adjustment unit, use the duration adjustment unit to determine whether Icc is greater than the first current threshold, and increase t_array to t_array + Δ when Icc is greater than the first current threshold. t 。

[0092] In a possible embodiment, as Figure 8 shown, the specific execution process of the power consumption adjustment device for adjusting the chip power consumption includes:

[0093] S801. During the process of the control unit reading the first cell of the first data channel in the chip, monitor the chip's Icc value in real time;

[0094] S802. The control unit determines whether Icc is less than the first current threshold; if so, execute step S803, if not, execute step S804;

[0095] S803. The control unit sends a second adjustment instruction to the duration adjustment unit, and the duration adjustment unit reduces t_array to t_array - Δ based on the second adjustment instruction t ;

[0096] S804. The control unit sends a non-switching operation instruction to the duration adjustment unit, and the duration adjustment unit maintains the original operation mode;

[0097] S805. End.

[0098] Here, the control unit can feedback the second adjustment instruction carrying n-bit to the duration adjustment unit in any one of the following ways:

[0099] Method 1: Through set feature, set parameter or a specific command in cooperation with NAND SCA;

[0100] Method 2: Through designing a separate port hardware in the port manner.

[0101] Optionally, in this embodiment, the control unit can also configure the duration adjustment unit to monitor the chip's Icc value in real time through the duration adjustment unit, use the duration adjustment unit to determine whether Icc is less than the first current threshold, and reduce t_array to t_array - Δ when Icc is less than the first current threshold. t 。

[0102] It should be noted that any of the above-described embodiments of the read operation is applicable to the write operation, which will not be elaborated here. The chip described in this application can be a NAND flash wafer or a NAND Flash single-chip package.

[0103] As Figure 9 shown, this application provides a power consumption adjustment device, which includes: a storage unit 901 and a duration adjustment unit 902;

[0104] The storage unit 901 is used to store data;

[0105] The duration adjustment unit 902 is used to monitor the current value of the chip in real time during the read and write operations on the first cell of the first data channel in the storage unit 901; when the current value of the chip is greater than the first current threshold, based on the data input / output duration of the first cell, increase the array read / write duration of the first cell, so that the current value in the chip decreases;

[0106] Wherein, the first data channel is any one of the data channels in the storage unit 901, and the first cell is any one of the cells in the first data channel.

[0107] In a possible embodiment of this application, when the current value of the chip is greater than the first current threshold during the normal read phase or normal program phase of the read and write operation, the value of the array read / write duration after increase is less than or equal to n - 1 times the data input / output duration, where n is a positive integer and n is determined according to the number of cells in the first data channel.

[0108] In a possible embodiment of this application, when the current value of the chip is greater than the first current threshold and less than or equal to the second current threshold during the normal read phase or normal program phase of the read and write operation, the value of the array read / write duration after increase is less than or equal to the first duration; wherein, the first duration is the difference between n - 1 times the data input / output duration and the second duration, and the second duration is the first target multiple of the current difference between the second current threshold and the first current threshold; n is a positive integer and n is determined according to the number of cells in the first data channel; the second current threshold is greater than the first current threshold.

[0109] In a possible embodiment of this application, when the current value of the chip is greater than the first current threshold during the cache read phase or cache program phase of the read and write operation, the value of the array read / write duration after increase is less than or equal to n times the data input / output duration, where n is a positive integer and n is determined according to the number of cells in the first data channel.

[0110] In a possible embodiment of the present application, during the cache reading stage or the cache programming stage of the read / write operation, when the current value of the chip is greater than the first current threshold and less than or equal to the third current threshold, the value of the array read / write duration after the increase is less than or equal to the third duration; wherein, the third duration is the difference between n times the data input / output duration and the fourth duration, and the fourth duration is the second target multiple of the current difference between the third current threshold and the first current threshold; n is a positive integer and is determined according to the number of cells in the first data channel, and the third current threshold is greater than the first current threshold.

[0111] In a possible embodiment of the present application, the duration adjustment unit 902 is further configured to, during the process of performing a read / write operation on the first cell of the first data channel in the storage unit 901, when the current value of the chip is less than the first current threshold, reduce the array read / write duration of the first cell, so as to increase the current value in the chip.

[0112] In a possible embodiment of the present application, the duration adjustment unit 902 is further configured to: when the current value of the chip is less than the first current threshold and greater than the fourth current threshold, the reduction ratio of the array read / write duration is determined according to the difference between the first current threshold and the fourth current threshold; wherein, the fourth current threshold is less than the first current threshold.

[0113] The present application may further provide a chip, including: a storage area and a controller; the storage area is used for storing data, and the controller is used to execute the method for adjusting the chip power consumption in any of the above possible embodiments.

[0114] The present application may further provide a storage device, including: a circuit board and the chip in any of the above possible embodiments, and the chip is disposed on the circuit board.

[0115] It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, there may be other division methods. In the embodiments of the present application, each functional module may be integrated into a processing module, or each module may exist physically alone, or two or more modules may be integrated into one module. The above integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0116] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A method for adjusting the power consumption of a chip, characterized in that, the method includes: During the process of reading and writing the first cell of the first data channel in the chip, when the current value of the chip is greater than the first current threshold, based on the data input / output duration of the first cell, increase the array read / write duration of the first cell, so that the current value in the chip decreases; Wherein, the first data channel is any one of the data channels in the chip, and the first cell is any one of the cells in the first data channel.

2. The method according to claim 1, characterized in that, When in the normal reading stage or normal program stage of the reading and writing operation, the current value of the chip is greater than the first current threshold, the value of the array read / write duration after increase is less than or equal to n-1 times of the data input / output duration, n is a positive integer, and n is determined according to the number of cells in the first data channel.

3. The method according to claim 1 or 2, characterized in that, When in the normal reading stage or normal program stage of the reading and writing operation, the current value of the chip is greater than the first current threshold and less than or equal to the second current threshold, the value of the array read / write duration after increase is less than or equal to the first duration; Wherein, the first duration is the difference between n-1 times of the data input / output duration and the second duration, the second duration is the first target multiple of the current difference between the second current threshold and the first current threshold; n is a positive integer, and n is determined according to the number of cells in the first data channel; the second current threshold is greater than the first current threshold.

4. The method according to any one of claims 1-3, characterized in that, When in the cache reading stage or cache program stage of the reading and writing operation, the current value of the chip is greater than the first current threshold, the value of the array read / write duration after increase is less than or equal to n times of the data input / output duration, n is a positive integer, and n is determined according to the number of cells in the first data channel.

5. The method according to any one of claims 1-4, characterized in that, When in the cache reading stage or cache program stage of the reading and writing operation, the current value of the chip is greater than the first current threshold and less than or equal to the third current threshold, the value of the array read / write duration after increase is less than or equal to the third duration; Wherein, the third duration is the difference between n times of the data input / output duration and the fourth duration, the fourth duration is the second target multiple of the current difference between the third current threshold and the first current threshold; n is a positive integer, and n is determined according to the number of cells in the first data channel, the third current threshold is greater than the first current threshold.

6. The method according to any one of claims 1-5, characterized in that, the method further includes: During the process of reading and writing the first cell of the first data channel in the chip, when the current value of the chip is less than the first current threshold, reduce the array read / write duration of the first cell, so that the current value in the chip increases.

7. The method according to claim 6, wherein, the method further includes: when the current value of the chip is less than the first current threshold and greater than the fourth current threshold, the reduction ratio of the array read / write duration is determined according to the difference between the first current threshold and the fourth current threshold; wherein, the fourth current threshold is less than the first current threshold.

8. A power consumption adjustment device applied to a chip, wherein, the device includes: a storage unit and a duration adjustment unit; the storage unit is used for storing data; the duration adjustment unit is used for monitoring the current value of the chip in real time during the read / write operation of the first cell of the first data channel in the storage unit; when the current value of the chip is greater than the first current threshold, based on the data input / output duration of the first cell, increasing the array read / write duration of the first cell so that the current value in the chip decreases; wherein, the first data channel is any one of the data channels in the storage unit, and the first cell is any one of the cells in the first data channel.

9. The device according to claim 8, wherein, when in the normal read stage or normal program stage of the read / write operation, the current value of the chip is greater than the first current threshold, the value of the increased array read / write duration is less than or equal to n - 1 times of the data input / output duration, n is a positive integer, and n is determined according to the number of cells in the first data channel.

10. The device according to claim 8 or 9, wherein, when in the normal read stage or normal program stage of the read / write operation, the current value of the chip is greater than the first current threshold and less than or equal to the second current threshold, the value of the increased array read / write duration is less than or equal to the first duration; wherein, the first duration is the difference between n - 1 times of the data input / output duration and the second duration, the second duration is the first target multiple of the current difference between the second current threshold and the first current threshold; n is a positive integer, and n is determined according to the number of cells in the first data channel; the second current threshold is greater than the first current threshold.

11. The device according to any one of claims 8 - 10, wherein, when in the cache read stage or cache program stage of the read / write operation, the current value of the chip is greater than the first current threshold, the value of the increased array read / write duration is less than or equal to n times of the data input / output duration, n is a positive integer, and n is determined according to the number of cells in the first data channel.

12. The device according to any one of claims 8 - 11, wherein, when in the cache read stage or cache program stage of the read / write operation, the current value of the chip is greater than the first current threshold and less than or equal to the third current threshold, the value of the increased array read / write duration is less than or equal to the third duration; Wherein, the third duration is the difference between n times the data input / output duration and the fourth duration, and the fourth duration is the second target multiple of the current difference between the third current threshold and the first current threshold; n is a positive integer and is determined according to the number of cells in the first data channel, and the third current threshold is greater than the first current threshold.

13. The device according to any one of claims 8-12, characterized in that the duration adjustment unit is further configured to, during the process of reading and writing the first cell of the first data channel in the storage unit, when the current value of the chip is less than the first current threshold, reduce the array read / write duration of the first cell, so as to increase the current value in the chip.

14. The device according to claim 13, characterized in that the duration adjustment unit is further configured to: when the current value of the chip is less than the first current threshold and greater than the fourth current threshold, the reduction ratio of the array read / write duration is determined according to the difference between the first current threshold and the fourth current threshold; wherein, the fourth current threshold is less than the first current threshold.

15. The device according to claim 13 or 14, characterized in that the device further comprises: a control unit; the control unit is connected to the duration adjustment unit; the control unit is configured to, during the process of reading and writing the first cell of the first data channel in the chip, when the current value of the chip is greater than the first current threshold, generate a first adjustment instruction and send the first adjustment instruction to the duration adjustment unit; wherein, the first adjustment instruction instructs to increase the array read / write duration of the first cell based on the data input / output duration of the first cell; the duration adjustment unit is configured to, after receiving the first adjustment instruction, increase the array read / write duration of the first cell based on the first adjustment instruction.

16. The device according to claim 15, characterized in that the control unit is further configured to, when the current value of the chip is less than the first current threshold, generate a second adjustment instruction and send the second adjustment instruction to the duration adjustment unit; wherein, the second adjustment instruction instructs to reduce the array read / write duration of the first cell; the duration adjustment unit is further configured to, after receiving the second adjustment instruction, reduce the array read / write duration of the first cell based on the second adjustment instruction.

17. A chip, characterized in that the chip comprises: a storage area and a controller; the storage area is used for storing data; the controller is configured to execute the method according to any one of claims 1-7.

18. A storage device, characterized in that it comprises: a circuit board and the chip according to claim 17, and the chip is disposed on the circuit board.

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