Generation method and system of standardized chip compiling link, electronic equipment and medium

Abstract

The invention provides a standardized chip compiling link generation method and system, an electronic device and a medium, and the method comprises the steps: firstly carrying out the information extraction of a link file grammar rule and a command manual of a target chip, then carrying out the description based on the information extraction to form an xml specific text, and then generating a standard link file based on the xml specific text. According to the method, the link file required by the project can be simply, conveniently and efficiently generated, the generated standard link file is uniform in generation process and format and high in adaptability, and various configuration information in the image interface can be verified in the process, so that the correctness of user configuration is verified in real time, configuration defects can be effectively reduced, and the user experience is improved. In this way, the difference of the link files generated by different chip platforms and different compiling linkers is accurately and efficiently shielded, a user can freely configure the image interface within a specified range, complete link files can be generated, part of link files can also be generated, and the requirements of different items using the microcontroller are met.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle-mounted controllers, and relates to a method for standardizing the compilation and linking of vehicle-mounted chips. More specifically, the present invention relates to a method, system, electronic device and medium for generating a standardized chip compilation and link. Background Art

[0002] With the transformation and upgrading of the automotive industry from traditional fuel vehicles to new energy vehicles, the proportion of automotive electronics and electrical appliances in the overall vehicle cost has increased significantly. Many microcontroller manufacturers have flocked to the field of vehicle-mounted controller design and research and development, forming a situation of a hundred flowers blooming and a hundred schools of thought contending in the field of vehicle-mounted microcontrollers. However, different microcontroller manufacturers choose different microcontroller cores and support different compilation linkers, which leads to additional software costs for vehicle manufacturers or Tier1s when switching microcontrollers, in addition to hardware costs. Among the software costs, code modification and linker file modification are included. For the modification of the linker file, even when switching to the same chip platform of the same manufacturer, the linker file adaptation will be different due to different chip models.

[0003] Linker files are closely related to the chip platform and the compilation linker, and belong to files with strong dependence on hardware. Therefore, the AUTOSAR organization has not been able to formulate relevant standards for the generation of linker files. When microcontroller application developers perform software adaptation or software transplantation, they need to understand the characteristics of the chip platform, consult relevant linker file syntax rules and command manuals, manually write linker files, and repeatedly debug them to form linker files for project use. The entire process requires a large amount of resources, resulting in an increase in the chip application cost in vehicles. Moreover, linker files written manually may have particularly hidden bugs, resulting in hidden defects in chip compilation and linking.

[0004] Therefore, there is an urgent need for a method, system, electronic device and medium for generating a standardized chip compilation and link that can shield the differences in linker files brought by different chip platforms and different compilation linkers, can verify the correctness of user configurations in real time, provide a unified compilation and link for microcontroller application developers, and reduce compilation and link defects. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a method, system, electronic device and medium for generating a standardized chip compilation and link, so as to solve the technical problems in the prior art that manually writing linker files and repeatedly debugging them to form linker files for project use requires a large amount of resources, resulting in an increase in the chip application cost in vehicles, and linker files written manually are prone to hidden bugs, resulting in hidden defects in chip compilation and linking.

[0006] In a first aspect, an embodiment of the present application provides a method for generating a standardized chip compilation link. The method for generating the standardized chip compilation link includes:

[0007] Obtain the link file syntax rules and command manual of the target chip as the file to be extracted, perform information extraction on the file to be extracted according to the preset extraction rules to obtain valid data, and write the valid data into a preset configuration item table;

[0008] Perform xml description according to the configuration item table through a preset description component to form xml specific text;

[0009] Import the xml specific text into a preset configuration tool, so that the configuration tool parses the xml specific text and fills the content generated by the parsing into the graphical interface of the configuration tool;

[0010] Verify each configuration information in the graphical interface. If the verification is successful, generate a standard link file based on the configuration information according to the preset compilation rules.

[0011] Optionally, performing information extraction on the file to be extracted according to the preset extraction rules to obtain valid data, and writing the valid data into a preset configuration item table includes:

[0012] Judge whether there is information vacancy in the configuration item table; where

[0013] If there is a vacancy, traverse each statement of the file to be extracted in turn. If a preset key character appears during the traversal, obtain the key information corresponding to the key character according to the preset keyword locking rule;

[0014] Search for the table header corresponding to the key character one by one in the configuration item table, and correspond the key information with the table header to fill the vacancy corresponding to the table header in the configuration item table; where the key character is preset in advance, and there is a table header corresponding to the key character one by one in the configuration item table;

[0015] If there is no vacancy, stop traversing the file to be extracted.

[0016] Optionally, performing xml description according to the configuration item table through a preset description component to form xml specific text includes:

[0017] Read the configuration item table and arrange the table headers in the configuration item table in sequence;

[0018] Match an xml description statement for each table header according to the preset corresponding rules, and add key information corresponding to the table header to the xml description statement to form a statement array;

[0019] Add an identifier and a function name to the statement array to form xml specific text.

[0020] Optionally, the configuration information of the image interface includes a node name, a start address, an end address, and a storage area size.

[0021] Optionally, verify the configuration information in the image interface, including:

[0022] Obtain the configuration information in the image interface, and determine whether the configuration information is compliant. If the configuration information is compliant, obtain the values of the configuration information in the image interface, and determine whether the values are within a preset value range; if the values are within the value range, select to perform a standard verification on the relevant files and relevant functions of the configuration information; if the relevant files and relevant functions pass the standard verification, perform a quantity verification on the child nodes in the image interface. If the child nodes pass the quantity verification; if the child nodes pass the quantity verification, the configuration information in the image interface is successfully verified.

[0023] Optionally, generate a standard link file based on the configuration information according to the preset compilation rules, including:

[0024] Confirm the basic information according to the link file syntax rules and the command manual, fill the basic information into a preset file to form a file header, and fill the configuration information into a preset link entity in sequence to form a link file entity;

[0025] Correspond and splice the file header and the link file entity to generate a link file;

[0026] Review and adjust the link file to form a standard link file.

[0027] Optionally, the basic information includes at least the author, the execution date, the file name of the command manual, the link file syntax rules, the version information of the command manual, and the modification history.

[0028] In a second aspect, an embodiment of the present application provides a generation system for standardizing chip compilation and linking, which implements the method for generating standardizing chip compilation and linking as described above. The system includes:

[0029] A data extraction and matching unit, configured to obtain the link file syntax rules and command manuals of a target chip as files to be extracted, perform information extraction on the files to be extracted according to preset extraction rules to obtain valid data, and write the valid data into a preset configuration item table;

[0030] A file description unit, configured to perform xml description according to the configuration item table through a preset description component to form xml specific text;

[0031] A file import unit, configured to import the xml specific text into a preset configuration tool, so that the configuration tool parses the xml specific text and fills the content generated by the parsing into the graphical interface of the configuration tool;

[0032] A link generation unit, configured to verify various configuration information in the graphical interface, and if the verification is successful, generate a standard link file based on the various configuration information according to preset compilation rules.

[0033] In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory, and a system bus; the processor and the memory are connected through the system bus; the memory is used to store one or more programs, and the one or more programs include instructions, and when the instructions are executed by the processor, the processor executes the generation method of the standardized chip compilation link according to any optional one in the first aspect.

[0034] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the generation method of the standardized chip compilation link according to any optional one in the first aspect is implemented.

[0035] As can be seen from the above technical solutions, an embodiment of the present application provides a method, a system, an electronic device, and a computer-readable storage medium for generating a standardized chip compilation link. Compared with the prior art, the present application has the following beneficial effects:

[0036] First, perform information extraction on the link file syntax rules and command manuals of the target chip, then perform description based on this to form xml specific text, and then fill the graphical interface of the configuration tool based on the xml specific text, and then generate a standard link file. Based on the entire process, the link file required for the project can be generated simply, conveniently, and efficiently, and the generation process and format of the generated standard link file are unified, and the adaptability is strong;

[0037] During the process, various configuration information in the image interface will be verified to real-time verify the correctness of the user configuration, which can effectively reduce configuration defects. In this way, it can accurately and efficiently shield the differences in the link files generated by different chip platforms and different compilation linkers. And the user can freely configure within the specified range through the image interface, and can generate a complete link file or a partial link file to meet the needs of projects using different microcontrollers. Description of the Drawings

[0038] By referring to the following description of the specification in conjunction with the drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easier to understand. In the drawings:

[0039] Figure 1 It is a flowchart of a method for generating a standardized chip compilation link according to an embodiment of the present invention;

[0040] Figure 2 It is a logic block diagram of a system for generating a standardized chip compilation link according to an embodiment of the present invention;

[0041] Figure 3 It is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Embodiments

[0042] When microcontroller application developers perform software adaptation or software transplantation, they need to understand the characteristics of the chip platform, consult the relevant link file syntax rules and command manuals, manually write link files, and repeatedly debug to form the link files used in the project. The entire process requires a large amount of resources, resulting in an increase in the chip application cost on automobiles. Moreover, through the manually written link files, there may be particularly hidden bugs, resulting in hidden defects in chip compilation links.

[0043] To address the above problems, the present invention provides a method, system, electronic device, and computer-readable storage medium for generating a standardized chip compilation link. First, obtain the link file syntax rules and command manuals of the target chip as the file to be extracted, extract information from the file to be extracted according to the preset extraction rules to obtain valid data, and write the valid data into the preset configuration item table. Then, perform xml description according to the configuration item table through the preset description component to form xml specific text. Then, import the xml specific text into the preset configuration tool, so that the configuration tool parses the xml specific text and fills the parsed content into the image interface of the configuration tool. Finally, verify the various configuration information in the image interface. If the verification is successful, generate a standard link file based on the various configuration information according to the preset compilation rules.

[0044] First, extract information from the link file syntax rules and command manuals of the target chip, then form specific XML text based on this description, and then fill the graphical interface of the configuration tool with the specific XML text. Subsequently, generate a standard link file. Based on this entire process, the link file required for the project can be generated simply, conveniently, and efficiently, and the generation process and format of the generated standard link file are unified, with strong adaptability. During the process, various configuration information in the graphical interface will be verified to real-time verify the correctness of the user configuration, effectively reducing configuration defects. In this way, the differences in link files generated by different chip platforms and different compilation linkers can be accurately and efficiently masked, and users can freely configure within the specified range through the graphical interface, generating either a complete link file or a partial link file to meet the needs of projects using different microcontrollers.

[0045] To enable those skilled in the art of this technology to better understand the solution of this application, the following will clearly and completely describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. The description of the following exemplary embodiments is actually only illustrative and in no way limits the present invention and its application or use. Technologies and devices known to those of ordinary skill in the relevant fields may not be discussed in detail, but where appropriate, such technologies and devices should be regarded as part of the specification. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0046] Figure 1 The flowchart of a method for generating a standardized chip compilation link provided by an embodiment of this application is as Figure 1 shown, and this method includes:

[0047] S1: Obtain the link file syntax rules and command manuals of the target chip as the file to be extracted, extract information from the file to be extracted according to the preset extraction rules to obtain valid data, and write the valid data to a preset configuration item table;

[0048] S2: Perform XML description according to the configuration item table through a preset description component to form specific XML text;

[0049] S3: Import the specific XML text into a preset configuration tool, so that the configuration tool parses the specific XML text and fills the content generated by the parsing into the graphical interface of the configuration tool;

[0050] S4: Verify each piece of configuration information in the image interface. If the verification is successful, generate a standard link file based on the configuration information according to the preset compilation rules.

[0051] Step S1 is a process of obtaining the link file syntax rules and command manual of the target chip as the file to be extracted, extracting information from the file to be extracted according to the preset extraction rules to obtain valid data, and writing the valid data to the preset configuration item table.

[0052] Among them, there is no specific limitation on the process of information extraction. It can use a preset program or plug-in for text extraction, or even use a more intelligent model for text recognition for information extraction. Of course, it can also be done manually. Here, it is not limited. In this embodiment, a preset data extraction and matching unit is used for information extraction. The specific form of the data extraction and matching unit is a preset program. Specifically, information is extracted from the file to be extracted according to the preset extraction rules to obtain valid data, and the valid data is written to the preset configuration item table, including:

[0053] S11: Determine whether there is information vacancy in the configuration item table; among them,

[0054] S12: If there is a vacancy, traverse each statement of the file to be extracted in turn. If a preset key character appears during the traversal, obtain the key information corresponding to the key character according to the preset keyword locking rule.

[0055] S13: Search for the table header in the configuration item table that corresponds one-to-one with the key character, and correspond the key information with the table header to fill the vacancy in the configuration item table corresponding to the table header; among them, the key character is preset in advance, and there is a table header in the configuration item table that corresponds one-to-one with the key character.

[0056] Among them, if there is no vacancy, stop traversing the file to be extracted.

[0057] Thus, the extraction of key information is completed.

[0058] For example, in the command manual of the compiler specified by a certain chip platform, the rule description of the MEMORY instruction is as follows:

[0059]

[0060] From the above manual, two parts of static information and dynamically configurable information can be extracted:

[0061] Static information: MEMORY, ORIGIN=, LENGTH=, {}

[0062] Dynamic configurable information: memory_block, origin_expression, length_expression.

[0063] Among them, the static information corresponds to the fixed fields in the generated link file, and the dynamic information corresponds to the configurable fields in the link file. By extracting the MEMORY instructions, the following configuration item table can be formed:

[0064]

[0065] In this embodiment, step S2 is a process of forming xml specific text by xml description according to the configuration item table through a preset description component. The type of this description component is not limited here, as long as it can complete the description based on the configuration item table. In this specific embodiment, the steps of forming xml specific text by xml description according to the configuration item table through a preset description component include:

[0066] S21: Read the configuration item table and arrange the table headers in the configuration item table in sequence;

[0067] S22: Match xml description statements for each table header according to a preset corresponding rule, and add key information corresponding to the table header to the xml description statements to form a statement array;

[0068] S23: Add identifiers and function names to the statement array to form xml specific text.

[0069] For example, in the above specific embodiment, for the configuration item of StartAddress (starting address), the xml specific text generated using xml language is as follows:

[0070]

[0071]

[0072] In a specific implementation, more specifically, the generation rules of xml specific text can include the following several items:

[0073] As shown above, the "ECUC-INTEGER-PARAM-DEF tag" is the unique identifier defined globally and is unique throughout the xml file, with the UUID as the unique identification value; the "SHORT-NAME tag" is used as the configuration item name to prompt the user about the function of the configuration item; the "VALUE-CONFIG-CLASSES tag" is used as the configuration class, representing whether the corresponding configuration item allows only one configuration value or multiple configuration values (MULTIPLICITY-CONFIG-CLASSES).

[0074] The "ECUC-VALUE-CONFIGURATION-CLASS tag" is for configuring the configuration item type, including pre-compilation type, runtime type, post-compilation type, etc.; the "CONFIG-CLASS tag" represents the configuration item type; the "CONFIG-VARIANT tag" identifies the configuration item type value; the "SYMBOLIC-NAME-VALUE tag" is the symbolic name value, intended to indicate whether the configuration item value depends on other configuration items; the "MAX tag" represents the maximum value of the configuration item; the "MIN tag" represents the minimum value of the configuration item; the "PLACE-HOLDER tag" represents the function description information for prompting the corresponding configuration item when the mouse hovers over the configuration item.

[0075] Step S3 is the process of importing the xml specific text into a preset configuration tool, enabling the configuration tool to parse the xml specific text and fill the content generated by the parsing into the graphical interface of the configuration tool. That is, after obtaining the xml specific text containing valid data, the xml specific text is imported into the preset configuration tool to fill the graphical interface, which is configurable. Before and after filling, the user can adjust the data therein by themselves to make the link generation more flexible.

[0076] There is no specific limitation on the types included in the graphical interface, which can be determined according to the data required by the microcontroller (chip) application vendor, and can be more detailed or brief. In this embodiment, a relatively brief graphical interface is selected, and the configuration information of the graphical interface includes node name, start address, end address, and storage area size.

[0077] Step S4 is the step of verifying each piece of configuration information in the graphical interface. If the verification is successful, a standard link file is generated based on each piece of configuration information according to the preset compilation rules; among them,

[0078] Verifying each piece of configuration information in the graphical interface includes:

[0079] Obtain the configuration information of each item in the image interface, and determine whether the configuration information of each item is compliant. If the configuration information of each item is compliant, obtain the values of the configuration information of each item in the image interface, and determine whether the values are within the preset value range; if the values are within the value range, select to perform standard verification on the relevant files and relevant functions of the configuration information of each item; if the relevant files and relevant functions pass the standard verification, perform a quantity verification on the child nodes in the image interface. If the child nodes pass the quantity verification; if the child nodes pass the quantity verification, the verification of the configuration information of each item in the image interface is successful.

[0080] More specifically, value range verification, verification of unconfigured required items, etc. can be performed; for example, verifying whether the naming conforms to the C language standard function name verification, whether the string conforms to the C language header file name standard verification; verifying whether the nodes that can only be referenced once are referenced multiple times; verifying whether the values of the configuration items conflict with the values of other configuration items; verifying whether the referenced nodes exist; verifying that there must be child nodes under the node; verifying whether the value of the configuration item must be greater than the value of another associated configuration item is really greater; verifying whether the number of child nodes exceeds the range.

[0081] In the verification prompt message, in addition to describing the verification information, corresponding modification suggestions can also be automatically popped up according to the preset rules. For example, in the value range verification, if the value of the configuration item filled in by the user is not compliant, the following configuration suggestions will be prompted in the verification prompt message:

[0082] Minimum value of the configuration item: xx;

[0083] Maximum value of the configuration item: yy;

[0084] Default value of the configuration item: zz.

[0085] Generate a standard link file based on the configuration information of each item according to the preset compilation rules, including:

[0086] Confirm the basic information according to the link file syntax rules and the command manual, fill the basic information into the preset file to form a file header, and fill the configuration information of each item into the preset link entity in sequence to form a link file entity;

[0087] Correspond and splice the file header and the link file entity to generate a link file;

[0088] Review and adjust the link file to form a standard link file.

[0089] Among them, the basic information at least includes the author, the execution date, the file name of the command manual, the link file syntax rules, the version information of the command manual, and the modification history.

[0090] That is to say, the link file consists of two parts. The first part is the file header, which describes the information of the link file, including the author, date, file name, version information, and modification history. The second part is the link file entity, both of which can be generated by the configuration tool.

[0091] Different manufacturers and different chip platforms use different compilation linkers; for the same manufacturer, different chip platforms use different compilation linkers; for the same manufacturer, the same chip platform uses different compilation linkers; for the same manufacturer, the same chip platform uses the same compilation linker, but the chip models are different. For the above scenarios, by extracting the chip platform information, the syntax rules of the link file, and the command manual, an XML specific text is formed. After importing this XML specific text into the tool, the data is filled into a unified graphical interface. During the configuration process, the tool will synchronously check the correctness of the configuration to ensure that no potential bugs (defects) occur. Finally, a verified link file is generated. Of course, a part of the link file can also be generated through user configuration as a standard link file for the target chip.

[0092] As described above, the method for generating a standardized chip compilation link provided by the present invention first extracts the information of the syntax rules of the link file and the command manual of the target chip, then forms an XML specific text based on this description, and then fills the graphical interface of the configuration tool based on this XML specific text, and then generates a standard link file. Based on the entire process, the link file required for the project can be generated simply, conveniently, and efficiently. Moreover, the generation process and format of the generated standard link file are unified, and the adaptability is strong. During the entire process, various configuration information in the graphical interface will be verified, so as to verify the correctness of the user configuration in real time, effectively reduce configuration defects, accurately and efficiently shield the differences in the link files generated by different chip platforms and different compilation linkers, and the user can freely configure within the specified range through the graphical interface, and can generate a complete link file or a partial link file to meet the needs of different projects using microcontrollers.

[0093] Next, a system for generating a standardized chip compilation link provided by an embodiment of the present application will be introduced. The system for generating a standardized chip compilation link described below can be correspondingly referred to the method for generating a standardized chip compilation link described above.

[0094] As Figure 2 shown, the present invention also provides a system 100 for generating a standardized chip compilation link, which can implement the method for generating a standardized chip compilation link as described above. The system includes:

[0095] A data extraction and matching unit 110 is configured to obtain the link file syntax rules and command manuals of a target chip as files to be extracted, perform information extraction on the files to be extracted according to preset extraction rules to obtain valid data, and write the valid data into a preset configuration item table;

[0096] A file description unit 120 is configured to perform xml description on the basis of the configuration item table through a preset description component to form xml specific text;

[0097] A file import unit 130 is configured to import the xml specific text into a preset configuration tool, so that the configuration tool parses the xml specific text and fills the content generated by the parsing into the image interface of the configuration tool;

[0098] A link generation unit 140 is configured to verify each item of configuration information in the image interface. If the verification is successful, a standard link file is generated based on the configuration information according to preset compilation rules.

[0099] In this embodiment, the data extraction and matching unit 110 includes a data extraction unit 111 and a data matching unit 112. Among them, the data extraction unit 111 includes a judgment module 1111, an information locking module 1112, and a header correspondence module 1113; among them,

[0100] The judgment module 1111 is configured to judge whether there is information vacancy in the configuration item table; among them, if there is no vacancy, traversing the files to be extracted is stopped;

[0101] If there is a vacancy, the information locking module 1112 traverses each statement of the files to be extracted in turn. If a preset key character appears during the traversal, key information corresponding to the key character is obtained according to preset key word locking rules;

[0102] The header correspondence module 113 is configured to find a header in the configuration item table that corresponds one-to-one to the key character, and correspond the key information to the header to fill the vacancy in the configuration item table corresponding to the header; among them, the key character is preset in advance, and a header corresponding one-to-one to the key character is preset in the configuration item table.

[0103] The file description unit 120 includes:

[0104] A header arrangement module 121 is configured to read the configuration item table and arrange the headers in the configuration item table in turn;

[0105] The statement formation module 122 is used to match xml description statements for each table header according to a preset corresponding rule, and add key information corresponding to the table header to the xml description statements to form a statement array;

[0106] The text integration module 123 is used to add identifiers and function names to the statement array to form xml specific text.

[0107] The link generation unit 140 includes an information verification module 141 and a file generation module 142; wherein,

[0108] The information verification module 141 is used to obtain various configuration information in the image interface, and determine whether the various configuration information is compliant. If the various configuration information is compliant, obtain the various values of the various configuration information in the image interface, and determine whether the various values are within a preset value range; if the various values are within the value range, select to perform standard verification on the relevant files and relevant functions of the various configuration information; if the relevant files and relevant functions pass the standard verification, perform a quantity verification on the child nodes in the image interface. If the child nodes pass the quantity verification; if the child nodes pass the quantity verification, the various configuration information in the image interface is successfully verified.

[0109] The file generation module 142 includes:

[0110] The file filling module 1421 is used to confirm basic information according to the link file syntax rule and the command manual, fill the basic information into a preset file to form a file header, and sequentially fill the various configuration information into a preset link entity to form a link file entity;

[0111] The file splicing module 1422 is used to correspond and splice the file header and the link file entity to generate a link file;

[0112] The file adjustment module 1423 is used to review and adjust the link file to form a standard link file.

[0113] The standardized chip compilation link generation system 100 provided by the present invention performs calculations in the same way as the aforementioned standardized chip compilation link generation method, and the more specific implementation process can refer to the specific embodiments of the above-mentioned standardized chip compilation link generation method.

[0114] As described above, the standardized chip compilation link generation system 100 provided by the present invention first obtains the link file syntax rules and command manuals of the target chip as the files to be extracted based on the data extraction and matching unit 110, extracts information from the files to be extracted according to the preset extraction rules to obtain valid data, and writes the valid data into the preset configuration item table. Then, based on the file description unit 120, xml description is performed according to the configuration item table through the preset description component to form xml specific text. Then, the xml specific text is imported into the preset configuration tool through the file import unit 130, so that the configuration tool parses the xml specific text and fills the content generated by the parsing into the graphical interface of the configuration tool. Finally, the link generation unit 140 verifies the configuration information in the graphical interface. If the verification is successful, a standard link file is generated based on the configuration information according to the preset compilation rules.

[0115] First, information is extracted from the link file syntax rules and command manuals of the target chip, then xml specific text is formed based on this description, and then the graphical interface of the configuration tool is filled based on the xml specific text. Subsequently, a standard link file is generated. Based on the entire process, the link file required for the project can be generated simply, conveniently and efficiently, and the generation process and format of the generated standard link file are unified and highly adaptable. During the process, the configuration information in the graphical interface is verified, so as to verify the correctness of the user configuration in real time, effectively reduce configuration defects, accurately and efficiently shield the differences of the link files generated by different chip platforms and different compilation linkers, and the user can freely configure within the specified range through the graphical interface, and can generate a complete link file or a partial link file to meet the needs of projects using different microcontrollers.

[0116] See Figure 3, This figure is a schematic structural diagram of an electronic device provided by an embodiment of the present application, including: a memory 11 for storing computer programs; a processor 12 for implementing the steps of the method for generating a standardized chip compilation link described in any of the above method embodiments when executing the computer programs. In this embodiment, the device can be an in-vehicle computer, a PC (Personal Computer), or a terminal device such as a smart phone, a tablet computer, a palm computer, a portable computer, etc. The device may include a memory 11, a processor 12, and a bus 13. Among them, the memory 11 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, a hard disk, a multimedia card, a card-type memory (such as an SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, etc. The memory 11 may be an internal storage unit of the device in some embodiments, such as the hard disk of the device. The memory 11 may also be an external storage device of the device in other embodiments, such as a plug-in hard disk equipped on the device, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Further, the memory 11 may also include both the internal storage unit and the external storage device of the device. The memory 11 can be used not only to store application software installed on the device and various types of data, such as program codes for executing the fault prediction method, etc., but also to temporarily store data that has been output or will be output. The processor 12 may be a Central Processing Unit (CPU) in some embodiments. The processor 12 may be a Central Processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chips in some embodiments, for running the program codes stored in the memory 11 or processing data, such as codes for executing the method for generating a standardized chip compilation link. The bus 13 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus. Further, the device may further include a network interface 14, and the network interface 14 may optionally include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), and is generally used to establish a communication connection between the device and other electronic devices.

[0117] Optionally, the device may further include a user interface 15, which may include a display, an input unit such as a keyboard, and optionally, the user interface 15 may further include a standard wired interface and a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) toucher, etc. Among them, the display may also be appropriately referred to as a display screen or a display unit, which is used to display the information processed in the device and to display a visual user interface. Figure 3 Only the device with components 11-15 is shown. Those skilled in the art can understand that Figure 3 the shown structure does not constitute a limitation on the device, and it may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0118] An embodiment of the present invention also provides a computer-readable storage medium, which may be non-volatile or volatile. The storage medium stores a computer program, and when the computer program is executed by a processor, it realizes:

[0119] Obtain the link file syntax rules and command manual of the target chip as the file to be extracted, perform information extraction on the file to be extracted according to the preset extraction rules to obtain valid data, and write the valid data into a preset configuration item table;

[0120] Perform xml description according to the configuration item table through a preset description component to form xml specific text;

[0121] Import the xml specific text into a preset configuration tool, so that the configuration tool parses the xml specific text and fills the content generated by the parsing into the image interface of the configuration tool;

[0122] Verify the configuration information in the image interface. If the verification is successful, generate a standard link file based on the configuration information according to the preset compilation rules.

[0123] Specifically, the specific implementation method when the computer program is executed by the processor can refer to the description of the relevant steps in the method for generating a standardized chip compilation link in the embodiment, which will not be elaborated here.

[0124] In several embodiments provided by the present invention, it should be understood that the disclosed device, apparatus and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation.

[0125] The module described as a separation component may or may not be physically separated. The component shown as a module may or may not be a physical unit, that is, it may be located in one place or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0126] In addition, in each embodiment of the present invention, each functional module can be integrated in a processing unit, can also be physically present separately for each unit, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a hardware plus software functional module.

[0127] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms.

[0128] Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed within the present invention. Any associated drawing marks in the claims should not be regarded as limiting the claimed rights.

[0129] In addition, it is obvious that the word "including" does not exclude other units or steps, and the singular does not exclude the plural. The multiple units or devices stated in the system claims can also be implemented by one unit or device through software or hardware. Words such as "second" are used to denote names and do not denote any particular order.

[0130] It should be noted that each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for methods, devices, electronic devices, and computer-readable storage media, since they are basically similar to the method embodiments, the description is relatively simple. The relevant parts can be referred to the partial description of the method embodiments. The methods, devices, electronic devices, and media described above are only illustrative. The units described as separation components may or may not be physically separated. The components prompted as units may or may not be physical units, that is, they may be located in one place or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement without creative work.

[0131] The method, system, electronic device and medium for generating a standardized chip compilation link according to the present invention are described above by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various improvements can be made to the above-mentioned method, system, electronic device and medium for generating a standardized chip compilation link according to the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the appended claims.

Claims

1. A method for generating a standardized chip compilation link, characterized in that: include: Acquire the link file syntax rules and command manual of the target chip as the file to be extracted, extract information from the file to be extracted according to the preset extraction rules to obtain valid data, and write the valid data into the preset configuration item table; Performing an XML description according to the configuration item table through a preset description component to form an XML specific text; Importing the XML specific text into a preset configuration tool, so that the configuration tool parses the XML specific text and fills the parsed content into the graphical interface of the configuration tool; Verify each item of configuration information in the graphic interface, and if the verification is successful, generate a standard link file based on the each item of configuration information according to a preset compilation rule.

2. The method for generating a standardized chip compilation link as claimed in claim 1, characterized in that: Extract information from the file to be extracted according to the preset extraction rules to obtain valid data, and write the valid data into a preset configuration item table, including: Determine whether there is any missing information in the configuration item table; wherein, If there is a vacancy, each sentence of the file to be extracted is traversed in turn. If a preset key character appears during the traversal process, key information corresponding to the key character is obtained according to a preset keyword locking rule; Searching for a table header corresponding to the key character in the configuration item table, and making the key information correspond to the table header to fill the vacancy corresponding to the table header in the configuration item table; wherein the key character is preset in advance, and a table header corresponding to the key character in the configuration item table is preset; If there is no vacancy, stop traversing the file to be extracted.

3. The method for generating a standardized chip compilation link as claimed in claim 2, characterized in that: Performing an XML description according to the configuration item table through a preset description component to form an XML specific text, including: Read the configuration item table, and arrange the table headers in the configuration item table in sequence; Matching an XML description statement for each table header according to a preset corresponding rule, and adding key information corresponding to the table header to the XML description statement to form a statement array; Add identifiers and function names to the statement array to form the xml specific text.

4. The method for generating a standardized chip compilation link as claimed in claim 1, characterized in that: The configuration information of the graphic interface includes a node name, a start address, an end address and a storage area size.

5. The method for generating a standardized chip compilation link as claimed in claim 1, characterized in that: Verify each configuration information in the graphic interface, including: Obtain various configuration information in the image interface, and determine whether the various configuration information is compliant; if the various configuration information is compliant, obtain various values ​​of the various configuration information in the image interface, and determine whether the various values ​​are within a preset value range; if the various values ​​are within the value range, select to perform standard verification on related files and related functions of the various configuration information; if the related files and related functions pass the standard verification, perform quantity verification on the subnodes in the image interface, if the subnodes pass the quantity verification; if the subnodes pass the quantity verification, the verification of various configuration information in the image interface is successful.

6. The method for generating a standardized chip compilation link as claimed in claim 1, characterized in that: Generate a standard link file based on the configuration information according to the preset compilation rules, including: Confirming basic information according to the link file syntax rule and the command manual, filling the basic information into a preset file to form a file header, and filling each item of configuration information into a preset link entity in sequence to form a link file entity; Matching and splicing the file header and the link file entity to generate a link file; The link files are reviewed and adjusted to form standard link files.

7. The method for generating a standardized chip compilation link as claimed in claim 6, characterized in that: The basic information at least includes the author, execution date, file name of the command manual, grammatical rules of the link file, version information of the command manual and modification history.

8. A standardized chip compilation and linking generation system, characterized in that: To implement the method for generating a standardized chip compilation link as described in any one of claims 1 to 7, the system comprises: A data extraction and matching unit, used to obtain the link file syntax rules and command manual of the target chip as a file to be extracted, extract information from the file to be extracted according to a preset extraction rule to obtain valid data, and write the valid data into a preset configuration item table; A file description unit, used for performing an XML description according to the configuration item table through a preset description component to form an XML specific text; A file importing unit, used for importing the XML specific text into a preset configuration tool, so that the configuration tool parses the XML specific text and fills the parsed content into the graphical interface of the configuration tool; The link generation unit is used to verify each item of configuration information in the image interface, and if the verification is successful, generate a standard link file based on the each item of configuration information according to a preset compilation rule.

9. An electronic device, characterized in that: The device includes: a processor, a memory and a system bus; the processor and the memory are connected via the system bus; the memory is used to store one or more programs, and the one or more programs include instructions, which, when executed by the processor, enable the processor to execute the standardized chip compilation and link generation method described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for generating a standardized chip compilation link according to any one of claims 1 to 7 is implemented.

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