Memory and task allocation method

Abstract

The invention provides a memory and a task allocation method, and the memory comprises a main control module which is used for receiving a host task; the cache units are used for executing the host tasks in the corresponding task queues; and the cache management module is used for acquiring the working state of the corresponding task queue according to the type of the host task and distributing the host task according to the working state of the task queue. According to the memory and the task allocation method provided by the invention, the cache utilization rate of the memory can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage, and particularly to a memory and a task allocation method. Background Art

[0002] With the wide application of memories in consumer electronic devices such as smart TVs, set-top boxes, and mobile terminals, the memory needs to achieve a balance among data reliability, stability, and operating efficiency. The memory adopts a cooperative architecture of an ARM architecture main control and a NAND flash module, and realizes core functions such as bad block management, garbage collection, and performance optimization through firmware. Its highly integrated characteristics result in a complex system environment with multiple modules operating in parallel inside.

[0003] The current technical bottleneck is that each functional module inside the memory (such as a data verification module, a cache module, etc.) is configured with an independent cache unit, but in the existing architecture, the cache resources adopt a static allocation mechanism, and each cache unit only serves the corresponding host task. Due to significant differences in aspects such as capacity, access speed, and data retention characteristics among different cache units, this single-mapping cache management mode leads to two prominent problems: on the one hand, high-load modules are prone to forming performance bottlenecks due to insufficient dedicated cache resources; on the other hand, the idle caches of low-load modules cannot be dynamically called by the system, resulting in low overall utilization rate of storage resources. Therefore, there is room for improvement. Summary of the Invention

[0004] The purpose of the present invention is to provide a memory and a task allocation method, which can improve the cache utilization rate of the memory.

[0005] To solve the above technical problems, the present invention is realized through the following technical solutions: The present invention provides a memory, including: A main control module, configured to receive host tasks; A plurality of cache units, configured to execute host tasks in the corresponding task queues; A cache management module, configured to obtain the working status of the corresponding task queue according to the type of the host task, and allocate the host task according to the working status of the task queue.

[0006] In an embodiment of the present invention, the cache management module includes: A cache monitoring unit, configured to obtain the working status of the corresponding task queue according to the type of the host task; A task allocation unit, configured to judge the working status of the task queue: when the task queue is in an idle state, allocate the host task to the corresponding task queue until the task queue is in a full-load state; when the task queue is in a full-load state, allocate the unallocated host task to the task queues of other cache units.

[0007] In an embodiment of the present invention, the task allocation unit allocates the unallocated host tasks according to the following steps: When the task queue is in a full load state, determine the working state of the task queues of other cache units: When there is at least one task queue in an idle state, allocate the unallocated host tasks to the same task queue.

[0008] In an embodiment of the present invention, the task allocation unit allocates the unallocated host tasks to the same task queue according to the following steps: Sort the idle capacities of all the task queues in an idle state to obtain the task queue with the largest idle capacity; Allocate the unallocated host tasks to the task queue with the largest idle capacity.

[0009] In an embodiment of the present invention, the task allocation unit allocates the unallocated host tasks according to the following steps: Judge the number of the unallocated host tasks and the largest idle capacity: When the number of the unallocated host tasks is less than or equal to the largest idle capacity, allocate all the unallocated host tasks to the task queue with the largest idle capacity; When the number of the unallocated host tasks is greater than the largest idle capacity, allocate some of the unallocated host tasks to the task queue with the largest idle capacity until the task queue with the largest idle capacity is in a full load state.

[0010] In an embodiment of the present invention, the task allocation unit allocates the unallocated host tasks according to the following steps: When the task queue of the cache unit is in a full load state, determine the working state of the task queues of other cache units: When there is at least one task queue in an idle state, allocate the unallocated host tasks to different task queues.

[0011] In an embodiment of the present invention, the task allocation unit allocates the unallocated host tasks to different task queues according to the following steps: Obtain the idle capacity, total capacity, current throughput, and average throughput of the task queues in an idle state; wherein, the current throughput represents the number of host tasks processed by the cache unit in its task queue per unit time, and the average throughput represents the average value of the number of host tasks processed by all cache units in their task queues per unit time; Calculate the ratio of the idle capacity to the total capacity of each of the task queues in the idle state, and the ratio of the current throughput to the average throughput, which are respectively denoted as the first ratio and the second ratio; Calculate the sum of the product of the first ratio and the corresponding adjustment coefficient and the product of the second ratio and the corresponding adjustment coefficient, which is expressed as a dynamic weight value; Split the unassigned host tasks according to the dynamic weight values of all the task queues in the idle state to obtain multiple groups of task sets; each task set includes at least one unassigned host task; Allocate the task sets to the corresponding task queues in the idle state.

[0012] In an embodiment of the present invention, the cache management module further includes a task queue unit, and the task queue unit is used to cache unassigned host tasks.

[0013] In an embodiment of the present invention, the task allocation unit allocates the host tasks cached by the task queue unit according to the following steps: Judge the working state of the corresponding task queue according to the task type of the cached host tasks: When the task queue is in the idle state, sequentially allocate the cached host tasks to the corresponding task queue until the task queue is in the full-load state.

[0014] The present invention also provides a task allocation method for a memory, the memory includes a main control module, a cache management module, and multiple cache units; the task allocation method includes: Receive host tasks through the main control module; The cache management module obtains the working state of the corresponding task queue according to the type of the host tasks, and allocates the host tasks according to the working state of the task queue; Execute the host tasks in the corresponding task queue through the cache unit.

[0015] As described above, the present invention provides a memory and a task allocation method. By breaking the static binding relationship between cache resources and functional modules in the traditional storage architecture and constructing a global dynamic scheduling system, it effectively solves the efficiency bottleneck problem caused by rigid resource allocation in the storage system, realizes intelligent collaboration of cache resources across modules and tasks, and significantly improves the overall system performance and resource utilization rate. Automatically dynamically allocate idle cache resources to high-load modules according to real-time task requirements, eliminating the resource waste phenomenon of "unequal busyness and idleness" in the traditional architecture. In the single-core scenario, dynamically allocate cache resources based on task priorities to avoid resource contention when a single core processes multiple tasks; in the multi-core scenario, achieve linear scalability through cross-core cache resource sharing and task parallel scheduling.

[0016] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0018] Figure 1 Schematic diagram of a memory in an embodiment of the present invention; Figure 2 Schematic diagram of a cache management module in an embodiment of the present invention.

[0019] In the figure: 10, power supply module; 20, first interface module; 30, main control module; 40, read-only storage module; 50, random cache unit; 60, mapping cache unit; 70, second interface module; 71, output cache unit; 72, input cache unit; 80, data verification module; 81, verification cache unit; 90, cache module; 91, write cache unit; 92, read cache unit; 100, flash memory module; 110, cache management module; 111, configuration management unit; 112, task queue unit; 113, status management unit; 114, cache monitoring unit; 115, task allocation unit; 116, interrupt processing unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] Please refer to Figure 1, the present invention provides a memory, which can be an Embedded MultiMedia Card (eMMC) or a Universal Flash Storage (UFS). The memory can communicate with an electronic device through the CMD line and the DATA0~7 lines, and execute operations such as reading, writing, and erasing by receiving instructions from the electronic device. The electronic device can send instructions through the CMD line and transmit data through the DATA0~7 lines. The communication protocol between the memory and the electronic device can follow the JEDEC protocol. The memory can include a power module 10, a first interface module 20, a main control module 30, a read-only storage module 40, a random cache unit 50, a mapping cache unit 60, a second interface module 70, a data verification module 80, a cache module 90, a flash module 100, a cache management module 110, etc.

[0022] In some embodiments, the power module 10 can be the power supply of the memory. The power module 10 can be used to receive the power from an external electronic device and provide power supply to each module inside the memory.

[0023] In some embodiments, the first interface module 20 (Universal Asynchronous Receiver / Transmitter, UART) can output the log information of the memory during operation. Developers can obtain the log information of the running state of the memory in real time without affecting the normal operation of the memory.

[0024] In some embodiments, the main control module 30 can be a Microcontroller Unit (MCU). The main control module 30 can be used to execute specific control tasks, such as reading data and processing instructions from the electronic device. The CPU core of the main control module 30 can be designed based on the RISC-V architecture to execute various control and calculation tasks. The main control module 30 may have one CPU core or multiple CPU cores. The CPU core is the basic unit in the main control module 30 that executes instructions and performs operations. Each CPU core can execute tasks independently, and each CPU core has its own registers, ALU (Arithmetic Logic Unit), and cache.

[0025] In some embodiments, the read-only storage module 40 may be a non-volatile memory (Read-Only Memory, ROM) for storing data in the long term. A program, such as firmware, may be stored in the read-only storage module 40. This program may be a set of pre-written instructions that guide the main control module 30 on how to start and run. These instructions include device initialization, peripheral configuration, and a possible Bootloader. The Bootloader can be used to load updated programs or operating systems, etc.

[0026] In some embodiments, the random cache unit 50 may be a volatile memory (Random Access Memory, RAM) for temporarily storing data and program code. The random storage module 50 can be used to temporarily store data. When the main control module 30 executes a program, the program code can be loaded from the read-only storage module 40 into the random storage module 50 for execution.

[0027] In some embodiments, the mapping cache unit 60 (Memory Mapping Table Module) can be used to manage the mapping relationship between virtual memory and physical memory. The mapping cache unit 60 converts a virtual address (used by a program) into a physical address (used by hardware) by maintaining a mapping table, thereby achieving efficient management and protection of memory. The mapping table can be a hierarchical structure (such as a page table) for recording the correspondence between virtual addresses and physical addresses. For example, in a paging mechanism, a virtual address is divided into a page number (Page Number) and an offset within the page. The mapping table looks up the corresponding physical page frame through the page number. When a program accesses a virtual address, the main control module 30 queries the mapping table to find the corresponding physical address. If there is no corresponding entry in the mapping table (i.e., a page fault occurs), a page fault exception will be triggered, and the main control module 30 is responsible for loading the required data from the disk into physical memory and updating the mapping table.

[0028] In some embodiments, the second interface module 70 (interface) can be a transmission interface between the memory and an electronic device. The second interface module 70 can receive instructions transmitted from the electronic device and return data or status information to the electronic device. The second interface module 70 can receive instructions from the electronic device through the CMD line and the DATA line, and return the result data or execution status to the electronic device through the DATA line.

[0029] In some embodiments, the second interface module 70 may include an output cache unit 71 and an input cache unit 72. The output cache unit 71 can be used to temporarily store data prepared by the main control module for sending to an external device (such as data to be written to the flash memory module 100). The input cache unit 72 can be used to temporarily store data received from an external device (such as an electronic device).

[0030] In some embodiments, the data verification module 80 (Error Checking and Correction Unit, ECCU) refers to the module in the memory used to detect and correct data transmission errors. The data verification module 80 can implement functions such as data verification (Error Detection), error correction (Error Correction), and data integrity guarantee. Data verification refers to checking whether errors (such as bit flips) occur during data transmission or storage. Error correction refers to automatically repairing the data if an error is found (such as single-bit error correction and multi-bit error detection). Data integrity guarantee refers to ensuring that the written / read data is consistent with the original data, improving the reliability of the storage system. Since the data verification module 80 takes time for calculation and data cannot be directly streamed, a verification cache unit 81 can be configured in the data verification module 80. The verification cache unit 81 can be used to temporarily store the data to be verified, avoiding waiting for the main control module 30 or the flash memory module 100 during the calculation of the verification code or error correction.

[0031] In some embodiments, the cache module 90 can include a write cache unit (Write Buffer) 91 and a read cache unit (Read Buffer) 92. The write cache unit 91 and the read cache unit 92 can serve as a high-speed temporary storage area between the main control module 30 and the flash memory module 100, used to store the data and instructions frequently accessed by the main control module 30. The write cache unit 91 is mainly to improve the efficiency of data writing and optimize the performance of the write operation. The read cache unit 92 is mainly to increase the speed of data reading and reduce the access to the flash memory module 100.

[0032] In some embodiments, the flash memory module 100 can be the physical unit (nand) in the memory used to store data. The flash memory module 100 can be composed of multiple storage blocks. Each storage block can contain multiple pages (Page). Each page is the minimum unit for read / write operations, while the block is the minimum unit for erase operations. Data is usually read and written in units of pages, while the entire block needs to be erased during erasure.

[0033] Please refer to Figure 1, in some embodiments, in a traditional memory architecture, each cache unit (such as random cache unit 50, mapped cache unit 60, output cache unit 71, input cache unit 72, parity cache unit 81, write cache unit 91, read cache unit 92, etc.) is usually statically assigned to a specific functional module, resulting in low resource utilization. For example, the cache units of some modules may be idle, while other modules may have insufficient cache (such as when the main control module 30 is under high load). The Memory Buffer Management Unit (MBMU) 110 integrates the originally scattered cache units into a unified resource pool through a global scheduling and elastic allocation mechanism to achieve on-demand allocation and load balancing. For example, the cache management module 110 can dynamically allocate the resources of cache units according to real-time host task requirements (such as a high-load module can temporarily occupy the idle cache of other modules).

[0034] Please refer to Figure 1 and Figure 2 , in some embodiments, the main control module 30 can be used to receive host tasks issued by external devices. Each cache unit can correspond to an independent task queue, and the task queue can store the host tasks to be processed and related data. The cache management module 110 can be used to track the working status of the task queues of each cache unit. The cache management module 110 can obtain the working status of the corresponding task queue according to the type of the host task, and allocate the host task according to the working status of the task queue. For example, the cache management module 110 can allocate write tasks to the write cache queue. The cache management module 110 can include a configuration management unit 111, a task queue unit 112, a status management unit 113, a cache monitoring unit 114, a task allocation unit 115, and an interrupt processing unit 116.

[0035] In some embodiments, the configuration management unit 111 can be used to configure and manage cache units, connect all cache units together to achieve interaction between different cache units. Specifically, the configuration management unit 111 can be used to establish a communication link between cache units to support data interaction across cache units (such as temporarily using the ECC cache as a write cache). In some embodiments, the task queue unit 112 can be used to store the task queues corresponding to all cache units, as well as host tasks that are not yet allocated in the cache. Specifically, the task queue unit 112 can be used to maintain an independent task queue for each cache unit (such as a write queue, a read queue, etc.). The task queue unit 112 can also temporarily store host tasks that cannot be immediately allocated because a certain task queue is full, waiting for subsequent scheduling.

[0036] In some embodiments, the status management unit 113 can be used to obtain the working status of the task queue. Specifically, the status management unit 113 can be used to obtain real-time information (such as queue depth, processing progress, etc.) from the task queues of each cache unit. The status management unit 113 can also synchronize the real-time information to the cache monitoring unit 114 and the task allocation unit 115.

[0037] In some embodiments, the cache monitoring unit 114 can be used to monitor the working status of each cache unit and the task queue. Specifically, the cache monitoring unit 114 can monitor how many host tasks are being executed in the task queue of each cache unit, how much free capacity is available in the task queue of each cache unit to cache other host tasks, the total capacity of the task queue of each cache unit, etc.

[0038] In some embodiments, the task allocation unit 115 can be used to determine the working status of the task queue: when the task queue is in an idle state, the host tasks are allocated to the corresponding task queue according to the type until the task queue is in a full-load state; when the task queue is in a full-load state, the unallocated host tasks are allocated to the task queues of other cache units.

[0039] In some embodiments, the interrupt processing unit 116 can be used to issue the corresponding interrupt status bit after each cache unit completes each host task, so as to timely notify the firmware to perform corresponding processing. Specifically, when a cache unit completes a certain host task, a corresponding interrupt signal (such as "write complete" or "ECC check failed") can be generated. Subsequently, the interrupt processing unit 116 can encode the interrupt type (such as success, error, timeout) as an interrupt status bit and notify the firmware for processing.

[0040] In some embodiments, when the main control module 30 has one CPU core and a certain task queue is in a full-load state and the remaining unallocated host tasks cannot be allocated to this task queue, the task allocation unit 115 can determine the working status of the task queues of other cache units: when there is at least one task queue in an idle state, the unallocated host tasks are allocated to the same task queue.

[0041] In some embodiments, when the task allocation unit 115 finds that a certain task queue is in a full-load state (such as the write queue cannot receive new host tasks), the task allocation unit 115 can check the task queue status of other cache units (such as whether the ECC queue is idle), and allocate the unallocated host tasks to the available queue (such as storing the write task in the ECC queue) to wait for processing. Through reallocation, it is ensured that the host tasks can be immediately allocated to the available queue without waiting, and the idle cache units (such as the ECC queue) can be fully utilized, reducing resource waste.

[0042] In some embodiments, when the task allocation unit 115 allocates unallocated host tasks to the same task queue, it can sort the free capacities of all free task queues to obtain the task queue with the largest free capacity; and allocate the unallocated host tasks to the task queue with the largest free capacity. Specifically, the task allocation unit 115 can monitor the status of the task queues of all buffer units in real time, sort the free capacities of all free task queues in descending order to generate a priority list, and then can select the task queue with the largest free capacity as the preferred allocation target. For example, for task queue A (remaining 80%), task queue B (remaining 50%), and task queue C (remaining 30%), at this time, task queue A can be preferentially selected.

[0043] In some embodiments, the task allocation unit 115 can also judge the number of unallocated host tasks and the largest free capacity: when the number of unallocated host tasks is less than or equal to the largest free capacity, all unallocated host tasks are allocated to the task queue with the largest free capacity; when the number of unallocated host tasks is greater than the largest free capacity, part of the unallocated host tasks are allocated to the task queue with the largest free capacity until the task queue with the largest free capacity is full. For example, for task queue A (remaining 80%, can cache 12 host tasks), when the number of unallocated host tasks reaches 20, the first 12 unallocated host tasks can be sequentially allocated to task queue A, and the remaining 8 unallocated host tasks are temporarily stored in the task queue unit 112 for subsequent processing.

[0044] In some embodiments, when the main control module 30 has multiple CPU cores and a certain task queue is full and the remaining unallocated host tasks cannot be allocated to this task queue, the task allocation unit 115 can judge the working status of the task queues of other buffer units: when there is at least one task queue in a free state, the unallocated host tasks are allocated to different task queues.

[0045] In some embodiments, when the main control module 30 adopts a multi-core CPU design (such as a 4-core / 8-core processor), the core challenges faced by the memory include task allocation efficiency, resource competition avoidance, and load balancing. Among them, task allocation efficiency refers to how to utilize the parallelism of multiple CPU cores to accelerate task scheduling. Resource competition avoidance refers to avoiding conflicts caused by multiple CPU cores operating on the same buffer unit simultaneously. Load balancing refers to ensuring that all multiple CPU cores and buffer units work together. For example, the first CPU core can be bound to the task queues of the random buffer unit 50 and the mapping buffer unit 60, and the second CPU core can be bound to the task queues of the output buffer unit 71 and the input buffer unit 72.

[0046] In some embodiments, the task allocation unit 115 may adopt a multi-dimensional weighted dynamic allocation algorithm to achieve intelligent load balancing by comprehensively evaluating the static resource capacity and dynamic processing efficiency of the task queue. The multi-dimensional weighted dynamic allocation algorithm can break through the allocation limitations of traditional single dimensions (such as idle capacity) to ensure the optimal performance of the system in high-throughput and high-concurrency scenarios. Among them, the idle capacity / total capacity can reflect the remaining resource ratio of the task queue (spatial dimension), and the current throughput / average throughput can reflect the processing efficiency of the task queue (temporal dimension). Specifically, when the task allocation unit 115 allocates unassigned host tasks to different task queues, the task allocation unit 115 can obtain the idle capacity, total capacity, current throughput, and average throughput of the task queues in the idle state; among them, the current throughput represents the number of host tasks processed by the cache unit in its task queue per unit time, and the average throughput represents the average value of the number of host tasks processed by all cache units in their task queues per unit time.

[0047] In some embodiments, the task allocation unit 115 may calculate the ratio of the idle capacity to the total capacity and the ratio of the current throughput to the average throughput of each task queue in the idle state, which are respectively denoted as the first ratio and the second ratio. For example, a certain task queue can be allocated 100 host tasks. At this time, 20 host tasks have been allocated in this task queue, and 80 host tasks can still be allocated. Then the first ratio can be 0.8. In unit time, 12 host tasks can be processed in this task queue, and the average value of the host tasks that can be processed by all task queues can be 10. Then the second ratio can be 1.2.

[0048] In some embodiments, the task allocation unit 115 may calculate the sum of the product of the first ratio and the corresponding adjustment coefficient and the product of the second ratio and the corresponding adjustment coefficient, which is expressed as the dynamic weight value. The magnitude of the adjustment coefficient corresponding to the first ratio may not be limited. For example, it can be 0.6; the magnitude of the adjustment coefficient corresponding to the second ratio may not be limited. For example, it can be 0.4; among them, the sum of the two adjustment coefficients needs to be set to 1.

[0049] In some embodiments, the task allocation unit 115 may split the unallocated host tasks according to the dynamic weight values of all the task queues in the idle state, obtaining multiple sets of task sets; a task set may include at least one unallocated host task. For example, if the number of unallocated host tasks is 100 and the dynamic weight values of the task queues in the idle state are 0.8, 0.7, and 0.5 respectively, then the 100 unallocated host tasks need to be split according to the ratio of the dynamic weight values to obtain multiple sets of task sets. Among them, the first set of task sets may include 40 host tasks, the second set of task sets may include 35 host tasks, and the third set of task sets may include 25 host tasks.

[0050] In some embodiments, the task allocation unit 115 may allocate the task sets to the corresponding task queues in the idle state. Through the multi-dimensional weighted dynamic allocation algorithm, the real-time service capabilities of each task queue can be quantitatively evaluated for task allocation.

[0051] In some embodiments, when the task allocation unit 115 allocates some unallocated host tasks to the task queue with the maximum idle capacity and when allocating the task sets to the corresponding task queues in the idle state, there may be some unallocated host tasks. These unallocated host tasks can be temporarily stored in the task queue unit 112. At this time, it is necessary to allocate the host tasks temporarily stored in the task queue unit 112.

[0052] In some embodiments, the task allocation unit 115 may judge the working state of the corresponding task queue according to the task types of the host tasks cached in the task queue unit 112: when the task queue is in the idle state, the cached host tasks are sequentially allocated to the corresponding task queue until the task queue is in the full-load state. By introducing a two-level buffer architecture, the problem of task retention in high-concurrency scenarios is solved. When the first allocation cannot completely consume the tasks, secondary allocation is realized through dynamic state monitoring to ensure the optimal balance of system throughput and resource utilization.

[0053] It can be seen that in the above solution, by breaking the static binding relationship between the cache resources and functional modules in the traditional storage architecture and constructing a global dynamic scheduling system, the efficiency bottleneck problem of the storage system caused by rigid resource allocation is effectively solved, the intelligent cooperation of cache resources across modules and tasks is realized, and the overall system performance and resource utilization are significantly improved. According to the real-time task requirements, the idle cache resources are automatically and dynamically allocated to high-load modules, eliminating the resource waste phenomenon of "unequal workloads" in the traditional architecture. In the single-core scenario, the cache resources are dynamically allocated based on task priorities to avoid resource contention when a single core processes multiple tasks; in the multi-core scenario, through cross-core cache resource sharing and task parallel scheduling, linear scalability is achieved.

[0054] The present invention also provides a task allocation method for a memory. This task allocation method can be applied to the above-mentioned memory, and the task allocation method includes: Receiving a host task through a main control module; The cache management module obtains the working status of the corresponding task queue according to the type of the host task, and allocates the host task according to the working status of the task queue; Executing the host task in the corresponding task queue through a cache unit.

[0055] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: The main control module is used to receive host tasks; A plurality of cache units, for executing host tasks in corresponding task queues; The cache management module is used to obtain the working status of the corresponding task queue according to the type of the host task, and allocate the host task according to the working status of the task queue.

2. The memory according to claim 1, characterized in that: The cache management module includes: A cache monitoring unit, used for obtaining the working status of the corresponding task queue according to the type of the host task; A task allocation unit is used to determine the working status of the task queue: when the task queue is in an idle state, the host task is allocated to the corresponding task queue until the task queue is fully loaded; when the task queue is fully loaded, the unallocated host task is allocated to the task queues of other cache units.

3. The memory according to claim 2, characterized in that: The task allocation unit allocates unallocated host tasks according to the following steps: When the task queue is in a fully loaded state, the working states of the task queues of other cache units are determined: When at least one task queue is in an idle state, the unassigned host tasks are assigned to the same task queue.

4. The memory according to claim 3, characterized in that: The task allocation unit allocates the unallocated host tasks to the same task queue according to the following steps: Sort the free capacities of all idle task queues and obtain the task queue with the largest free capacity; The unassigned host tasks are assigned to the task queue with the largest free capacity.

5. The memory according to claim 4, characterized in that: The task allocation unit allocates the unallocated host tasks according to the following steps: Determine the number of unassigned host tasks and the maximum free capacity: When the number of the unallocated host tasks is less than or equal to the maximum free capacity, allocating all the unallocated host tasks to the task queue with the maximum free capacity; When the number of the unallocated host tasks is greater than the maximum free capacity, some of the unallocated host tasks are allocated to the task queue with the maximum free capacity until the task queue with the maximum free capacity is in a full-load state.

6. The memory according to claim 2, characterized in that: The task allocation unit allocates the unallocated host tasks according to the following steps: When the task queue of a cache unit is fully loaded, determine the working status of the task queues of other cache units: When at least one task queue is in an idle state, the unassigned host tasks are assigned to different task queues.

7. The memory according to claim 6, characterized in that: The task allocation unit allocates the unallocated host tasks to different task queues according to the following steps: Obtain the idle capacity, total capacity, current throughput, and average throughput of the task queue in an idle state; wherein the current throughput represents the number of host tasks in its task queue processed by the cache unit per unit time, and the average throughput represents the average value of the number of host tasks in its task queue processed by all cache units per unit time; Calculate the ratio of the idle capacity to the total capacity and the ratio of the current throughput to the average throughput of each of the idle task queues, and record them as the first ratio and the second ratio respectively; Calculating a sum of a product of the first ratio and a corresponding adjustment coefficient and a product of the second ratio and a corresponding adjustment coefficient, and expressing the sum as a dynamic weight value; Splitting the unassigned host tasks according to the dynamic weight values ​​of all the task queues in the idle state to obtain multiple groups of task sets; the task sets include at least one unassigned host task; The task set is allocated to the corresponding task queue in the idle state.

8. The memory according to any one of claims 3, 5, 6 and 7, characterized in that: The cache management module further includes a task queue unit, and the task queue unit is used to cache unallocated host tasks.

9. The memory according to claim 8, characterized in that: The task allocation unit allocates the host tasks cached by the task queue unit according to the following steps: According to the task type of the cached host task, the working status of the corresponding task queue is determined: When the task queue is in an idle state, the cached host tasks are allocated to the corresponding task queues in order until the task queue is in a full state.

10. A method for allocating tasks of a memory, characterized in that: The memory includes a main control module, a cache management module, and multiple cache units; the task allocation method includes: Receiving host tasks through the main control module; The cache management module obtains the working status of the corresponding task queue according to the type of the host task, and allocates the host task according to the working status of the task queue; The host tasks in the corresponding task queue are executed through the cache unit.

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