Transmit fault feedback scheme for crosstalk reduction

Abstract

The present application is directed to a transmit fault feedback scheme for reducing crosstalk. The memory device may detect an error in the received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum of the received data and may detect a transmit error. The memory device may transmit an indication of a detected error to the controller, and may transmit the indication using a line different from an error detection code (EDC) line. A low speed tracking clock signal may also be transmitted by the memory device via a line different from the EDC line. The memory device may transmit the generated checksum to the controller and apply a time offset to the checksum signaled via the EDC line.

Description

[0001] Relevant information of divisional application

[0002] This is a divisional application. The parent application of this divisional application is a patent application for invention with the application date of August 13, 2019, application number 201980053500.2, and invention title "Transmission Failure Feedback Scheme for Reducing Crosstalk".

[0003] Cross-reference

[0004] This patent application claims priority to PCT Application No. PCT / US2019 / 046400, titled "TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK", filed by Mayer et al. on August 13, 2019, which claims priority to U.S. Patent Application No. 16 / 538,537, titled "TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK", filed by Mayer et al. on August 12, 2019, and U.S. Provisional Patent Application No. 62 / 720,385, titled "TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK", filed by Mayer et al. on August 21, 2018. Each of the foregoing documents is assigned to the assignee hereof and each of the foregoing documents is hereby expressly incorporated by reference in its entirety.

[0005] The technical field relates to a system including at least one memory device, and more particularly to a transmission failure feedback scheme for reducing crosstalk. Background Art

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, a binary device can store one of two states, often represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program the state in the memory device.

[0007] There are different types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memories such as FeRAM can maintain their stored logical states for a long time, even in the absence of an external power supply. Volatile memory devices (e.g., DRAM) may lose their stored states over time unless they are periodically refreshed by an external power supply.

[0008] Memory devices can include various channels for communicating information with other devices (e.g., controllers) within a system. For example, a memory device can use one or more channels to transmit and / or receive data from a controller, but improved signaling between the controller and the memory device may be required for error detection and other functions. Summary of the Invention

[0009] Describe a method. The method can include: receiving data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; receiving, by the memory device via an error detection code (EDC) line coupled to the controller, checksum information of the data received via the plurality of data lines; detecting, by the memory device, an error in the data at least in part based on the checksum information; and transmitting, at least in part based on the detected error, transmit failure information indicating the error in the data to the controller.

[0010] Describe a device. The device can include a processor, a memory electronically connected to the processor, and instructions stored in the memory. The instructions can be executed by the processor to cause the device: to receive data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; to receive, by the memory device via an EDC line coupled to the controller, checksum information of the data received via the plurality of data lines; to detect, by the memory device, an error in the data at least in part based on the checksum information; and to transmit, at least in part based on the detected error, transmit failure information indicating the error in the data to the controller.

[0011] Describe another device. The device may include: means for receiving data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; means for receiving, by the memory device, checksum information of the data received via the plurality of data lines via an EDC line coupled to the controller; means for detecting, by the memory device, an error in the data at least in part based on the checksum information; and means for transmitting, at least in part based on the detected error, fault information indicating the error in the data to the controller.

[0012] Describe a non-transitory computer-readable medium storing code. The code may include instructions that may be executed by a processor to: receive data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; receive, by the memory device, checksum information of the data received via the plurality of data lines via an EDC line coupled to the controller; detect, by the memory device, an error in the data at least in part based on the checksum information; and transmit, at least in part based on the detected error, fault information indicating the error in the data to the controller.

[0013] Describe a method. The method may include: receiving data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; determining, by the memory device, a timing offset for transmitting a checksum of the data; and transmitting the checksum to the controller at a transmission time shifted according to the timing offset.

[0014] Describe a device. The device may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the device to: receive data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; determine, by the memory device, a timing offset for transmitting a checksum of the data; and transmit the checksum to the controller at a transmission time shifted according to the timing offset.

[0015] Describe another device. The device may include: means for receiving data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; means for determining, by the memory device, a timing offset for transmitting a checksum of the data; and means for transmitting the checksum to the controller at a transmission time shifted according to the timing offset.

[0016] Describe a non-transitory computer-readable medium storing code. The code may include instructions that may be executed by a processor to: receive data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; determine, by the memory device, a timing offset for transmitting a checksum of the data; and transmit the checksum to the controller at a transmission time shifted according to the timing offset.

[0017] Describe a method. The method may include: transmitting data to be written to a memory cell array via a plurality of data lines coupled to a memory device; transmitting checksum information of the transmitted data via an EDC line coupled to the memory device; and receiving transmission failure information indicating an error in the data from the memory device at least in part based on the transmitted checksum information.

[0018] Describe a device. The device may include a processor, a memory electronically connected to the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the device to: transmit data to be written to a memory cell array via a plurality of data lines coupled to a memory device; transmit checksum information of the transmitted data via an EDC line coupled to the memory device; and receive transmission failure information indicating an error in the data from the memory device at least in part based on the transmitted checksum information.

[0019] Describe another device. The device may include: means for transmitting data to be written to a memory cell array via a plurality of data lines coupled to a memory device; means for transmitting checksum information of the transmitted data via an EDC line coupled to the memory device; and means for receiving transmission failure information indicating an error in the data from the memory device at least in part based on the transmitted checksum information.

[0020] Describe a non-transitory computer-readable medium storing code. The code may include instructions that may be executed by a processor to: transmit data to be written to a memory cell array via a plurality of data lines coupled to a memory device; transmit checksum information of the transmitted data via an EDC line coupled to the memory device; and receive transmission failure information indicating an error in the data from the memory device at least in part based on the transmitted checksum information.

[0021] Describe a device. The device may include: a memory cell array; a receiver coupled to a plurality of data lines and an EDC line, the receiver being configured to receive data to be written to the memory cell array via the plurality of data lines and receive checksum information regarding the data received via the plurality of data lines; a comparator configured to detect an error in the data at least in part based on the checksum information; and one or more lines coupled to a controller and configured to transmit at least one of a clock signal or transmission failure information indicating an error detected in the data, the one or more lines being different from the EDC line. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Illustrate an example of a system supporting a transmission failure feedback scheme for reducing crosstalk as disclosed herein.

[0023] Figure 2 A block diagram showing an apparatus supporting a transmit fault feedback scheme for reducing crosstalk as disclosed herein.

[0024] Figure 3 An example showing a system supporting a transmit fault feedback scheme for reducing crosstalk as disclosed herein.

[0025] Figure 4 An example showing a system supporting a transmit fault feedback scheme for reducing crosstalk as disclosed herein.

[0026] Figure 5 A process flow in a system supporting a transmit fault feedback scheme for reducing crosstalk as disclosed herein is shown.

[0027] Figure 6 A process flow in a system supporting a transmit fault feedback scheme for reducing crosstalk as disclosed herein is shown.

[0028] Figures 7 to 9 One or more methods supporting a transmit fault feedback scheme for reducing crosstalk as disclosed herein are shown. Detailed Description

[0029] A memory device may communicate with another device (e.g., a controller or a host device such as a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a central processing unit (CPU)) via one or more channels. These channels (e.g., corresponding to conductive lines) may couple pins of the memory device to pins of other devices. For example, these channels may couple data (DQ) pins of the memory device to corresponding pins of other devices and may transfer data between the memory device and other devices via one or more data lines. Thus, these data lines may be used to receive data to be written to a memory cell array at the memory device (e.g., for a write operation) and to transmit data from the memory device to other devices (e.g., for a read operation).

[0030] In some cases, an Error Detection Code (EDC) line can be used to transmit different types of information from a memory device. For example, the EDC line can be used to transmit error detection information (e.g., a checksum) about data received from a controller during a write operation. In such cases, after receiving data to be written to a memory cell array, the memory device can generate a checksum derived from the received data and used to identify transmission errors. This checksum can be transmitted back to the controller via the EDC line, and the controller can then compare the checksum received from the memory device with the checksum information of the transmitted data (e.g., known to the controller before transmission). Based on the comparison of the respective checksums, the controller can determine whether the data received at the memory device has an error, and the controller can retransmit the data in case an error is detected. In other instances, the memory device can use the EDC line to transmit other types of signals (e.g., a clock signal representing the timing of the memory device, a keeper pattern).

[0031] However, the information transmitted via the EDC line can cause interference to one or more signals transmitted on a data channel. For example, the EDC line can be located near one or more data lines (e.g., adjacent to one or more data lines), and data transmission can be affected by crosstalk from various signals transmitted on or associated with the EDC line. This crosstalk can have an unwanted effect on the data received on the data lines by coupling (e.g., capacitively coupling) the EDC signal to the data transmitted on one or more data lines. Thus, an increase in errors in the received data can lead to more frequent rewriting of the data, thereby introducing inefficiencies and latency into the system and its operation.

[0032] As described herein, various techniques can allow information from a memory device to be fed back to another device (e.g., a controller) while reducing or eliminating crosstalk. For example, error information (e.g., information indicating that an error has been detected for the received data) can be transmitted from the memory device when an error is detected in the data, thus reducing the frequency of signaling against the received data (e.g., in the opposite direction of the received data). In some cases, the error information can be transmitted on a line different from the EDC line (e.g., a line located away from the data lines) to reduce or eliminate crosstalk to the data lines.

[0033] At the memory device, transmit error information may be determined by comparing checksum information received from another device (e.g., a controller that transmits data) with a checksum generated by the memory device. Based on the comparison, the memory device may identify an error in the received data and then transmit the transmit error information as needed (e.g., a binary indication sent using one bit). The memory device may also transmit a clock signal (e.g., a low-speed tracking clock) to other devices using a line different from the EDC line, which may be the same as or different from the line used to transmit the transmit error information. Thus, the EDC line may not be used to transmit information from the memory device when receiving data at the memory device, thereby reducing crosstalk from the signaling sent on the EDC line.

[0034] Additionally or alternatively, a delay or timing offset may be introduced into the signaling sent by the memory device on the EDC line, which may also be capable of reducing or eliminating crosstalk. For example, when transmitting a generated checksum to the controller via the EDC line, a fine-tuning offset may be applied to the timing of the checksum transmission. By shifting the signals transmitted on the EDC line in time, crosstalk may be reduced or eliminated via a coherently introduced delay that reduces crosstalk from the EDC signaling on the data received at the memory device. In some cases, the timing offset may be selected (e.g., at power-up) from a determined set of offsets, where the determined offsets may be based on one or more operating conditions of the memory device.

[0035] The present disclosure is described herein Figure 1 at an exemplary memory system hierarchy level in the context of Figure 2 and further described with respect to an exemplary memory device in the context of Figures 3 to 5 Specific examples of systems and techniques for transmitting error feedback are then described in the context of Figure 7 and 8 These and other features of the present disclosure related to a transmit fault feedback scheme for reducing crosstalk are illustrated by flow diagrams of Figure 7 and 8 and described with reference to the flowcharts of

[0036] Figure 1 FIG. 1 shows an example of a system 100 that includes a device supporting a transmit fault feedback scheme for reducing crosstalk, according to an example disclosed herein. System 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 to the memory device 110. System 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0037] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. Memory device 110 may be a system component configured to store data for one or more other components of System 100. In some instances, System 100 is configured to communicate bidirectionally wirelessly with other systems or devices using a base station or an access point. In some instances, System 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0038] At least a portion of System 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to execute processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a notebook computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, etc. In some cases, the host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 105. In some cases, external memory controller 105 may be referred to as the host or host device. In some instances, System 100 is a graphics card.

[0039] In some cases, memory device 110 may be a stand-alone device or component that is configured to communicate with other components of System 100 and provide physical memory addresses / spaces that System 100 may use or refer to. In some instances, memory device 110 may be configurable to work with at least one or more different types of System 100. Signaling between components of System 100 and memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packages for System 100 and memory device 110, clock signaling and synchronization between System 100 and memory device 110, timing conventions, and / or other factors.

[0040] Memory device 110 may support techniques for reducing crosstalk when transmitting or receiving information. As an example, and as described in further detail below, memory device 110 may be configured with channels (e.g., dedicated channels) for a clock signal and / or error indications of received data. In some cases, the channels may be different from EDC channels (e.g., channels for transmitting EDC information). Additionally, memory device 110 may be configured to detect errors in data to be written to the memory cell array, where the error detection may be based on information (e.g., checksum information) received from a device that transmitted the data (e.g., external memory controller 105). In some instances, memory device 110 may also be configured to introduce a timing offset in the signaling transmitted via the EDC channel.

[0041] Memory device 110 may be configured to store data for components of system 100. In some cases, memory device 110 may act as a slave device of system 100 (e.g., responsive to and executing commands provided by system 100 via external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0042] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may be coupled to or in electronic communication with each other using a bus 140.

[0043] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or it may be a combination of these types of components. In such cases, processor 120 may be an example of a CPU, GPU, GPGPU, or system on a chip (SoC), among other examples.

[0044] The BIOS component 125 can be a software component that includes BIOS operating as firmware, which can initialize and run various hardware components of the system 100. The BIOS component 125 can also manage the data flow between the processor 120 and various components of the system 100, such as the peripheral components 130, the I / O controller 135, etc. The BIOS component 125 can include programs or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0045] The peripheral component 125 can be any input device or output device, or an interface for such devices, which can be integrated into or integrated with the system 100. Examples can include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot (e.g., a peripheral component interconnect (PCI) or accelerated graphics port (AGP) slot). The peripheral component 125 can be other components that can be understood by those skilled in the art as peripheral devices.

[0046] The I / O controller 135 can manage data communication between the processor 120 and the peripheral components 13, the input device 145, or the output device 150. The I / O controller 135 can manage peripheral devices that are not integrated into or not integrated with the system 100. In some cases, the I / O controller 135 can represent a physical connection or port to an external peripheral component.

[0047] The input 145 can represent a device or signal that is external to the system 100 and can provide information, signals, or data to the system 100 or its components. This can include a user interface or an interface with other devices or an interface between other devices. In some cases, the input 145 can be a peripheral device interfacing with the system 100 via one or more peripheral components 130, or can be managed by the I / O controller 135.

[0048] The output 150 can represent a device or signal that is external to the system 100 and is configured to receive an output from any of the system 100 or its components. Examples of the output 150 can include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, the output 150 can be a peripheral device interfacing with the system 100 via one or more peripheral components 130, or can be managed by the I / O controller 135.

[0049] The components of system 100 may consist of general or special-purpose circuitry designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements. In some cases, a memory device may include one or more comparators, which may be coupled to a device (e.g., external memory controller 105 or memory device 110) or included in and used by the device to compare error detection information (e.g., checksum) to identify errors in data transmitted within system 100.

[0050] Memory device 110 may include device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection (e.g., grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Refer Figure 2 The characteristics of memory array 170 and / or the memory cells are further described.

[0051] Memory device 110 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as levels, tiers, layers, or dies. A 3D memory device may include any number of stacked memory dies 160-N (e.g., dual, triple, quadruple, quintuple, sextuple, septuple, octuple). This may increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which may in turn reduce production costs, improve the performance of the memory array, or both. In some 3D memory devices, different levels may share at least one common access line, such that some levels may share at least one of a word line, digit line, and / or plate line.

[0052] The device memory controller 155 may include circuitry or components configured to control the operation of the memory device 110. As such, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information regarding the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, the one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105.

[0053] For example, the memory device 110 may receive a write command instructing the memory device 110 to store specific data on behalf of a component of the system 100 (e.g., the processor 120), or a read command instructing the memory device 110 to provide specific data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, etc.

[0054] The local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate with the device memory controller 155 (e.g., receive and transmit data and / or commands). The local memory controller 165 may support the device memory controller 155 in controlling the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include the device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, communicate with other local memory controllers 165, or communicate directly with the external memory controller 105 or the processor 120.

[0055] The external memory controller 105 may be configured to implement the transfer of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110 such that the components of the system 100 need not know the operational details of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 may translate or transcribe the communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0056] In some cases, the external memory controller 105 or other components of the system 100 or its functionality described herein may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, software, or some combination thereof implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functionality described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, software, or some combination thereof implemented by the device memory controller 155 or one or more local memory controllers 165.

[0057] In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110 such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Similarly, in some cases, one or more functions attributed to the device memory controller 155 or the local memory controller 165 herein may, in some cases, be performed by the external memory controller 105 (separate from or included in the processor 120). In some instances, the external memory controller 105 may be configured to receive an indication of an error in data transmitted to and received from the memory device 110. For example, the external memory controller 105 may receive a bit having a binary value that indicates the presence of an error in the data received at the memory device 110. As such, the external memory controller may determine to retransmit the data containing the error based on the received indication.

[0058] The components of system 100 may exchange information with the memory device 110 using multiple channels 115. In some instances, the channels 115 may enable communication between the external memory controller 105 and the memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of system 100. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the external memory controller 105 and one or more pins or pads at the memory device 110. The pins may be examples of conductive input or output points of the devices of system 100, and the pins may be configured to act as part of the channel. In some cases, the pins or pads of the terminals may be part of the signal path of the channel 115. Additional signal paths may be coupled to the terminals of the channel to route signals within the components of system 100. For example, the memory device 110 may include signal paths (e.g., signal paths internal to the memory device 110 or its components, such as within the memory die 160) that route signals from the terminals of the channel 115 to various components of the memory device 110 (e.g., the device memory controller 155, the memory die 160, the local memory controller 165, the memory array 170).

[0059] The channel 115 (and associated signal paths and terminals) may be dedicated to transmitting a particular type of information. In some cases, the channel 115 may be an aggregated channel and may thus include multiple individual channels. For example, a data channel 192 may be x4 (e.g., include four signal paths), x8 (e.g., include eight signal paths), x16 (include sixteen signal paths), etc. In some instances, the channel 115 may correspond to a physical line (e.g., a conductive wire). For example, signaling transmitted between devices may be carried by the channel 115 on one or more conductive wires located within system 100.

[0060] In some cases, the channel 115 may include one or more command and address (CA) channels 186. The CA channels 186 may be configured to transmit commands between the external memory controller 105 and the memory device 110, including control information (e.g., address information) associated with the commands. For example, the CA channel 186 may include a read command regarding the address of the desired data. In some cases, the CA channels 186 may be latched on the rising clock signal edge and / or the falling clock signal edge. In some cases, the CA channels 186 may include eight or nine signal paths.

[0061] In some cases, channel 115 may include one or more clock signal (CK) channels 188. The CK channels 188 may be configured to transmit one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to transition (e.g., oscillate) between a high state and a low state and to coordinate the operations of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., CK_t signal and CK_c signal), and the signal paths of the CK channels 188 may be configured accordingly.

[0062] In some cases, the clock signal may be single-ended. In some cases, the clock signal may be a 1.5 GHz signal. The CK channels 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., CK_t signal and CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110 or for other system-wide operations of the memory device 110. The clock signal CK may thus be alternatively referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.).

[0063] In some cases, channel 115 may include one or more data (DQ) channels 190. The data channels 190 may be configured to transmit data and / or control information between the external memory controller 105 and the memory device 110. For example, the data channels 190 may transmit information to be written to the memory device 110 (e.g., bidirectionally) or information read from the memory device 110. The data channels 190 may transmit signals that may be modulated using a variety of different modulation schemes (e.g., NRZ, PAM4).

[0064] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths. In some cases, the other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally represent "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference typically used for access operations of the memory device 110 (e.g., a timing reference for both read and write operations).

[0065] Therefore, the write clock signal WCK can also be referred to as the data clock signal WCK. The WCK channel can be configured to transmit a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal can be configured to coordinate the access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal can be a differential output (e.g., the WCK_t signal and the WCK_c signal), and the signal path of the WCK channel can be configured accordingly. The WCK channel can include any number of signal paths. The data clock signal WCK can be generated from a data clock, which can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.).

[0066] The channel 115 can couple the external memory controller 105 and the memory device 110 using various different architectures. Examples of various architectures can include buses, point-to-point connections, crossbar switches, high-density interposers such as silicon interposers, or channels formed in an organic substrate, or a combination thereof. For example, in some cases, the signal path can at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0067] The signals transmitted through the channel 115 can be modulated using a variety of different modulation schemes. In certain cases, a binary symbol (or binary level) modulation scheme can be used to modulate the signals transmitted between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme can be configured to represent one bit of digital data (e.g., the symbol can represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include (but are not limited to) non-return-to-zero (NRZ), unipolar coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and so on.

[0068] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals transmitted between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an instance of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include (but are not limited to) PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and the like. A multi-symbol signal or a PAM4 signal may be a signal modulated using a modulation scheme that includes at least three levels for encoding more than one bit of information. The multi-symbol modulation scheme and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0069] In some cases, other channels 192 may include one or more EDC channels. The EDC channels may be configured for multiple functions, such as error correction during read and write operations, and feedback regarding timing shifts in the memory device 110 during read operations. For example, the EDC lines may be used to transmit back a checksum (e.g., a cyclic redundancy check (CRC) checksum) of data written to the memory device 110. In such cases, an 8-bit checksum may be generated by the memory device 110 for eight (8) data bits received via one or more data channels 190 (or data lines). In other cases, data received on multiple data channels 190 or during one or more data bursts may be combined when generating the checksum.

[0070] In any case, the memory device 110 may provide the generated checksum to the external memory controller 105 (e.g., a GPU) via an EDC pin. The external memory controller 105 may likewise generate a checksum of the transmitted data and determine whether the data was correctly received at the memory device 110 based on a comparison between the checksums. If an error is detected, any data containing the error may be retransmitted to the memory device 110 to rewrite the information regarding the error.

[0071] In the absence of checksum data to be provided to the external memory controller 105, the EDC lines may alternatively be used to transmit timing signals (e.g., clock-like patterns) to the external memory controller 105 for tracking the timing of the memory device 110. Such clock-like patterns may include a hold pattern (e.g., an EDC hold pattern) driven by the EDC signaling and defined by one or more mode register settings (e.g., the number of bits in the mode register may define the hold pattern). The hold pattern may include a certain number of bits (e.g., four (4) bits), which may be repeatedly / continuously transmitted by the memory device 110 for clock and data recovery operations.

[0072] In some cases, the timing of memory device 110 may be affected by changes in temperature or supply voltage and other parameters, which may cause variations in the operation of memory device 110 (e.g., increased voltage noise (e.g., due to thermal agitation of charge carriers), temperature-induced jitter). As such, the clocking pattern or clock signal of memory device 110 may drift with changes in temperature and / or supply voltage, causing the data eye position to shift away from the trained (e.g., optimal) data eye position, potentially increasing the probability of transmission errors.

[0073] In such cases, based on the transmitted (e.g., via the EDC channel) clock signal, external memory controller 105 may determine whether retraining is needed to account for the shift in the timing of memory device 110, or whether a timing offset on the read data received from memory device 110, for example, needs to be applied. Accordingly, the clocking pattern transmitted by memory device 110 via the EDC pin enables external memory controller 105 to recognize and adapt to changes in memory timing and other conditions.

[0074] However, the EDC signal from memory device 110 may interfere with the relatively weak data signal of external memory controller 105 at the receiver proximate to memory device 110. For example, the EDC line may be located between or near one or more data lines (e.g., corresponding to data channel 190). Crosstalk may affect the data received at memory device 110 when the checksum information or clocking pattern is transmitted on the EDC line that extends across the data transmitted on one or more data lines (in its opposite direction).

[0075] As an example, a gapless write cycle may use continuous data transfer from the EDC line in the direction opposite to the one or more data lines (e.g., and at the same rate as the transmitted data). If the EDC line drives signaling away from memory device 110 simultaneously or in parallel (or at nearly the same time) as data is latched in memory device 110, interference may occur on one or more data channels (e.g., near-end crosstalk, also referred to as backward crosstalk).

[0076] Crosstalk can be referred to as a signal that inadvertently affects other signals (e.g., nearby signals) within a system via electromagnetic effects, and can correspond to the coupling of one signal to another (e.g., where two or more signals can be coupled such that a change in one signal can unexpectedly affect and be observed in another signal). The coupling can include capacitive, inductive, and / or conductive coupling between signals, and can also include substrate coupling of signals (e.g., coupling signals via the substrate of an integrated circuit). Additionally, crosstalk can be described in terms of an "aggressor" signal affecting a "victim" signal, where the "victim" signal can be, for example, the weaker of the two (e.g., lower power). Crosstalk can occur in some systems that use high-frequency transmissions, and crosstalk can introduce unwanted interference into system 100, degrading the quality and efficiency of the transmitted information.

[0077] In some cases, crosstalk caused by EDC signaling can create a trade-off between using EDC lines in the presence of crosstalk and avoiding using EDC lines altogether. For example, the transmission of checksum information can interrupt the system to such a point that the execution of periodic retraining may be more efficient (e.g., every 300 microseconds (μs)) than using EDC lines for error correction and timing tracking. Thus, the negative effects of crosstalk from EDC signaling can be so large that periodic retraining (and any associated efficiency loss) may be more advantageous than operating without error detection capabilities (e.g., when EDC pins are avoided altogether). In such cases, the external memory controller 105 can perform one or more actions (e.g., a sequence of steps) to synchronize the clocks of the external memory controller 105 and the memory device 110, and can further determine the data eye positions for the input and output of the memory device 110. For example, retraining can include modifying the delay in the clock signal transmitted via the CK channel 188 to align the corresponding clocks and identify the time delays associated with one or more read and / or write operations. In some cases, various commands can then be signaled to the memory device 110 to determine the data eye positions.

[0078] System 100 can support techniques for reducing or eliminating crosstalk between different channels 115, such as those described herein with reference to signaling transmitted via the EDC channel. As an example, the memory device 110 can detect errors in the received data and transmit an indication of the error when detected, thereby reducing the frequency of error detection feedback from the memory device 110. In such cases, the error detection process can be performed at the memory device 110 rather than at the external memory controller 105.

[0079] For example, a memory device may receive data via data channel 190 and may also receive checksum information for the data via the EDC channel. In such cases, the data and the checksum information may be transmitted from the external memory controller 105 to the memory device 110 simultaneously (e.g., in parallel) and in the same direction (e.g., from one device to another device). The memory device 110 may accordingly generate a checksum for the received data and may detect a transmission error, for example, by comparing the generated checksum with the checksum information received from the external memory controller 105. The memory device 110 may then transmit an indication of an error detected in the received data to the external memory controller 105, and the indication (e.g., a single bit) may be transmitted using a line different from the EDC line.

[0080] In some cases, a low-speed tracking clock signal may alternatively or additionally be transmitted by the memory device 110 via a line different from the EDC line. For example, to avoid using signaling on the EDC line of the received data, the memory device 110 may transmit a clock signal or a clock-like pattern on a different line located away from the data lines to eliminate crosstalk on one or more nearby data lines. A reduced rate of the clock-like pattern (e.g., compared to the data transfer rate of the system 100) may further reduce crosstalk in the system 100. Additionally, the low-speed tracking clock signal may be a low-voltage differential signal that enables further reduction of crosstalk in the system 100.

[0081] Alternatively or additionally, the memory device 110 may transmit the generated checksum to the external memory controller 105 and have a time offset applied to the checksum signaled via the EDC line. For example, the EDC signaling may be delayed to provide an offset between the edge transmitted on the data line and the EDC line. A particular offset in the EDC signaling may be selected from a set of offsets that may be determined (e.g., calculated) based on operating conditions at the memory device 110.

[0082] The described techniques for reducing crosstalk in the system 100 may be used individually, in combination, or both at different times. For example, transmitting a low-speed clock signal via a line different from the EDC line may be advantageous in some cases, while reducing the swing of the EDC signaling or adding a timing offset to the EDC signaling may be preferred in other cases. Implementing the described solutions may save resources (e.g., printed circuit board (PCB) space) by using one or more of the described solutions, where the circuitry for one or more of these techniques may be included on the PCB.

[0083] Figure 2 An example of a memory die 200 that supports a transmit fault feedback scheme for reducing crosstalk in accordance with examples disclosed herein is shown. The memory die 200 may be a reference Figure 1An example of the described memory die 160. In some situations, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, a memory cell 205 may be configured to store one bit of digital logic at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0084] The memory cell 205 may store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor that includes a dielectric material to store charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, non-linear dielectric materials may be employed.

[0085] Operations such as reading and writing may be performed on the memory cell 205 by activating or selecting access lines such as word lines 210 and / or digit lines 215. In some cases, the digit line 215 may also be referred to as a bit line. References to access lines, word lines, and digit lines or the like may be used interchangeably without affecting understanding or operation. Activating or selecting the word line 210 or the digit line 215 may include applying a voltage to the corresponding line.

[0086] The memory die 200 may include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid pattern. The memory cells 205 may be located at the intersections of the word lines 210 and the digit lines 215. By biasing the word lines 210 and the digit lines 215 (e.g., applying a voltage to the word line 210 or the digit line 215), a single memory cell 205 may be accessed at their intersection.

[0087] Access to the memory cells 205 can be controlled by the row decoder 220 or the column decoder 225. For example, the row decoder 220 can receive a row address from the local memory controller 260 and activate the word line 210 based on the received row address. The column decoder 225 can receive a column address from the local memory controller 260 and can activate the digit line 215 based on the received column address. For example, the memory die 200 can include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, by activating the word line 210 and the digit line 215, such as WL_1 and DL_3, the memory cell 205 at their intersection can be accessed. The intersection of the word line 210 and the digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of the memory cell 205.

[0088] The memory cell 205 can include a logic storage component, such as a capacitor 230 and a switching component 235. The capacitor 230 can be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of the capacitor 230 can be coupled to the switching component 235, and a second node of the capacitor 230 can be coupled to a voltage source 240. In some cases, the voltage source 240 is grounded, such as Vss. In some cases, the voltage source 240 can be an example of a plate line coupled to a plate line driver. The switching component 235 can be an example of a transistor or any other type of switching device that selectively establishes or stops the electrical connection between two components.

[0089] Selecting or deselecting the memory cell 205 can be achieved by activating or deactivating the switching component 235. The capacitor 230 can be electrically connected to the digit line 215 using the switching component 235. For example, the capacitor 230 can be isolated from the digit line 215 when the switching component 235 is deactivated, and the capacitor 230 can be coupled to the digit line 215 when the switching component 235 is activated. In some cases, the switching component 235 is a transistor and its operation can be controlled by applying a voltage to the transistor gate, where the voltage difference between the transistor gate and the transistor source can be greater than or less than the threshold voltage of the transistor. In some cases, the switching component 235 can be a p-type transistor or an n-type transistor. The word line 210 can be electrically connected to the gate of the switching component 235, and the switching component 235 can be activated / deactivated based on the voltage applied to the word line 210.

[0090] The word line 210 can be a conductive wire that is electronically connected to the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 can be electronically connected to the gate of the switching component 235 of the memory cell 205 and can be configured to control the switching component 235 of the memory cell. In some architectures, the word line 210 can be electronically connected to the node of the capacitor of the memory cell 205, and the memory cell 205 may not include a switching component.

[0091] The digit line 215 can be a conductive wire connecting the memory cell 205 and the sensing component 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during a portion of the access operation. For example, the word line 210 and the switching component 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be electronically connected (e.g., constantly) to the digit line 215.

[0092] The sensing component 245 can be configured to detect the state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be extremely small. Thus, the sensing component 245 can include one or more sense amplifiers to amplify the signal output by the memory cell 205. The sense amplifier can detect small changes in the charge of the digit line 215 during a read operation and can generate a signal corresponding to logic state 0 or logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 can output (e.g., discharge) a signal to its corresponding digit line 215. The signal can cause the voltage of the digit line 215 to change.

[0093] The sense component 245 can be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 250 (e.g., a reference voltage). The sense component 245 can determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a voltage higher than the reference signal 250, the sense component 245 can determine that the storage state of the memory cell 205 is logic 1, and if the digit line 215 has a voltage lower than the reference signal 250, the sense component 245 can determine that the storage state of the memory cell 205 is logic 0. The sense component 245 can include various transistors or amplifiers to detect and amplify the differences in the signals. The detected logic state of the memory cell 205 can be output as an output 255 by the column decoder 225. In some cases, the sense component 245 can be part of another component (e.g., the column decoder 225, the row decoder 220). In some situations, the sense component 245 can be electronically connected to the row decoder 220 or the column decoder 225.

[0094] The local memory controller 260 can control the operation of the memory cell 205 via various components (e.g., the row decoder 220, the column decoder 225, and the sense component 245). The local memory controller 260 can be an example of the local memory controller 165 described in the reference Figure 1 In some cases, one or more of the row decoder 220, the column decoder 225, and the sense component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be configured to receive commands and / or data from the external memory controller 105 (or the device memory controller 155 described in the reference Figure 1 translate the commands and / or data into information that the memory die 200 can use, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations.

[0095] The local memory controller 260 can generate row and column address signals to activate the target word line 210 and the target digit line 215. The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein can be adjusted or varied and can be different for the various operations discussed in operating the memory die 200.

[0096] In some instances, the local memory controller 260 may detect an error in data received during an access operation (e.g., a write operation). For example, the local memory controller may compare checksum information of data to be written to the memory cell 205, where the checksum associated with the data may be generated by the local memory controller 260 and may be compared to a checksum generated prior to transmitting the data (e.g., as provided by another device). Based on the comparison, an error may be detected in the case where the respective checksums are different, indicating that the received data is different from the transmitted data. In the case where an error is detected in the received data, the local memory controller 260 may transmit an indication indicating the error to other devices, which may trigger a retransmission of the data. In other cases, there may be no error detected via the checksum comparison (e.g., the checksums are the same), and the local memory controller 260 may continue with the access operation using the received data.

[0097] In some cases, the local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During the write operation, the memory cells 205 of the memory die 200 may be programmed to store the desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cells 205 on which the write operation is to be performed. The local memory controller 260 may identify the target word line 210 and the target digit line 215 that are electronically connected to the target memory cells 205 (e.g., the address of the target memory cells 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cells 205. The local memory controller 260 may apply a specific signal (e.g., a voltage) to the digit line 215 during the write operation to store a specific state (e.g., a charge) in the capacitor 230 of the memory cell 205, and the specific state (e.g., the charge) may indicate the desired logical state.

[0098] In some cases, the local memory controller 260 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cells 205 on which the read operation is to be performed. The local memory controller 260 may identify the target word line 210 and the target digit line 215 that are electronically connected to the target memory cells 205 (e.g., the address of the target memory cells 205).

[0099] The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 can transfer a signal to the sensing component 245 in response to a biased access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate the sensing component 245 (e.g., latch the sensing component), and thereby compare the signal received from the memory cell 205 with the reference signal 250. Based on the comparison, the sensing component 245 can determine the logical state stored on the memory cell 205. The local memory controller 260 can transfer the logical state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155) as part of a read operation.

[0100] In some memory architectures, accessing the memory cell 205 may degrade or destroy the logical state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or fully discharge the capacitor of the target memory cell. The local memory controller 260 can perform a rewrite operation or a refresh operation to restore the memory cell to its original logical state. The local memory controller 260 can rewrite the logical state to the target memory cell after a read operation. In some cases, the rewrite operation can be considered part of the read operation. Additionally, activating a single access line (e.g., the word line 210) may interfere with the states stored in some memory cells that are electronically connected to the access line. Thus, a rewrite operation or a refresh operation can be performed on one or more memory cells that may not have been accessed.

[0101] The memory die 200 shows a two-dimensional (2D) memory cell array. In some cases, the memory device can include a three-dimensional (3D) array or memory cells. The 3D memory array can include two or more 2D memory arrays stacked on top of each other. In some cases, the 2D memory arrays in the 3D memory array can be referred to as levels, tiers, layers, or dies. The 3D memory array can include any number of stacked 2D memory arrays (e.g., dual, triple, quadruple, quintuple, sextuple, septuple, octuple). Compared with a single 2D memory array, this can increase the number of memory cells that can be positioned on a single die or substrate, which in turn can reduce the production cost or improve the performance of the memory array, or both. In some 3D memory arrays, different levels can share at least one common access line, such that some levels can share at least one of the word line 210 or the digit line 215.

[0102] Figure 3An example of a system 300 that supports a transmit fault feedback scheme for reducing crosstalk, in accordance with the examples disclosed herein, is shown. The system 300 may include a controller 305 and a memory device 310, each of which may implement aspects of the described techniques. For example, the controller 305 may be an example of an external memory controller 105 as described herein (e.g., a GPU, GPGPU, CPU, etc.). Additionally, the memory device 310 may be an example of a memory device 110 as referenced Figure 1 and described (e.g., a graphics double data rate (GDDR) memory device). Figure 1 and 2 The controller 305 and the memory device 310 are shown in an example of the system 300 that are coupled to each other via multiple lines (e.g., data lines 315-a and 315-b, and EDC line 320), where each line may correspond to a channel 115, as referenced

[0103] and described. It should be understood that the controller 305 and the memory device 310 may be coupled to each other and may exchange signals via any number of lines. Figure 1 and described. It should be understood that the controller 305 and the memory device 310 may be coupled to each other and may exchange signals via any number of lines.

[0104] For example, the controller 305 and the memory device 310 may be coupled via one data line 315 or via multiple data lines 315 (e.g., above the data line 315-a and / or below the data line 315-b, as depicted Figure 3 in). Each of the data lines 315 and the EDC line 320 may be a unidirectional or multi-directional line for communication between the controller 305 and the memory device 310.

[0105] In some cases, the data lines 315-a and 315-b may be examples of conductive lines corresponding to data channels (e.g., data channel 190, as referenced Figure 1 and described), and the EDC line 320 may correspond to an EDC channel as referenced Figure 1 and described. As such, the controller 305 may drive or transmit signals on each of the data lines 315 using one or more transmitters 325. For example, the first transmitter 325-a or another transmitter 325-c or both may be configured to transmit data to be written to a memory cell array (e.g., a memory array 170 as referenced Figure 1 and described) at the memory device 310.

[0106] In addition, the controller 305 may include a second transmitter 325-b configured to transmit information on the EDC line 320. The memory device 310 may include one or more receivers 330 (e.g., receivers 330-a, 330-b, and 330-c) configured to receive signals transmitted by the controller 305. As shown, the EDC line 320 may be located between the data lines 315-a and 315-b. Thus, signaling sent from the memory device 310 to the controller 305 via the EDC line 320 may cause crosstalk on one or more data lines 315 (e.g., data line 315-a or data line 315-b or other data lines 315 not shown or any combination thereof).

[0107] In some aspects, the system 300 may implement techniques to reduce or eliminate crosstalk from the EDC line 320 to the data lines 315. For example, the controller 305 may provide checksum information (e.g., CRC checksum) of data transmitted via one or more data lines 315 (e.g., for a write operation from the controller 305 to the memory device 310). That is, the controller 305 may perform a checksum calculation on the data to be transmitted, and the controller 305 may provide the checksum information along with the data. The checksum information may be transmitted to the memory device 310 via the EDC line 320. In these cases, the signaling on the EDC line 320 (from the controller 305 to the memory device 310) may be aligned in time with the data transmitted on the data lines 315. Thus, the signaling being sent in the same direction as the data may achieve reduced crosstalk at the memory device 310 and thus fewer errors in the data to be written to the memory cell array.

[0108] In addition, the memory device 310 may generate a checksum of the received data and may identify errors in the received data. That is, the checksum comparison may be directly performed by the memory device 310. In certain cases, the memory device 310 may include a comparator 335 for comparing the checksum of the received data with the checksum received from the controller 305.

[0109] In the event that a fault is identified in the received data, the memory device 310 may transmit an indication to the controller 305 to request rewriting of the data with an error (e.g., the data where the fault occurred). In some instances, the indication of the faulty data may be transmitted by the memory device 310 using the EDC line 320. Additionally or alternatively, the memory device 310 may include a transmitter 340 that receives an indication of the faulty data (e.g., from the comparator 335) and may in turn send information about the transmission fault to the controller 305 (e.g., via the error feedback line 345). For example, the error feedback line 345 may include additional signal lines on the die or substrate separate from the EDC line 320, and the error feedback line 345 may be configured for (e.g., dedicated to) the transmission of error feedback information (e.g., transmission error information). In some instances, the error feedback line 345 may be a Joint Test Action Group (JTAG) signal line or another line different from the EDC line.

[0110] In some instances, the transmission fault information may include a single bit having a binary value (e.g., 0 or 1) that serves as a flag that the data received from the controller 305 has faulted (e.g., the compared checksums are different). The single data bit may verify (or correspond to) the completed write process, which may eliminate per-byte or per-bit information fed back to the controller 305 (e.g., since the rewrite operation may rewrite an entire data burst) and thus reduce crosstalk for the signaling sent via the EDC line 320. In some instances, the indication transmitted with the transmission error information may not be transmitted as frequently as the continuous checksum transmission from the memory device 310 to the controller 305.

[0111] In certain cases, the number of errors may be relatively low (e.g., partly due to the reduced return signaling from the memory device 310), and any crosstalk that may be caused by the infrequent return signaling (using the EDC line 320 or the error feedback line 345 or both) may be correspondingly minimized. In some aspects, the binary indication may provide feedback (e.g., continuous feedback) to the controller 305 regarding whether the transmitted data was received correctly, which may enable the controller 305 to monitor the status of the data sent to the memory device 310.

[0112] Additionally or alternatively, a low-density (e.g., low-frequency) clock signal can be used for timing tracking between the feedback memory device 310 and the controller 305. In such cases, the clock 350 can transmit the clock signal to the controller 305 using a timing feedback line 355 different from the EDC line 320. In such cases, the frequency of the clock signal driven by the clock 350 (e.g., the number of edges) can be less than the frequency of the clock signal or clock-like pattern transmitted via the EDC line 320. For example, the frequency of the clock signal can be reduced (e.g., by a factor of 10), such that fewer edges are transmitted from the memory device 310 to the controller 305, and thus crosstalk in the system 300 is reduced. In some cases, the clock signal can include a hold pattern (e.g., a clock-like signal) of the number of bits repeated by the memory device 310 (e.g., for providing feedback on the timing of the memory device 310).

[0113] In some cases, the clock signal driven by the clock 350 can be a differential signal with a low voltage swing (e.g., compared to the voltage swing of other signals transmitted within the system 300). For example, the clock signal can be a low-swing differential clock signal (e.g., according to an industry standard or specification such as the Joint Electron Device Engineering Council (JEDEC) standard or the Low Voltage Differential Signaling (LVDS) standard), which can have a low voltage swing (e.g., the difference between the maximum output voltage and the minimum output voltage), operate at low power, run at high speed, and transmit information using the difference between the voltages on a pair of wires or lines. Such signals can use a fraction of the voltage swing of other signals used within the system, but can still achieve high data rates and low power consumption. Thus, by reducing the voltage swing of the clock signal, or reducing the number of edges of the tracking clock signal from the memory device 310, or transmitting the signal on the timing feedback line 355, or any combination thereof, crosstalk within the system 300 can be reduced.

[0114] In some cases, any combination of lines may be used by the memory device 310 when sending transmit error messages or clock signals or both. For example, the corresponding lines (e.g., both the error feedback line 345 and the timing feedback line 355) may be used for the corresponding signals sent by the memory device 310, as shown in system 300. In such instances, the individual lines may be driven at different speeds, or the signals sent on the corresponding lines may be different, or a combination thereof. For example, errors in the received data may occur less frequently than the clock signal driven by clock 350, and the clock signal may be sent on the timing feedback line 355 with a lower voltage swing compared to the transmit error message sent on the error feedback line 345. In other instances, the various lines may be used independently or dynamically to switch between different functionality and feedback schemes. In these cases, the memory device 310 may use the error feedback line 345 or the timing feedback line or the EDC line 320 or any combination thereof, based on one or more conditions, to transmit information to the controller 305.

[0115] Additionally or alternatively, a single line different from the EDC line 320 may be used to transmit a low-speed clock and error feedback reports. That is, different types of information may be sent using the same signal. In these cases, different encoding / decoding schemes may be applied to each type of information. For example, the clock signal may use a first type of encoding, and if a fault in the received data is detected, a different encoding (e.g., a longer 0 phase or a longer 1 phase) may be used to transmit the error message, such that the controller 305 can identify the difference between a change in the clock signal and an indication of an error in the received data. Thus, the error feedback information may be embedded in the low-speed clock signal, and the controller 305 may decode the different types of signals according to the decoding scheme.

[0116] Figure 4 An example of a system 400 that supports a transmit fault feedback scheme for reducing crosstalk, in accordance with the examples disclosed herein, is shown. System 400 may include a controller 405 and a memory device 410, each of which may implement aspects of the described techniques. For example, the controller 405 may be an example of an external memory controller 105 (e.g., a GPU), as described herein with reference to Figure 1 what is described. Additionally, the memory device 410 may be an example of a memory device 110 (e.g., a GDDR memory device), as referenced Figures 1 to 3 what is described.

[0117] The controller 405 and the memory device 410 are shown in an example of system 400 as being coupled to each other via multiple lines (e.g., data lines 415-a and 415-b, and an EDC line 420), where each line may be or correspond to a channel 115, as referenced Figure 1as described. It should be understood, however, that the controller 405 and the memory device 410 may be coupled to each other and may exchange signals via any number of lines or channels 115. For example, the controller 405 and the memory device 410 may be coupled via one data line 415 or via multiple data lines 415 (e.g., located above the data line 415-a and / or below the data line 415-b, as Figure 4 depicted in

[0118] Each of the data lines 415 and the EDC lines 420 may be a unidirectional or multi-directional line for communication between the controller 405 and the memory device 410. In some cases, the data lines 415-a and 415-b may be or correspond to data channels (e.g., data channel 190, as referenced Figure 1 as described), and the EDC line 420 may be or correspond to an EDC channel as referenced Figure 1 as described. As such, the controller 405 may drive or transmit signals on each of the data lines 415 using one or more transmitters 425.

[0119] For example, the first transmitter 425-a or the second transmitter 425-b or both may be configured to transmit data to be written to a memory cell array (not shown) at the memory device 410. The memory device 410 may include one or more receivers 430 (e.g., including the first receiver 430-a and the second receiver 430-b) configured to receive signals transmitted by the controller 405. As shown, the EDC line 420 may be located between the data line 415-a and the data line 415-b. As such, the signaling sent from the memory device 410 to the controller 405 via the EDC line 420 may create crosstalk on one or more of the data lines 415 (e.g., the data line 415-a or the data line 415-b or another data line 415 not shown or any combination thereof).

[0120] In some cases, the system 400 may implement techniques to reduce or eliminate crosstalk 435 from the EDC line 420 to the data line 415. For example, the memory device 410 may shift an aggressor signal (e.g., transmitted via the EDC line 420) in time relative to a victim signal (e.g., on an adjacent data line) to reduce crosstalk in the system 400. For example, a timing offset (or programmable delay) may be added to the EDC feedback path (corresponding to the EDC pin) from the memory device 410 to the controller 405. The timing offset on the EDC path may shift or adjust the edge of the EDC signal relative to the edge of the signal received via the data line 415.

[0121] Accordingly, the timing offset can adjust the timing of the EDC signaling (e.g., checksum information, transmit error information, timing signals, clock patterns) from the memory device 410 such that the crosstalk 435 experienced on the data lines 415-a and 415-b can be minimized and the data eye can be optimized accordingly. Specifically, by offsetting the edges of the data signal transmitted on the data line 415 and the edges of the information transmitted on the EDC line 420, the coupling between the two signals can be minimized, thereby minimizing the interference from the crosstalk 435.

[0122] As an illustrative example, the memory device 410 can calculate a checksum 440 using the data received on one or more data lines 415. The checksum can thus have a timing offset 445 (or programmable delay (d)) applied before transmission. For example, the time offset can be introduced into the signal using one or more inverters. However, it should be understood that any method for introducing a delay into the transmit path can be used. The offset signal (e.g., the signal to which the timing offset has been applied) can then be transmitted to the controller 405 via the EDC line 420 using the transmitter 450.

[0123] In some cases, the timing offset applied to the EDC signaling can be selected from a set of predefined timing offsets. For example, the memory device 410 can support multiple timing offsets that can be applied to the EDC signal, and the various timing offsets can be stored at the memory device 410 by a mode register. In such cases, one or more mode registers used by the memory device 410 can define different timing offsets, and different delay steps or offsets can be selected, which can, for example, select (e.g., add) or deselect (e.g., remove) inverters from the transmit path to apply the desired delay. That is, the transmit path can have a set of inverters that can be dynamically selected to achieve a programmable delay in the signaling. Thus, the timing of the EDC signaling can be shifted in time relative to the timing of the data transmission on the one or more data lines 415.

[0124] The predefined timing offset can be configured based on various conditions at the memory device 410. For example, various EDC output timings can be configured to achieve the lowest crosstalk 435 (and corresponding maximum data eye) from the EDC signal based on array-specific conditions of the memory device 410.

[0125] For example, the timing offset may be configured based on the speed at which system 400 is operating (e.g., operating speed, clock speed) or the temperature at which system 400 is operating. In some cases, a certain amount of capabilities may be stored in a mode register (e.g., drive strength of an off-chip driver (OCD), termination offset), which may be adjusted based on various conditions at the memory device 410, and these capabilities may be modified to find a timing offset that minimizes crosstalk. In some instances, a predefined timing offset may be stored in the BIOS and loaded into the mode register after system startup. Thus, when system 400 starts up, the drive strength and termination offset may be recognized, and a preferred timing offset may be selected from the mode register based on (among other things) these parameters, and the preferred timing offset may be used to minimize crosstalk 435.

[0126] Figure 5 FIG. 500 shows a process flow that supports an emission fault feedback scheme for reducing crosstalk in accordance with the examples disclosed herein. In some instances, aspects of the process flow 500 may be implemented by a controller 505 and a memory device 510, which may be examples of the corresponding devices described with reference to Figures 1-4 described. For example, the controller 505 may be an example of the external memory controller 105 described with reference to Figure 1 (e.g., a GPU). Additionally, the memory device 510 may be an example of the memory device 110 described with reference to Figure 1 described. The process flow 500 may show the use of one or more channels different from the EDC channel used to transmit EDC feedback information to the controller 505.

[0127] For example, at 515, via one or more data channels (e.g., corresponding to data lines) coupled to the memory device 510, the controller 505 may transmit and the memory device 510 may receive data to be written to the memory cell array. In some cases, the data may be transmitted via a common data channel coupling the controller 505 and the memory device 510. In some instances, the one or more data channels may be examples of the data channels 190 described herein and may be unidirectional or bidirectional data channels.

[0128] At 520, the controller 505 may transmit and the memory device 510 may receive checksum information for the transmitted data. In some cases, the checksum information may be transmitted via an EDC channel (e.g., corresponding to a data line) coupled to the memory device 510.

[0129] At 525, the memory device 510 may generate a checksum of the data received via each of the one or more data channels. For example, the memory device 510 may generate the checksum by dividing a set of bits representing the received data and a set of bits representing a generator polynomial, where the remainder of the operation may include the checksum. In some cases, the checksum may be generated using software or hardware.

[0130] At 530, the memory device 510 may compare the generated checksum of the received data with the received checksum information. In some cases, due to techniques implemented in the system to reduce crosstalk by reducing or modifying the feedback signaling made by the memory device 510, and as described herein with reference to Figure 3 what is described, errors detected via the comparison may be relatively infrequent. If no error is detected in the received data, the data may be written to the memory cell array at the memory device 510.

[0131] However, in some cases, the memory device 510 may detect an error in the data at 535 based on the checksum information. For example, detecting the error may be based on a comparison of the generated checksum of the received data with the received checksum information. If the compared checksums are different, an error in the received data may be identified. Thus, the memory device 510 may calculate the difference between the generated checksum and the received checksum information based on comparing the respective checksums to identify a fault in the received data.

[0132] At 540, based on detecting an error in the received data, the memory device 510 may transmit transmit fault information indicating the error in the data to the controller 505. In some cases, the transmit fault information may be transmitted via a first channel coupled to the controller 505, where the first channel is different from the EDC channel.

[0133] Additionally or alternatively, the transmit fault information may be transmitted via the EDC channel. In cases where the EDC channel is not in use, the memory device 510 may block transmitting information to the controller 505 via the EDC channel to further minimize or eliminate crosstalk in the system. In some instances, the indication may include a logical value (e.g., a single bit providing a 1 or 0), and / or may indicate to the controller 505 whether the data transmitted at 515 was successfully received without error. As an example, a logical value of 1 (or alternatively, 0) may act as a flag for the controller 505 that the data received at the memory device 510 has failed.

[0134] At 545, the memory device 510 may also transmit a clock signal via a second channel coupled to the controller 505. The second channel may also be different from the EDC channel, and the clock signal may have a frequency different from (e.g., lower than) the frequency of the received data. In other words, the clock signal may be a low-speed tracking clock signal (e.g., a low-swing differential signal or a hold pattern or both), and may be used by the controller 505 to track the timing of the memory device 510.

[0135] In some cases, the clock signal and the transmit fault information may be transmitted via the same channel (e.g., a channel different from the EDC channel). In such cases, the clock signal and the transmit fault information may each be modulated in a different manner such that the controller 505 can identify each type of signal being sent by the memory device 510 based on the modulation used for the clock signal or the transmit fault information or both.

[0136] At 550, the memory device 510 may receive a retransmission of data to be written to the memory cell array from the controller 505 based on transmit fault information indicating an error. The memory device 510 may then continue to write the data according to the access operation (e.g., to the memory cell array at the memory device 510).

[0137] Figure 6 A process flow 600 is shown that supports a transmit fault feedback scheme for reducing crosstalk in accordance with examples disclosed herein. In some examples, aspects of the process flow 600 may be implemented by a controller 605 and a memory device 610, which may be examples of the corresponding devices described with reference to Figures 1-5 For example, the controller 605 may be an example of the external memory controller 105 described with reference to Figure 1 (e.g., a GPU). Additionally, the memory device 610 may be an example of the memory device 110 described with reference to Figure 1 The process flow 600 may illustrate the use of timing offsets for signals transmitted via the EDC channel.

[0138] At 615, the controller 605 and the memory device 610 may perform an initialization sequence during which the memory device 610 may receive information setting one or more preconfigured timing offsets for transmitting EDC information. At 620, the memory device 610 may store the preconfigured timing offsets in a mode register configured by the controller 605.

[0139] At 625, the controller 605 may transmit and the memory device 610 may receive data to be written to the memory cell array of the memory device 610, where the data may be received via one or more data channels (e.g., corresponding to data lines). At 630, the memory device 610 may generate a checksum of the data received via each of the one or more data channels. At 635, the memory device 610 may determine a timing offset for transmitting the generated checksum. In some cases, the timing offset may be selected from the one or more predetermined timing offsets stored in the mode register, e.g., at 620.

[0140] At 640, the memory device may transmit the checksum at a transmission time shifted according to the timing offset. The checksum may be transmitted to the controller 605 via the EDC channel. In these cases, the timing offset (or delay) may be applied to the checksum transmission such that the transmission is shifted relative to the data received from the controller 605. By transmitting the checksum to the controller at the shifted transmission time, crosstalk from the EDC channel to the data channel may be reduced or minimized.

[0141] Based on receiving the checksum information from the memory device 610, the controller 605 may determine whether the data received by the memory device 610 has failed by comparing the checksum received from the memory device 610 with the checksum generated by the controller 605 at 645. In the case where the data received by the memory device 610 has failed, the controller 605 may re - transmit the data (e.g., at least a portion of the data received in error) to the memory device 610. Alternatively, if the checksum comparison passes (e.g., the corresponding checksums are the same), then the controller 605 may determine that the data transmitted at 625 was received at the memory device 610 without error.

[0142] Figure 7 A flowchart in accordance with an example disclosed herein is shown, which illustrates a method 700 that supports a transmit fault feedback scheme for reducing crosstalk. Operations of the method 700 may be implemented by a memory device or its components, as referenced Figures 1-6 as described. For example, operations of the method 700 may be performed by the memory device 310, as referenced Figure 3 as described. In some instances, the memory device may execute a set of instructions or code to control the functional elements of the memory device to perform the functions described herein.

[0143] At 705, the memory device may receive data to be written to the memory cell array of the memory device from the controller via a set of data lines. In some instances, the data may be received via one data line, or via multiple data lines (e.g., channels), which may correspond to one or more DQ pins. It may be according to the referenceFigures 1-6 Perform the operation of 705 by the method described.

[0144] At 710, the memory device may receive checksum information of the data received via the plurality of data lines via an EDC line coupled to the controller. In some cases, the checksum information may be received simultaneously with the data received from the controller via a set of data lines, or may be received at a different time from the data transmission. In some instances, the checksum information may be a CRC checksum of the data transmitted by the controller, or may be another type of error detection code calculated by the controller. The operation of 710 may be performed according to the method described with reference to Figures 1-6 Perform the operation of 710 by the method described.

[0145] At 715, the memory device may detect an error in the data based on the checksum information. In some cases, the memory device may generate a checksum of the data received on the set of data lines and may compare the generated checksum with the checksum information received from the controller to detect an error in the received data. The operation of 715 may be performed according to the method described with reference to Figures 1-6 Perform the operation of 715 by the method described.

[0146] At 720, the memory device may transmit transmit failure information indicating an error in the data to the controller at least in part based on detecting an error in the data. The transmit failure information may provide an indication of whether an error has been detected in the data received via the set of data lines. For example, the indication may include a bit value (e.g., 0 or 1) that acts as a flag for the controller indicating that an error has been detected based on a checksum-based comparison. The operation of 720 may be performed according to the method described with reference to Figures 1-6 Perform the operation of 720 by the method described.

[0147] In some instances, a device as described herein may perform one or more methods, such as method 700. The device may include features, components, or instructions for the following operations (e.g., a non-transitory computer-readable medium storing instructions executable by a processor): receiving data to be written to a memory cell array of the memory device from a controller via a set of data lines; receiving, by the memory device via an EDC line coupled to the controller, checksum information of the data received via the set of data lines; detecting, by the memory device, an error in the data based on the checksum information; and transmitting, based on detecting the error, transmit failure information indicating an error in the data to the controller.

[0148] Some instances of the method 700, device, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for the following operations: generating a checksum of the data received on each data line of the set of data lines; and comparing the generated checksum of the received data with the received checksum information, wherein detecting the error may be based on comparing the generated checksum of the received data with the received checksum information.

[0149] Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: determining a difference between a generated checksum and received checksum information based on comparing the generated checksum and the received checksum information, wherein detecting an error in received data may be based on the determined difference between the generated checksum and the received checksum information.

[0150] Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: transmitting the transmit fault information via a first line coupled to a controller, the first line being different from the EDC line. Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: preventing transmission of a signal to the controller using the EDC line based on the transmit fault information transmitted via the first line.

[0151] Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: transmitting a clock signal via a second line coupled to a controller, the second line being different from the EDC line, wherein the clock signal may have a first frequency that is lower than a second frequency of the received data. In some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein, the clock signal comprises a low-swing differential signal or a hold pattern or both.

[0152] Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: transmitting the transmit fault information via a first line coupled to a controller, the first line being different from the EDC line, wherein the transmit fault information may be transmitted using a first modulation scheme; and transmitting a clock signal via the first line coupled to the controller, wherein the clock signal may be transmitted using a second modulation scheme different from the first modulation scheme.

[0153] In some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein, the clock signal includes a hold pattern. Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: receiving, from a controller, a retransmission of data to be written to a memory cell array based on transmit fault information indicating an error. Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: transmitting a logical value indicating an error detected in the received data.

[0154] Figure 8 Shows a flowchart in accordance with an example disclosed herein, which illustrates a method 800 that supports a transmit fault feedback scheme for reducing crosstalk. Operations of method 800 may be implemented by a memory device or components thereof, as referenced Figures 1-6 described. For example, operations of method 800 may be performed by a memory device 410, as referenced Figure 4 described. In some examples, the memory device may execute a set of instructions or code to control functional elements of the memory device to perform the functions described herein.

[0155] At 805, the memory device may receive, via a set of data lines, data to be written to a memory cell array of the memory device. In some examples, the data may be received via one data line, or via multiple data lines (or channels) (e.g., corresponding to one or more DQ pins). Operations of 805 may be performed in accordance with the method referenced Figures 1-6 described.

[0156] At 810, the memory device may determine a timing offset for transmitting a checksum of a clock signal (or clock pattern) and data. For example, the timing offset may be coherently selected based on the timing of the data received at the memory device for transmitting the clock signal and / or the checksum. As such, the timing offset may shift the transmit timing of the clock signal and / or the checksum such that crosstalk is minimized. Operations of 810 may be performed in accordance with the method referenced Figures 1-6 described.

[0157] At 815, the memory device may transmit the checksum to the controller at a transmit time shifted according to the timing offset. That is, the selected timing offset may be applied to the transmit path for transmitting the checksum. Operations of 815 may be performed in accordance with the method referenced Figures 1-6 described.

[0158] In some instances, a device as described herein may execute one or more methods, such as method 800. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving data to be written to a memory cell array of a memory device from a controller via a set of data lines; determining, by the memory device, a timing offset for transmitting a checksum of a clock signal and the data; and transmitting the checksum to the controller at a transmission time shifted according to the timing offset.

[0159] Some instances of method 800, the device, and the non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: selecting the timing offset from one or more preconfigured timing offsets, where each preconfigured timing offset may be based on operating conditions at the memory device.

[0160] Some instances of method 800, the device, and the non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: receiving, during an initialization sequence, configuration information that sets the one or more preconfigured timing offsets, where the selection of the timing offset from the one or more preconfigured timing offsets may be based on the configuration information.

[0161] Some instances of method 800, the device, and the non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: storing the one or more preconfigured timing offsets in a mode register configurable by the controller. In some instances of method 800, the device, and the non-transitory computer-readable medium described herein, the operating conditions include a data termination state or a driver strength or both.

[0162] Figure 9 A flowchart is shown in accordance with an example disclosed herein, which illustrates a method 900 that supports a transmit fault feedback scheme for reducing crosstalk. Operations of method 900 may be implemented by the controller or its components described in Figures 1-6 reference. For example, operations of method 900 may be performed by a controller 305 as described in Figure 3 reference or a controller 405 as described in Figure 4 reference. In some instances, the controller may execute a set of code to control functional elements of a device (e.g., a memory device 310, which may include a memory device 110) to perform the functions described herein.

[0163] At 905, the controller may transmit data to be written to the memory cell array via a set of data lines coupled to the memory device. That is, the data may be transmitted by the controller as part of a write operation (e.g., including a gapless write cycle). The operation at 905 may be performed according to the method described in reference Figures 1-6 The operation at 905 may be performed according to the method described in reference

[0164] At 910, the controller may transmit checksum information of the transmitted data via an EDC line coupled to the memory device. In some cases, the checksum information may be transmitted simultaneously with the data transmission. The operation at 910 may be performed according to the method described in reference Figures 1-6 The operation at 910 may be performed according to the method described in reference

[0165] At 915, the controller may receive transmission error information indicating an error in the data from the memory device based on the transmitted checksum information. For example, the memory device may identify a transmission error based on the checksum provided by the controller. In some cases, the controller may determine to rewrite the failed data based on the received transmission error information and the indicated error. The operation at 915 may be performed according to the method described in reference Figures 1-6 The operation at 915 may be performed according to the method described in reference

[0166] In some instances, a device as described herein may perform one or more methods, such as method 900. The device may include features, components, or instructions for the following operations (e.g., a non-transitory computer-readable medium storing instructions executable by a processor): transmitting data to be written to a memory cell array via a set of data lines coupled to a memory device; transmitting checksum information of the transmitted data via an EDC line coupled to the memory device; and receiving transmission failure information indicating an error in the data from the memory device based on the transmitted checksum information.

[0167] Some instances of the method 900, device, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for the following operation: receiving transmission failure information via a first line coupled to the memory device, the first line being different from the EDC line.

[0168] Some instances of the method 900, device, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for the following operation: receiving a clock signal via a second line coupled to the memory device, the second line being different from the EDC line, wherein the clock signal may have a first frequency different from a second frequency of the received data.

[0169] Some examples of the method 900, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: retransmitting data to be written to a memory cell array based on transmit failure information indicating an error.

[0170] Some examples of the method 900, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: receiving transmit failure information and a clock signal via a first line coupled to a memory device. Some examples of the method 900, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: decoding the transmit failure information using a first modulation scheme and decoding the clock signal using a second modulation scheme different from the first modulation scheme.

[0171] Note that the method descriptions herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, aspects from two or more of the methods may be combined.

[0172] In some examples, a device or apparatus may perform aspects of the functions described herein. In certain cases, the apparatus may include: a memory cell array; a receiver coupled to a set of data lines and an EDC line, the receiver configured to receive data to be written to the memory cell array via the set of data lines and receive checksum information regarding the data received via the set of data lines; a comparator configured to detect an error in the data based on the checksum information; and one or more lines coupled to a controller and configured to transmit at least one of a clock signal or transmit failure information indicating an error detected in the data, the one or more lines being different from the EDC line.

[0173] In some examples, the apparatus may include a first transmitter coupled to a first line of the one or more lines. The first transmitter is configured to transmit the transmit failure information via the first line of the one or more lines. In certain cases, the apparatus may include a clock, and a second transmitter coupled to a second line of the one or more lines, the second transmitter configured to transmit a signal from the clock via the one or more lines.

[0174] Any one of a variety of different technologies and techniques can be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may show a signal as a single signal; however, those of ordinary skill in the art will understand that the signal can represent a signal bus, where the bus can have a variety of bit widths.

[0175] The terms "electrically connected", "electrically contacted", "connected", and "coupled" can refer to the relationship between components that supports the flow of signals between the components. Components are considered to be electrically connected (or electrically contacted with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between components that are electrically connected (or electrically contacted or connected or coupled) can be an open circuit or a closed circuit. The conductive path between the connected components can be a direct conductive path between the components, or the conductive path between the connected components can be an indirect conductive path, which can include intermediate components such as switches, transistors, or other components. In some cases, the flow of signals between the connected components can be interrupted for a period of time, for example, by using one or more intermediate components such as switches or transistors.

[0176] The term "coupled" refers to the condition of moving from an open-circuit relationship between components to a closed-circuit relationship between components, where in the open-circuit relationship, signals cannot currently be transmitted between the components via a conductive path, and in the closed-circuit relationship, signals can be transmitted between the components via a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path that previously did not allow signal flow.

[0177] The term "isolated" refers to the relationship between components where signals cannot currently flow between the components. If there is an open circuit between the components, the components are isolated from each other. For example, the components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, the controller implements the following change: preventing signals from flowing between the components using a conductive path that previously allowed signal flow.

[0178] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) does not have to be absolute but is close enough to achieve the advantages of the characteristic.

[0179] The devices described herein that include a memory array can be formed on a semiconductor substrate such as silicon, germanium, silicon germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemicals including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0180] The switching components or transistors described herein can represent field-effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic components via a conductive material such as metal. The source and the drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and the drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are signals), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned off" or "deactivated".

[0181] The description presented herein in conjunction with the figures describes example configurations and does not represent all examples that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred over" or "superior to" other examples. The detailed description includes specific details that provide an understanding of the described technology. However, the technology can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0182] In the figures, similar components or features can have the same reference numerals. Additionally, various components of the same type can be distinguished by following the reference numeral with a dashed line and a second numeral, which differentiates among the similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0183] Any of a number of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by a voltage, current, electromagnetic wave, magnetic field or magnetic particle, optical field or optical particle, or any combination thereof.

[0184] The various illustrative blocks and modules described in connection with the present disclosure may be implemented or performed with a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor; but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0185] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. The features implementing the functions may also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations. And, as used herein, including in the claims, the "or" in a list of items (e.g., a list of items that begins with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed to refer to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0186] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium, the communication medium including any medium that facilitates transfer of a computer program from one place to another. The non-transitory storage medium can be any available medium that can be accessed by a general or special purpose computer. By way of example, and not limitation, the non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the desired program code means in the form of instructions or data structures and that can be accessed by a general or special purpose computer or a general or special purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs use lasers to optically reproduce data. Combinations of the above are also included within the scope of computer-readable medium.

[0187] The description provided herein enables a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for reducing crosstalk, which comprises: transmitting data to be written to a memory cell array of the memory device via a plurality of data lines; and receiving a checksum from the memory device at a transmission time shifted according to a timing offset, wherein the timing offset is programmed via a plurality of mode registers of the memory device.

2. The method according to claim 1, wherein the timing offset is from one or more pre-configured timing offsets, and wherein each pre-configured timing offset is at least partially based on operating conditions at the memory device.

3. The method according to claim 2, which further comprises: transmitting configuration information for setting the one or more pre-configured timing offsets during an initialization sequence, wherein the selection of the timing offset from the one or more pre-configured timing offsets is at least partially based on the configuration information.

4. The method according to claim 2, wherein the one or more pre-configured timing offsets are stored in a first mode register of the plurality of mode registers.

5. The method according to claim 2, wherein the one or more pre-configured timing offsets are stored in a first mode register and a second mode register of the plurality of mode registers.

6. The method according to claim 2, wherein the operating conditions include data termination state or driver strength or both.

7. An apparatus for reducing crosstalk, which comprises: one or more memory arrays; and one or more controllers coupled to the one or more memory arrays and configured to: transmit data to be written to the one or more memory arrays via a plurality of data lines; and receive a checksum from the memory device at a transmission time shifted according to a timing offset, wherein the timing offset is programmed via a plurality of mode registers.

8. The apparatus according to claim 7, wherein the timing offset is from one or more pre-configured timing offsets, and wherein each pre-configured timing offset is at least partially based on operating conditions at the memory device.

9. The apparatus according to claim 8, wherein the one or more controllers are further configured to: transmit configuration information for setting the one or more pre-configured timing offsets during an initialization sequence, wherein the selection of the timing offset from the one or more pre-configured timing offsets is at least partially based on the configuration information.

10. The apparatus according to claim 8, wherein the one or more pre-configured timing offsets are stored in a first mode register of the plurality of mode registers.

11. The apparatus according to claim 8, wherein the one or more pre-configured timing offsets are stored in a first mode register and a second mode register of the plurality of mode registers.

12. The apparatus according to claim 8, wherein the operating conditions include data termination state or driver strength or both.

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