SOE event writing and querying method based on off-chip nonvolatile memory

Abstract

The invention relates to the technical field of industrial control automation, in particular to an SOE event writing method based on an off-chip nonvolatile memory, which comprises the following steps: S1, after a PLC (Programmable Logic Controller) is powered on, a processor reads a pointer stored in the off-chip nonvolatile memory and performs diagnosis processing on the pointer to complete power-on self-test; s2, after an event is triggered, a processor collects event information to generate an SOE event; and S3, the processor obtains the pointer from the off-chip nonvolatile memory, judges the state of the pointer, forms a new pointer value, stores the SOE event into the off-chip nonvolatile memory, and executes a new pointer write-back operation, so that the SOE event is written into the off-chip nonvolatile memory. According to the method, an SOE server does not need to participate in maintenance, so that the overhead is reduced, and the problems of repeated reading and record loss are prevented; and storage pointer errors caused by power failure faults are avoided, the storage pointers are diagnosed and recovered, and the recording reliability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial control automation, and particularly relates to a method, a system and a storage medium for writing and querying SOE events based on an off-chip non-volatile memory. Background Art

[0002] In the field of automation control technology, many application scenarios of PLCs are in harsh environments of temperature, humidity, and strong electromagnetic interference. Based on this environment, the detection and fault analysis of equipment are becoming increasingly important. Among them, the SOE event recording function provides effective evidence for on-site accidents and equipment fault analysis by recording the accurate time of changes in multiple digital input signals when on-site events occur, and plays an important role in event analysis.

[0003] In the existing methods for power-off preservation and reading of SOE events in off-chip non-volatile memories, there are usually the following two problems: First, after power-on after power-off, the SOE server needs to read all the memory data and perform analysis and sorting to avoid duplicate SOE records. As the system scale increases and the number of cards increases, it will inevitably lead to an increase in communication load and SOE server overhead; Second, after the PLC powers off and then powers on to start working, new SOE will be placed at the initial position and subsequent positions, and these spaces may store SOE records before power-off. If the SOE server does not read all the stored data, several SOE records before power-off will be lost. Summary of the Invention

[0004] The purpose of the present invention is to solve the disadvantages existing in the prior art, and provides a method for writing SOE events based on an off-chip non-volatile memory, including the following steps: S1: After the PLC powers on, the processor reads the head pointer and the tail pointer stored in the pointer management area of the off-chip non-volatile memory in triple redundancy, judges the pointer state according to the reading result, and processes the head pointer and the tail pointer according to the pointer state to complete the power-on self-check; S2: After an event is triggered, the processor collects event information including a time stamp, an event type, and a device identifier, and generates an SOE event according to the event information; S3: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, judges the pointer state, forms a new pointer value, and the processor stores the SOE event in the external non-volatile memory and performs a new pointer write-back operation to complete writing the SOE event into the off-chip non-volatile memory.

[0005] Preferably, in step S1, judging the pointer state according to the reading result and processing the head pointer and the tail pointer according to the pointer state further includes: The processor performs a 2OO3 vote using the triple-redundant pointer values read from the off-chip non-volatile memory to determine whether the head pointer and the tail pointer are valid, and processes the head pointer and the tail pointer according to the determination result; Among them, if at least two of the head pointer value or the tail pointer value are equal, it is determined that the head pointer or the tail pointer is valid. In the case of validity, it is confirmed whether pointer writing back is required, and the head pointer and the tail pointer are processed according to the confirmation result; If the pointer values among the head pointer value or the tail pointer value are not equal to each other pairwise, it is determined that the head pointer or the tail pointer is invalid, the head pointer and the tail pointer are initialized, written back to the pointer management area, and the power-on self-test is exited.

[0006] Preferably, processing the head pointer and the tail pointer according to the confirmation result further includes: If three of the head pointer value or the tail pointer value are equal, the correct pointer value is output, pointer writing back is not required, and the power-on self-test is exited; If two of the head pointer value or the tail pointer value are equal, the correct pointer value is output, writing back to the pointer management area is required, and the power-on self-test is exited.

[0007] Preferably, in step S3, writing the SOE event to the off-chip non-volatile memory includes: S31: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, and determines the pointer status according to the obtaining result; S32: Write the SOE event to the off-chip non-volatile memory according to the pointer status, complete a single write of the SOE record to the off-chip non-volatile memory, process the head pointer and the tail pointer, perform a pointer write-back operation, monitor the next SOE event written, and return to step S31.

[0008] Preferably, in step S32, writing the SOE event to the off-chip non-volatile memory according to the pointer status further includes: If the processor obtains that the write pointer status is valid, write the SOE event to the off-chip non-volatile memory according to the external memory status; If the processor obtains that the write pointer status is invalid, initialize the head pointer and the tail pointer, write the SOE event to the off-chip non-volatile memory, then increment the head pointer value by 1, and perform a pointer write-back operation.

[0009] Preferably, writing the SOE event to the off-chip non-volatile memory according to the external memory status further includes: If the processor obtains the head pointer and the tail pointer, and determines that the external memory status is full, it releases the earliest SOE event, writes the SOE event into the off-chip non-volatile memory according to the head pointer, increments the head pointer value and the tail pointer value by 1, and performs a pointer write-back operation; If the processor obtains the head pointer and the tail pointer, and determines that the external memory status is not full, it writes the SOE event into the off-chip non-volatile memory according to the head pointer, increments the head pointer value by 1, and performs a pointer write-back operation.

[0010] Based on the same concept, the present invention also provides a method for querying SOE events based on an off-chip non-volatile memory, including the following steps: After the PLC is powered on, the processor reads the head pointer and the tail pointer stored in the pointer management area of the off-chip non-volatile memory in triple redundancy, determines the power-on pointer status according to the reading result, and processes the head pointer and the tail pointer according to the power-on pointer status to complete the power-on self-check; In response to a read instruction from the SOE server, the processor obtains the head pointer and the tail pointer. If the read pointer status is invalid, it initializes the head pointer and the tail pointer, and writes the head pointer and the tail pointer back to the pointer management area, then completes reading the SOE event from the off-chip non-volatile memory; If the read pointer status is valid, it reads the SOE event in the off-chip non-volatile memory according to the external memory status. After reading, it processes the head pointer and the tail pointer, writes the head pointer and the tail pointer back to the pointer management area, and listens for the next read of the SOE event to complete reading the SOE event from the off-chip non-volatile memory.

[0011] Preferably, reading the off-chip non-volatile memory according to the external memory status further includes: If the external memory status is empty, it writes the head pointer and the tail pointer back to the pointer management area, then completes reading the SOE event from the off-chip non-volatile memory; If the external memory status is not empty, it reads out the SOE event from the off-chip non-volatile memory, then increments the tail pointer value by 1 to point to the next space to be read, and performs a pointer write-back operation.

[0012] Based on the same concept, the present invention also provides a system for writing and querying SOE events based on an off-chip non-volatile memory, including: A PLC for data communication with an SOE server through Ethernet; The PLC includes a processor module and an off-chip non-volatile memory; Among them, the processor module includes a memory read / write driving unit, a pointer diagnosis unit, an SOE record read / write control unit, a memory information management unit, and a power-on self-check unit; The power-on self-check unit is used to control the memory read / write driving unit to read the head pointer and the tail pointer from the external non-volatile memory when the PLC is powered on, and output them to the pointer diagnosis unit. The pointer diagnosis unit gives the correct head pointer value and tail pointer value, which are used as the write or read operation pointers for SOE events after this power-on; The memory read / write driving unit is used for the read / write timing of the external non-volatile memory. Among them, the read / write operation is in units of single bytes; The pointer diagnosis unit is used to read the head pointer and the tail pointer, judge the pointer status according to the reading result, process the head pointer and the tail pointer according to the pointer status, and perform a pointer write-back operation; The SOE record read / write control unit is used to control the memory read / write driving unit to write and / or read the entire SOE record. Among them, it receives the SOE event, performs an SOE write operation according to the memory status, responds to the SOE server, reads the SOE event and replies according to the memory status, maintains the head pointer value and the tail pointer value of the read and / or write operation, and writes the pointer value back to the non-volatile memory; The memory information management unit is used to judge the memory status and output the memory status to the SOE record read / write control unit.

[0013] Based on the same concept, the present invention also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, one or more processors are caused to execute the steps of the SOE event writing method based on an off-chip non-volatile memory as described in the embodiment.

[0014] Compared with the prior art, the beneficial effects of the present invention are: The present invention reads the head pointer and the tail pointer stored in the pointer management area of the off-chip non-volatile memory in triple redundancy through the processor, judges the power-on pointer status according to the reading result, and processes the head pointer and the tail pointer according to the power-on pointer status, so as to realize power-on after power-off and prevent the problem of SOE records being overwritten and lost; The present invention obtains the head pointer and the tail pointer through the processor, judges the write pointer status according to the obtained result, and writes the SOE event from the internal memory to the off-chip non-volatile memory according to the write pointer status, so that the SOE server does not need to distinguish SOE records, so as to avoid SOE duplication and prevent the problem of increased deployment cost caused by the increase of SOE server overhead and communication load; The present invention obtains the head pointer and the tail pointer through a processor. If the read pointer status is invalid, the head pointer and the tail pointer are initialized, and the head pointer and the tail pointer are written back to the pointer management area of the off-chip non-volatile memory, then the reading of the SOE event from the off-chip non-volatile memory is completed. If the read pointer status is valid, the SOE event in the off-chip non-volatile memory is read. This method enables the SOE server to avoid reading all the information in the memory, preventing SOE duplication and reducing the scale of the storage area that the SOE server needs to read. Description of the Drawings

[0015] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of illustrating the preferred embodiments and are not considered to be a limitation of the present invention.

[0016] Figure 1 Schematic diagram of the off-chip non-volatile memory of the present invention; Figure 2 Flowchart of a method for writing SOE events based on an off-chip non-volatile memory of the present invention; Figure 3 Power-on self-test flowchart of the present invention; Figure 4 Pointer diagnosis flowchart of the present invention; Figure 5 Flowchart of a method for querying SOE events based on an off-chip non-volatile memory of the present invention; Figure 6 Schematic diagram of the structure of a system for writing and querying SOE events based on an off-chip non-volatile memory of the present invention. Detailed Embodiments

[0017] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0018] Those skilled in the art of the present technology can understand that unless specifically stated otherwise, the singular forms "a", "an", and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present invention means the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups.

[0019] The first embodiment Please refer to Figure 1 As shown in the figure, the space without stripes in the figure represents free space, and the space with stripes represents the presence of SOE records. The first 32 bytes of the storage space of the off-chip non-volatile memory are used for the pointer management area. One pointer occupies 4 bytes of space. The head pointer occupies the space from 0x0000 to 0x000B, and the tail pointer occupies the space from 0x000C to 0x0017, which cannot be used for SOE storage. Both the head pointer and the tail pointer are uniformly maintained by the processor without the participation of other components to avoid status conflicts caused by information asynchronization. In addition, the space from 0x0018 to 0x001F is reserved. The storage space allocation is continuous, and there is no gap between SOE records. The space for SOE records starts to be stored from 0x0020. Taking the length of one SOE record as a small unit (usually 16 bytes, and other values can be used according to actual needs, based on the space occupied by one SOE record), it is used to store one SOE record.

[0020] Please refer to Figure 2 As shown in the figure, a method for writing SOE events based on an off-chip non-volatile memory provided in this embodiment includes the following steps: Please refer to Figure 3 As shown in the figure, S1: After the PLC is powered on, the processor reads the head pointer and the tail pointer stored in the pointer management area of the off-chip non-volatile memory with triple redundancy, judges the pointer status according to the reading result, and processes the head pointer and the tail pointer according to the pointer status to complete the power-on self-check. Specifically, in this embodiment, after the PLC is powered on, the processor obtains 24 bytes of redundant pointer values from the external storage area. The head pointer points to the next space to be written, and the tail pointer points to the space that has been read currently. The tail pointer + 1 being equal to the head pointer indicates that the storage area is full, and the head pointer being equal to the tail pointer indicates that the storage area is empty. By storing the head and tail pointers with triple redundancy, it is possible to avoid the failure of a single operation pointer from causing the failure to be unrecognizable and recoverable. The head pointer and the tail pointer are maintained in the form of a circular queue. After the power is restored, the SOE records before the power-off will not be lost due to the sudden power-off process.

[0021] Please refer to Figure 3 and Figure 4 As shown in the figure, in step S1, judging the power-on pointer status according to the reading result and processing the head pointer and the tail pointer according to the power-on pointer status further includes: The processor performs a 2OO3 vote on the triple-redundant pointer values read from the off-chip non-volatile memory to determine whether the head pointer and the tail pointer are valid, and processes the head pointer and the tail pointer according to the judgment result. Specifically, in this embodiment, the pointer value depends on the voting result of the redundant pointer values in the off-chip memory, and this voted value is applied in the memory read and write process to ensure the reliability of the pointer operation in the memory read and write process; Among them, if at least two of the head pointer value or the tail pointer value are equal, it is determined that the head pointer or the tail pointer is valid. In the case of validity, it is confirmed whether it is necessary to write back the pointer, and the head pointer and the tail pointer are processed according to the confirmation result. Specifically, in this embodiment, it is determined that the pointer is valid, and at the same time, it has the function of restoring the pointer value to restore the faulty pointer value, so that the faults will not accumulate and the storage reliability is increased; If the pointer values in the head pointer value or the tail pointer value are not equal to each other, it is determined that the head pointer or the tail pointer fails, the head pointer and the tail pointer are initialized, and written back to the pointer management area, and the power-on self-test is exited. Specifically, in this embodiment, the processor initializes the head pointer value and the tail pointer value to 0x0020, that is, clears the memory content, but the probability of two errors occurring in such a short time is very small and can be ignored; If any of the head pointer and the tail pointer has an irrecoverable fault, that is, fails, it is determined that the content of the off-chip non-volatile memory is unavailable. Specifically, in this embodiment, during the read and write operation process, the faulty pointer value is corrected, improving the reliability, and this maintenance action does not require the participation of the SOE server.

[0022] Preferably, processing the head pointer and the tail pointer according to the confirmation result further includes: If three of the head pointer value or the tail pointer value are equal, the correct pointer value is output, there is no need to write back the pointer, and the power-on self-test is exited; If two of the head pointer value or the tail pointer value are equal, the correct pointer value is output, it is necessary to write back to the pointer management area, and the power-on self-test is exited. Specifically, in this embodiment, the processor writes the correct pointer value into the pointer management area of the non-volatile memory to correct a single error.

[0023] Through the power-on self-test, the processor can obtain the pointer value before the PLC power-off, and through the redundant voting method, this process is made more reliable, almost impossible to be irrecoverable, and at the same time has a single-error correction mechanism, so that the faults will not accumulate until they are irrecoverable.

[0024] S2: After the event is triggered, the processor collects event information including the timestamp, event type, and device identifier, and generates an SOE event according to the event information.

[0025] S3: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, judges the pointer status, forms a new pointer value, stores the SOE event in the external non-volatile memory, and performs the new pointer write-back operation to complete writing the SOE event into the off-chip non-volatile memory.

[0026] Preferably, in step S3, writing the SOE event into the off-chip non-volatile memory includes: S31: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, and judges the pointer status according to the obtained result; S32: Write the SOE event into the off-chip non-volatile memory according to the pointer status, complete a single write of the SOE record into the off-chip non-volatile memory, process the head pointer and the tail pointer, perform the pointer write-back operation, monitor the next SOE event to be written, and return to step S31.

[0027] Preferably, in step S32, writing the SOE event from the internal memory into the off-chip non-volatile memory according to the write pointer status further includes: If the processor obtains that the write pointer status is valid, write the SOE event into the off-chip non-volatile memory according to the external memory status; If the processor obtains that the write pointer status is invalid, initialize the head pointer and the tail pointer, write the SOE event into the off-chip non-volatile memory, then increment the head pointer value by 1, and perform the pointer write-back operation.

[0028] Preferably, writing the SOE event into the off-chip non-volatile memory according to the external memory status further includes: If the processor obtains the head pointer and the tail pointer and judges that the external memory status is full, release an earliest SOE event, write the SOE event into the off-chip non-volatile memory according to the head pointer, increment the head pointer value and the tail pointer value by 1, and perform the pointer write-back operation. Specifically, in this embodiment, if the head pointer + 1 = the tail pointer, the external memory status is full, and increment the head pointer value and the tail pointer value by 1, and write the updated head pointer value and tail pointer value into the pointer management area of the off-chip non-volatile storage area; If the processor obtains the head pointer and the tail pointer and judges that the external memory status is not full, write the SOE event into the off-chip non-volatile memory according to the head pointer, increment the head pointer value by 1, and perform the pointer write-back operation. Specifically, in this embodiment, increment the head pointer value by 1, and write the updated head pointer value into the pointer management area of the off-chip non-volatile storage area.

[0029] Through the method of this embodiment, there is no problem of duplicate SOE records. Based on this feature, the SOE server does not need to sort the SOE records inside a single PLC. Also based on this feature, faulty SOE records can be identified through the SOE timestamp, ensuring the reliability of storage. And according to the characteristics of SOE records, which increase monotonically in terms of timestamp, a certain number of incorrect SOE records can also be identified through the method of this embodiment, achieving a reduction in the overhead of the SOE server and the communication load of the system in large-scale application scenarios.

[0030] Second Embodiment Please refer to Figure 5 As shown, this embodiment provides a method for querying SOE events based on an off-chip non-volatile memory, which is applied to the internal memory and external memory adapted in Embodiment 1. It is characterized by including the following steps: After the PLC is powered on, the processor reads the head pointer and tail pointer stored in the pointer management area of the off-chip non-volatile memory in triple redundancy, determines the power-on pointer status according to the reading result, and processes the head pointer and tail pointer according to the power-on pointer status to complete the power-on self-check. In response to the read instruction from the SOE server, the processor obtains the head pointer and tail pointer. If the read pointer status is invalid, the head pointer and tail pointer are initialized and written back to the pointer management area, then the reading of SOE events from the off-chip non-volatile memory is completed. If the read pointer status is valid, the SOE events in the off-chip non-volatile memory are read according to the external memory status. After reading, the head pointer and tail pointer are processed, and the head pointer and tail pointer are written back to the pointer management area, and the next SOE event to be read is monitored to complete the reading of SOE events from the off-chip non-volatile memory.

[0031] Preferably, reading the off-chip non-volatile memory according to the external memory status further includes: If the external memory status is empty, the head pointer and tail pointer are written back to the pointer management area, then the reading of SOE events from the off-chip non-volatile memory is completed. Specifically, in this embodiment, the head pointer and tail pointer are maintained in the form of a circular queue. If the head pointer is equal to the tail pointer, the external memory status is empty. If the external memory status is non-empty, the SOE events are read out from the off-chip non-volatile memory, then the tail pointer value is incremented by 1 to point to the next space to be read, and the pointer write-back operation is executed. Specifically, in this embodiment, when reading SOE events from the off-chip non-volatile memory, the tail pointer value is incremented by 1 only after the transmission is completed, and the incremented tail pointer value is written into the pointer management area of the off-chip non-volatile storage area to prevent the loss of SOE records caused by transmission errors.

[0032] Through this embodiment, the processor can correctly maintain the read SOE operation of the memory. Before the read operation, pointer diagnosis is performed first, so that faults can be recovered in time to avoid the accumulation of faults.

[0033] The third embodiment Please refer to Figure 6 As shown, this embodiment provides an SOE event writing and querying system based on an off-chip non-volatile memory, which is characterized by including: A PLC for data communication with an SOE server through Ethernet; The PLC includes a processor module and an off-chip non-volatile memory; Among them, the processor module includes a memory read / write driving unit, a pointer diagnosis unit, an SOE record read / write control unit, a memory information management unit, and a power-on self-test unit; The power-on self-test unit is used to control the memory read / write driving unit to read the head pointer and the tail pointer from the external non-volatile memory when the PLC is powered on, and output them to the pointer diagnosis unit. The pointer diagnosis unit gives the correct head pointer value and tail pointer value as the write or read operation pointer of the SOE event after this power-on; The memory read / write driving unit is used for the read / write timing with the external non-volatile memory, where the read / write operation is in units of single bytes; The pointer diagnosis unit is used to read the head pointer and the tail pointer, judge the pointer state according to the read result, process the head pointer and the tail pointer according to the pointer state, and perform a pointer write-back operation; The SOE record read / write control unit is used to control the memory read / write driving unit to write and / or read the entire SOE record. Among them, it receives the SOE event, performs an SOE write operation according to the memory state, responds to the SOE server, reads the SOE event and replies according to the memory state, maintains the head pointer value and the tail pointer value of the read and / or write operation, and writes back the pointer value to the non-volatile memory; The memory information management unit is used to judge the memory state and output the memory state to the SOE record read / write control unit.

[0034] The fourth embodiment The present invention also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, one or more processors are caused to execute the steps of the SOE event writing method based on an off-chip non-volatile memory or the SOE event query method based on an off-chip non-volatile memory in an embodiment of the present invention.

[0035] It can be understood that for the aforementioned method of writing SOE events based on an off-chip non-volatile memory, if it is implemented in the form of software function modules and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer server, a network device, etc.) to execute all or part of the steps of the methods in various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, optical disks, and other various media that can store program codes.

[0036] A computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries the readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium can also be any readable medium other than the readable storage medium, and this readable medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination of the above.

[0037] The above description is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A SOE event writing method based on an off-chip non-volatile memory, characterized in that: The following steps are involved: S1: After the PLC is powered on, the processor reads the head pointer and the tail pointer of the pointer management area stored in the off-chip non-volatile memory in triply redundancy, determines the pointer state according to the reading result, and processes the head pointer and the tail pointer according to the pointer state to complete the power-on self-test; S2: After the event is triggered, the processor collects event information including timestamp, event type and device identification, and generates an SOE event according to the event information; S3: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, determines the pointer state, forms a new pointer value, stores the SOE event in the external non-volatile memory, and performs a new pointer write-back operation to complete writing the SOE event into the off-chip non-volatile memory.

2. The SOE event writing method based on off-chip non-volatile memory according to claim 1, characterized in that: In step S1, judging the pointer state according to the reading result, and processing the head pointer and the tail pointer according to the pointer state, further comprising: The processor performs 2OO3 voting on the triple redundant pointer value read from the off-chip non-volatile memory to determine whether the head pointer and the tail pointer are valid, and processes the head pointer and the tail pointer according to the determination result; If at least two pointer values ​​of the head pointer value or the tail pointer value are equal, the head pointer or the tail pointer is determined to be valid, and if valid, whether the pointer needs to be written back is confirmed, and the head pointer and the tail pointer are processed according to the confirmation result; If the pointer values ​​in the head pointer value or the tail pointer value are not equal to each other, the head pointer or the tail pointer is determined to be invalid, the head pointer and the tail pointer are initialized, and written back to the pointer management area, and the power-on self-test is exited.

3. The SOE event writing method based on off-chip non-volatile memory according to claim 2, characterized in that: Processing the head pointer and the tail pointer according to the confirmation result further includes: If the three pointer values ​​of the head pointer value or the tail pointer value are equal, the correct pointer value is output, the pointer does not need to be written back, and the power-on self-test is exited; If the two pointer values ​​of the head pointer value or the tail pointer value are equal, the correct pointer value is output and needs to be written back to the pointer management area to exit the power-on self-test.

4. The SOE event writing method based on off-chip non-volatile memory according to claim 3, characterized in that: In step S3, the SOE event is written into the off-chip non-volatile memory, including: S31: the processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, and determines the pointer state according to the acquisition result; S32: Write the SOE event into the off-chip non-volatile memory according to the pointer state, complete a single write of the SOE record into the off-chip non-volatile memory, process the head pointer and the tail pointer, perform a pointer write-back operation, monitor the next write of the SOE event, and return to step S31.

5. The SOE event writing method based on off-chip non-volatile memory according to claim 4, characterized in that: In step S32, writing the SOE event into the off-chip non-volatile memory according to the pointer state further includes: If the processor obtains that the write pointer state is valid, the SOE event is written into the off-chip non-volatile memory according to the external memory state; If the processor obtains that the write pointer state is invalid, the head pointer and the tail pointer are initialized, the SOE event is written into the off-chip non-volatile memory, and then the head pointer value is increased by 1 to perform a pointer write-back operation.

6. The SOE event writing method based on off-chip non-volatile memory according to claim 5, characterized in that: Writing the SOE event into the off-chip non-volatile memory according to the external memory state further comprises: If the processor obtains the head pointer and the tail pointer and determines that the external memory is full, the earliest SOE event is released, the SOE event is written into the off-chip non-volatile memory according to the head pointer, the head pointer value and the tail pointer value are increased by 1, and a pointer write-back operation is performed; If the processor obtains the head pointer and the tail pointer and determines that the external memory is not full, the SOE event is written into the off-chip non-volatile memory according to the head pointer, the head pointer value is increased by 1, and a pointer write-back operation is performed.

7. A SOE event query method based on an off-chip non-volatile memory, applied to an internal memory and an external memory adapted by the writing method described in any one of claims 1 to 6, characterized in that: The steps include: After the PLC is powered on, the processor reads the head pointer and the tail pointer in the pointer management area stored in the off-chip non-volatile memory in triply redundancy, determines the power-on pointer state according to the reading result, and processes the head pointer and the tail pointer according to the power-on pointer state to complete the power-on self-test; In response to a read instruction from the SOE server, the processor obtains the head pointer and the tail pointer, and if the read pointer state is invalid, initializes the head pointer and the tail pointer, and writes the head pointer and the tail pointer back to the pointer management area, thereby completing the reading of the SOE event from the off-chip non-volatile memory; If the read pointer state is valid, the SOE event in the off-chip non-volatile memory is read according to the external memory state. After reading, the head pointer and the tail pointer are processed, and the head pointer and the tail pointer are written back to the pointer management area, and the next read of the SOE event is listened to to complete the reading of the SOE event from the off-chip non-volatile memory.

8. The SOE event query method based on off-chip non-volatile memory according to claim 7, characterized in that: Reading the off-chip non-volatile memory according to the external memory state further includes: If the state of the external memory is empty, the head pointer and the tail pointer are written back into the pointer management area, thereby completing the reading of the SOE event from the off-chip non-volatile memory; If the state of the external memory is not empty, the SOE event is read from the off-chip non-volatile memory, and then the tail pointer value is increased by 1 to point to the next space to be read, and a pointer write-back operation is performed.

9. A SOE event writing and querying system based on off-chip non-volatile memory, characterized in that: include: PLC, used for data communication with SOE server via Ethernet; The PLC includes a processor module and an off-chip non-volatile memory; Wherein, the processor module includes a memory read-write drive unit, a pointer diagnosis unit, an SOE record read-write control unit, a memory information management unit and a power-on self-test unit; The power-on self-check unit is used to control the memory read-write drive unit when the PLC is powered on, read the head pointer and the tail pointer from the external non-volatile memory, and output them to the pointer diagnosis unit, and the pointer diagnosis unit gives the correct head pointer value and tail pointer value as the write or read operation pointer of the SOE event after the current power-on; The memory read / write driver unit is used for the read / write timing with the external non-volatile memory, wherein the read / write operation is in units of a single byte; The pointer diagnosis unit is used to read the head pointer and the tail pointer, determine the pointer status according to the reading result, process the head pointer and the tail pointer according to the pointer status, and perform a pointer write-back operation; The SOE record read and write control unit is used to control the memory read and write drive unit to write and / or read the entire SOE record, wherein the SOE event is received, and according to the memory state, the SOE write operation is performed, the SOE server is responded to, and according to the memory state, the SOE event is read and replied, the head pointer value and the tail pointer value of the read and / or write operation are maintained, and the pointer value is written back to the non-volatile memory; The memory information management unit is used to determine the memory status and output the memory status to the SOE record read and write control unit.

10. A storage medium storing computer-readable instructions, characterized in that: When the computer-readable instructions are executed by one or more processors, the one or more processors are caused to perform the steps of the SOE event writing method based on an off-chip non-volatile memory according to any one of claims 1 to 6.

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