A Method for Writing and Querying SOE Events Based on Off-Chip Non-Volatile Memory

Abstract

The present invention relates to the technical field of industrial control automation, and particularly relates to a method for writing SOE events based on an off-chip non-volatile memory, including the following steps: S1: After the PLC is powered on, the processor reads the pointer stored in the off-chip non-volatile memory and performs diagnostic processing on the pointer to complete the power-on self-check; S2: After an event is triggered, the processor collects event information to generate an SOE event; S3: The processor obtains the pointer from the off-chip non-volatile memory, judges the pointer status, forms a new pointer value, and the processor stores the SOE event in the off-chip non-volatile memory and executes the new pointer write-back operation to complete the writing of the SOE event into the off-chip non-volatile memory. The present invention does not require the participation of an SOE server for maintenance, reduces overhead, and prevents problems such as repeated reading and record loss; and avoids storage pointer errors caused by power-off faults, diagnoses and recovers the storage pointer, and increases the reliability of the records.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial control automation, and particularly to a method, a system, and a storage medium for writing and querying SOE events based on an off-chip non-volatile memory. Background Art

[0002] In the field of automation control technology, many application scenarios of PLCs are in harsh environments with high temperature, high humidity, and strong electromagnetic interference. Based on this environment, the detection and fault analysis of equipment are becoming increasingly important. Among them, the SOE event recording function provides effective evidence for on-site accidents and equipment fault analysis by recording the accurate time of changes in multiple digital input signals when on-site events occur, and plays an important role in event analysis.

[0003] In the existing methods for power-off preservation and reading of SOE events in off-chip non-volatile memories, there are usually the following two problems: First, after power-off and then power-on again, the SOE server needs to read all the memory data and perform analysis and sorting to avoid duplicate SOE records. As the system scale increases and the number of cards increases, it will inevitably lead to an increase in communication load and SOE server overhead. Second, after the PLC is powered off and then powered on to start working, new SOEs will be placed at the initial position and subsequent positions, and these spaces may store SOE records before power-off. If the SOE server does not read all the stored data, some SOE records before power-off will be lost. Summary of the Invention

[0004] The purpose of the present invention is to solve the disadvantages existing in the prior art, and provides a method for writing SOE events based on an off-chip non-volatile memory, including the following steps:

[0005] S1: After the PLC is powered on, the processor reads the head pointer and the tail pointer stored in the pointer management area of the off-chip non-volatile memory in triple redundancy, judges the pointer status according to the reading result, and processes the head pointer and the tail pointer according to the pointer status to complete the power-on self-check.

[0006] S2: After an event is triggered, the processor collects event information including a timestamp, an event type, and a device identifier, and generates an SOE event according to the event information.

[0007] S3: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, judges the pointer status, forms a new pointer value, the processor stores the SOE event in the external non-volatile memory, and performs a new pointer write-back operation to complete writing the SOE event into the off-chip non-volatile memory.

[0008] Preferably, in step S1, the pointer status is judged according to the reading result, and the head pointer and the tail pointer are processed according to the pointer status. Further, it includes:

[0009] The processor performs a 2OO3 vote on the triple redundant pointer values read from the off-chip non-volatile memory to judge whether the head pointer and the tail pointer are valid, and processes the head pointer and the tail pointer according to the judgment result;

[0010] Among them, if at least two of the head pointer value or the tail pointer value are equal, it is determined that the head pointer or the tail pointer is valid. In the case of validity, it is confirmed whether the pointer needs to be written back, and the head pointer and the tail pointer are processed according to the confirmation result;

[0011] If the pointer values in the head pointer value or the tail pointer value are not equal to each other in pairs, it is determined that the head pointer or the tail pointer is invalid, the head pointer and the tail pointer are initialized, and written back to the pointer management area, and the power-on self-check is exited.

[0012] Preferably, processing the head pointer and the tail pointer according to the confirmation result further includes:

[0013] If three of the head pointer value or the tail pointer value are equal, the correct pointer value is output, there is no need to write back the pointer, and the power-on self-check is exited;

[0014] If two of the head pointer value or the tail pointer value are equal, the correct pointer value is output, it needs to be written back to the pointer management area, and the power-on self-check is exited.

[0015] Preferably, in step S3, writing the SOE event into the off-chip non-volatile memory includes:

[0016] S31: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, and judges the pointer status according to the obtained result;

[0017] S32: Write the SOE event into the off-chip non-volatile memory according to the pointer status, complete a single write of the SOE record into the off-chip non-volatile memory, process the head pointer and the tail pointer, perform a pointer write-back operation, monitor the next SOE event to be written, and return to step S31.

[0018] Preferably, in step S32, writing the SOE event into the off-chip non-volatile memory according to the pointer status further includes:

[0019] If the processor obtains that the write pointer status is valid, write the SOE event into the off-chip non-volatile memory according to the external memory status;

[0020] If the processor gets that the write pointer status is invalid, it initializes the head pointer and the tail pointer, writes the SOE event into the off-chip non-volatile memory, then increments the value of the head pointer, and performs a pointer write-back operation.

[0021] Preferably, writing the SOE event into the off-chip non-volatile memory according to the external memory status further includes:

[0022] If the processor gets the head pointer and the tail pointer and determines that the external memory status is full, it releases the earliest SOE event, writes the SOE event into the off-chip non-volatile memory according to the head pointer, increments the values of the head pointer and the tail pointer, and performs a pointer write-back operation;

[0023] If the processor gets the head pointer and the tail pointer and determines that the external memory status is not full, it writes the SOE event into the off-chip non-volatile memory according to the head pointer, increments the value of the head pointer, and performs a pointer write-back operation.

[0024] Based on the same concept, the present invention also provides a method for querying SOE events based on an off-chip non-volatile memory, including the following steps:

[0025] After the PLC is powered on, the processor reads the head pointer and the tail pointer stored in the pointer management area of the off-chip non-volatile memory with triple redundancy, determines the power-on pointer status according to the reading result, and processes the head pointer and the tail pointer according to the power-on pointer status to complete the power-on self-check;

[0026] In response to a read instruction from the SOE server, the processor obtains the head pointer and the tail pointer. If the read pointer status is invalid, it initializes the head pointer and the tail pointer, and writes the head pointer and the tail pointer back into the pointer management area, then completes reading the SOE event from the off-chip non-volatile memory;

[0027] If the read pointer status is valid, it reads the SOE event in the off-chip non-volatile memory according to the external memory status. After reading, it processes the head pointer and the tail pointer, writes the head pointer and the tail pointer back into the pointer management area, and listens for the next reading of the SOE event to complete reading the SOE event from the off-chip non-volatile memory.

[0028] Preferably, reading the off-chip non-volatile memory according to the external memory status further includes:

[0029] If the external memory status is empty, write the head pointer and the tail pointer back to the pointer management area, and then the reading of the SOE event from the off-chip non-volatile memory is completed;

[0030] If the external memory status is non-empty, read the SOE event from the off-chip non-volatile memory, then increment the tail pointer value by 1 to point to the next space to be read, and perform the pointer write-back operation.

[0031] Based on the same concept, the present invention further provides a SOE event writing and querying system based on an off-chip non-volatile memory, including:

[0032] A PLC for data communication with an SOE server through Ethernet;

[0033] The PLC includes a processor module and an off-chip non-volatile memory;

[0034] Wherein, the processor module includes a memory read / write driving unit, a pointer diagnosis unit, an SOE record read / write control unit, a memory information management unit, and a power-on self-test unit;

[0035] The power-on self-test unit is used to control the memory read / write driving unit to read the head pointer and the tail pointer from the external non-volatile memory when the PLC is powered on, and output them to the pointer diagnosis unit. The pointer diagnosis unit gives the correct head pointer value and tail pointer value as the write or read operation pointer of the SOE event after this power-on;

[0036] The memory read / write driving unit is used for the read / write timing with the external non-volatile memory, wherein the read / write operation is in units of single bytes;

[0037] The pointer diagnosis unit is used to read the head pointer and the tail pointer, judge the pointer status according to the reading result, process the head pointer and the tail pointer according to the pointer status, and perform the pointer write-back operation;

[0038] The SOE record read / write control unit is used to control the memory read / write driving unit to write and / or read the entire SOE record. Wherein, it receives the SOE event, performs the SOE write operation according to the memory status, responds to the SOE server, reads the SOE event and makes a reply according to the memory status, maintains the head pointer value and the tail pointer value of the read and / or write operation, and writes the pointer value back to the non-volatile memory;

[0039] The memory information management unit is used to judge the memory status and output the memory status to the SOE record read / write control unit.

[0040] Based on the same concept, the present invention also provides a storage medium storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to execute the steps of the SOE event writing method based on an off-chip non-volatile memory as described in the embodiments.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] In the present invention, the processor reads the head pointer and the tail pointer stored in the pointer management area of the off-chip non-volatile memory in triple redundancy, determines the power-on pointer state according to the reading result, and processes the head pointer and the tail pointer according to the power-on pointer state, so as to realize power-on after power-off and prevent the problem of SOE records being overwritten and lost.

[0043] In the present invention, the processor obtains the head pointer and the tail pointer, determines the write pointer state according to the obtained result, and writes the SOE event from the internal memory to the off-chip non-volatile memory according to the write pointer state, so that the SOE server does not need to distinguish SOE records, avoiding SOE duplication and preventing the problem of increased deployment cost caused by the increase of SOE server overhead and communication load.

[0044] In the present invention, the processor obtains the head pointer and the tail pointer. If the read pointer state is invalid, the head pointer and the tail pointer are initialized and written back to the pointer management area of the off-chip non-volatile memory, then the reading of the SOE event from the off-chip non-volatile memory is completed. If the read pointer state is valid, the SOE event in the off-chip non-volatile memory is read. This way enables the SOE server to avoid reading all the information in the memory, preventing SOE duplication and reducing the scale of the storage area that the SOE server needs to read. Description of the Drawings

[0045] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention.

[0046] Figure 1 It is a schematic diagram of the off-chip non-volatile memory of the present invention;

[0047] Figure 2 It is a flowchart of a method for writing SOE events based on an off-chip non-volatile memory according to the present invention;

[0048] Figure 3 It is a flowchart of power-on self-check of the present invention;

[0049] Figure 4 It is a flowchart of pointer diagnosis of the present invention;

[0050] Figure 5 This is a flowchart of a method for querying SOE events based on an off-chip non-volatile memory according to the present invention;

[0051] Figure 6 This is a schematic structural diagram of a system for writing and querying SOE events based on an off-chip non-volatile memory according to the present invention. Specific embodiments

[0052] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Obviously, the described embodiments are part of the embodiments of the present application, but not all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0053] Those skilled in the art of this technology can understand that, unless specifically stated, the singular forms "a", "an", and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present invention means the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0054] The first embodiment

[0055] Please refer to Figure 1 As shown, the space without stripes in the figure represents free space, and the space with stripes represents the presence of SOE records. The first 32 bytes of the storage space of the off-chip non-volatile memory are used for the pointer management area. One pointer occupies 4 bytes of space. The head pointer occupies the space from 0x0000 to 0x000B, and the tail pointer occupies the space from 0x000C to 0x0017, which cannot be used for SOE storage. Both the head pointer and the tail pointer are uniformly maintained by the processor without the participation of other components to avoid state conflicts caused by information asynchronization. In addition, the space from 0x0018 to 0x001F is reserved. The storage space allocation is continuous, there is no gap between SOE records, and the space for SOE records starts to be stored from 0x0020. Taking the length of one SOE record as a small unit (generally 16 bytes, and other values can be used according to actual needs, based on the space occupied by one SOE record), it is used to store one SOE record.

[0056] Please refer to Figure 2 As shown, a method for writing SOE events based on an off-chip non-volatile memory provided in this embodiment includes the following steps:

[0057] Please refer toFigure 3 As shown, S1: After the PLC is powered on, the processor reads the head pointer and tail pointer of the pointer management area stored in the off-chip non-volatile memory in triple redundancy, judges the pointer status according to the reading result, and processes the head pointer and tail pointer according to the pointer status to complete the power-on self-check. Specifically, in this embodiment, after the PLC is powered on, the processor obtains 24 bytes of redundant pointer values from the external storage area. The head pointer points to the next space to be written, and the tail pointer points to the space that has been read. Tail pointer + 1 being equal to the head pointer indicates that the storage area is full, and the head pointer being equal to the tail pointer indicates that the storage area is empty. The head and tail pointers are stored in triple redundancy to avoid the failure of a single operation pointer resulting in unrecognizable and irrecoverable faults. The head pointer and tail pointer are maintained in the form of a circular queue. After a power-on reset, the SOE records before the power-off will not be lost due to a sudden power-off process.

[0058] Please refer to Figure 3 and Figure 4 As shown, in step S1, judging the power-on pointer status according to the reading result and processing the head pointer and tail pointer according to the power-on pointer status further includes:

[0059] The processor performs a 2OO3 vote on the triple redundant pointer values read from the off-chip non-volatile memory to judge whether the head pointer and tail pointer are valid, and processes the head pointer and tail pointer according to the judgment result. Specifically, in this embodiment, the pointer value depends on the voting result of the redundant pointer values in the off-chip memory, and this voted value is applied to the memory read and write process, ensuring the reliability of the pointer operation in the memory read and write process;

[0060] Among them, if at least two of the head pointer value or the tail pointer value are equal, it is determined that the head pointer or the tail pointer is valid. In the case of validity, confirm whether it is necessary to write back the pointer, and process the head pointer and tail pointer according to the confirmation result. Specifically, in this embodiment, it is determined that the pointer is valid, and at the same time, it has the function of restoring the pointer value, and restores the faulty pointer value, so that the faults will not accumulate and the reliability of storage is increased;

[0061] If the pointer values of the head pointer value or the tail pointer value are not equal to each other, it is determined that the head pointer or the tail pointer fails, the head pointer and the tail pointer are initialized, and written back to the pointer management area, and the power-on self-check is exited. Specifically, in this embodiment, the processor initializes the head pointer value and the tail pointer value to 0x0020, that is, clears the memory content, but the probability of two errors occurring in such a short time is very small and can be ignored;

[0062] If any of the head pointer and the tail pointer experiences an irrecoverable failure, that is, a failure, it is determined that the content of the off-chip non-volatile memory is unavailable. Specifically, in this embodiment, during the read / write operation, the incorrect pointer value is corrected, improving the reliability, and this maintenance operation does not require the participation of the SOE server.

[0063] Preferably, processing the head pointer and the tail pointer according to the confirmation result further includes:

[0064] If three of the head pointer value or the tail pointer value are equal, output the correct pointer value, no need to write back the pointer, and exit the power-on self-test.

[0065] If two of the head pointer value or the tail pointer value are equal, output the correct pointer value, which needs to be written back to the pointer management area, and exit the power-on self-test. Specifically, in this embodiment, the processor will write the correct pointer value to the pointer management area of the non-volatile memory to correct a single error.

[0066] Through the power-on self-test, the processor can obtain the pointer value before the PLC power-off, and through the redundant voting method, this process is made more reliable, with almost no possibility of being irrecoverable. At the same time, it has a single-error correction mechanism, so that the faults will not accumulate to the point of being irrecoverable.

[0067] S2: After the event is triggered, the processor collects event information including the timestamp, event type, and device identifier, and generates an SOE event according to the event information.

[0068] S3: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, judges the pointer status, forms a new pointer value, and the processor stores the SOE event in the external non-volatile memory and performs a new pointer write-back operation to complete writing the SOE event into the off-chip non-volatile memory.

[0069] Preferably, in step S3, writing the SOE event into the off-chip non-volatile memory includes:

[0070] S31: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory and judges the pointer status according to the obtained result;

[0071] S32: Write the SOE event into the off-chip non-volatile memory according to the pointer status, complete a single write of the SOE record into the off-chip non-volatile memory, process the head pointer and the tail pointer, perform a pointer write-back operation, monitor the next SOE event to be written, and return to step S31.

[0072] Preferably, in step S32, writing the SOE event from the internal memory into the off-chip non-volatile memory according to the write pointer status further includes:

[0073] If the processor obtains that the write pointer status is valid, write the SOE event into the off-chip non-volatile memory according to the external memory status;

[0074] If the processor obtains that the write pointer status is invalid, initialize the head pointer and the tail pointer, write the SOE event into the off-chip non-volatile memory, then increment the head pointer value by 1, and perform the pointer write-back operation.

[0075] Preferably, writing the SOE event into the off-chip non-volatile memory according to the external memory status further includes:

[0076] If the processor obtains the head pointer and the tail pointer, and determines that the external memory status is full, release the earliest SOE event, write the SOE event into the off-chip non-volatile memory according to the head pointer, increment the head pointer value and the tail pointer value by 1, and perform the pointer write-back operation. Specifically, in this embodiment, if the head pointer + 1 = the tail pointer, the external memory status is full, and increment the head pointer value and the tail pointer value by 1, and write the updated head pointer value and tail pointer value into the pointer management area of the off-chip non-volatile storage area;

[0077] If the processor obtains the head pointer and the tail pointer, and determines that the external memory status is not full, write the SOE event into the off-chip non-volatile memory according to the head pointer, increment the head pointer value by 1, and perform the pointer write-back operation. Specifically, in this embodiment, increment the head pointer value by 1, and write the updated head pointer value into the pointer management area of the off-chip non-volatile storage area.

[0078] Through the method of this embodiment, there is no problem of duplicate SOE records. Based on this feature, the SOE server does not need to sort the SOE records inside a single PLC. Also based on this feature, faulty SOE records can be identified through the SOE timestamp, ensuring the reliability of storage. And according to the characteristics of the SOE records, they are monotonically increasing in terms of timestamp. Through the method of this embodiment, a certain number of incorrect SOE records can also be identified, reducing the overhead of the SOE server and the communication load of the system in large-scale application scenarios.

[0079] Second Embodiment

[0080] Please refer to Figure 5 As shown, this embodiment provides a method for querying SOE events based on off-chip non-volatile memory, which is applied to the internal memory and the external memory adapted in Embodiment 1, and is characterized by including the following steps:

[0081] After the PLC is powered on, the processor reads the head pointer and the tail pointer stored in the triple-redundant pointer management area of the off-chip non-volatile memory, determines the power-on pointer status according to the reading result, and processes the head pointer and the tail pointer according to the power-on pointer status to complete the power-on self-check;

[0082] In response to the read instruction from the SOE server, the processor acquires the head pointer and the tail pointer. If the read pointer status is invalid, it initializes the head pointer and the tail pointer, and writes the head pointer and the tail pointer back to the pointer management area, then completes reading the SOE event from the off-chip non-volatile memory.

[0083] If the read pointer status is valid, it reads the SOE event in the off-chip non-volatile memory according to the external memory status. After reading, it processes the head pointer and the tail pointer, writes the head pointer and the tail pointer back to the pointer management area, and listens for the next SOE event read to complete reading the SOE event from the off-chip non-volatile memory.

[0084] Preferably, reading the off-chip non-volatile memory according to the external memory status further includes:

[0085] If the external memory status is empty, it writes the head pointer and the tail pointer back to the pointer management area, then completes reading the SOE event from the off-chip non-volatile memory. Specifically, in this embodiment, the head pointer and the tail pointer are maintained in the form of a circular queue. If the head pointer is equal to the tail pointer, the external memory status is empty.

[0086] If the external memory status is non-empty, it reads the SOE event from the off-chip non-volatile memory, then adds 1 to the tail pointer value to point to the next space to be read, and performs the pointer write-back operation. Specifically, in this embodiment, when reading the SOE event from the off-chip non-volatile memory, it waits for the transmission to complete before adding 1 to the tail pointer value and writing the incremented tail pointer value to the pointer management area of the off-chip non-volatile storage area to prevent the loss of SOE records due to transmission errors.

[0087] Through this embodiment, the processor can correctly maintain the read SOE operation of the memory. Before the read operation, it first performs pointer diagnosis, enabling timely recovery of faults and avoiding the accumulation of faults.

[0088] The third embodiment

[0089] Please refer to Figure 6 As shown, this embodiment provides an SOE event writing and querying system based on an off-chip non-volatile memory, which is characterized by including:

[0090] A PLC for data communication with the SOE server through Ethernet;

[0091] The PLC includes a processor module and an off-chip non-volatile memory;

[0092] Wherein, the processor module includes a memory read / write drive unit, a pointer diagnosis unit, an SOE record read / write control unit, a memory information management unit, and a power-on self-test unit;

[0093] When the PLC is powered on, the power-on self-check unit is used to control the memory read / write drive unit to read the head pointer and the tail pointer from the external non-volatile memory and output them to the pointer diagnosis unit. The pointer diagnosis unit gives the correct head pointer value and tail pointer value, which are used as the write or read operation pointers for SOE events after this power-on.

[0094] The memory read / write drive unit is used for the read / write timing of the external non-volatile memory. Among them, the read / write operation is in units of single bytes.

[0095] The pointer diagnosis unit is used to read the head pointer and the tail pointer, judge the pointer status according to the read result, process the head pointer and the tail pointer according to the pointer status, and execute the pointer write-back operation.

[0096] The SOE record read / write control unit is used to control the memory read / write drive unit to write and / or read the entire SOE record. Among them, it receives the SOE event, executes the SOE write operation according to the memory status, responds to the SOE server, reads the SOE event and makes a reply according to the memory status, maintains the head pointer value and the tail pointer value of the read and / or write operation, and writes back the pointer value to the non-volatile memory.

[0097] The memory information management unit is used to judge the memory status and output the memory status to the SOE record read / write control unit.

[0098] Fourth Embodiment

[0099] The present invention also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors are caused to execute the steps of the SOE event writing method based on an off-chip non-volatile memory or a SOE event query method based on an off-chip non-volatile memory in an embodiment of the present invention.

[0100] It can be understood that for the aforementioned method for writing SOE events based on an off-chip non-volatile memory, when it is implemented in the form of software functional modules and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer server, a network device, etc.) to execute all or part of the steps of the methods in various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, optical discs, and other various media that can store program codes.

[0101] A computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries the readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium can also be any readable medium other than the readable storage medium, and this readable medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination of the above.

[0102] The above description is only a preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A method for writing SOE events based on off-chip non-volatile memory, characterized in that It includes the following steps: S1: After the PLC is powered on, the processor reads the head pointer and the tail pointer of the pointer management area stored in the off-chip non-volatile memory in triple redundancy, determines the pointer status according to the read result, and processes the head pointer and the tail pointer according to the pointer status to complete the power-on self-check; S2: After an event is triggered, the processor collects event information including a timestamp, an event type, and a device identifier, and generates an SOE event according to the event information; S3: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, determines the pointer status, forms a new pointer value, stores the SOE event in the external non-volatile memory, and performs a new pointer write-back operation to complete writing the SOE event into the off-chip non-volatile memory.

2. The SOE event writing method based on an off-chip non-volatile memory according to claim 1, wherein In step S1, determining the pointer status according to the read result and processing the head pointer and the tail pointer according to the pointer status further includes: The processor performs a 2OO3 vote on the triple-redundancy pointer values read from the off-chip non-volatile memory to determine whether the head pointer and the tail pointer are valid, and processes the head pointer and the tail pointer according to the determination result; Among them, if at least two of the head pointer value or the tail pointer value are equal, it is determined that the head pointer or the tail pointer is valid. In the case of validity, it is confirmed whether the pointer needs to be written back, and the head pointer and the tail pointer are processed according to the confirmation result; If the pointer values in the head pointer value or the tail pointer value are not equal to each other, it is determined that the head pointer or the tail pointer is invalid, the head pointer and the tail pointer are initialized, and written back to the pointer management area, and the power-on self-check is exited.

3. The SOE event writing method based on an off-chip non-volatile memory according to claim 2, wherein Processing the head pointer and the tail pointer according to the confirmation result further includes: If the three pointer values in the head pointer value or the tail pointer value are equal, the correct pointer value is output, there is no need to write back the pointer, and the power-on self-check is exited; If two of the head pointer value or the tail pointer value are equal, the correct pointer value is output, it needs to be written back to the pointer management area, and the power-on self-check is exited.

4. The method for writing SOE events based on an off-chip non-volatile memory according to claim 3, wherein In step S3, writing the SOE event into the off-chip non-volatile memory includes: S31: The processor obtains the head pointer and the tail pointer from the off-chip non-volatile memory, and determines the pointer status according to the obtained result; S32: Write the SOE event into the off-chip non-volatile memory according to the pointer status, complete a single write of the SOE record into the off-chip non-volatile memory, process the head pointer and the tail pointer, perform a pointer write-back operation, monitor the next SOE event to be written, and return to step S31.

5. The method for writing SOE events based on off-chip non-volatile memory according to claim 4, characterized in that, In step S32, writing the SOE event into the off-chip non-volatile memory according to the pointer status further includes: If the processor obtains that the write pointer status is valid, write the SOE event into the off-chip non-volatile memory according to the external memory status; If the processor obtains that the write pointer status is invalid, it initializes the head pointer and the tail pointer, writes the SOE event into the off-chip non-volatile memory, then increments the head pointer value, and performs a pointer write-back operation.

6. The method for writing SOE events based on an off-chip non-volatile memory according to claim 5, wherein Writing the SOE event into the off-chip non-volatile memory according to the external memory status further includes: If the processor obtains the head pointer and the tail pointer and determines that the external memory status is full, it releases the earliest SOE event, writes the SOE event into the off-chip non-volatile memory according to the head pointer, increments the head pointer value and the tail pointer value, and performs a pointer write-back operation; If the processor obtains the head pointer and the tail pointer and determines that the external memory status is not full, it writes the SOE event into the off-chip non-volatile memory according to the head pointer, increments the head pointer value, and performs a pointer write-back operation.

7. A method for querying SOE events based on an off-chip non-volatile memory, which is applied to an internal memory and an external memory adapted by the writing method described in any one of claims 1 to 6, and is characterized in that, It includes the following steps: After the PLC is powered on, the processor reads the head pointer and the tail pointer stored in the pointer management area of the off-chip non-volatile memory in triple redundancy, judges the power-on pointer status according to the reading result, and processes the head pointer and the tail pointer according to the power-on pointer status to complete the power-on self-check; In response to the read instruction of the SOE server, the processor obtains the head pointer and the tail pointer. If the read pointer status is invalid, it initializes the head pointer and the tail pointer, and writes the head pointer and the tail pointer back into the pointer management area, then completes reading the SOE event from the off-chip non-volatile memory; If the read pointer status is valid, it reads the SOE event in the off-chip non-volatile memory according to the external memory status. After reading, it processes the head pointer and the tail pointer, writes the head pointer and the tail pointer back into the pointer management area, and listens for the next reading of the SOE event to complete reading the SOE event from the off-chip non-volatile memory.

8. The method for querying SOE events based on an off-chip non-volatile memory according to claim 7, wherein Reading the off-chip non-volatile memory according to the external memory status further includes: If the external memory status is empty, it writes the head pointer and the tail pointer back into the pointer management area, then completes reading the SOE event from the off-chip non-volatile memory; If the external memory status is not empty, it reads out the SOE event from the off-chip non-volatile memory, then increments the tail pointer value to point to the next space to be read, and performs a pointer write-back operation.

9. An SOE event writing and querying system based on an off-chip non-volatile memory, characterized in that, It includes: A PLC for performing data communication with an SOE server through Ethernet; The PLC includes a processor module and an off-chip non-volatile memory; Wherein, the processor module includes a memory read / write driving unit, a pointer diagnosis unit, an SOE record read / write control unit, a memory information management unit, and a power-on self-check unit; The power-on self-check unit is used to control the memory read / write drive unit to read the head pointer and the tail pointer from the external non-volatile memory when the PLC is powered on, and output them to the pointer diagnosis unit. The pointer diagnosis unit gives the correct head pointer value and tail pointer value, which are used as the write or read operation pointers for the SOE events after this power-on. The memory read / write drive unit is used for the read / write timing with the external non-volatile memory. Among them, the read / write operation is in units of single bytes. The pointer diagnosis unit is used to read the head pointer and the tail pointer, judge the pointer status according to the read result, process the head pointer and the tail pointer according to the pointer status, and perform the pointer write-back operation. The SOE record read / write control unit is used to control the memory read / write drive unit to write and / or read the entire SOE record. Among them, it receives the SOE event, performs the SOE write operation according to the memory state, responds to the SOE server, reads the SOE event and makes a reply according to the memory state, maintains the head pointer value and the tail pointer value of the read and / or write operation, and writes back the pointer value to the non-volatile memory. The memory information management unit is used to judge the memory state and output the memory state to the SOE record read / write control unit.

10. A storage medium storing computer-readable instructions, characterized in that, When the computer-readable instructions are executed by one or more processors, the one or more processors are caused to execute the steps of the method for writing SOE events based on an off-chip non-volatile memory according to any one of claims 1 to 6.

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