PCIe automatic branching method and system

Abstract

The embodiment of the invention provides a PCIe automatic branching method and system, and the method comprises the steps: obtaining a backboard identifier of a backboard where each PCIe device is located and a serial number of a used transmission bus for each backboard connected with a BMC and the used transmission bus, and determining channel splitting configuration information of each PCIe interface according to the acquired backboard identifier and the serial number of the transmission bus so as to be used by a BIOS (Basic Input / Output System), according to the method and the device, the problem that the BIOS maintenance difficulty is increased due to the fact that the channel splitting configuration information of the PCIe interface with the wrong BIOS is set and the BIOS of a new version needs to be released in a new application scene in the related technology is solved, the correctness of setting the branch mode of the PCIe interface by the BIOS is improved, and the maintenance difficulty of the system and the BIOS is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the computer field, and in particular, to a PCIe automatic branching method and system. Background Art

[0002] In server devices, processors and peripheral devices are connected via the Peripheral Component Interconnect Express (PCIe). A processor usually has multiple standard PCIe interfaces, which are used to connect different devices, such as solid state drives (SSDs), graphics cards, network cards, data processing units (DPUs), etc.

[0003] A standard PCIe interface usually has 16 lanes, which can be used to connect different PCIe devices at the same time. To achieve this function, it is necessary to set the PCIe interface channel splitting information (PCIe Bifurcation) through the Basic Input / Output System (BIOS) to divide the 16 lanes of the PCIe interface into different communication channels to connect different PCIe devices.

[0004] In the prior art, a single BIOS firmware image is used to support different computer systems. In this image, the PCIe Bifurcation configurations of different systems are stored to adapt to the hardware design associated with each system. A mapping table is usually provided in the BIOS, which records the PCIe Bifurcation configurations corresponding to different systems. When the BIOS is powered on, it detects the system type and sets the correct PCIe Bifurcation according to the mapping table. If the BIOS sets the wrong PCIe Bifurcation, it may cause the system to be unable to use the PCIe devices installed on the system, or cause the PCIe devices to run at a reduced speed.

[0005] When a server processor is used in two different application scenarios and different PCIe devices are connected externally, it can be considered as two different systems. In order to ensure the normal operation of the system, it is necessary to first identify the current system and provide the corresponding correct PCIe Bifurcation settings according to the system. In more and more complex scenarios, this process may cause the BIOS to set the wrong PCIe Bifurcation configuration, which will have a negative impact on the function and performance of the system. In addition, every time a new application scenario emerges, a new version of BIOS needs to be released to support the changes in PCIe Bifurcation. These potential changes increase the difficulty of maintaining the system and the BIOS itself.

[0006] There is no solution yet for the problem of PCIe Bifurcation with incorrect BIOS settings in the related art and the need to release a new version of BIOS when facing new application scenarios, which increases the difficulty of BIOS maintenance. Summary of the invention

[0007] The embodiment of the present invention provides an automatic branching method and system for a peripheral device interconnection expansion bus PCIe, so as to at least solve the problem of PCIe Bifurcation with incorrect BIOS setting in the related art and the need to release a new version of BIOS when facing new application scenarios, which increases the difficulty of BIOS maintenance.

[0008] According to one embodiment of the present invention, there is provided an automatic branching system of a peripheral device interconnection expansion bus PCIe, comprising:

[0009] A processor, provided with one or more PCIe interfaces, connected to one or more PCIe devices through the PCIe interfaces; one or more backplanes, each of which is configured with a backplane identifier and used to identify the maximum link width supported by the PCIe device plugged into the backplane, and each of the PCIe devices is plugged into a corresponding backplane;

[0010] A baseboard management controller BMC is connected to the backplane to which the PCIe device is plugged through a transmission bus, each transmission bus is provided with a number and connected to a corresponding one of the backplanes, and there is a preset corresponding relationship between the number of each transmission bus and the PCIe interface to which the PCIe device plugged into its corresponding backplane is connected. The BMC obtains the backplane identifier of the backplane to which the PCIe device is plugged and the number of the used transmission bus, and determines the channel splitting configuration Bifurcation information of each PCIe interface according to the obtained backplane identifier and the number of the transmission bus for use by the basic input and output system BIOS.

[0011] In an exemplary embodiment, determining the channel splitting configuration Bifurcation information of each PCIe interface according to the acquired backplane identifier and the number of the transmission bus includes:

[0012] For each backplane connected to the BMC and the transmission bus used, the BMC determines the maximum link width supported by the PCIe device plugged into the backplane according to the acquired backplane identifier, and determines the PCIe interface to which the PCIe device is connected according to the acquired number of the transmission bus and the preset correspondence between the number of the transmission bus and the PCIe interface;

[0013] Bifurcation information of each PCIe interface is determined according to the maximum link width supported by each PCIe device connected to each PCIe interface.

[0014] In an exemplary embodiment, the system further comprises:

[0015] The memory is used to store the Bifurcation information of each PCIe interface set by the BMC;

[0016] The BIOS is connected to the processor and is used to read the Bifurcation information in the memory and set the branch mode of the PCIe interface in the processor according to the Bifurcation information.

[0017] In an exemplary embodiment, the processor is one of the following: a central processing unit CPU, a data processing unit DPU, and a graphics processing unit GPU.

[0018] In an exemplary embodiment, the transmission bus is one of the following: a serial bidirectional communication interface bus I2C, a serial peripheral interface bus SPI, and a universal asynchronous receiver-transmitter bus URAT.

[0019] According to another embodiment of the present invention, there is provided an automatic branching method of a peripheral device interconnection expansion bus PCIe, which is applied to any of the above automatic branching system embodiments, and includes:

[0020] For each backplane connected to the BMC and the transmission bus used, obtain the backplane identifier of the backplane where each PCIe device is located and the number of the transmission bus used;

[0021] The Bifurcation information of each PCIe interface is determined according to the acquired backplane identifier and the number of the transmission bus for use by a basic input / output system BIOS.

[0022] In an exemplary embodiment, after determining the Bifurcation information of each PCIe interface according to the acquired backplane identifier and the number of the transmission bus, the method further includes:

[0023] Storing the Bifurcation information in a memory;

[0024] The Bifurcation information in the memory is read through BIOS, and the branch mode of each PCIe interface is set in the processor according to the Bifurcation information.

[0025] In an exemplary embodiment, determining the Bifurcation information of each PCIe interface according to the acquired backplane identifier and the number of the transmission bus includes:

[0026] Determine the maximum link width supported by the PCIe device plugged into each backplane according to the acquired backplane identifier, and determine the PCIe interface to which the PCIe device is connected according to the acquired transmission bus number and the preset correspondence between the transmission bus number and each PCIe interface;

[0027] Bifurcation information of each PCIe interface is determined according to the maximum link width supported by each PCIe device connected to each PCIe interface.

[0028] In an exemplary embodiment, before obtaining the number of the transmission bus used by each PCIe device, the method further includes:

[0029] A corresponding relationship between the numbers of the PCIe interface and the transmission bus is set.

[0030] In an exemplary embodiment, before obtaining the backplane identifier of the backplane where each PCIe device is located, the method further includes:

[0031] The correspondence between the maximum link width supported by the PCIe device and the backplane identifier is set.

[0032] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when run.

[0033] In the above-mentioned embodiment of the present invention, by establishing a correspondence between the backplane ID and the type of PCIe device plugged into the PCIe interface of the CPU, and establishing a correspondence between the transmission bus number of the PCIe device and the plugged PCIe interface, the BMC can perform correct PCIeBifurcation configuration on the PCIe interface of the CPU based on the plugged PCIe device, thereby avoiding the problem in the related art that a mapping table is set in the BIOS, and PCIeBifurcation is set according to the mapping table, which may cause BIOS setting errors and the need to release a new version of BIOS when facing new application scenarios, which increases the difficulty of BIOS maintenance. The correctness of the branch mode of the PCIe interface set by the BIOS is improved, and the difficulty of system and BIOS maintenance is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a block diagram of an automatic branching system of a peripheral interconnection expansion bus PCIe according to an embodiment of the present invention;

[0035] Figure 2 is a flow chart of an automatic branching method of a peripheral interconnection expansion bus PCIe according to an embodiment of the present invention;

[0036] Figure 3 The present invention is a flowchart of a specific execution process of an automatic branching system of a peripheral interconnection expansion bus PCIe according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0039] In existing server devices, the CPU and peripheral devices are connected through PCIe. A CPU usually has multiple standard PCIe interfaces for connecting SSDs, graphics cards, network cards, DPUs and other devices. A standard PCIe interface usually has 16 lanes. A standard PCIe interface may be used to connect different PCIe devices at the same time. It is necessary to set PCIeBifurcation through BIOS to divide the 16 PCIe lanes into different communication channels to connect different PCIe devices.

[0040] In order to solve the problem that the BIOS may set an incorrect PCIe Bifurcation configuration in a complex scenario, the present invention provides an implementation method of PCIe automatic branching in the following embodiment.

[0041] Example 1

[0042] According to one embodiment of the present invention, there is provided an automatic branching system for a peripheral interconnect expansion bus PCIe, Figure 1 is a block diagram of an automatic branching system of a peripheral interconnect expansion bus PCIe according to an embodiment of the present invention, such as Figure 1 As shown, including:

[0043] Processor 101, sets one or more ( Figure 1 Only two are shown) PCIe interfaces 108a and 108b, through which the PCIe interface 108b is connected to one or more ( Figure 1 Only two are shown) PCIe devices 102a and 102b are connected ( Figure 1 Only one PCIe interface is shown connected to two PCIe devices);

[0044] One or more backplanes ( Figure 1 Only two are shown in the figure, and the two backplanes 103a and 103b are marked with identifiers (such as 1 and 0), and the identifiers are used to identify the maximum link width supported by the PCIe device plugged into the backplanes. The PCIe devices 102a and 102b are plugged into the backplanes 103a and 103b, and the identifiers of the backplanes 103a and 103b and the numbers of the transmission buses 104a and 104b are obtained. According to the obtaining of the identifiers of the backplanes 103a and 103b and the numbers of the transmission buses 104a and 104b, the channel splitting configuration information of the PCIe interface 108b is determined, and the channel splitting configuration information of the PCIe interface 108b is stored in the memory 109 for use by the BIOS 107. The memory 109 is connected to the BMC 106 and the BIOS 107, respectively.

[0045] In this embodiment, by establishing a correspondence between the backplane ID and the type of PCIe device plugged into the PCIe interface of the CPU, and establishing a correspondence between the transmission bus number of the PCIe device and the plugged PCIe interface, the BMC can perform correct PCIe Bifurcation configuration on the PCIe interface of the CPU based on the plugged PCIe device.

[0046] In an exemplary embodiment, determining the channel splitting configuration information of the PCIe interface 108b according to the obtaining of the identifiers of the backplanes 103a and 103b and the serial numbers of the transmission buses 104a and 104b includes:

[0047] The BMC 106 determines the maximum link width (such as x8) supported by the PCIe device 102a plugged into the backplane 103a based on the acquired backplane identification (such as 0) of the backplane 103a, and determines that the PCIe interface connected to the PCIe device 102a is PCIe108b based on the acquired transmission bus number (such as 1a) and the preset correspondence between the transmission bus number and the PCIe108b interface. Similarly, the BMC 106 determines the maximum link width (such as x4) supported by the PCIe device 102b plugged into the backplane 103b based on the acquired backplane identification (such as 1) of the backplane 103b, and determines that the PCIe interface connected to the PCIe device 102b is PCIe interface 108b based on the acquired transmission bus number (such as 1b) and the preset correspondence between the transmission bus number and the PCIe108b interface.

[0048] According to the maximum link width (such as x8, x4) supported by the PCIe devices 102a and 102b connected to the PCIe interface 108, the channel splitting configuration information (x8+x4+x4) of the PCIe interface 108 is determined.

[0049] In an exemplary embodiment, the memory 109 is used to store the channel splitting information of the PCIe interfaces 108a and 108b set by the BMC 106. That is, the BMC 106 outputs different PCIe Bifurcations and stores them in the memory 109 and gives them to the BIOS for use, so the BIOS no longer needs to retrieve the PCIe Bifurcation from the mapping table, and the possibility of the PCIe device being unusable or running at a reduced speed due to configuration errors is reduced.

[0050] In an exemplary embodiment, the BIOS 107 is connected to the processor 101 and is used to read the channel splitting information in the memory 109 and set the branch mode of the PCIe interface in the processor 101 according to the channel splitting information.

[0051] In an exemplary embodiment, the processor 101 may be a central processing unit (CPU), a data processing unit (DPU), or a graphics processing unit (GPU).

[0052] In an exemplary embodiment, the transmission buses 104a and 104b may be, for example, serial bidirectional communication interface bus (Inter-Integrated Circuit, referred to as I2C), serial peripheral interface bus (Serial Peripheral Interface, referred to as SPI) or universal asynchronous receiver transmitter bus (Universal Asynchronous Receiver Transmitter, referred to as URAT).

[0053] Example 2

[0054] According to another embodiment of the present invention, there is provided an automatic branching method for a peripheral device interconnect expansion bus PCIe, which is applied to any of the above automatic branching system embodiments. Figure 2 1 is a flow chart of an automatic branching method of a peripheral device interconnection expansion bus PCIe according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0055] Step S202: When the BMC 106 detects that the BMC 106 is connected to the backplanes 103a and 103b to which the PCIe devices 102a and 102b are plugged, the BMC 106 obtains the backplane identifiers of the backplanes 103a and 103b where the PCIe devices 102a and 102b are located, and the numbers of the transmission buses 104a and 104b connected to the PCIe devices 102a and 102b.

[0056] When the BMC 106 detects that it is connected to the backplanes 103 a and 103 b , the BMC 106 acquires signals from the backplanes 103 a and 103 b through the transmission buses 104 a and 104 b .

[0057] Step S204: The BMC 106 sets the channel splitting information of the PCIe interface 108b according to the obtained identifiers of the backplanes 103a and 103b and the numbers of the transmission buses 104a and 104b.

[0058] Specifically, the maximum link widths supported by the PCIe devices 102a and 102b are determined according to the identifiers of the backplanes 103a and 103b, and the PCIe interfaces 108b to which the PCIe devices 102a and 102b are connected are determined according to the numbers of the transmission buses 104a and 104b.

[0059] For example, BMC 106 can determine based on the backplane identifier that the maximum link widths supported by PCIe devices 102a and 102b are x8 and x4 respectively, and determine based on the transmission bus number that PCIe devices 102a and 102b are both plugged into PCIe interface 108b. Therefore, BMC 106 can configure the channel splitting information of PCIe interface 108b to x8+x4+x4.

[0060] The relationship between the maximum link width supported by 102a and 102b and the channel splitting configuration information of the PCIe interface 108b is shown in Table 1:

[0061]

[0062] Table 1

[0063] Step S206, the channel splitting information is stored in the memory 109 for use by the BIOS 107, and the memory 109 is respectively connected to the BMC 106 and the BIOS 107. For example, the channel splitting information x8+x4+x4 of the PCIe interface 108b is saved in the memory 109, so that the BIOS does not need to take out the PCIe Bifurcation from the mapping table, and configuration errors are reduced.

[0064] In an exemplary embodiment, step 208 is also included:

[0065] Step S208, after the processor is powered on, the channel splitting information in the memory 109 is read by the BIOS 107, and the PCIe branching mode is set in the processor 101 according to the channel splitting information, so that the PCIe device plugged into the PCIe interface can work normally. For example, the BIOS can set the branching mode of the PCIe interface 108b to x8+x4+x4 during processing based on the channel splitting information x8+x4+x4 stored in the memory 109.

[0066] In this embodiment, before executing step S202, the correspondence between the PCIe interface and the number of the transmission bus can be preset, and the correspondence between the maximum link width supported by the PCIe device and the backplane identifier can be set.

[0067] Figure 31 is a flowchart of a specific execution process of an automatic branching system of a peripheral interconnection expansion bus PCIe according to an embodiment of the present invention. Figure 3 As shown, including:

[0068] Step S300, setting the correspondence between the PCIe interface and the transmission bus number, the correspondence may be that the transmission bus of PCIe108a is set to 0a / 0b / 0c / 0d, and the transmission bus number of PCIe108b is set to 1a / 1b / 1c / 1d, which correspond to lane0-lane3, lane4-lane7, lane8-lane11, lane12-lane15 of PCIe108a / b in sequence;

[0069] The correspondence between the maximum link width supported by the PCIe device and the backplane identifier is set, and the correspondence may be that the maximum link width x8 supported by the PCIe device corresponds to the backplane numbered 1 plugged into the device, and the maximum link width x4 supported by the PCIe device corresponds to the backplane numbered 0 plugged into the device;

[0070] In this embodiment, when two PCIe devices 102a and 102b (maximum link widths are x8 and x4, respectively) are externally connected to the processor, backplanes with different numbers are selected according to the maximum link widths of the PCIe devices, the PCIe device 102a is plugged into the backplane with backplane number 1, and the PCIe device 102b is plugged into the backplane with backplane number 0, and transmission buses with different numbers are selected according to the connected PCIe interfaces, the two PCIe devices are connected to the PCIe interface 108b, and two transmission buses numbered 1a and 1b are selected to connect the two PCIe devices to the BMC 106. When the BMC 106 detects that it is connected to the backplanes 103a and 103b, the BMC 106 includes: the BMC obtains signals from the backplanes 103a and 103b through the transmission buses 104a and 104b.

[0071] Step S302, determining that the maximum link widths supported by the PCIe devices 102a and 102b are x8 and x4 according to the identifications (1 and 0) of the backplanes 103a and 103b, and determining that the PCIe interface to which the PCIe devices 102a and 102b are connected is the PCIe interface 108b according to the numbers (1a and 1b) of the transmission buses 104a and 104b;

[0072] Step S304: Set the channel splitting information of the PCIe interface 108b to x8+x4+x4 according to the maximum link widths x8 and x4 supported by the PCIe devices 102a and 102b and the PCIe interface 108b.

[0073] Step S306, storing the channel splitting information in the memory 109 for use by the BIOS 107, wherein the memory 109 is connected to the BMC 106 and the BIOS 107.

[0074] Step S308: After the processor is powered on, BIOS 107 retrieves the channel splitting information in the memory 109 and sets the branch mode of the PCIe interface in the processor.

[0075] In the above embodiment of the present invention, each peripheral is plugged into a backplane, each backplane has a different ID, each backplane communicates with the BMC via I2C, the BMC can determine whether it is an X4 / X8 / X16 device based on the backplane ID, the BMC can confirm which group of X16 interfaces the backplane is plugged into based on the I2C number, and finally set each group of standard PCIe interfaces to the correct branch mode in the BIOS stage;

[0076] The corresponding relationship between the PCIe interface and the number of PCIe devices is shown in Table 2:

[0077]

[0078]

[0079] Table 2

[0080] As can be seen from Table 2, in the corresponding table of this embodiment, N=2, the maximum link width supported by the N PCI devices is (x8, x4). From the table, the transmission bus number is (1a, 1b), which shows that the connected PCIe interface is PCIe108b, and then the channel splitting information of the PCIe108b interface is (x8+x4+x4). Compared with the prior art, the technical solution provided by the present invention is very flexible to use, and there is no need to release a new version of BIOS to adapt to the change of PCIe Bifurcation due to the change of the external PCIe device of the server CPU; in addition, BMC outputs different PCIe Bifurcation according to the change of the CPU external device, stores it in the RAM of CPLD and gives it to BIOS for use, and no longer needs BIOS to take out PCIe Bifurcation from the mapping table, which also reduces the possibility of PCIe devices being unusable or running at a reduced speed due to configuration errors.

[0081] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0082] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An automatic branching system for a Peripheral Component Interconnect Express (PCIe) expansion bus, characterized in that, it includes: A processor, which is provided with one or more PCIe interfaces and is connected to one or more PCIe devices through the PCIe interfaces; One or more backplanes, each of which is configured with a backplane identifier and is used to identify the maximum link width supported by the PCIe devices plugged into the backplane, and each PCIe device is plugged into a corresponding backplane; A Baseboard Management Controller (BMC), which is connected to the backplane plugged with the PCIe device through a transmission bus. Each transmission bus is numbered and connected to a corresponding one of the backplanes in the backplane. There is a preset correspondence between the number of each transmission bus and the PCIe interface to which the PCIe device plugged into its corresponding backplane is connected. The BMC obtains the backplane identifier of the backplane plugged with the PCIe device and the number of the transmission bus used, and determines the channel splitting configuration (Bifurcation) information of each PCIe interface for the Basic Input / Output System (BIOS) to use according to the obtained backplane identifier and the number of the transmission bus.

2. The system according to claim 1, characterized in that, it includes: For each backplane connected to the BMC and the transmission bus used, the BMC determines the maximum link width supported by the PCIe devices plugged into the backplane according to the obtained backplane identifier, and determines the PCIe interface to which the PCIe device is connected according to the obtained number of the transmission bus and the preset correspondence between the number of the transmission bus and the PCIe interface; Determine the Bifurcation information of each PCIe interface according to the maximum link width supported by each PCIe device connected to each PCIe interface.

3. The system according to claim 1, characterized in that, The system further includes: The memory, which is used to store the Bifurcation information of each PCIe interface set by the BMC; The BIOS, which is connected to the processor and is used to read the Bifurcation information in the memory and set the branching mode of the PCIe interface in the processor according to the Bifurcation information.

4. The system according to claim 1, characterized in that, The processor is one of the following: Central Processing Unit (CPU), Data Processing Unit (DPU), Graphics Processing Unit (GPU).

5. The system according to claim 1, characterized in that, The transmission bus is one of the following: Inter-Integrated Circuit (I2C) bus, Serial Peripheral Interface (SPI) bus, Universal Asynchronous Receiver / Transmitter (UART) bus.

6. An automatic branching method for a Peripheral Component Interconnect Express (PCIe) expansion bus, which is applied to the automatic branching system of PCIe, characterized in that, the method includes: For each backplane connected to the BMC and the transmission bus used, obtain the backplane identifier of the backplane where each PCIe device is located and the number of the transmission bus used; Determine the Bifurcation information of each PCIe interface according to the obtained backplane identifier and the number of the transmission bus for use by the BIOS.

7. The method according to claim 6, wherein, after determining the Bifurcation information of each PCIe interface according to the obtained backplane identifier and the number of the transmission bus, further comprising: storing the Bifurcation information in a memory; reading, by the BIOS, the Bifurcation information in the memory, and setting, in the processor, the branch mode of each PCIe interface according to the Bifurcation information.

8. The method according to claim 6, wherein, determining the Bifurcation information of each PCIe interface according to the obtained backplane identifier and the number of the transmission bus includes: determining the maximum link width supported by the PCIe device plugged into each backplane according to the obtained backplane identifier, and determining the PCIe interface to which the PCIe device is connected according to the obtained transmission bus number and the preset correspondence between the transmission bus number and each PCIe interface; determining the Bifurcation information of each PCIe interface according to the maximum link width supported by each PCIe device connected to each PCIe interface.

9. The method according to claim 7, wherein, before obtaining the number of the used transmission bus, further comprising: setting the correspondence between the PCIe interface and the number of the transmission bus.

10. The method according to claim 7, wherein, before obtaining the backplane identifier of each backplane where each PCIe device is located, further comprising: setting the correspondence between the maximum link width supported by the PCIe device and the backplane identifier.

11. A computer-readable storage medium, wherein, a computer program is stored in the storage medium, and wherein the computer program is configured to execute the method described in any one of claims 6 to 10 when running.

Images