System on chip and power management method therefor

Abstract

The invention relates to a system-on-chip and a power management method for the system-on-chip. A system on chip includes a central processing unit, a memory directly coupled to the central processing unit, and a power controller. The power supply controller is configured to set the central processing unit and the memory in a normal operation power supply mode (the central processing unit and the memory are powered by a normal operation power supply voltage) or a standby power supply mode (the central processing unit is no longer powered and the memory is powered by a standby power supply voltage). The central processing unit is configured to execute a first microinstruction sequence before being set in a standby power mode, which is configured to copy an execution context of the computer program in the at least one data memory, the execution of the computer program being interrupted by the central processing unit to switch to the standby power mode; when leaving the standby power mode, the second microinstruction sequence is executed to restore the execution context stored in the memory in order to resume the execution of the interrupted computer program.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of French Application No. 2313113, filed on November 27, 2023, which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to systems on a chip, and in particular embodiments relates to the optimization of the energy consumption of such systems on a chip. Background Art

[0004] Systems on a chip are generally used in various electronic devices such as "smartphones", digital tablet computers, laptop computers, embedded systems, Internet of Things (IoT) devices, etc.

[0005] A system on a chip (also referred to by the acronym "SoC" from the English expression "System on a Chip") is an electronic component that incorporates several basic elements of a computer or electronic system on a single silicon chip. For example, a system on a chip includes a central processing unit, memory, and a communication interface on a single chip.

[0006] To avoid uselessly consuming energy, it is very important to optimize the energy consumption of a system on a chip. In particular, a system on a chip can be powered by a battery with a limited capacity. Therefore, the energy consumption stored in the battery should be limited as much as possible to increase the duration of use of the system on a chip between two recharges of the battery.

[0007] To optimize the energy consumption of a system on a chip, the system on a chip can include several power domains. Power domains (referred to in English as "power domains") correspond to different and electrically isolated regions of the system on a chip. These power domains allow different functional blocks or subsystems of the system on a chip to be powered independently. Therefore, using power domains allows for more efficient management of energy consumption and control of the power supply of its components according to the usage or operating state of the system on a chip.

[0008] In particular, power domains allow for selectively controlling and managing the power supply of the components of a system on a chip by adapting the power supply of these components to their needs. Therefore, when some components of the system on a chip are not in use, the energy consumption can be reduced.

[0009] The management of the power supply of the different components of a system on a chip can be ensured by an energy management system.

[0010] In particular, a system on a chip can include a power domain associated with its central processing unit and a power domain associated with its energy management system.

[0011] When the central processing unit is inactive, it is crucial to optimize the power consumption of the system-on-chip. In particular, during the execution of a computer program, the central processing unit can be made inactive. Then, it is crucial to be able to stop the power supply to the central processing unit while preserving the execution context of the interrupted computer program so that the execution context can be restored to resume the execution of the computer program after the power supply to the central processing unit is re-established.

[0012] In this regard, software solutions are known that allow the power supply to the central processing unit to be stopped while preserving the execution context of the interrupted computer program. However, these software solutions are generally complex and require the execution of a large number of instructions. Therefore, the storage and restoration of the execution context may be relatively slow.

[0013] During the execution of a computer program, when the power supply to the central processing unit is interrupted, flip-flops can also be used to preserve the execution context. However, the disadvantage of such flip-flops is that they occupy a large amount of space in the system-on-chip. Summary of the Invention

[0014] According to an embodiment, a system-on-chip includes: a central processing unit; a memory directly coupled to the central processing unit; a power controller configured to set the central processing unit and the memory to: be in a normal operating power mode (where the central processing unit and the memory are powered by a normal operating power voltage), or be in a standby power mode (where the central processing unit is no longer powered, and the memory is powered by a standby power voltage that is lower than the normal operating power voltage and sufficient to preserve the data stored in the memory). The central processing unit is configured to: before being set to be in the standby power mode, execute a first micro-instruction sequence configured to copy the execution context of the computer program in at least one data memory directly coupled to the central processing unit, the execution of the computer program by the central processing unit being interrupted to switch to the standby power mode; and when leaving the standby power mode, execute a second micro-instruction sequence to restore the execution context stored in the memory to resume the execution of the interrupted computer program.

[0015] According to an embodiment, a power management method for a system on a chip includes: setting, by a power controller, a central processing unit and a memory to be in a normal operation power mode, in which the central processing unit and the memory are powered by a normal operation power voltage. The system on a chip includes a central processing unit, a memory directly coupled to the central processing unit, and a power controller. The method includes: before being set to be in a standby power mode, executing, by the central processing unit, a first micro-instruction sequence configured to copy an execution context of a computer program in at least one data memory directly coupled to the central processing unit, and the execution of the computer program by the central processing unit is interrupted to switch to the standby power mode. The method includes: setting, by the power controller, the central processing unit and the memory to be in the standby power mode, in which the central processing unit is not powered, and the memory is powered by a standby power voltage, which is lower than the normal operation power voltage and is sufficient to save data stored in the memory. The method includes: setting, by the power controller, the central processing unit and the memory back to the normal operation power mode. The method includes: when leaving the standby power mode, executing, by the central processing unit, a second micro-instruction sequence to restore the execution context stored in the memory so as to resume the execution of the interrupted computer program. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more fully understand the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 illustrates a system on a chip (SOC);

[0018] Figure 2 illustrates a power supply management method for a system on a chip (SOC) such as previously described;

[0019] Figure 3 illustrates the states of registers REGF, CSR, PPR of a central processing unit (CPU) and the state of a memory (TCM) before switching to the standby power mode;

[0020] Figure 4 illustrates the saving of an execution context in the standby power mode; and

[0021] Figure 5 illustrates the restoration of the execution context when leaving the standby power mode. DETAILED DESCRIPTION

[0022] Accordingly, it would be advantageous to allow the power supply of the central processing unit of a system on a chip to be interrupted during the execution of a computer program and then to relatively quickly restart the central processing unit after the power supply is restored.

[0023] It is also advantageous to have a limited impact on the size of the system on chip.

[0024] According to one aspect, there is provided a system on chip comprising: a central processing unit; a memory directly coupled to the central processing unit; a power controller configured to set the central processing unit and the memory to: be in a normal operating power mode in which the central processing unit and the memory are powered by a normal operating power voltage, or be in a standby power mode in which the central processing unit is no longer powered and the memory is powered by a standby power voltage that is lower than the normal operating power voltage and sufficient to preserve the data stored in the memory, and wherein the central processing unit is configured to: before being set to be in the standby power mode, execute a first micro-instruction sequence that is specifically injected into the processing chain of the central processing unit by the execution of an instruction "goto_retention", the first micro-instruction sequence being adapted to copy the execution context of a computer program in at least one data memory directly coupled to the central processing unit, and the execution of the computer program by the central processing unit being interrupted to switch to the standby power mode; when leaving the standby power mode, execute a second micro-instruction sequence that is specifically injected into the processing chain of the central processing unit by the execution of an instruction "release_retention" to restore the execution context stored in the memory in order to resume the execution of the interrupted computer program.

[0025] Thus, before switching to the standby power mode, such a system on chip uses the memory directly coupled to the central processing unit to store the execution context of the computer program executed by the central processing unit.

[0026] Thus, when the central processing unit is inactive, the power supply to the central processing unit can be stopped while maintaining sufficient power supply to the memory directly coupled to the central processing unit to preserve the execution context until the power supply to the central processing unit is restored. This allows for a significant reduction in the power consumption of the system on chip.

[0027] Furthermore, once the power supply to the central processing unit is re-established, keeping the execution context in the memory directly coupled to the central processing unit enables the simple and rapid restoration of the execution context of the interrupted computer program. Thus, after the power supply to the central processing unit is re-established, the execution of the computer program can be quickly resumed.

[0028] This system-on-chip also has the following advantages, namely, storing and restoring the execution context in a memory directly coupled to the central processing unit to switch to and from the standby power mode is performed by the state machine of the central processing unit, rather than by a software component. This allows for a simpler and faster execution of switching to and from the standby power mode. This also allows ensuring that the entire execution context is correctly stored and restored in at least one data memory directly coupled to the central processing unit. In particular, this system-on-chip is configured to restore information about the context in a read-only register that can only be modified by a hardware component and not by a software component.

[0029] This system-on-chip also has the advantage of not using additional and bulky low-power components (such as flip-flops) to save the execution context of an interrupted computer program.

[0030] In an advantageous embodiment, the central processing unit includes a power mode controller configured to communicate with the power controller in order to negotiate with the power controller a switch to the standby power mode.

[0031] Advantageously, the central processing unit includes a control unit configured to execute a state machine that allows the execution of microinstructions to: store the execution context in at least one data memory directly coupled to the central processing unit before switching to the standby power mode, and restore the execution context in at least one data memory directly coupled to the central processing unit when leaving the standby power mode.

[0032] Preferably, the central processing unit is configured to execute instructions for entering and leaving the standby power mode, in particular the instruction "goto_retention" for entering the standby power mode and the instructions "luiX2 / addX2", "release_retention" and "mret" for leaving the standby power mode, which are stored in at least one program memory directly coupled to the central processing unit.

[0033] Advantageously, the central processing unit further includes a register configured to store an auxiliary stack pointer, which is configured to store the value of the main stack pointer before switching to the standby power mode, a first microinstruction sequence is configured to store the auxiliary stack pointer in at least one data memory directly coupled to the central processing unit before switching to the standby power mode, and a second microinstruction sequence is configured to restore the value of the auxiliary stack pointer to use it as the main stack pointer.

[0034] In an advantageous embodiment, the power controller is configured to: transmit a signal when leaving the standby power mode, which signal allows indicating to the central processing unit that the latter is returning from the standby power mode, such that the central processing unit executes the second microinstruction sequence.

[0035] According to another aspect, a power management method for the previously described system-on-chip is provided, the method comprising: before being set to be in a standby power mode, a first micro-instruction sequence is executed by a central processing unit, the first micro-instruction sequence being particularly injected into the processing chain of the central processing unit by executing an instruction "goto_retention", the first micro-instruction sequence being adapted to copy the execution context of a computer program in at least one data memory directly coupled to the central processing unit, and the execution of the computer program by the central processing unit being interrupted to switch to the standby power mode. The method comprises: when leaving the standby power mode, a second micro-instruction sequence is executed by the central processing unit, the second micro-instruction sequence being particularly injected into the processing chain of the central processing unit by executing an instruction "release_retention" to restore the execution context stored in the memory so as to resume the execution of the interrupted computer program.

[0036] In an advantageous implementation, the method comprises communication between a standby mode controller of the central processing unit and a power controller to negotiate switching to the standby power mode.

[0037] Advantageously, the method comprises: the central processing unit executes micro-instructions supplied by a state machine of a control unit of the central processing unit to: before switching to the standby power mode, store the execution context in at least one data memory directly coupled to the central processing unit, and when leaving the standby power mode, restore the execution context in at least one data memory directly coupled to the central processing unit.

[0038] Preferably, the method comprises the central processing unit executing instructions, particularly the instructions "goto_retention", "luiX2 / addX2", "release_retention" and "mret", to enter and leave the standby power mode, and these instructions are stored in at least one program memory directly coupled to the central processing unit.

[0039] Advantageously, the method further comprises: storing an auxiliary stack pointer in a register of the central processing unit, the auxiliary stack pointer allowing the value of the main stack pointer to be stored before switching to the standby power mode, the execution of the first micro-instruction sequence allowing the auxiliary stack pointer to be stored in at least one data memory directly coupled to the central processing unit before switching to the standby power mode, and the execution of the second micro-instruction sequence allowing the value of the auxiliary stack pointer to be restored to be used as the main stack pointer.

[0040] In an advantageous implementation, the method further includes: when leaving the standby power mode, a signal is transmitted by the power controller, which signal allows to indicate to the central processing unit that the latter is returning from the standby power mode, such that the central processing unit executes a second micro-instruction sequence.

[0041] Other advantages and features of the present invention will become apparent when examining the specific implementations of some non-limiting embodiments and through the accompanying drawings, in which:

[0042] Figure 1 Illustrates a system-on-chip (SOC).

[0043] The system-on-chip (SOC) includes a central processing unit (CPU), a power controller (PCTRL), and memories (TCM) directly coupled to the central processing unit (CPU) (these memories can also be referred to by the expression "tightly coupled memories").

[0044] The central processing unit (CPU) is configured to execute instructions of a computer program, in particular instructions of a computer program of the "firmware" type.

[0045] In particular, the central processing unit (CPU) includes elements well known to those skilled in the art, such as an arithmetic and logic unit (ALU), an address generation unit (AGU), a multiplication / division unit (MUL), etc.

[0046] The system-on-chip (SOC) uses several power modes, allowing to adapt its power consumption according to the use of different elements of the system-on-chip (SOC). The system-on-chip (SOC) is divided into several power domains, allowing to independently adapt the power between different power domains.

[0047] In particular, the system-on-chip includes a first power domain (PD_SOC) containing the power controller (PCTRL).

[0048] The system-on-chip (SOC) includes a second power domain (PD_CPU) containing the central processing unit (CPU).

[0049] The system-on-chip (SOC) includes a third power domain (PD_TCM) containing the memories (TCM).

[0050] The central processing unit (CPU) can be set to different power modes.

[0051] In particular, the central processing unit (CPU) can be set to a normal operation power mode. In this mode, the central processing unit (CPU) is powered by a voltage Vcore.

[0052] The central processing unit (CPU) can also be set to an inactive power mode. In this mode, the central processing unit (CPU) is no longer powered.

[0053] The central processing unit CPU can also be set to be in the standby power mode. In this mode, the central processing unit CPU is no longer powered, but is configured to save the execution context of the program before its power supply is cut off.

[0054] The switch from the normal operating power mode to the standby power mode is accomplished by executing a "goto_retention" instruction that can inject microinstructions into the processing chain ("pipeline") of the central processing unit CPU.

[0055] The central processing unit CPU includes a register bank REGF (or "register file"). The register bank REGF is used to temporarily store data during the execution of a computer program and during the processing of instructions by the central processing unit CPU.

[0056] The central processing unit CPU includes a memory controller coupled to a memory TCM. The memory TCM is a memory that is directly coupled and juxtaposed to the central processing unit CPU. The memory TCM is configured to provide fast access to the central processing unit, especially faster access compared to an external memory RAM or other types of memories that are far from the central processing unit. Thus, these memories TCM allow the performance of the computer program executed by the central processing unit CPU to be improved by reducing the number of memory accesses. The memory TCM also has a low latency, i.e., the duration elapsed between the request to access the memory and the memory providing the data. In particular, the latency of the memory TCM is within the range of one cycle of the central processing unit. Each memory TCM has a peripheral circuit and an array. The array is used to record data or instructions. The peripheral circuit is used to operate the memory TCM. For the same power mode, the peripheral circuit and the array can receive two different voltages.

[0057] The memory TCM can be set to be in the normal operating power mode or in the standby power mode. In the normal operating power mode, the peripheral circuit and the array of each memory TCM are powered by the voltage Vcore. In the standby power mode, the peripherals of each memory TCM are not powered, but the array of each memory TCM is powered by the voltage Vret to retain the information contained therein. The voltage Vret is a voltage lower than the voltage Vcore. The voltage Vret is adjusted to be lower than the voltage Vcore, but sufficient to enable the data in the memory TCM to be retained, and more specifically, as described later, to retain the execution context. For example, the voltage Vret is in the range of 0.6 volts.

[0058] The memory TCM includes a program memory TCPM and a data memory TCDM. The program memory TCPM is configured to store instructions of a computer memory to be executed by a central processing unit. During the execution of a computer program, the central processing unit uses an instruction pointer that points to the instruction to be executed stored in the program memory TCPM.

[0059] The data memory TCDM includes a main stack (region DZ of the data memory TCDM) that is configured to store data generated during the execution of a computer program, in particular, temporary data derived from a register bank REGF. The central processing unit also uses a main stack pointer SP that points to the address of the main stack of the data memory TCDM.

[0060] This main stack allows the content of the register bank REGF to be saved when changing the execution context. When restoring the execution context, this content is reconstructed in the register bank REGF. Then, the main stack pointer SP points to the address of the last piece of data saved in the region DZ of the data memory TCDM.

[0061] In addition, the data memory TCDM is also configured to have a standby region RETZ. This standby region RETZ is used to store the execution context of a program before the central processing unit CPU switches to the standby mode. The standby region RETZ starts at an address "retention_context_address" known to the control unit CTRLU of the central processing unit CPU.

[0062] The central processing unit CPU also includes a control and status register CSR ("control and status register"). The register CSR is configured to store the operation parameters of the central processing unit CPU and information about the status of the central processing unit CPU.

[0063] The central processing unit CPU also includes an interface P_PETR for private peripherals. This interface P_PETR includes registers PPR for private peripherals. The registers PPR for private peripherals allow the operation of peripherals on the system-on-chip (such as an interrupt controller, a memory protection unit) to be configured and controlled.

[0064] The central processing unit CPU also includes a control unit CTRLU. The control unit CTRLU is configured to implement a state machine FSM that allows microinstructions to be injected into the processing chain of the central processing unit CPU before the central processing unit CPU switches to the standby power mode and when leaving the standby power mode. In particular, before switching to the standby power mode, the instruction "goto_retention" is executed. The instruction "goto_retention" allows the state machine FSM to be implemented to inject a sequence of microinstructions into the processing chain of the central processing unit CPU. This sequence of microinstructions allows the execution context of a computer program to be saved in the memory TCM before switching to the standby power mode.

[0065] When leaving the standby power mode, the central processing unit CPU executes a series of microinstructions injected by the state machine FSM in the processing chain of the central processing unit. This series of microinstructions allows the execution context of an interrupted computer program to be restored in order to resume the execution of the computer program.

[0066] The execution context corresponds to all the data used by a computer program that needs to be saved in order to interrupt the computer program and then resume its execution at the point where the computer program was interrupted. The execution context includes the data stored in the register bank REGF, the data stored in the control and status register CSR, and the data stored in the register PPR for private peripherals.

[0067] The central processing unit CPU also includes a register SSP that is configured to store an auxiliary stack pointer ("shadow stack pointer"). Before switching to the standby power mode, the auxiliary stack pointer takes the value of the main stack pointer that points to the area in the data memory TCDM where the execution context of the interrupted computer program is stored. Thus, the register SSP allows the auxiliary stack pointer SP2 that points to the address of the main stack pointer to be stored before continuing to save the execution context in the data memory TCDM. The sequence of microinstructions injected by the state machine is configured to: before switching to the standby power mode, execute storing the auxiliary stack pointer SP2 in the standby area RETZ of the data memory TCDM. The storage of this auxiliary stack pointer SP2 allows the address of the main stack pointer corresponding to the top address of the area DZ of the data memory TCDM to be restored when leaving the standby power mode, and the area DZ stores the temporary data generated during the execution of the computer program before switching to the standby power mode.

[0068] The program memory TCPM further includes a region WRZ for storing instructions, which allows to exit the standby power mode by restoring the execution context of the interrupted program and then by inserting an instruction after the last instruction of the computer program executed before switching to the standby power mode. This region WRZ starts at the address "warm_restart_addr[31:0]". In particular, the control unit CTRLU knows the boot address "boot_address_i[31:0]" and the offset value, allowing to obtain the address "warm_restart_addr[31:0]" by adding it to the boot address.

[0069] In particular, this region WRZ of the program memory TCPM includes the instruction "luiX2 / addX2", which allows to load the value at the end of the standby region into register X2 of the register bank.

[0070] This region WRZ of the program memory TCPM further includes the "release_retention" instruction. This instruction allows to restore the execution context of the interrupted program stored in the data memory TCDM. In particular, this instruction "release_retention" allows to restore the data stored in the standby region of the program memory TCPM, which are associated with the register bank REGF, with the control and status register CSR, and with the registers PPR for the peripherals, in order to reconstruct these data in the corresponding registers. The instruction "release retention" is also configured to decrement the stack pointer loaded by the instruction "luiX2 / addX2" in register X2 of the register bank.

[0071] This region WRZ of the program memory TCPM further includes the instruction "mret". This instruction allows to restore the value of the instruction pointer ("program counter") stored in the data memory TCDM for use as the instruction pointer in order to execute the instruction inserted after the last instruction of the computer program executed before switching to the standby power mode.

[0072] The central processing unit CPU further includes an interrupt controller INT_CTRL. The interrupt controller is configured to receive interrupt signals. The interrupt signals may allow to stop the execution of the computer program.

[0073] The central processing unit CPU includes a power mode controller RET_CTRL. The power mode controller RET_CTRL is configured to communicate with the power controller PCTRL.

[0074] The power controller PCTRL is included in the first power domain. All elements of the first power domain are always powered by the voltage VSOC.

[0075] The power controller PCTRL is configured to control the power supply of different power domains of the system-on-chip.

[0076] In particular, the system-on-chip SOC is configured to generate a voltage VSOC, a standby voltage Vret, and a power supply voltage Vcore. These voltages are generated by a power supply, in particular, the generator of the system-on-chip SOC.

[0077] The system-on-chip SOC includes a first power switch PWRS1 and a second power switch PWRS2 included in the power domain PD_SOC.

[0078] The first switch PWRS1 is controlled by the power controller PCTRL. The first switch PWRS1 is configured to receive the voltage Vret and output or not output the voltage Vret in the power domain PD_TCM according to the command of the power controller PCTRL. In particular, the first switch outputs the voltage Vret only when the system-on-chip SOC is in the standby mode.

[0079] The second switch PWRS2 is controlled by the power controller PCTRL. The second switch PWRS2 is configured to receive the voltage Vcore and then output or not output the voltage Vcore to the power domains PD_TCM and PD_CPU according to the command of the power controller PCTRL. In particular, the second switch PWRS2 outputs the voltage Vcore only when the system-on-chip SOC is in the normal operating power mode.

[0080] The power controller PCTRL is configured to: when the central processing unit CPU requests the power controller PCTRL to switch to the standby mode, receive the signal RET_REQ sent by the power mode controller RET_CTRL of the central processing unit CPU.

[0081] The power controller PCTRL is configured to: when the power controller PCTRL accepts to switch the central processing unit CPU to the standby mode after receiving the signal RET_REQ, transmit the signal RET_ACK to the power mode controller RET_CTRL of the central processing unit CPU.

[0082] The power controller PCTRL is configured to: when the central processing unit CPU receives the signal RET_ACK, receive the signal RET_O sent by the power mode controller RET_CTRL of the central processing unit CPU. The power controller PCTRL is configured to switch the central processing unit CPU to the standby mode after receiving the signal RET_O.

[0083] The power controller PCTRL is also configured to transmit a signal RST_CSE to the central processing unit CPU when the power controller PCTRL switches the central processing unit CPU from the standby mode to the normal operation mode. The signal RST_CSE allows the control unit CTRLU of the central processing unit CPU to be instructed to execute a standby mode exit program to restore the execution context of the interrupted program.

[0084] The system-on-chip SOC also includes isolation units ISOC. These isolation units ISOC are included in the power domain PD_SOC. When the power supply is interrupted, the isolation units allow the domain PD_CPU to be isolated from the rest of the system-on-chip SOC. In particular, when the central processing unit no longer supplies power to other components of the system-on-chip SOC, the isolation units allow the propagation of floating signals originating from the central processing unit to be prevented.

[0085] Figure 2 Illustrated is a power supply management method for a system-on-chip SOC such as previously described. In particular, the power management method allows switching to a standby power mode and then returning to the normal operation power mode.

[0086] Before switching to the standby power mode, in step 20, the central processing unit CPU operates normally and executes a computer program, particularly a computer program of the "firmware" type. Thus, the central processing unit CPU and the memory TCM are set to be in the normal operation power mode NORM_M. Therefore, the power controller PCTRL controls the second switch PWRS2 such that the central processing unit CPU is powered by the voltage Vcore.

[0087] Figure 3 Illustrated is the state of the registers REGF, CSR, PPR of the central processing unit CPU and the state of the memory TCM before switching to the standby power mode.

[0088] Thereafter, in step 21, the computer program receives an interruption, causing the execution of the computer program and the execution of the instruction "goto_retention" to stop. The interruption may originate from a peripheral device of the system-on-chip SOC. Alternatively, the instruction "goto_retention" may be present in the executable code of the computer program and is executed during the execution of the computer program.

[0089] The instruction "goto_retention" allows a micro-instruction sequence to be injected into the processing chain of the central processing unit CPU.

[0090] In particular, once all outstanding memory accesses are completed, the instruction sequence is executed.

[0091] The microinstruction sequence injected by the instruction "goto_retention" by implementing the finite state machine FSM allows the interruption controller INT_CTRL of the central processing unit CPU to stop processing interrupts, so as to avoid any interrupts occurring when switching to the standby power mode.

[0092] Executing the microinstruction sequence enables the execution context of the interrupted program to be stored in the standby area RETZ of the data memory TCDM. In particular, executing the microinstruction sequence enables the value REGF_V of the register bank REGF, the value CSR_V of the control and status register CSR, and the value PPR_V of the register PPR for the peripheral device to be stored.

[0093] Thereafter, the microinstruction sequence allows the power mode controller RET_CTRL to generate a signal RET_REQ and transmit it to the power controller PCTRL.

[0094] Thereafter, the power controller PCTRL waits for the system on chip SOC to be ready to switch to the standby power mode, and then generates a signal RET_ACK and transmits it to the power mode controller RET_CTRL of the central processing unit CPU.

[0095] Once the signal RET_ACK is received, the execution of the microinstruction sequence allows the power mode controller RET_CTRL to generate a signal RET_O and transmit it to the power controller PCTRL thereafter. This signal RET_O allows indicating that the central processing unit is ready to switch to the standby power mode.

[0096] In step 22, once the signal RET_O is received, the power controller PCTRL switches the central processing unit CPU and the memory TCM to the retention power mode. To this end, the power controller PCTRL controls the first power switch PWRS1 to output the voltage Vret to the memory TCM. The power controller PCTRL also controls the second power switch PWRS2 to stop supplying power to the central processing unit CPU.

[0097] The power controller PCTRL also stops the timestamp signal and forces a reset of the central processing unit CPU with a reset signal ("reset").

[0098] The power controller also controls the isolation unit ISOC to isolate the central processing unit CPU.

[0099] Accordingly, the central processing unit CPU and the memory TCM are set to be in the standby power mode RET_M. In particular, the central processing unit CPU is not powered, and the memory TCM is powered by the voltage Vret. Accordingly, the data of the register bank REFF, the data of the control and status register CSR, and the data of the register PPR for the peripheral devices are cleared but retained in the standby area RETZ of the data memory TCDM.

[0100] Figure 4 The figure illustrates the saving of the context during the standby power mode.

[0101] Thereafter, at step 23, the power controller PCTRL can cause the central processing unit CPU and the memory TCM to leave the standby power mode depending on the needs of the system-on-chip SOC. In particular, when the central processing unit should process a new data sequence of the peripheral devices of the system-on-chip SOC, the standby power mode is exited.

[0102] To leave the standby power mode, the power controller PCTRL controls the first switch PWRS1 and the second switch PWRS2 to output the voltage Vcore to the central processing unit CPU and the memory TCM. Then, the central processing unit CPU and the memory TCM switch to the normal operation power mode NORM_M.

[0103] The power controller PCTRL also reconstructs the clock signal and the reset signal.

[0104] The power controller PCTRL also controls the isolation unit ISOC to stop the isolation of the central processing unit CPU.

[0105] The power controller PCTRL also transmits the signal RST_CSE to the central processing unit. This signal RST_CSE allows to indicate to the central processing unit CPU that the standby power mode is being left. Then, the central processing unit CPU can implement the program for leaving the standby power mode. This program is implemented by executing the power mode return function. In particular, the state machine FSM of the control unit CTRLU is configured to inject a micro-instruction sequence of the instruction "release_retention" into the processing chain ("pipeline") of the central processing unit CPU. Thereafter, the central processing unit CPU executes this micro-instruction sequence.

[0106] Specifically, the instruction "release_retention" is executed to restore the data stored in the standby area RETZ of the data memory TCDM, i.e., the execution context of the interrupted computer program. As previously indicated, some data REGF_V is associated with the register bank REGF, other data CSR_V is associated with the control and status register CSR, and still other data PPR_V is associated with the registers PPR for peripheral devices. These data are restored and then copied respectively into the register bank REGF, the control and status register CSR, and the registers PPR for peripheral devices. In addition, the value of the main stack pointer is modified by taking the value of the auxiliary stack pointer stored in the standby area RETZ, such that the main stack pointer points to the address at the top of the area DZ of the data memory TCDM. The value of the instruction pointer is also restored and stored in the control and status register CSR.

[0107] Figure 5 Illustrated is the restoration of the execution context when leaving the standby power mode.

[0108] Then, the instruction "mret" is executed to restore the instruction pointer from the control and status register CSR, in order to reconstruct the execution of the computer program from the address of the instruction N_INST, which follows the last instruction L_INST of the computer program executed before switching the central processing unit to the standby power mode.

[0109] Thereafter, the handling of interrupts by the interrupt controller INT_CTRL is reconstructed.

[0110] Thereafter, the execution of the computer program can be resumed in step 24.

[0111] The system-on-chip and the method described previously use a memory directly coupled to the central processing unit to store the execution context of the computer program executed by the central processing unit before switching to the standby power mode.

[0112] Thus, when the central processing unit is inactive, the power supply to the central processing unit can be stopped while maintaining sufficient power supply to the memory directly coupled to the central processing unit to save the execution context until the power supply to the central processing unit is restored. This allows for a significant reduction in the power consumption of the system-on-chip.

[0113] In addition, once the power supply to the central processing unit is reconstructed, storing the execution context in the memory directly coupled to the central processing unit enables a simple, fast, complete, and accurate restoration of the execution context of the interrupted computer program. Thus, after reconstructing the power supply to the central processing unit, the execution of the computer program can be quickly resumed.

[0114] The system-on-chip and the previously described method also have the following advantage, namely, storing and restoring the execution context in a memory directly coupled to the central processing unit to switch to and from the standby power mode is performed by the state machine of the central processing unit, rather than by a software component. This allows for a simpler, faster, and more accurate execution of switching to and from the standby power mode. In particular, this allows ensuring that the entire execution context is correctly stored and restored in at least one data memory directly coupled to the central processing unit. In particular, such a system-on-chip is configured to restore information about the context in read-only registers that can only be modified by hardware components and not by software components.

[0115] The system-on-chip also has the advantage of not using additional and bulky low-power components (such as flip-flops) to save the execution context of an interrupted computer program.

Claims

1. A system on chip, comprising: Central Processing Unit, memory, which is directly coupled to the central processing unit, A power controller is configured to set the central processing unit and the memory to: in a normal operating power mode in which the central processing unit and the memory are powered by a normal operating power voltage, or in a standby power mode in which the central processing unit is no longer powered and the memory is powered by a standby power voltage that is lower than the normal operating power voltage and sufficient to preserve data stored in the memory, and The central processing unit is configured as follows: prior to being placed in a standby power mode, executing a first sequence of microinstructions configured to replicate an execution context of a computer program in at least one data memory directly coupled to said central processing unit, said execution of said computer program by said central processing unit being interrupted to switch to the standby power mode, and When leaving the standby power mode, a second microinstruction sequence is executed to restore the execution context stored in the memory to resume the execution of the interrupted computer program. 2 . The system on chip of claim 1 , wherein the central processing unit comprises a power mode controller configured to communicate with the power controller to negotiate with the power controller to switch to the standby power mode.

3. The system on chip of claim 1 , wherein the central processing unit comprises a control unit configured to execute a state machine that allows execution of microinstructions to: Prior to switching to the standby power mode, storing the execution context in the at least one data memory directly coupled to the central processing unit, and Upon leaving the standby power mode, the execution context is restored in the at least one data memory directly coupled to the central processing unit.

4. The system on chip of claim 1, wherein the central processing unit is configured to execute instructions to enter and exit the standby power mode, the instructions being stored in at least one program memory directly coupled to the central processing unit.

5. The system on chip of claim 1 , wherein the central processing unit further comprises a register configured to store an auxiliary stack pointer, the auxiliary stack pointer being configured to store the value of the primary stack pointer before switching to the standby power mode, the first microinstruction sequence being configured to store the auxiliary stack pointer in the at least one data memory directly coupled to the central processing unit before switching to the standby power mode, and the second microinstruction sequence being configured to restore the value of the auxiliary stack pointer to use the auxiliary stack pointer as the primary stack pointer.

6. The system on chip according to claim 1, wherein the power controller is configured to: Upon leaving the standby power mode, transmitting a signal to the central processing unit, wherein the signal indicates to the central processing unit that the central processing unit is returning from the standby power mode, wherein, In response to receiving the signal, the central processing unit executes the second microinstruction sequence.

7. The system on chip of claim 1, wherein the first microinstruction sequence is injected into the processing chain of the central processing unit through the execution of a goto_retention instruction, and the second microinstruction sequence is injected into the processing chain of the central processing unit through the execution of a release_retention instruction.

8. The system on chip according to claim 7, wherein: The central processing unit is configured to execute the goto_retention instruction; When executed by the central processing unit, the goto_retention instruction causes a state machine to inject the first microinstruction sequence into the processing chain of the central processing unit; and The first microinstruction sequence is configured as: disabling the processing of interrupts by an interrupt controller of the central processing unit; causing the execution context of the interrupted computer program to be stored in a standby area of ​​the at least one data storage device; as well as A communication is initiated with the power controller to request a switch to the standby power mode.

9. The system on chip according to claim 7, wherein: The central processing unit is configured to execute the release_retention instruction; When executed by the central processing unit, the release_retention instruction causes a state machine to inject the second microinstruction sequence into the processing chain of the central processing unit; and The second microinstruction sequence is configured as: restoring data stored in a standby area of ​​the at least one data memory associated with the register set, the control and status registers, and the registers for the peripheral devices; reconstructing the restored data in a corresponding register of the central processing unit; modifying the value of the primary stack pointer based on the stored secondary stack pointer; as well as The value of the instruction pointer is restored to resume execution of the interrupted computer program.

10. The system on chip of claim 1, wherein the memory directly coupled to the central processing unit comprises: a program memory configured to store instructions of the computer program executed by the central processing unit; as well as a data memory including a main stack configured to store data generated during said execution of said computer program, said data including temporary data derived from a register set of said central processing unit, wherein said data memory further comprises a standby area configured to store said execution context of said computer program before said central processing unit switches to said standby power mode, said standby area starting at a reserved context address known to a control unit of said central processing unit.

11. The system on chip according to claim 1, further comprising: a first power switch, controlled by the power controller and configured to: receive the standby power voltage and output the standby power voltage to the power domain of the memory when the system on chip is in the standby power mode; as well as The second power switch is controlled by the power controller and is configured to receive the normal operation power supply voltage and output the normal operation power supply voltage to the power domain of the central processing unit and the power domain of the memory when the system on chip is in the normal operation power mode.

12. The system on chip according to claim 1, further comprising: An isolation unit is included in a power domain of the power controller, and the isolation unit is configured to: isolating a power domain of the central processing unit from other elements of the system on chip when power supply to the central processing unit is interrupted; as well as When the central processing unit is no longer supplying power to other components of the system-on-chip, floating signals originating from the central processing unit are prevented from propagating.

13. The system on chip according to claim 1, wherein the power controller is configured to: receiving a reservation request signal from a power mode controller of the central processing unit requesting switching to the standby power mode; After receiving the reserve request signal, transmitting a reserve confirmation signal to the power mode controller of the central processing unit to accept the switching to the standby power mode; and After the central processing unit receives the reserve confirmation signal, a ready signal is received from the power mode controller of the central processing unit, the ready signal indicating a ready switch to the standby power mode.

14. A power management method for a system on chip, the method comprising: The power controller sets a central processing unit and a memory to be in a normal operation power mode, in which the central processing unit and the memory are powered by a normal operation power voltage, the system on chip comprising the central processing unit, the memory directly coupled to the central processing unit and the power controller; prior to being placed in a standby power mode, executing by said central processing unit a first sequence of microinstructions, said first sequence of microinstructions being configured to replicate an execution context of a computer program in at least one data memory directly coupled to said central processing unit, said execution of said computer program by said central processing unit being interrupted to switch to the standby power mode; placing, by the power controller, the central processing unit and the memory in the standby power mode, in which the central processing unit is not powered and the memory is powered by a standby power voltage that is lower than the normal operating power voltage and sufficient to preserve data stored in the memory; setting the central processing unit and the memory back to the normal operating power mode by the power controller; as well as When leaving the standby power mode, a second microinstruction sequence is executed by the central processing unit to restore the execution context stored in the memory to resume the execution of the interrupted computer program.

15. The method according to claim 14, further comprising: The power mode controller of the central processing unit communicates with the power controller to negotiate switching to the standby power mode.

16. The method of claim 15, wherein the communicating comprises: The power mode controller of the central processing unit transmits a reservation request signal to the power controller to request switching to the standby power mode; receiving, by the power mode controller, a reserve confirmation signal from the power controller that accepts the switch to the standby power mode; as well as A preparation signal is transmitted from the power mode controller to the power controller, wherein the preparation signal indicates that the central processing unit is ready to switch to the standby power mode.

17. The method according to claim 14, further comprising: The microinstructions supplied by the state machine of the control unit of the central processing unit are executed by the central processing unit to: Prior to switching to the standby power mode, storing the execution context in the at least one data memory directly coupled to the central processing unit, and Upon leaving the standby power mode, the execution context is restored in the at least one data memory directly coupled to the central processing unit.

18. The method according to claim 14, further comprising: Instructions for entering and leaving the standby power mode are executed by the central processing unit and are stored in at least one program memory directly coupled to the central processing unit.

19. The method according to claim 14, further comprising: An auxiliary stack pointer is stored in a register of the central processing unit, the auxiliary stack pointer allowing the value of the primary stack pointer to be stored before switching to the standby power mode, the execution of the first microinstruction sequence allowing the auxiliary stack pointer to be stored in the at least one data memory directly coupled to the central processing unit before switching to the standby power mode, the execution of the second microinstruction sequence allowing the value of the auxiliary stack pointer to be restored to use the auxiliary stack pointer as the primary stack pointer.

20. The method according to claim 19, further comprising: When leaving the standby power mode, the power controller transmits a signal to the central processing unit; wherein the signal indicates to the central processing unit that the central processing unit is returning from the standby power mode; and In response to receiving the signal, the second microinstruction sequence is executed by the central processing unit.

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