DC voltage drop calculation method, computer equipment and storage medium

Abstract

The invention provides a direct-current voltage drop calculation method, computer equipment and a storage medium. The method comprises the following steps: acquiring a design file of a PCB (Printed Circuit Board) and setting initial simulation parameters; performing spatial discretization processing on a metal layer of the PCB on a two-dimensional plane according to the geometric layout information to generate a grid composed of triangular units; enabling packaging nodes in the initial simulation parameters to correspond to grid nodes, and calculating a conductance value of an edge of each triangular unit when the edge is equivalent to a linear resistor; enabling a non-current source device which cannot be represented by linear admittance in the PCB to be equivalent to an external circuit, enabling the edge of the triangular unit to be equivalent to a linear resistor in the external circuit, and constructing a circuit network model; and constructing a linear equation set matrix according to the circuit network model, and solving the linear equation set matrix to obtain the DC voltage drop of the PCB. According to the scheme, the requirement for computing resources can be remarkably reduced, the computing speed is increased, the simulation precision is ensured, and an accurate direct-current voltage drop computing result is provided for power supply integrity analysis.

Description

Technical Field

[0001] The present invention relates to the technical field of power integrity analysis, and in particular to a direct current voltage drop calculation method, a computer device and a storage medium. Background Art

[0002] Signal Integrity and Power Integrity analysis is used to study how to ensure the quality of power transmission and distribution in electronic systems. In signal integrity analysis, the calculation of DC IR-drop caused by conductor resistance loss in complex electronic systems such as printed circuit boards (PCBs) is particularly important. Most existing DC IR-drop calculation methods are based on three-dimensional finite element methods. By modeling the PCB board in three dimensions and discretizing the model space, the voltage distribution and current density on the PCB board are analyzed and calculated to obtain numerical results that affect the power integrity of the electronic system.

[0003] However, the three-dimensional finite element method inevitably causes extremely high computational complexity, especially when dealing with large-scale, highly complex power supply networks. The large number of discrete elements means an expanded matrix dimension and more consumption of computing resources. At the same time, geometric modeling of PCB boards is a crucial pre-processing step for finite element analysis. However, the complex traces, vias, and pads of each layer in the multi-layer structure of PCBs bring extremely high difficulty to geometric modeling. Many tiny geometric features on the structure have high modeling difficulties and have an important impact on the simulation results. At this time, overly detailed modeling will undoubtedly increase the requirements for computing resources, and over-simplification will lead to substandard simulation results. Therefore, there is an urgent need for a model processing method that can perform simulation calculations of DC voltage drop with higher efficiency, more conciseness, and clarity, to provide numerical support for the power integrity analysis of PCB boards. Summary of the invention

[0004] The purpose of the present invention is to provide a DC voltage drop calculation method, a computer device and a storage medium. By discretizing the space of the physical system of a PCB board into a two-dimensional circuit network model and using matrix solving technology to simulate complex voltage and current distribution, the demand for computing resources can be significantly reduced, the computing speed can be improved, and high simulation accuracy can be guaranteed, so as to provide accurate DC voltage drop calculation results for power integrity analysis.

[0005] The technical solution provided by the present invention is as follows: In a first aspect, the present invention provides a DC voltage drop calculation method for power integrity analysis of a PCB board, comprising the steps of: Obtaining a design file of a PCB board and setting initial simulation parameters, wherein the design file includes geometric layout information and electrical parameter information of the PCB board; Performing spatial discretization processing on the metal layer of the PCB board on a two-dimensional plane according to the geometric layout information to generate a grid composed of triangular units; Matching the package nodes in the initial simulation parameters with the grid nodes, and calculating the conductance value of the edge of each triangular unit when it is equivalent to a linear resistor; The non-current source devices in the PCB board that cannot be represented by linear admittance are equivalent to external circuit elements, and the sides of the triangular unit are equivalent to linear resistances in the external circuit elements, so as to construct a circuit network model; A linear equation matrix for calculating the voltage distribution of the PCB board is constructed according to the circuit network model, and the linear equation matrix is ​​solved to obtain the DC voltage drop of the PCB board.

[0006] In some embodiments, after obtaining the design file of the PCB board and setting the initial simulation parameters, before generating a mesh composed of triangular units, the method further includes: The PCB board is geometrically preprocessed according to the geometric layout information to determine the vertical vias of the PCB board, and the PCB board is decomposed layer by layer to determine the boundary of the calculation domain and the grid boundary, so as to generate grids for the metal layer of the PCB board layer by layer.

[0007] In some implementations, the constructing of the circuit network model further includes: The vertical vias of the PCB board are equivalent to linear resistors, and the two-dimensional sub-circuit network models constructed by the metal layers of different layers of the PCB board are merged into an overall two-dimensional circuit network model through the linear resistors.

[0008] In some embodiments, generating a mesh composed of triangular units includes: The metal layer of the PCB board is meshed layer by layer by a two-dimensional triangular mesh generation method based on Delaunay subdivision rule, and the generated mesh data is stored in the simulation data, wherein the mesh data includes mesh nodes and edges of the triangular unit.

[0009] In some implementations, after obtaining the DC voltage drop of the PCB board, the method further includes: The DC voltage drop is visualized to generate a voltage distribution diagram.

[0010] In some embodiments, after generating the voltage distribution diagram, the method further includes: Determining a target area where the DC voltage drop exceeds a preset value according to the voltage distribution diagram; The area to be adjusted of the PCB board is determined according to the target area, so as to adjust the geometric layout of the area to be adjusted of the PCB board.

[0011] In some implementations, the linear equation matrix for calculating the voltage distribution of the PCB board is constructed according to the circuit network model, including: Construct the two-dimensional Laplace equation and boundary conditions for describing the DC voltage distribution in the two-dimensional passive region; The linear equation system matrix is ​​constructed according to the simulation data and the two-dimensional Laplace equation.

[0012] In some implementations, the linear equation matrix for calculating the voltage distribution of the PCB board is constructed according to the circuit network model, including: Each edge of the discrete element in the grid is equivalent to a linear resistor to form a resistor network in the entire computational domain; constructing an admittance matrix of the resistor network; The linear equation system matrix is ​​constructed according to the admittance matrix.

[0013] In a second aspect, the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of a DC voltage drop calculation method described in the first aspect.

[0014] In a third aspect, the present application provides a computer storage medium having a computer program or instructions stored thereon, wherein the computer program or instructions, when executed by a processor, implements the steps of a DC voltage drop calculation method described in the first aspect.

[0015] The DC voltage drop calculation method, computer device and storage medium provided by the present invention can significantly reduce the demand for computing resources, improve the computing speed, ensure high simulation accuracy, and provide accurate DC voltage drop calculation results for power integrity analysis by discretizing the space of the physical system of the PCB board into a two-dimensional circuit network model and using matrix solving technology to simulate complex voltage and current distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present solution.

[0017] Figure 1 It is a schematic diagram of the overall process of an embodiment of the present invention; Figure 2is a schematic diagram of a PCB grid according to an embodiment of the present invention; Figure 3 It is a schematic diagram of voltage distribution visualization according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0019] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0020] Signal Integrity and Power Integrity analysis is used to study how to ensure the quality of power transmission and distribution in electronic systems. In power integrity analysis, the calculation of DC IR-drop caused by conductor resistance loss in complex electronic systems such as printed circuit boards (PCBs) and integrated circuits (ICs) is particularly important. Most of the existing DC IR-drop calculation methods are based on three-dimensional finite element methods. By modeling the PCB board in three dimensions and discretizing the model space, the voltage distribution and current density on the PCB board are analyzed and calculated to obtain numerical results that affect the power integrity of the electronic system.

[0021] However, the three-dimensional finite element method inevitably causes extremely high computational complexity, especially when dealing with large-scale and highly complex power networks. The large number of discrete elements means an expanded matrix dimension and more consumption of computing resources. At the same time, geometric modeling of PCB boards is a crucial pre-processing step for finite element analysis. However, the complex traces, vias, and pads of each layer in the multi-layer structure of PCBs bring extremely high difficulty to geometric modeling. Many tiny geometric features on the structure have high modeling difficulties and have an important impact on the simulation results. At this time, overly detailed modeling will undoubtedly increase the requirements for computing resources, and over-simplification will lead to substandard simulation results. In addition, the finite element boundary conditions of the power network are often very complex, especially in multi-layer PCB and package design. These complex boundary conditions may cause deviations between the simulation results and the actual situation, making it difficult to accurately predict power integrity problems, and complex boundary conditions will increase the difficulty of constructing finite element calculation matrices. Therefore, there is an urgent need for a model processing method that can perform simulation calculations of DC voltage drop with higher efficiency, more conciseness, and clarity, to provide numerical support for power integrity analysis of PCB boards and integrated circuits.

[0022] This solution can significantly reduce the demand for computing resources, improve the computing speed, and ensure high simulation accuracy by discretizing the space of the physical system of the PCB board into a two-dimensional circuit network model and using matrix solving technology to simulate complex voltage and current distribution, thus providing accurate DC voltage drop calculation results for power integrity analysis. The following is a detailed description of this solution in conjunction with the attached drawings: In one embodiment, the reference specification Figure 1 The present invention provides a DC voltage drop calculation method for power integrity analysis of a PCB board (or integrated circuit), comprising the steps of: S100, obtaining a design file of a PCB board and setting initial simulation parameters, wherein the design file includes geometric layout information and electrical parameter information of the PCB board.

[0023] Specifically, before the simulation process begins, this solution first reads in the design file of the PCB board (usually in the commonly used ODB++ format), and loads and stores the corresponding geometric layout information, electrical parameter information, etc. into the data structure. At the same time, the initial simulation parameters are set (including power distribution module, load power consumption standard, etc.) to complete the simulation preparation work.

[0024] S200, performing spatial discretization processing on the metal layer of the PCB board on a two-dimensional plane according to the geometric layout information, and generating a grid composed of triangular units.

[0025] This solution uses the core idea of ​​2D finite element to perform spatial discretization on the metal layer of the PCB board on a 2D plane and generate a mesh composed of triangular units. This solution simplifies the complex 3D problem into a 2D analysis by ignoring the effect of the metal layer thickness on the voltage distribution. This simplification is reasonable in most PCB designs because the thickness of the metal layer is usually very small and the effect on the voltage distribution can be ignored. Through this simplification, the complex 3D simulation problem of the PCB board can be converted into a discretization analysis on a 2D plane, which significantly reduces the complexity of modeling and the consumption of computing resources. The spatial discretization on the 2D plane not only improves the computational efficiency, but also can accurately restore the complex and tiny details in the PCB, such as the voltage distribution of the traces and vias. Especially in the design of PCBs with high-density wiring, this method can effectively balance the simulation accuracy and computational overhead, ensuring that sufficiently accurate simulation results are obtained within limited time and resources, providing a fast and effective solution for PCB power integrity analysis, especially suitable for design optimization and early design evaluation stages.

[0026] S300 , matching the package nodes in the initial simulation parameters with the grid nodes, and calculating the conductance value of the edge of each triangular unit when it is equivalent to a linear resistor.

[0027] After the mesh is generated, the conductance value of each mesh unit edge as a linear resistor is calculated. The formula for calculating the conductance value is based on the correspondence between the two-dimensional finite element K matrix and the admittance matrix in the node analysis method. The specific package nodes of the introduced initial simulation parameters are matched with the generated mesh nodes. The mesh generation is based on the two-dimensional geometric modeling of the PCB board, and the package nodes are not used as constraints for generating the mesh.

[0028] S400, non-current source devices in the PCB board that cannot be represented by linear admittance are equivalent to external circuit elements, and the sides of the triangular unit are equivalent to linear resistances in the external circuit elements to construct a circuit network model.

[0029] In the power integrity simulation of the PCB board, the packages and chips on the board are equivalent to external circuit elements. The boundary conditions that need to be considered in the finite element simulation can correspond to the way of adding power to the circuit in the improved node analysis method. In the improved node analysis method (MNA), each non-current source device that cannot be represented by linear admittance can be added to the calculation matrix as an additional equation. The addition of external circuit elements to the matrix of the circuit linear equation system is equivalent to the treatment of the boundary conditions of the finite element boundary value problem in mathematical form. Therefore, this scheme equates the non-current source devices in the PCB board that cannot be represented by linear admittance to external circuit elements, and equates the edges of the triangular unit to the linear resistance in the external circuit elements, so as to construct a circuit network model. Whether from the perspective of finite element electromagnetic simulation or circuit analysis, the circuit network model is essentially based on the linear relationship between nodes, and in the case of uniform conductive materials, the physical system reflected is the same, so their mathematical forms are consistent (the finite element K matrix is ​​consistent with the admittance matrix in the improved node analysis method in mathematical form).

[0030] S500: construct a linear equation matrix for calculating the voltage distribution of the PCB board according to the circuit network model, and solve the linear equation matrix to obtain the DC voltage drop of the PCB board.

[0031] After obtaining the circuit network model, a linear equation matrix for calculating the voltage distribution of the PCB board can be constructed according to the circuit network model. By solving the linear equation matrix, the DC voltage drop of the PCB board can be obtained, which can be used for power integrity analysis of the PCB board.

[0032] In one embodiment, based on the above-mentioned embodiment, a linear equation matrix for calculating the voltage distribution of the PCB board is constructed according to the circuit network model, including: The two-dimensional Laplace equation and boundary conditions for describing the DC voltage distribution in the two-dimensional passive area are constructed, and the matrix of the linear equation system is constructed according to the simulation data and the two-dimensional Laplace equation.

[0033] The core of this solution is still the finite element analysis of the boundary value problem describing the DC voltage distribution in the two-dimensional passive area. The control equation is expressed as a two-dimensional Laplace equation, as follows:

[0034] The boundary conditions can be expressed as:

[0035] In a multi-layer PCB structure, the change in voltage distribution in the metal layer thickness dimension can be ignored, so the variational formula for solving the two-dimensional finite element problem can be obtained:

[0036] Considering the case without any external excitation source, a set of linear equations for calculating the voltage distribution on the PCB board can be constructed based on this functional.

[0037] In one embodiment, based on the aforementioned embodiment, a matrix of a linear equation group for calculating the voltage distribution of a PCB board is constructed according to a circuit network model, and the following technical scheme may also be adopted: each edge of a discrete element in a grid is equivalent to a linear resistor to form a resistor network of the entire calculation domain; an admittance matrix of the resistor network is constructed; and a matrix of a linear equation group for calculating the voltage distribution of a PCB board is constructed according to the admittance matrix.

[0038] Specifically, the mathematical form of the matrix of the linear equations (passive part) used in this solution to calculate the voltage distribution of the PCB board can also be obtained by constructing the admittance matrix of the linear resistor network. The specific method is to equate each edge of the discrete element to a linear resistor to form the resistor network of the entire calculation domain. The two methods of constructing the matrix of the linear equations used to calculate the voltage distribution of the PCB board have their own advantages and disadvantages for different data structures, but they essentially reflect the same physical model, and the mathematical expression form is completely consistent, which has no effect on the results of the simulation calculation itself. However, no matter which method is used, the number of unknown quantities to be solved (i.e., the node voltage of each grid (circuit) node) is much smaller than the traditional three-dimensional finite element method. Therefore, the required computing resources are significantly reduced, and the simulation efficiency is significantly improved while still maintaining a high simulation accuracy.

[0039] In one embodiment, after obtaining the design file of the PCB board and setting the initial simulation parameters, before generating a mesh composed of triangular units, the method further includes: The PCB board is geometrically preprocessed according to the geometric layout information to determine the vertical vias of the PCB board. The PCB board is then decomposed layer by layer to determine the boundary of the calculation domain and the grid boundary, so as to generate grids for the metal layers of the PCB board layer by layer.

[0040] Constructing the circuit network model also includes: equating the vertical vias of the PCB board to linear resistors, and merging the two-dimensional sub-circuit network models constructed by the metal layers of different layers of the PCB board into an overall two-dimensional circuit network model through the linear resistors.

[0041] Generate a mesh composed of triangular units, including: generating meshes for the metal layer of the PCB board layer by layer through a two-dimensional triangular mesh generation method based on Delaunay subdivision rule, and storing the generated mesh data in simulation data, the mesh data including mesh nodes and edges of the triangular units.

[0042] Although this solution turns the voltage distribution problem on each metal plate into a two-dimensional problem by approximately ignoring the voltage distribution on the thickness of the metal layer, the entire PCB multilayer structure is still a three-dimensional structure, and another approximate method is still needed to describe the connection relationship between each metal plate. The present invention approximates the vertical via structure between each layer by equivalent to a linear resistor. Based on Ohm's law, the expression for calculating the linear resistor can be expressed as:

[0043] Through the connection of via resistors, metal plates of different layers in the PCB can be analyzed in the same 2D model. This approach takes advantage of the characteristics of DC transmission, eliminates the complex steps of 3D modeling for vias, and makes the overall simulation process more efficient. In addition, special treatment of via connections can also successfully integrate multi-layer PCB structures on the model to obtain qualified simulation results.

[0044] This solution performs corresponding geometric preprocessing based on the input PCB board geometry layout information, including layer-by-layer decomposition of vias and calculation of abstract linear resistors, determination of computational domain boundaries and mesh boundaries, and simplification of graphic constraint edges. After completing the preprocessing process, this solution uses a two-dimensional triangular mesh generator based on the Delaunay subdivision rule to generate meshes for the metal layer of the PCB layer by layer, retaining only the metal part, and storing the generated mesh data in the simulation data. In an example, the generated mesh is as follows: Figure 2 shown.

[0045] In one embodiment, based on the above embodiment, after obtaining the DC voltage drop of the PCB board, the method further includes: visualizing the DC voltage drop to generate a voltage distribution diagram.

[0046] After the voltage distribution diagram is generated, the method further includes: determining a target area where the DC voltage drop exceeds a preset value according to the voltage distribution diagram; and determining an area to be adjusted of the PCB board according to the target area, so as to adjust the geometric layout of the area to be adjusted of the PCB board.

[0047] After completing the simulation calculation process, this solution can also visualize the simulation results, i.e., the voltage distribution, and generate a voltage distribution diagram, such as Figure 3 As shown, it is convenient for users to better check whether the voltage meets the design specifications, more easily identify areas with excessive voltage, and find "hot spots" caused by uneven voltage distribution, so as to adjust the power distribution, routing, load layout, etc. in the design to obtain a more reliable and high-quality design.

[0048] The DC voltage drop calculation method provided by the present invention has at least the following technical effects: 1) Better simulation efficiency. This solution can significantly reduce the demand for computing resources by simplifying the DC analysis problem into an abstractly connected two-dimensional model. It is expected to increase the computing speed by 30%. It can also reduce the time consumption in the geometric preprocessing, mesh generation, electrical information processing and other links due to approximate operations.

[0049] 2) Maintaining simulation accuracy: This solution not only improves simulation efficiency, but also maintains high simulation accuracy (within 1% of the error of mature commercial software in the industry), providing accurate DC voltage drop analysis results for power integrity analysis. This high-precision DC voltage drop analysis result can provide important guarantees for ensuring the effectiveness, reliability and overall system performance of the power network design.

[0050] 3) Better applicability and flexibility. This solution can model various types of PCB models, adapt to the design requirements of circuit boards of different complexities and scales, and is suitable for a variety of application scenarios. At the same time, it allows users to flexibly set power supply parameters, accurately simulate various power supply distribution conditions, and help to more realistically reflect the actual operation. It can also easily add, delete, and adjust circuit elements in the simulation circuit, which is conducive to rapid iteration and comparative testing of the design.

[0051] 4) Reduce the cost of PCB and IC design and testing. Due to the savings in computing resources and time, this solution can reduce the cost of PCB and IC design and testing, especially reduce design rework and product failure rate caused by power integrity issues, thereby improving the economic benefits of the product.

[0052] In one embodiment, the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of a DC voltage drop calculation method of the aforementioned embodiment.

[0053] In one embodiment, the present application provides a computer storage medium having a computer program or instruction stored thereon, and when the computer program or instruction is executed by a processor, the steps of a DC voltage drop calculation method of the aforementioned embodiment are implemented.

[0054] In one embodiment, the present application provides a computer program product, including a computer program or instructions, which implements the steps of a DC voltage drop calculation method of the aforementioned embodiment when the computer program or instructions are executed by a processor.

[0055] A DC voltage drop calculation method of the present application can be implemented with program codes executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0056] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A method for calculating a DC voltage drop, characterized in that: Used for power integrity analysis of PCB boards, including the following steps: Obtaining a design file of a PCB board and setting initial simulation parameters, wherein the design file includes geometric layout information and electrical parameter information of the PCB board; Performing spatial discretization processing on the metal layer of the PCB board on a two-dimensional plane according to the geometric layout information to generate a grid composed of triangular units; Matching the package nodes in the initial simulation parameters with the grid nodes, and calculating the conductance value of the edge of each triangular unit when it is equivalent to a linear resistor; The non-current source devices in the PCB board that cannot be represented by linear admittance are equivalent to external circuit elements, and the sides of the triangular unit are equivalent to the linear resistance of the external circuit elements, so as to construct a circuit network model; A linear equation matrix for calculating the voltage distribution of the PCB board is constructed according to the circuit network model, and the linear equation matrix is ​​solved to obtain the DC voltage drop of the PCB board.

2. A DC voltage drop calculation method according to claim 1, characterized in that: After obtaining the design file of the PCB board and setting the initial simulation parameters, before generating a mesh composed of triangular units, the method further includes: The PCB board is geometrically preprocessed according to the geometric layout information to determine the vertical vias of the PCB board, and the PCB board is decomposed layer by layer to determine the boundary of the calculation domain and the grid boundary, so as to generate grids for the metal layer of the PCB board layer by layer.

3. A DC voltage drop calculation method according to claim 2, characterized in that: The construction of the circuit network model further includes: The vertical vias of the PCB board are equivalent to linear resistors, and the two-dimensional sub-circuit network models constructed by the metal layers of different layers of the PCB board are merged into an overall two-dimensional circuit network model through the linear resistors.

4. A DC voltage drop calculation method according to claim 2, characterized in that: The generating of a mesh composed of triangular units comprises: The metal layer of the PCB board is meshed layer by layer by a two-dimensional triangular mesh generation method based on Delaunay subdivision rule, and the generated mesh data is stored in the simulation data, wherein the mesh data includes mesh nodes and edges of the triangular unit.

5. A DC voltage drop calculation method according to claim 1, characterized in that: After obtaining the DC voltage drop of the PCB board, the method further includes: The DC voltage drop is visualized to generate a voltage distribution diagram.

6. A DC voltage drop calculation method according to claim 5, characterized in that: After the voltage distribution diagram is generated, the method further includes: Determining a target area where the DC voltage drop exceeds a preset value according to the voltage distribution diagram; The area to be adjusted of the PCB board is determined according to the target area, so as to adjust the geometric layout of the area to be adjusted of the PCB board.

7. A DC voltage drop calculation method according to claim 1, characterized in that: The linear equation matrix for calculating the voltage distribution of the PCB board is constructed according to the circuit network model, including: Construct the two-dimensional Laplace equation and boundary conditions for describing the DC voltage distribution in the two-dimensional passive region; The linear equation system matrix is ​​constructed according to the simulation data and the two-dimensional Laplace equation.

8. A DC voltage drop calculation method according to claim 1, characterized in that: The linear equation matrix for calculating the voltage distribution of the PCB board is constructed according to the circuit network model, including: Each edge of the discrete element in the grid is equivalent to a linear resistor to form a resistor network in the entire computational domain; constructing an admittance matrix of the resistor network; The linear equation system matrix is ​​constructed according to the admittance matrix.

9. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of a DC voltage drop calculation method according to any one of claims 1 to 8.

10. A computer storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of a DC voltage drop calculation method according to any one of claims 1 to 8 are implemented.

Images