Chip Logic Function Verification Method, Computer Device, Program Product and Medium

Abstract

The present invention provides a method for verifying the logic function of a chip, a computer device, a program product, and a medium, including: obtaining a partitioning scheme of the backend design for each sub-module of the chip to re-partition the chip into several modules to be verified; obtaining an RTL design scheme corresponding to the module to be verified; keeping the ports of the module to be verified unchanged and obtaining a gate-level netlist corresponding to the RTL design scheme; performing physical implementation of the module to be verified through the gate-level netlist and EDA tools, and obtaining a design netlist after physical implementation; obtaining the timing information of each module to be verified after timing convergence and the first delay from the port of each module to be verified to the target register according to the design netlist, and respectively marking the ports of each module to be verified by subtracting the first delay from a preset delay, so as to perform logic function verification with timing information on the module to be verified. This solution can optimize the human and calculator resources in the entire design process and improve the efficiency of chip logic function verification.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a chip logic function verification method, a computer device, a program product and a medium. Background Art

[0002] The design stage of a chip is divided into a front-end design stage and a back-end design stage according to the process: the front-end design stage is responsible for logic function design and logic function verification without timing information; the back-end design stage is to perform physical implementation and physical verification based on the netlist file containing design information provided by the front-end design, and provide the netlist and timing information file after physical implementation based on the physical information of the design; the front-end design then performs logic function verification with timing information based on the netlist and timing information file after physical implementation, and the chip design is completed if the verification passes.

[0003] With the rapid development of integrated circuits, the scale of chips is getting larger and larger, and they will contain many modules of different sizes. However, the criteria for module division of the entire chip in the front-end design and the back-end design are different. When the front-end design and verification are mainly based on the tightness of logical connections, the back-end design also needs to consider the scale of logic size on the basis of the tightness of logical connections. This leads to conflicts in the processing of modules between the front-end design and the back-end design: based on the considerations of efficiency and timing verification, the front-end design expects each module to be processed as it is; for some larger-scale modules, the back-end design expects to disassemble them into multiple smaller modules for processing to avoid exceeding the processing scale of EDA tools. Similarly, for some smaller modules, the back-end design expects to merge them for processing to improve the back-end verification efficiency. Therefore, there is an urgent need for a chip logic function verification solution that can take into account the requirements of the front-end design and the back-end design without increasing the complexity of the entire design process, and optimize the human and calculator resources in the entire design process. Summary of the Invention

[0004] The purpose of the present invention is to provide a chip logic function verification method, a computer device, a program product and a medium, which can realize the disassembly and merging of any module at the original level of the front-end by the back-end without increasing the workload of the front-end or the back-end, thereby optimizing the human and calculator resources in the entire design process and improving the efficiency of chip logic function verification.

[0005] The technical solution provided by the present invention is as follows:

[0006] In a first aspect, the present application provides a chip logic function verification method, including the steps of:

[0007] Obtain the division scheme of each sub-module of the chip to be verified by the back-end design, and re-divide the chip to be verified into several modules to be verified;

[0008] Perform a logic function verification on the module to be verified without timing information, and obtain a register transfer level design scheme corresponding to the module to be verified;

[0009] Keep the ports of the module to be verified unchanged, and obtain a gate-level netlist corresponding to the register transfer level design scheme;

[0010] Keep the ports of the module to be verified unchanged, perform physical implementation of the module to be verified through the gate-level netlist and EDA tools, and obtain a design netlist corresponding to the module to be verified after physical implementation;

[0011] Obtain the timing information of each module to be verified after timing convergence according to the design netlist;

[0012] Obtain the first delay from the port of each module to be verified to its corresponding target register according to the timing information, and label the ports of each module to be verified with the second delay obtained by subtracting the first delay from a preset delay respectively, so as to perform a logic function verification on the module to be verified with timing information.

[0013] In some embodiments, when disassembling the first sub-module into several first modules to be verified through the partitioning scheme, perform a logic function verification on the first modules to be verified without timing information, obtain the register transfer level design schemes of two levels of the first sub-module and several first modules to be verified corresponding to the first sub-module, keep the ports of the first sub-module unchanged, and obtain the gate-level netlist corresponding to the register transfer level design scheme.

[0014] In some embodiments, when merging several second sub-modules into a second module to be verified through the partitioning scheme, perform a logic function verification on the second module to be verified without timing information, obtain the register transfer level design schemes of two levels of the second module to be verified and several second sub-modules corresponding to the second module to be verified, keep the ports of several second sub-modules unchanged, and obtain the gate-level netlist corresponding to the register transfer level design scheme.

[0015] In some embodiments, the obtaining the timing information of each module to be verified after timing convergence according to the design netlist includes:

[0016] Keep the ports of the module to be verified unchanged, perform timing repair of the module to be verified according to the design netlist until timing convergence is achieved, and obtain the timing information of each module to be verified after timing convergence.

[0017] In some embodiments, the preset delay is 60%-80% of the entire clock cycle from the port of the module to be verified to the target register.

[0018] In some embodiments, the partitioning scheme includes disassembling, combining, or leaving unchanged each sub-module of the chip to be verified.

[0019] In some embodiments, obtaining the first delay from the port of each module to be verified to the target register according to the timing information includes:

[0020] Scraping the first delay from the port of each module to be verified to the target register from the timing information through a script.

[0021] In a second aspect, the present application provides a computer device, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the chip logic function verification method described in the first aspect.

[0022] In a third aspect, the present application provides a computer storage medium, on which a computer program or instruction is stored. When the computer program or instruction is executed by a processor, the steps of the chip logic function verification method described in the first aspect are implemented.

[0023] In a fourth aspect, the present application provides a computer program product, including a computer program or instruction. When the computer program or instruction is executed by a processor, the steps of the chip logic function verification method described in the first aspect are implemented.

[0024] Through a chip logic function verification method, computer device, program product, and medium provided by the present invention, in the entire chip design process, only simple tool settings are added, the hierarchy and its ports to be maintained at the front end are retained, and the timing information is updated and statistically analyzed using short script commands, so that any splitting and combining of the original hierarchy at the front end can be achieved at the back end without increasing the workload at the front end or the back end, realizing the optimization of human and calculator resources in the entire design process, and at the same time being able to optimize the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following will further illustrate the above characteristics, technical features, advantages, and implementation methods of the solution in a clear and understandable manner in combination with the drawings of the preferred embodiments.

[0026] Figure 1 is a schematic flowchart of the logic function verification in the chip design process;

[0027] Figure 2 is a schematic diagram of the distribution of each module at the top layer of a chip;

[0028] Figure 3 It is a schematic diagram of module splitting after backend optimization of a chip;

[0029] Figure 4 It is a timing schematic diagram of different ports when each module of a chip is processed separately and its logical function is verified;

[0030] Figure 5 It is a timing schematic diagram of different ports when each module of a chip is processed together and its logical function is verified;

[0031] Figure 6 It is a schematic diagram of the overall process of an embodiment of the present invention;

[0032] Figure 7 It is a first delay schematic diagram captured by each module to be verified in an embodiment of the present invention. Detailed implementation manners

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation manners of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings and other implementation manners can be obtained.

[0034] To make the drawings concise, only the parts related to the present invention are schematically shown in each drawing, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, components with the same structure or function are only schematically shown for one of them, or only one of them is marked. In this article, "one" not only means "only one", but also means "more than one" situation.

[0035] As Figure 1 shown, the design stage of the chip is divided into a front-end design stage and a backend design stage according to the process: the front-end design stage is responsible for logical function design and logical function verification without timing information; the backend design stage is to perform physical implementation and physical verification based on the netlist file containing design information provided by the front-end design, and provide the netlist after physical implementation and the timing information file based on the physical information of the design; the front-end design then performs logical function verification with timing information based on the netlist and timing information file after physical implementation, and if the verification is passed, the chip design is completed.

[0036] However, with the rapid development of integrated circuits, the scale of chips is getting larger and larger, and they will contain many modules of different sizes. For example, as Figure 2The top layer of a chip shown includes multiple modules such as A, B, C, D, E, F, and G. During the design process, generally different designers are responsible for the parallel development of the top layer and each of the modules A, B, C, D, E, F, and G respectively to accelerate the chip design progress.

[0037] During this design process, the criteria for module division in the front-end design and the back-end design of the entire chip are not consistent. Therefore, it will also lead to inconsistent module schemes expected to be divided for the chip, resulting in certain conflicts. Specifically, during the front-end design and verification, it is mainly based on the tightness of logical connections, while during the back-end design, on the basis of the tightness of logical connections, the scale of logical size also needs to be considered. This leads to conflicts in the processing of modules between the front-end design and the back-end design: considering efficiency and timing verification, the front-end design expects each module to be processed as it is; for some larger-scale modules, the back-end design expects to break them down into multiple smaller modules for processing to avoid exceeding the processing scale of EDA tools. Similarly, for some smaller modules, the back-end design expects to merge them for processing to improve the back-end verification efficiency.

[0038] Specifically, taking Figure 2 the chip distribution shown as an example, modules B and C are relatively suitable for the processing scale of back-end EDA tools; while the scale of module A is much larger than that of modules B and C, exceeding the processing scale that the back-end EDA tools can handle. Therefore, from the back-end perspective, it is necessary to split module A into smaller modules, such as splitting it into module A1 and module A2 for processing; while modules D / E / F / G are relatively small in scale, and the back-end EDA tools can handle a larger scale. Therefore, from the back-end perspective, it is more inclined to merge modules D / E / F / G together for processing, and merging multiple modules can avoid the waste of human resources and machine resources caused by simultaneously processing multiple modules in parallel. At the same time, merging modules D / E / F / G may also bring area optimization. For example, the area of module D itself is mainly occupied by wiring, and the area occupied by its logical units is relatively low, while module E itself has less wiring and mainly the logical units need to occupy area. If modules D and E are separated into two modules for physical implementation, their physical boundaries are isolated from each other and cannot be utilized; but if modules D and E are merged together, their areas can be mutually absorbed, and the total area used will be smaller than the area when modules D and E are separately implemented. Therefore, according to the above example, the original Figure 2 corresponding module splitting scheme has been modified by the back-end to the module distribution shown in Figure 3 .

[0039] To sum up, in the module merging and splitting schemes, there are two types of conflicts in the processing between the front-end and the back-end that need to be resolved:

[0040] (1)Larger front-end modules need to be further disassembled at the back end;

[0041] (2)Smaller front-end modules need to be further combined at the back end.

[0042] In conflict (1), the reason the front end does not want further disassembly is as follows: The front-end verification platform hopes that A is a complete subsystem. In this way, the input and output ports are clear, there is a mature protocol, and it is easier to verify. It can quickly verify whether the subsystem is correct with fewer input combinations and corresponding clear output results. Moreover, when A is split into two smaller modules A1 + A2, the division of A1 and A2 is more a structure combined by scale within the system. The input and output ports of A1 and A2 themselves no longer correspond well to the mature protocol. When front-end designers need to verify, they need to spend more energy studying the input combinations of the various functions of the disassembled subsystem at the A1 / A2 ports and the corresponding clear output results. This workload may be very large (even impossible to complete within a certain period).

[0043] In conflict (2), the reason the front end does not want further combination is as follows: When optimizing the D / E / F / G modules at the back end, for each module, the back-end EDA tool may generate / copy some new ports and optimize / merge some original ports. In this way, when front-end designers perform timing information verification based on the netlist after back-end physical design, they need to do a lot of research to map to the original ports and understand the functional changes. This workload will be extremely large, even impossible to complete within a certain period. Moreover, because the processing of the EDA tool may be inconsistent each time, it is necessary to wait until the netlist of the final version of the physical design optimization is completed before specifically studying the mapping between ports. This is even more unacceptable in the work plan. At the same time, when D / E / F / G are treated as separate modules, each module in D / E / F / G has a fixed physical boundary. Therefore, there is a certain consistency in the timing between different ports of each module. When performing logic function verification with timing functions at the front end, as Figure 4 shown, a fixed delay can be given to all ports, and it is very convenient to adjust the timing of the ports so that the timing of the entire port is satisfied, completing the function verification with timing information. However, when D / E / F / G are combined into a new module, the ports of D / E / F / F themselves have become the module pins of a soft module. Therefore, the timing difference between different ports of each module is relatively large. As Figure 5 shown, it is very difficult for the front end to adjust the port timing with the same fixed delay, resulting in a still large subsequent workload.

[0044] Therefore, there is an urgent need for a chip logic function verification solution that can balance the requirements of front-end design and back-end design without increasing the complexity of the entire design process, and optimize the human and calculator resources in the entire design process. This solution addresses the conflict in the module division scheme between the front-end and back-end designs in the entire chip design process. Without increasing the complexity of the entire design process, it takes the optimization of the module division scheme by the back-end design as the standard, which can achieve the optimization of the human and machine resources in the entire back-end process design and take into account the optimization of the chip area. At the same time, through script and tool settings, it can meet the requirements of front-end verification without changing (i.e., without adding / removing and changing the port function definitions) the ports of each front-end defined module to be verified, and can conveniently provide the required timing information for the ports to meet the timing of the ports. The following will describe this solution in detail with reference to the accompanying drawings:

[0045] In one embodiment, referring to the attached drawings of the specification Figure 6 , this application provides a chip logic function verification method, including the steps:

[0046] S100. Obtain the division scheme of each sub-module of the chip to be verified by the back-end design, and re-divide the chip to be verified into several modules to be verified.

[0047] Specifically, the division scheme includes disassembling, merging or maintaining the status quo of each sub-module of the chip to be verified. Taking Figure 2 the chip distribution shown as an example, modules B and C are relatively suitable for the scale that can be processed by back-end EDA tools and can remain unchanged; while the scale of module A is relatively large and exceeds the scale that the back-end EDA tools can process, so module A is split into smaller modules A1 and A2; while the scales of modules D / E / F / G are relatively small, modules D / E / F / G can be merged into module H for processing. This application does not limit the specific disassembly and merging schemes, which can be flexibly adjusted according to requirements and hardware conditions.

[0048] S200. Perform logic function verification without timing information on the modules to be verified, and obtain the register transfer level design scheme corresponding to the modules to be verified.

[0049] That is, after re-dividing the chip to be verified into several modules to be verified, first perform front-end design, perform logic function verification without timing information on the modules to be verified, and obtain the register transfer level design scheme corresponding to the modules to be verified.

[0050] For different types of modules to be verified, when the first sub-module is disassembled into several first modules to be verified in the partitioning scheme, the logical function verification of the first module to be verified without timing information is to obtain the register transfer level (RTL) design schemes at two levels of the first sub-module and several first modules to be verified corresponding to the first sub-module, so as to Figure 2 Taking the chip distribution shown in Figure 2 as an example, this scheme obtains the RTL design at two levels of A+A1 / A2. When several second sub-modules are combined into a second module to be verified in the partitioning scheme, the logical function verification of the second module to be verified without timing information is to obtain the RTL design schemes at two levels of the second module to be verified and several second sub-modules corresponding to the second module to be verified. Similarly, taking the chip distribution shown in

[0051] as an example, the obtained RTL design is at two levels of H+D / E / F / G.

[0052] Based on the RTL design provided by the front-end and the list information of the modules to be verified, keeping the ports of the modules to be verified unchanged, generate the gate-level netlist corresponding to the front-end RTL design. When the first sub-module is disassembled into several first modules to be verified in the partitioning scheme, keep the ports of the first sub-module unchanged and obtain the gate-level netlist corresponding to the RTL design scheme. Taking the chip distribution shown in Figure 2 as an example, keep the ports of module A unchanged and obtain the gate-level netlist corresponding to the RTL design scheme. When several second sub-modules are combined into a second module to be verified in the partitioning scheme, keep the ports of the several second sub-modules unchanged and obtain the gate-level netlist corresponding to the RTL design scheme. Taking the chip distribution shown in Figure 2 as an example, keep the ports of modules D / E / F / G unchanged and obtain the gate-level netlist corresponding to the RTL design scheme.

[0053] S400. Keep the ports of the modules to be verified unchanged, and perform the physical implementation of the modules to be verified through the gate-level netlist and EDA tools, and obtain the design netlist corresponding to the modules to be verified after physical implementation.

[0054] The physical implementation includes automatic placement and routing, etc. Perform the physical implementation of the modules to be verified according to the gate-level netlist information through EDA tools, and during the physical implementation process of EDA tools, keep the ports of the modules to be verified unchanged to generate the design netlist after physical implementation.

[0055] S500. Obtain the timing information of each module to be verified after timing convergence according to the design netlist.

[0056] In a specific implementation, timing information of each module to be verified after timing convergence is obtained according to the design netlist, including: keeping the ports of the module to be verified unchanged, performing timing repair on the module to be verified according to the design netlist until timing convergence is achieved, and obtaining the timing information of each module to be verified after timing convergence.

[0057] S600. Obtain the first delay from the port of each module to be verified to its corresponding target register according to the timing information, and label the ports of each module to be verified with the second delay obtained by subtracting the first delay from the preset delay respectively, so as to perform logic function verification with timing information on the module to be verified.

[0058] Obtaining the first delay from the port of each module to be verified to the target register according to the timing information includes: scraping the first delay from the port of each module to be verified to its corresponding target register from the timing information through a script. The specific form of the script is not limited in this application, as long as it can complete the scraping work. As Figure 7 shown, in this solution, a script is used to scrape the first delay T_delay from the port of each module to be verified that needs to be maintained at the front end to the target register. Generally, in order to meet the setup time and hold time, the delay from the port to the target register is increased to the preset delay, and the preset delay is 60%-80% of the entire clock cycle from the port of the module to be verified to the target register. For example, 70% of the entire clock cycle. At each front end where the port of the module to be verified needs to be maintained, it is labeled with the second delay of 0.7×cycle - T_delay, so as to perform logic function verification with timing information on the module to be verified.

[0059] Through the chip logic function verification method provided by this application, in the entire chip design process, only simple tool settings are added, the hierarchy and its ports that the front end wants to maintain are kept, and short script commands are used to complete the update and statistics of timing information, so that any splitting and merging of the original hierarchy at the front end can be achieved at the back end without increasing the workload of the front end or the back end, realizing the optimization of human and calculator resources in the entire design process, and at the same time being able to further optimize the chip area.

[0060] In one embodiment, this application provides a computer device, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the chip logic function verification method in the foregoing embodiment.

[0061] In one embodiment, this application provides a computer storage medium, on which a computer program or instruction is stored. When the computer program or instruction is executed by a processor, the steps of the chip logic function verification method in the foregoing embodiment are implemented.

[0062] In one embodiment, the present application provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the steps of the chip logic function verification method in the foregoing embodiment.

[0063] It should be noted that the above embodiments can be freely combined as needed. The foregoing is only the preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for verifying the logic function of a chip, characterized in that Including the steps: Obtain the partitioning scheme of each sub-module of the chip to be verified by the backend design, and re-partition the chip to be verified into several modules to be verified; Perform logic function verification without timing information on the modules to be verified, and obtain the register transfer level design scheme corresponding to the modules to be verified; Keep the ports of the modules to be verified unchanged, and obtain the gate-level netlist corresponding to the register transfer level design scheme; Keep the ports of the modules to be verified unchanged, perform physical implementation of the modules to be verified through the gate-level netlist and EDA tools, and obtain the design netlist corresponding to the modules to be verified after physical implementation; Obtain the timing information of each of the modules to be verified after timing convergence according to the design netlist; Obtain the first delay from the port of each of the modules to be verified to its corresponding target register according to the timing information, and label the ports of each of the modules to be verified with the second delay obtained by subtracting the first delay from a preset delay, so as to perform logic function verification with timing information on the modules to be verified.

2. The chip logic function verification method according to claim 1, wherein When disassembling the first sub-module into several first modules to be verified through the partitioning scheme, perform logic function verification without timing information on the first modules to be verified, and obtain the register transfer level design schemes of two levels, namely, the first sub-module and the several first modules to be verified corresponding to the first sub-module; Keep the ports of the first sub-module unchanged, and obtain the gate-level netlist corresponding to the register transfer level design scheme; 3. The chip logic function verification method according to claim 1, characterized in that When merging several second sub-modules into a second module to be verified through the partitioning scheme, perform logic function verification without timing information on the second module to be verified, and obtain the register transfer level design schemes of two levels, namely, the second module to be verified and the several second sub-modules corresponding to the second module to be verified; Keep the ports of the several second sub-modules unchanged, and obtain the gate-level netlist corresponding to the register transfer level design scheme; 4. The chip logic function verification method according to claim 1, wherein The obtaining the timing information of each of the modules to be verified after timing convergence according to the design netlist includes: Keep the ports of the modules to be verified unchanged, perform timing repair of the modules to be verified according to the design netlist until timing convergence is achieved, and obtain the timing information of each of the modules to be verified after timing convergence.

5. The chip logic function verification method according to claim 1, wherein The preset delay is 60%-80% of the entire clock cycle from the port of the module to be verified to the target register.

6. The chip logic function verification method according to claim 1, wherein The partitioning scheme includes disassembling, merging or leaving unchanged each sub-module of the chip to be verified.

7. The chip logic function verification method according to claim 1, characterized in that The obtaining the first delay from the port of each of the modules to be verified to the target register according to the timing information includes: Grab the first delay from the port of each of the modules to be verified to its corresponding target register from the timing information through a script.

8. A computer device, comprising a memory, a processor, and a computer program stored on the memory, characterized in that, The processor executes the computer program to implement the steps of the chip logic function verification method according to any one of claims 1-7.

9. A computer storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instruction is executed by the processor, the steps of the chip logic function verification method according to any one of claims 1-7 are implemented.

10. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instruction is executed by a processor, it implements the steps of the chip logic function verification method described in any one of claims 1-7.

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