A method for automatic circuit generation based on AI

Abstract

The present invention discloses a method for automatically generating circuits based on AI, belonging to the field of circuit design. The method comprises obtaining design indicators; utilizing an attention mechanism to capture the dependencies between the design indicators, utilizing a multi-layer Transformer structure to extract features, obtaining the overall structure and high-level feature representation of the circuit, and matching the high-level feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain the current circuit structure; simulating the current circuit structure to obtain a simulation report, extracting error information from the simulation report; correcting the current circuit structure based on the error information, simulating the corrected circuit structure again, looping until no errors are present in the simulation report, and outputting a circuit schematic and simulation results. The present invention solves the problem that existing methods are generally limited and difficult to quickly and flexibly perform automatic design of complex circuits.

Description

Technical Field

[0001] The present invention belongs to the field of circuit design, and in particular relates to a method for automatically generating circuits based on AI. Background Art

[0002] The traditional circuit design process typically relies on engineers manually designing the circuit structure and then repeatedly adjusting, modifying, and verifying it using EDA tools (such as Cadence and Hspice). Because manual design requires years of experience, simulation errors must be manually troubleshooted, and circuit performance requires multiple iterations, modifications, and simulations, this process suffers from long design cycles, low debugging efficiency, and high resource consumption. This, in turn, leads to limitations in the integrated circuit field, including long development cycles, slow product upgrades, and high costs. While some EDA tools for automated design have emerged, they generally have limitations, hindering the rapid and flexible execution of complex designs, especially for analog circuits, and lack intelligent automated design capabilities. Summary of the Invention

[0003] In response to the above-mentioned deficiencies in the prior art, the present invention provides a method for automatically generating circuits based on AI, which solves the problem that the existing methods are generally limited and difficult to design complex circuits quickly, automatically and flexibly.

[0004] To achieve the above-mentioned purpose, the present invention adopts the following technical solution: a method for automatically generating circuits based on AI, obtaining design indicators, and storing the design indicators as structured data; the design indicators include circuit performance indicators, component indicators, circuit type indicators, and component connection methods;

[0005] The attention mechanism is used to capture the dependencies between various design indicators. The multi-layer Transformer structure is used for feature extraction to obtain the overall structure and high-level feature representation of the circuit. Based on the overall structure of the circuit, the high-level feature representation is matched with the standard circuit netlist template to obtain the current circuit structure.

[0006] Simulate the current circuit structure, obtain a simulation report, and extract error information from the simulation report;

[0007] Based on the error information, the current circuit structure is corrected, and the corrected circuit structure is simulated again. This cycle is repeated several times until there are no errors in the simulation report, and the circuit structure is output.

[0008] The present invention achieves the following beneficial effects: it automatically generates circuit netlists from functional requirements. By introducing a natural language parsing module and a circuit structure embedding encoding mechanism, it can automatically convert user-entered circuit design goals into structured representations and further generate candidate circuit structures, reducing manual modeling processes and improving design efficiency. A closed-loop simulation correction mechanism effectively improves the first-pass simulation pass rate. After the initial circuit generation, it automatically identifies syntax errors and performance deviations in the netlist based on simulation feedback, and invokes syntax repair, parameter optimization, or structural adjustment strategies based on the error type, effectively improving the usability of the netlist and the convergence speed of circuit performance. A multi-layer attention mechanism extracts deep design semantics. The multi-head self-attention module in the Transformer architecture captures structural correlations and cross-module information in the circuit, providing stronger design transferability and generalization capabilities, and increasing applicability in complex circuit scenarios. It also provides multi-platform compatible netlist output. According to user-specified EDA software standards, it automatically maps internally generated design data into netlist formats supported by the target platform (such as HSPICE and NGspice), ensuring compatibility with mainstream simulation platforms and improving deployment flexibility. Supporting expansion into multiple design tasks, including analog circuits and integrated circuits, this method utilizes multi-layer feature extraction and template migration mechanisms to handle complex circuit modules with continuous time-domain behavior and high-frequency signal characteristics, demonstrating broad adaptability. This effectively reduces simulation times and computational resource overhead. Through advanced feature compression and template screening strategies, the system rapidly locates potential feasible solutions within the design space, avoiding redundant simulations and exhaustive traversals, significantly shortening circuit development cycles and conserving computing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0010] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0011] like Figure 1 As shown, in one embodiment of the present invention, a method for automatically generating a circuit based on AI includes:

[0012] Obtaining design indicators and storing them as structured data; the design indicators include circuit performance indicators, component indicators, circuit type indicators, and component connection methods;

[0013] The attention mechanism is used to capture the dependencies between various design indicators. The multi-layer Transformer structure is used for feature extraction to obtain the overall structure and high-level feature representation of the circuit. Based on the overall structure of the circuit, the high-level feature representation is matched with the standard circuit netlist template to obtain the current circuit structure.

[0014] Simulate the current circuit structure, obtain a simulation report, and extract error information from the simulation report;

[0015] Based on the error information, the current circuit structure is corrected, and the corrected circuit structure is simulated again. This cycle is repeated several times until there are no errors in the simulation report, and the circuit structure is output.

[0016] In this embodiment, design indicators input by the user are received, such as circuit performance indicators (gain, noise, etc.), component indicators (capacitors, resistors, etc.), circuit type indicators (amplifiers, filters, etc.) and component connection methods (series, parallel, etc.). For example, a user may request the design of a low-noise amplifier operating in the 2GHz-6GHz frequency range, with the following requirements: 1. Operating frequency band: 2GHz-6GHz; 2. Gain: 10dB±1dB; 3. Noise figure: better than 5dB; 4. Linearity: Input 1dB compression point better than -10dBm; 5. Power consumption: 40mW; 6. Circuit stability: kf greater than 1; 7. Input and output impedance: 50 ohms (S11, S22 ≤ -10dB). The local circuit design model analyzes the user's requirements, breaking the input text into subwords using a tokenizer. Using natural language processing techniques, the tokenized results extract key design metrics, such as "amplifier," "low noise," "operating frequency band: 2GHz-6GHz," "noise figure: 5dB," and "gain: 10dB±1dB." The system then parses these design metrics and converts them into structured data, typically represented as key-value pairs, with each metric corresponding to a specific value, to facilitate further processing. These structured data include specific values of each design requirement and its corresponding type, such as circuit type, performance requirements and parameter range.

[0017] Get the current circuit structure, specifically:

[0018] Based on the structured data, the normalization operation is used to calculate the relevant weights of each design indicator:

[0019]

[0020] in, For the The relevant weights of the design indicators; For the Initial weight scores of design indicators; is the temperature coefficient; For the Initial weight scores of design indicators;

[0021] The self-attention mechanism is used to calculate the dependencies between various design indicators:

[0022]

[0023] in, is the dependency relationship between the current design indicator and all design indicators; is the activation function; is the query matrix, which represents the current design index; is the key matrix, which is composed of various design indicators; is the dimension of the key; is the bias term; is a value matrix representing the weight vector associated with the design indicator; is transposed;

[0024] Based on the dependencies between various design indicators, a multi-layer Transformer structure is used to extract features and obtain the overall structure and high-level feature representation of the circuit;

[0025] Calculate the matching score between each feature in the advanced feature representation and the embedded representation in the standard circuit netlist template, extract the embedded representation with a matching score greater than a threshold, and obtain a set of matching templates;

[0026] Based on the overall structure of the circuit, any one embedding representation is selected from the matching templates of each feature of the high-level feature representation, and the current circuit structure is obtained based on the embedding representation selected corresponding to each feature.

[0027] In this embodiment, the converted structured data is used to dynamically calculate the relevant weights of each design indicator based on the attention mechanism to measure the importance and mutual correlation of each parameter. The temperature coefficient is used to control the smoothness of the distribution. This weight is used to guide the model to focus on high-priority design requirements while ensuring that secondary parameters are not ignored. In terms of dependency capture, the self-attention mechanism is mainly used to calculate the dependencies between parameters. Through this mechanism, it is possible to automatically learn which design indicators have strong correlations, such as gain, noise figure and linearity, which often affect each other in amplifiers, thereby optimizing the design scheme. The captured dependencies will be used to guide the feature extraction process of the Transformer layer to ensure that the network pays attention to the core constraints of the circuit design.

[0028] Based on the dependencies between various design indicators, a multi-layer Transformer structure is used for feature extraction to obtain the overall structure and high-level feature representation of the circuit, including:

[0029] The first layer of Transformer structure is used to extract local parameter relationships based on the dependencies between various design indicators;

[0030] The second layer Transformer structure is used to extract global features based on local parameter relationships;

[0031] The third-layer Transformer structure is used to extract the overall structure and high-level feature representation of the circuit based on global features, combined with circuit templates and historical circuit design cases.

[0032] According to the dependency relationship between the design indicators, the local parameter relationship is extracted, specifically:

[0033] The structured data is linearly transformed and positionally encoded to obtain the circuit extraction input data:

[0034]

[0035] in, extracting a query vector of input data for the circuit; For structured data; 、 and Both are trainable weight matrices; Extract the key vector of input data for the circuit; Extracting a value vector of input data for the circuit;

[0036] The input data extracted by the circuit is input into the multi-head self-attention mechanism to obtain the local parameter relationship; the bias term of the multi-head self-attention mechanism of the first layer Transformer structure is the dependency relationship between the various design indicators.

[0037] The expression of the global feature is:

[0038]

[0039] in, is a global feature; is the layer normalization operation; is the intermediate representation; It is a feedforward neural network; is the local parameter relationship; 、 and Both are trainable weight matrices that map data into vectors.

[0040] The overall structure and high-level features of the circuit are expressed as:

[0041]

[0042] in, is the overall structure of the circuit; Generate functions for structures; is the hidden state of the final fusion; is the activation function; is the structural mapping matrix used to project the high-dimensional feature space into the structural label space; A circuit feature representation that integrates the structural semantics of the current circuit state and historical circuit templates; is the bias vector; For connection operation; is a global feature; Encoding historical circuits; is the fusion weight matrix; For high-level feature representation; is the hidden state used to obtain the final fusion Extract key design features from high-dimensional feature mapping functions; It is a high-dimensional mapping layer; is global average pooling; is the weight of the high-dimensional mapping layer; is the number of structural units in the circuit; is the final feature sequence after fusion; is the bias of the high-dimensional mapping layer.

[0043] In this embodiment, in the Transformer structure, the input data is the processed circuit design parameter matrix, which is composed of the structured design indicators extracted in the early stage, including circuit performance indicators, component indicators, circuit type indicators, and component connection methods, etc. After encoding and normalization, it forms a numerical input format acceptable to the model. Each layer of Transformer block consists of a multi-head self-attention mechanism and a feedforward neural network. The output of the previous layer serves as the input of the next layer, enabling the model to learn the feature relationships of different levels in depth. The first layer mainly learns local parameter relationships, such as the matching between frequency range and gain.

[0044] The first-layer attention mechanism incorporates dependencies between design metrics (such as voltage-current relationships and gain-frequency coupling) as explicit bias information into the attention score calculation. Specifically, when calculating the attention score, the bias term is composed of the extracted design dependency matrix, which strengthens the focus on the intrinsic coupling between key design metrics. This mechanism guides attention distribution during feature aggregation to more closely align with circuit design logic, thereby improving the ability to model circuit behavioral characteristics.

[0045] The middle layer focuses on global features, including circuit stability and power optimization; after receiving the output of the previous layer After that, the layer processes its input again through the multi-head attention mechanism, and combines residual connection with layer normalization. The data processing flow formula is as follows:

[0046]

[0047] in, Represents the intermediate feature representation from the previous layer, which encodes the parameter information of the preliminary representation of each circuit component (such as resistors, capacitors, transistors, etc.) and their topological connection structure. 、 and is the trainable weight matrix in the first layer of attention mechanism, which is used to transform the input features Mapped into query, key, and value vectors. In this task, the query represents the structural requirements or target characteristics of the current circuit component, the key represents the response characteristics of other components, and the value is the actual feature vector used for information aggregation. The attention module calculates the similarity between the query and the key (i.e., the coupling degree between components, such as signal path correlation and electrical parameter influence) to obtain attention weights, which are then weighted and aggregated on the value vector to model the global circuit dependency structure.

[0048] The obtained Attention output and the original input Add (residual connection), and then normalize through LayerNorm to obtain the intermediate representation , effectively alleviating the problem of gradient vanishing and feature drift. Subsequently, the feedforward neural network FFN (generally two linear layers + ReLU activation function) is used to further Perform nonlinear transformation to improve the ability to express complex circuit modes (such as feedback structures, coupling paths, etc.), and finally perform LayerNorm again to obtain As the output of the current layer.

[0049] During this process, the Attention layer explicitly models the physical and structural relationships between components, while the FFN enhances the nonlinear combination of local features. The combination of the two facilitates unified representation of circuit structure and behavior modeling. This layer preserves the original features while enhancing global semantic understanding, such as overall circuit stability, noise sensitivity, and power consumption paths.

[0050] The subsequent layers further combine circuit templates and historical circuit design cases to extract the overall structure and high-level feature representation of the circuit. In the initialization stage, the initial feature vector of the task will be extracted based on the user's circuit requirements, including structural dimensions (such as the number of components, coupling relationships), parameter distribution (such as statistical characteristics of voltage, resistance, and capacitance), and performance index requirements (such as frequency response, gain range, etc.). These feature vectors are mapped through a lightweight encoding network and input into a pre-trained circuit family classifier to determine the most likely matching circuit type for the task (such as amplifiers, filters, regulators, etc.), and dynamically set the number of layers of the Transformer network based on the task complexity score (such as the degree of nonlinearity, parameter span). In scenarios with complex structures or higher design goals, the number of layers of the Transformer network can be expanded, and the effective modeling of multi-level structures, complex topologies, and long-range dependencies of circuits can be achieved through automatic adjustment of the number of layers. This process uses a multi-layer Transformer network to classify the output features of the previous layer. and historical circuit coding Fusion is performed to enhance the ability to recognize different design styles and typical modules.

[0051] In this embodiment, structure migration and high-level representation generation are achieved by matching the structural encodings (e.g., topological features and component layouts) in the template library with the feature representation of the current circuit design. The structure generation function is used to extract visual structural information, such as topological connectivity matrices and module boundaries, from the high-dimensional representation.

[0052] In this embodiment, the fused circuit feature representation integrates the structural semantics of the current circuit state and the historical circuit template; It is a structural mapping matrix used to project the high-dimensional feature space into the structural label space; is the bias vector; is an optional activation function (such as softmax or sigmoid) used to generate module belonging probability or edge connection strength; output S Represents a set of structural matrices, including intermediate visual structural information such as topological connection matrix A and module boundary vector M.

[0053] In this embodiment, The key design features are extracted from the function, which is a specific mapping function designed by combining Transformer output, structural encoding, and historical case representation. Represents the final feature sequence after fusion; GlobalAvgPool averages the feature vectors at all positions to extract the global circuit behavior representation; 、 is the weight and bias of the high-dimensional mapping layer (MLP); output FRepresents the extracted key design feature vector.

[0054] In this embodiment, Represents the high-level circuit feature vector extracted from the fusion module, covering key design indicators such as noise margin, power stability coefficient, reliability score, etc.

[0055] The expression for the matching score is:

[0056]

[0057] in, for and Matching score; Calculate the cosine similarity function; The first high-level feature representation Features For the Embedding representation; is the norm of the vector.

[0058] In this embodiment, a matching scoring mechanism based on cosine similarity is introduced to further determine the degree of match between the current design and each template in the template library. Based on the matching results, a set of template structures highly relevant to the current design is selected to form a matching template set. This set not only provides a reference framework for structure generation but also offers candidate solutions for subsequent circuit topology fine-tuning. Firstly, a preliminary circuit structure can be quickly generated based on typical connection methods and component configurations in the matching templates. Secondly, by comparing the structural differences between the matching templates and the current design, fine-tuning can be guided at key nodes (such as adjusting module boundaries, inserting or replacing components, optimizing connection paths, etc.), thereby improving circuit performance and feasibility while reducing design risks.

[0059] When mapping the EDA software specified in the user input to the standard netlist format stored in the knowledge base, the generated circuit design data (including component types, connectivity relationships, parameter values, etc.) is structured and mapped into a standard netlist representation format that meets the parsing requirements of the target EDA tool, preferentially based on the circuit template associated with the previously successfully matched high-level features. These successfully matched features have clear structural guidance and parameter settings, making them directly usable in the netlist generation process. For high-level features that fail to match the template, a backtracking mechanism is activated, using historical experience with similar circuit designs to attempt to infer the most likely circuit structure or parameter configuration for completion, ensuring the correctness and compatibility of subsequent simulation and verification processes. The corresponding symbols for each key entity are extracted from the component symbol library for a one-to-one mapping. Key entities are automatically identified from the circuit template based on the user's circuit design requirements and the inference model. For example, based on the design's functional requirements (e.g., low-noise amplifier, filter), the relevant circuit modules (e.g., transistor, operational amplifier, etc.) are identified. Match the component models required for the design with the process library (PDK) provided by the process manufacturer. The component models required for the design refer to the specific models of each component in the standard component library that meet the circuit design requirements (such as capacitor, resistor, and transistor models). These models include the component's electrical characteristics, behavioral model, and corresponding physical structure. By matching the component information with the process library, the specific process required is determined.

[0060] By combining circuit templates, component libraries, standard circuit design rules, and historical circuit design examples in the knowledge base, the system automatically selects appropriate circuit templates (such as common amplifier and filter module structures) based on the user's circuit design requirements, providing a basic framework for the design. Circuit templates include not only the functional implementation structure but also common module connections and layouts. The component library provides specific component models, parameters, and symbols for each circuit module. Based on the module defined in the template, the system automatically selects appropriate components from the component library and assigns them appropriate electrical characteristics and symbols, ensuring design accuracy and feasibility. Standard circuit design rules ensure that the design complies with various constraints (such as netlist format and component parameters). Automated checks ensure design validity, preventing errors and non-compliance during the design process. Furthermore, historical circuit design examples provide successful and failed examples from similar designs. By comparing the characteristics of the current design with those in the historical examples, potential design issues can be identified, and the current design can be optimized by learning from successful experiences or avoiding past mistakes.

[0061] On this basis, the model first preprocesses the user's required circuit parameters (such as resistance, voltage, and frequency) using methods such as normalization and discretization to convert physical quantities into computable numerical representations, enhancing the method's parsability and generalization capabilities. These circuit parameters specifically refer to the technical specifications of each component in the circuit, such as resistance, capacitance, voltage, current, and frequency. After preprocessing, the data is scaled to facilitate subsequent inference and calculation. The model then extracts a high-dimensional feature vector for the circuit by calculating key circuit features such as resonant frequency, gain characteristics, and impedance matching parameters. The resonant frequency is calculated based on the formula for LC or RC circuits, the gain characteristic is derived using the gain calculation formula, and the impedance matching parameters are calculated by calculating the matching degree between the input and output impedances and the load impedance. These key features are used to construct a high-dimensional feature vector for the circuit, representing its electrical performance and behavioral characteristics. A dimensionality reduction method (such as PCA or autoencoders) is then used to convert the high-dimensional feature vector into a compact, low-dimensional feature representation, reducing computational complexity and improving matching efficiency. Finally, these compact feature representations serve as query vectors, not only matching them with the netlist encodings in the structural template library but also assisting in querying historical circuit designs stored in the cache to introduce empirical structures or parameter settings, improving design rationality and convergence speed. Historical circuit design data is typically stored in vector form, containing component parameters, circuit characteristics, and performance metrics (such as gain, frequency response, and stability). These historical design vectors are matched with the query vector of the current design by calculating similarity (such as cosine similarity or Euclidean distance), thereby identifying the historical design most similar to the current design, and performing recursive reasoning and optimization based on this design.

[0062] When the calculated similarity between the input features and the key-value pairs in the cache exceeds the set threshold, the most relevant circuit pattern (i.e., the circuit structure similar to the current design requirements) is dynamically retrieved, and the neural units related to "symbol recognition, formula matching, and netlist generation" are gradually triggered.

[0063] Symbol recognition neurons extract component symbol features through self-supervised learning and combine them with graph neural networks for pattern matching and connection rule analysis to identify circuit topology and construct a preliminary circuit diagram representation. This process uses calculated circuit parameters (such as resistance, voltage, and frequency) and circuit characteristics (such as resonant frequency, gain characteristics, and impedance matching parameters) as input data to help understand the electrical behavior and performance metrics of each component. Symbol recognition neurons use self-supervised learning to extract the symbolic features of each component from the circuit template, such as the graphical symbols of components like resistors, capacitors, and transistors. By learning the relationship between each symbol's geometry, dimensions, and electrical parameters, they construct a high-dimensional feature representation of the symbol. Graph neural networks capture the graph structure of the circuit, with components as nodes and the electrical connections between components as edges. By analyzing the characteristics of the nodes and edges, they identify the relationships between different circuit modules (for example, the connection between a gain amplifier and a filter). The pattern matching process not only analyzes the electrical connection relationships but also incorporates symbolic features for matching, ensuring accurate identification of the circuit module layout and electrical connections. Based on graph neural network analysis, symbol recognition neurons can infer the circuit topology and establish a preliminary circuit diagram representation, which in turn provides the basis for subsequent netlist generation and circuit simulation. This circuit diagram representation includes the specific location of components, their connections, and the electrical relationships between them. It is not just a component arrangement, but a structured representation that includes electrical characteristics, providing an accurate preliminary design framework for circuit optimization and verification.

[0064] Formula matching neurons use an attention mechanism to search for optimal circuit equations and computationally match extracted characteristic parameters to these equations to derive key circuit metrics such as resonant frequency, gain, and impedance. Calculated circuit parameters (such as resistance, capacitance, voltage, and frequency) and circuit characteristics (such as gain and frequency response) serve as input, helping the formula matching neurons accurately find equations that are appropriate for the current circuit design. Specifically, the attention mechanism enables the neurons to prioritize the most relevant equations for matching among a large number of possible circuit equations. After matching, the neurons further derive circuit performance metrics such as resonant frequency (based on LC or RC circuit equations), gain (using gain calculation formulas), and impedance (by analyzing the matching of input and output impedances and load impedance). Using these calculations, the neurons optimize key circuit parameters to ensure that circuit performance meets design requirements and standards.

[0065] Building on the previous two approaches, netlist generation neurons utilize multi-layer perceptrons to perform nonlinear transformations, converting the symbolic circuit topology (circuit structure derived through symbol recognition and graph neural networks) into a standardized circuit description language. Specifically, the symbolized circuit topology information includes component types, connection relationships, parameters, and more. The netlist generation neurons process this information through multi-layer perceptrons, extracting the circuit's structural and behavioral characteristics and converting them into a netlist format that meets the requirements of EDA software. This process not only standardizes circuit components and their parameters but also ensures that every connection in the circuit complies with netlist compilation specifications. Ultimately, the neurons use these transformed representations to generate a netlist that meets the parsing requirements of simulation tools and EDA software, providing the foundation for subsequent simulation and verification.

[0066] Throughout the reasoning process, a chain-like thinking prompt is used to guide the system through the gradual breakdown of the problem, generating step-by-step results in a logical sequence of symbol recognition, circuit parameter calculation, and netlist conversion. When calculating weight distribution, parameter matching results, or connection relationships, ambiguity is determined by analyzing the inherent structure and interrelationships of the input data. Specifically, based on the calculated circuit characteristics, component parameters, and circuit topology, a rule engine and deep learning model are used to identify potential conflicts or inconsistencies. For example, during parameter matching, if the parameters of multiple components in the circuit are inconsistent or fail to meet the predetermined design requirements, this anomaly is detected and a backtracking mechanism is determined based on a preset tolerance threshold. Similarly, if there is ambiguity in the connection relationship, such as if the connection relationship between certain nodes (components) in the circuit diagram is unclear or does not match the circuit's functional requirements, this will be identified and the backtracking mechanism will be triggered.

[0067] The core of the backtracking mechanism is to make corrections based on the error type, the current netlist, and correction suggestions. First, the ambiguous parts are classified and the error type is identified. Common error types include parameter mismatches (such as inconsistent resistance and capacitance values), connection relationship errors (such as disconnected signal paths, or inappropriate input and output connections of circuit modules), and circuit function mismatches (such as insufficient gain, frequency response that does not meet requirements, etc.). For each error type, correction suggestions are generated based on historical cases, design specifications, and previous calculation results. For example, when it is found that the resistance value is inconsistent with expectations, it may be recommended to change the resistance value or select a resistor of different specifications; when a connection relationship error is identified, the connection method will be automatically adjusted according to the circuit topology and functional requirements to ensure the correct signal path.

[0068] Once the error type is identified and classified, recursive reasoning is used to correct the error based on historical design experience and optimization strategies. Specifically, a portion of the netlist is regenerated based on the correction suggestions, and the corrected circuit parameters and connections are verified to meet the design requirements. If the corrected netlist still contains issues, backtracking is continued, iterating through different correction solutions until the circuit design meets all design specifications and functional requirements.

[0069] In this way, the backtracking mechanism can not only automatically identify potential problems in circuit design, but also perform precise repairs based on the error type and correction suggestions, thereby ensuring the accuracy and feasibility of the circuit design.

[0070] After all key steps are completed, the complete netlist file is finally output and integrated to meet the standard syntax format requirements of the simulation software.

[0071] The error information includes the error type and error location.

[0072] Correct the current circuit structure based on the error information, specifically:

[0073] Based on the error location, find the corresponding node and take the preset corrective action based on the error type.

[0074] In this embodiment, the local computer automatically establishes protocol communication with the server, calls the EDA tool installed in the server, and the EDA software in the server simulates and tests the netlist, returns the generated simulation results to the local computer, and automatically creates a log file and saves the simulation results;

[0075] Error diagnosis and correction module: First, the simulation log is parsed to identify the types of errors in the netlist, including syntax errors (such as missing component parameters and incorrect connection formats), physical constraint violations (such as impedance mismatch and abnormal bias points), and circuit performance deviations (such as gain and noise figure exceeding the design range).

[0076] Then, error information is extracted based on regular expressions and AST parsing. Error information usually includes the following categories:

[0077] The first is the error type, which is the specific type of problem detected in the circuit design, such as parameter mismatch, connection error, circuit function mismatch, etc.; the second is the error location, which indicates the specific location where the error occurred, such as the pin connection error of a specific component, or a signal path that is not connected correctly. The error description is a specific description of the problem, such as "the resistance value is outside the allowable range" or "the input port is not connected to the appropriate voltage source." In addition, the error context information is also included, such as the relevant circuit parameters (such as the specific values of resistors and capacitors) and connection status (such as the path of the connection line and the location of the component) when the error occurred.

[0078] The data representation of these error messages is in structured text or digital format. For example, error messages can be converted to JSON format, which contains the following fields: error type, error location, error description, context parameters, etc. Specifically, by parsing the netlist and graphic information of the circuit design, each component and its connection relationship will be identified. Then, regular expressions will be used to perform pattern matching on the formulas or connection expressions in the circuit design to extract potential errors. For example, when analyzing resistors, it may be detected that the value of a resistor does not meet the design specifications, or when connecting two components, the signal line is not correctly connected to the circuit.

[0079] These error messages are extracted and used as input data for further analysis. Once this input data is received, correction suggestions are generated using historical design experience and optimization strategies. These suggestions include, but are not limited to, adjusting parameters, rearranging circuit connections, and replacing components. This approach automatically identifies and corrects errors in circuit design, improving design accuracy and efficiency.

[0080] During the iterative correction process, the netlist is dynamically adjusted based on the error category. For syntax errors, the first step is to identify grammatical issues in the circuit description, such as incorrect component connections, incorrect component symbols, or expressions that do not conform to the netlist writing specifications. Syntax errors typically occur when the netlist format is incorrect. For example, the connection expression between components is illegal, or the description of electrical parameters does not conform to the prescribed format (such as incorrect parameter units). When correcting these errors, based on the rules of regular expressions and standard netlist formats, the non-compliant parts are automatically modified and converted into a correct structure that meets the grammatical requirements. The modified netlist will be restored to a valid representation that conforms to the standard netlist format and can continue to be input into the simulation software for subsequent processing.

[0081] Parameter anomalies typically refer to physical constraint violations in the circuit design, such as component values exceeding the specified tolerance range (e.g., resistor values too small or capacitor values too large), or electrical characteristics in the circuit design (such as current and voltage) exceeding the maximum tolerance of the component. By comparing with historical circuit design cases, common parameter settings in similar designs are analyzed, and parameters in the current design are adjusted based on this historical data. For example, if a resistor value is found to be outside the preset range, a successful design in a historical case study may be referenced to select an appropriate resistor value that meets the circuit performance requirements and automatically adjust the parameters. The adjusted parameters are reflected in the new netlist, ensuring that the circuit design is within the physical constraints.

[0082] Circuit performance deviation typically refers to a discrepancy between simulation results and design targets. For example, parameters such as gain, frequency response, and power consumption fail to meet predetermined targets. The deviation between the design target and simulation results is first calculated to identify the source and key factors of the deviation. Based on these deviations, the circuit topology and key parameters (such as component values and bias point settings) are analyzed and corrected. Specifically, if simulation results indicate insufficient gain, the bias point of the gain amplifier may be adjusted or more appropriate components selected. Alternatively, if the frequency response does not meet requirements, the filter parameters may be re-optimized or the component connections adjusted. This correction process targets key circuit components, such as optimizing the input and output impedances and adjusting the frequency response curve, to ensure the design meets target requirements. Each revised netlist is re-entered into the simulation software for verification until the simulation results meet the design requirements.

Claims

1. A method for automatically generating circuits based on AI, characterized in that: include: Obtaining design indicators and storing the design indicators as structured data; The design indicators include circuit performance indicators, component indicators, circuit type indicators and component connection methods; The attention mechanism is used to capture the dependencies between various design indicators, and a multi-layer Transformer structure is used for feature extraction to obtain the overall structure and high-level feature representation of the circuit. Based on the overall structure of the circuit, the high-level feature representation is matched with the standard circuit netlist template to obtain the current circuit structure. The use of a multi-layer Transformer structure for feature extraction to obtain the overall structure and high-level feature representation of the circuit specifically includes: The first layer of Transformer structure is used to extract local parameter relationships based on the dependencies between various design indicators; The second layer Transformer structure is used to extract global features based on local parameter relationships; The third-layer Transformer structure is used to extract the overall structure and high-level feature representation of the circuit based on global features, combined with circuit templates and historical circuit design cases. The expressions for the overall structure and high-level feature representation of the circuit are: in, is the overall structure of the circuit; Generate functions for structures; is the hidden state of the final fusion; is the activation function; is the structural mapping matrix used to project the high-dimensional feature space into the structural label space; A circuit feature representation that integrates the structural semantics of the current circuit state and historical circuit templates; is the bias vector; For connection operation; is a global feature; Encoding historical circuits; is the fusion weight matrix; For high-level feature representation; is the hidden state used to obtain the final fusion Extract key design features from high-dimensional feature mapping functions; It is a high-dimensional mapping layer; is global average pooling; is the weight of the high-dimensional mapping layer; is the number of structural units in the circuit; is the final feature sequence after fusion; is the bias of the high-dimensional mapping layer; Simulate the current circuit structure, obtain a simulation report, and extract error information from the simulation report; Based on the error information, the current circuit structure is corrected, and the corrected circuit structure is simulated again. This cycle is repeated several times until there are no errors in the simulation report, and the circuit structure is output.

2. The method for automatically generating circuits based on AI according to claim 1, characterized in that: The current circuit structure is obtained as follows: Based on the structured data, the normalization operation is used to calculate the relevant weights of each design indicator: in, For the The relevant weights of the design indicators; For the Initial weight scores of design indicators; is the temperature coefficient; For the Initial weight scores of design indicators; The self-attention mechanism is used to calculate the dependencies between various design indicators: in, is the dependency relationship between the current design indicator and all design indicators; is the activation function; is the query matrix, which represents the current design index; is the key matrix, which is composed of various design indicators; is the dimension of the key; is the bias term; is a value matrix representing the weight vector associated with the design indicator; is transposed; Based on the dependencies between various design indicators, a multi-layer Transformer structure is used to extract features and obtain the overall structure and high-level feature representation of the circuit; Calculate the matching score between each feature in the advanced feature representation and the embedded representation in the standard circuit netlist template, extract the embedded representation with a matching score greater than a threshold, and obtain a set of matching templates; Based on the overall structure of the circuit, any one embedding representation is selected from the matching templates of each feature of the high-level feature representation, and the current circuit structure is obtained based on the embedding representation selected corresponding to each feature.

3. The method for automatically generating circuits based on AI according to claim 1, characterized in that: The local parameter relationship is extracted based on the dependency relationship between the design indicators, specifically: The structured data is linearly transformed and positionally encoded to obtain the circuit extraction input data: in, extracting a query vector of input data for the circuit; For structured data; 、 and Both are trainable weight matrices; Extract the key vector of input data for the circuit; Extracting a value vector of input data for the circuit; The input data extracted by the circuit is input into the multi-head self-attention mechanism to obtain the local parameter relationship; the bias term of the multi-head self-attention mechanism of the first layer Transformer structure is the dependency relationship between the various design indicators.

4. The method for automatically generating circuits based on AI according to claim 1, characterized in that: The expression of the global feature is: in, is a global feature; is the layer normalization operation; is the intermediate representation; It is a feedforward neural network; is the local parameter relationship; 、 and Both are trainable weight matrices that map data into vectors.

5. The method for automatically generating circuits based on AI according to claim 2, characterized in that: The expression of the matching score is: in, for and Matching score; Calculate the cosine similarity function; The first high-level feature representation Features For the Embedding representation; is the norm of the vector.

6. The method for automatically generating circuits based on AI according to claim 1, characterized in that: The error information includes the error type and the error location.

7. The method for automatically generating circuits based on AI according to claim 1, characterized in that: Correct the current circuit structure based on the error information, specifically: Based on the error location, find the corresponding node and take the preset corrective action based on the error type.

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