Method for rapidly extracting large-scale mesh resistance of basic array layout and electronic equipment

Abstract

The invention discloses a method for rapidly extracting large-scale mesh resistance of a basic array layout and electronic equipment. The method comprises the following steps: determining a reusable graphic unit on the array layout; cutting the reusable graph unit to generate a plurality of sub-graphs; based on the multiple sub-graphs, 3 * 3 expansion is carried out on the reusable graph unit, and overlapped sub-graphs in the reusable graph unit are combined to generate template sub-graphs; image matching is carried out on the template subgraph, an array expansion type is determined, and the array expansion type comprises at least one of a global array expansion type, a boundary array expansion type and a four-corner array expansion type; and performing finite element subdivision on the template sub-graph, performing reduction to obtain a port-based resistance network, and performing array expansion on the template sub-graph based on the port-based resistance network to generate the whole resistance network. According to the method, the problems existing in large-scale and complex array layout resistance extraction of a traditional method are effectively solved, and an efficient and feasible solution is provided for resistance extraction.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design and manufacturing technologies, and particularly to a method for quickly extracting large-scale mesh resistors in a basic array layout and an electronic device. Background Art

[0002] With the continuous growth of consumers' demand for electronic products, the requirements for performance indicators such as the image quality, size, and power consumption of display screens have become increasingly stringent, which has promoted the rapid development of flat panel display (FPD) process technologies. When faced with the increasing screen design size and resolution, how to efficiently and accurately extract resistor values from large-scale integrated circuit layouts has become a challenge. At the same time, the complexity and diversity of large-scale integrated circuit layout design have increased day by day. Using traditional methods to directly extract resistors from large-scale layouts, the speed often cannot meet the actual needs, and even in some cases, the extraction task cannot be completed. Therefore, how to quickly and accurately extract resistor values from large-scale layouts has become one of the key technologies in FPD design tools.

[0003] In comprehensive layout design, a hierarchical design mode is usually adopted to organize pixel units into an array form, and each pixel unit can be regarded as a reusable graphic unit. When the structure of the reusable graphic unit is simple and the layout scale is small, through graphic geometric operations and finite element methods, etc., the rapid and accurate extraction of resistor values can be achieved. However, when the structure of the reusable graphic unit is complex and the layout scale is large, the time consumption of this process increases significantly, and even becomes infeasible in some cases. Summary of the Invention

[0004] Embodiments of this application provide a method for quickly extracting large-scale mesh resistors in a basic array layout and an electronic device to solve or alleviate the above technical problems in the prior art.

[0005] A method for quickly extracting large-scale mesh resistors in a basic array layout includes:

[0006] Determine the reusable graphic units on the array layout;

[0007] Cut the reusable graphic units to generate multiple sub-graphics;

[0008] Based on the multiple sub-graphics, expand the reusable graphic units in a 3*3 manner and merge the overlapping sub-graphics therein to generate a template sub-graph;

[0009] Perform image matching on the template sub-graph to determine the type of array expansion, and the type of array expansion includes at least one of a global array expansion type, a boundary array expansion type, and a four-corner array expansion type;

[0010] Perform finite element meshing on the template sub - graph, and reduce it to obtain a port - based resistance network, and perform array expansion on the template sub - graph based on the port - based resistance network to generate the entire resistance network.

[0011] Optionally, the determining the reusable graphic units on the array layout includes:

[0012] Divide the functional areas of the array layout to determine the area where the reusable graphic units are located;

[0013] Extract the features of the area where the reusable graphic units are located to obtain the features of the reusable graphic units;

[0014] Calculate the similarity and repeatability of the reusable graphic units based on the features of the reusable graphic units to determine the reusable graphic units on the array layout.

[0015] Optionally, the cutting the reusable graphic units to generate multiple sub - graphics includes:

[0016] Cut the reusable graphic units based on the functional features and electrical features of the reusable graphic units to generate multiple preliminary cut sub - graphics;

[0017] Judge whether the multiple preliminary cut sub - graphics meet the set cutting valid verification constraints. If they meet, stop the segmentation, and use the preliminary cut sub - graphics when the cutting valid verification constraints are met as the sub - graphics. Otherwise, re - cut the reusable graphic units until the preliminary cut sub - graphics that meet the cutting valid verification constraints are obtained.

[0018] Optionally, the cutting valid verification constraint is that the maximum size of a single preliminary cut sub - graphic is less than the layout cells of 3 rows or 3 columns.

[0019] Optionally, the 3×3 expansion of the reusable graphic units based on the multiple sub - graphics and the merging of the overlapping sub - graphics to generate a template sub - graph includes:

[0020] Based on the multiple sub - graphics, expand the reusable graphic units in the row and column directions by 3×3, and mark the positions of each expanded reusable graphic unit;

[0021] Based on the position marks, determine the overlapping sub - graphics in the expanded reusable graphic units to merge the overlapping sub - graphics and generate a template sub - graph accordingly.

[0022] Optionally, the determining the overlapping sub - graphics in the expanded reusable graphic units based on the position marks to merge the overlapping sub - graphics and generate a template sub - graph accordingly includes:

[0023] Based on the position markers of all reusable graphic units, assign a square rectangular area annotation to each reusable graphic unit and record the sub-graphics within the square rectangular area to generate a position index sequence;

[0024] Based on the position index sequence, determine the overlapping sub-graphics in the expanded reusable graphic units to merge the overlapping sub-graphics and generate a template sub-graph accordingly.

[0025] Optionally, perform image matching on the template sub-graph to determine the type of array expansion. The types of array expansion include global array expansion type, boundary array expansion type, and four-corner array expansion type, including:

[0026] Traverse the graphics of each template sub-graph to match the positions of the 3x3 grid;

[0027] If the graphics of a template sub-graph intersect with the 9 position coordinates of the 3x3 grid, mark it as the global array expansion type;

[0028] If a template sub-graph only intersects with the four-side positions, mark it as the boundary array expansion type;

[0029] If a template sub-graph only appears at the four-corner positions, mark it as the four-corner array expansion type.

[0030] Optionally, perform finite element meshing on the template sub-graph, and reduce it to obtain a port-based resistance network and expand the template sub-graph based on the port-based resistance network to generate the entire resistance network, including:

[0031] Obtain the port information annotated for each template sub-graph;

[0032] Based on the port information, perform finite element meshing on the corresponding template sub-graph to generate a resistance network;

[0033] Perform equivalent reduction on the resistance network to generate an equivalent resistance network based on ports.

[0034] Expand the template sub-graph based on the equivalent resistance network based on ports to generate the entire resistance network.

[0035] Optionally, the method further includes:

[0036] Obtain the cutting ports when cutting the reusable graphic units;

[0037] Assign split markers to each cutting port to generate the port information annotated for each template sub-graph based on the split markers obtained for each sub-graphic.

[0038] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of a method for quickly extracting large-scale mesh resistors of a basic array layout as described in the embodiments of the present application.

[0039] The present application has the following advantages:

[0040] (1) The present invention first determines reusable graphic units on the array layout and then cuts them to generate multiple sub-graphics. This cutting operation decomposes a large-scale and complex mesh array area into a small-scale and simpler graphic combination. For example, for a reusable graphic unit containing a multi-layer complex circuit structure, after cutting, parts with different functions or structures can be separated, making the structure of each sub-graphic easier to understand and process. In the subsequent process of expanding 3*3 based on multiple sub-graphics and merging overlapping sub-graphics to generate a template sub-graph, since the sub-graphics are relatively simple, it is more convenient to perform layout, merging, and analysis, greatly reducing the graphic processing difficulty of the array area and being more efficient than traditional methods when dealing with complex graphics.

[0041] (2) By performing image matching on the template sub-graph to determine the type of array expansion (including global array expansion type, boundary array expansion type, and corner array expansion type, etc.) and generating an array expansion template sub-graph accordingly, this strategy has significant advantages. Specific expansions for different types of template sub-graphs can more accurately construct the resistor network. For example, the template sub-graph of the global array expansion type can be uniformly expanded and processed throughout the array area, making full use of its global characteristics; the template sub-graphs of the boundary array expansion type and the corner array expansion type can be processed specifically according to their position characteristics at the edge or corner of the array, avoiding unnecessary calculations and complex processing processes. Compared with traditional methods, the present invention can more effectively organize and calculate the resistor network, greatly improving the resistor extraction speed. In the extraction of small-scale mesh resistors based on the array layout, the extraction speed of the present invention is one order of magnitude faster than the simple finite element extraction method, which can significantly improve work efficiency in practical applications and meet the requirements for rapid extraction of large-scale layout resistors.

[0042] (3) Perform finite element meshing on the template sub-graph to generate a port-based resistance network. Based on the previous operations such as cutting, unfolding, and matching in the present invention, the finite element meshing can be carried out more effectively. Since the template sub-graph has been optimized, parameters such as the element shape and material properties can be determined more accurately during the finite element meshing process, reducing the calculation error and the amount of calculation. Moreover, by templatizing the processing process, the entire process from determining the reusable graphic unit to generating the resistance network becomes more standardized and efficient, further improving the calculation processing speed and making the large-scale mesh resistance extraction based on the array layout feasible in actual operation, overcoming the difficulties faced by traditional methods in processing large-scale layouts. Description of the Drawings

[0043] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0044] Figure 1 Schematic diagram of the steps of a method for rapid extraction of large-scale mesh resistors of a basic array layout in an embodiment of the present application.

[0045] Figure 2 Schematic diagram of the cutting of reusable graphic units according to the present invention.

[0046] Figure 3 Schematic diagram of the 3x3 grid position marking according to the present invention.

[0047] Figure 4 Schematic diagram of the 3x3 unfolding of the reusable graphic unit and the final template sub-graph according to the present invention.

[0048] Figure 5 Schematic diagram of the resistance network port marking of the array unfolding template sub-graph according to the present invention. Detailed Embodiments

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0050] Figure 1 Schematic diagram of the process of a method for rapid extraction of large-scale mesh resistors of a basic array layout in an embodiment of the present application. As Figure 1As shown in the figure, it includes:

[0051] Determine the reusable graphic units on the array layout;

[0052] Cut the reusable graphic units to generate multiple sub-graphics;

[0053] Based on the multiple sub-graphics, expand the reusable graphic units in a 3*3 manner and merge the overlapping sub-graphics to generate a template sub-graph;

[0054] Perform image matching on the template sub-graph to determine the type of array expansion, where the type of array expansion includes at least one of the global array expansion type, the boundary array expansion type, and the four-corner array expansion type;

[0055] Perform finite element meshing on the template sub-graph, and reduce it to obtain a port-based resistance network, and perform array expansion on the template sub-graph based on the port-based resistance network to generate the entire resistance network.

[0056] Optionally, the determination of the reusable graphic units on the array layout includes:

[0057] Divide the functional areas of the array layout to determine the area where the reusable graphic units are located;

[0058] Extract the features of the area where the reusable graphic units are located to obtain the features of the reusable graphic units;

[0059] Calculate the similarity and repeatability of the reusable graphic units according to the features of the reusable graphic units to determine the reusable graphic units on the array layout.

[0060] Specifically, the specific implementation details of each step of determining the reusable graphic units on the array layout are as follows:

[0061] 1. Divide the functional areas of the array layout to determine the area where the reusable graphic units are located

[0062] Preliminary division based on design rules and empirical knowledge: First, deeply study the design documents of the array layout, including circuit schematics, layout plans, and relevant technical specifications. According to the common design patterns and standards of flat panel display (FPD) process technology, combined with the experience of previous similar projects, identify the approximate ranges of different functional areas. For example, in the display layout, there are usually obvious pixel array areas, control circuit areas, power supply areas, etc. By understanding the positional relationships, connection methods, and signal flow directions of these areas, preliminarily determine the approximate position and boundary of the pixel array area that may contain reusable graphic units.

[0063] Using EDA tools for graphic analysis to assist in partitioning: Use professional EDA design tools, which have powerful graphic viewing and analysis functions. After importing the array layout file, utilize functions such as layer management and graphic search provided by the tool to further refine the functional area partitioning. For example, by setting different display layers, the distribution of different elements can be clearly observed, and parts with similar graphic features and connection relationships can be grouped into one category, thereby more accurately determining the scope of the pixel array area. At the same time, utilize the graphic measurement function of the tool, such as measuring parameters such as the distance and area between elements, to assist in judging the boundaries and functional characteristics of the area.

[0064] Verifying and adjusting in combination with electrical characteristics: Conduct electrical characteristic analysis on the preliminarily partitioned functional areas, which can be achieved through simple circuit simulation or electrical rule checking in EDA tools. For example, check whether the circuit connections within the pixel array area conform to the expected electrical connection rules, such as whether the signal transmission path is continuous and whether the power distribution is reasonable. If areas with electrical characteristics not conforming to the expectations are found, it may be necessary to re-examine and adjust the functional area partitioning to ensure that the area where the reusable graphic unit is located is reasonable and independent in terms of electrical function.

[0065] 2. Extract the features of the area where the reusable graphic unit is located to obtain the features of the reusable graphic unit

[0066] Geometric shape feature extraction: For each graphic element within the area where the reusable graphic unit is located, extract its geometric shape-related features. This includes the type of the graphic (such as rectangle, polygon, circle, etc.), dimension parameters (length, width, radius, perimeter, area, etc.), angle information (such as the interior angles of a polygon, the included angle between graphics, etc.), and the position coordinates of the graphic (relative to a certain reference point or coordinate system). Utilize the graphic analysis function of the EDA tool to accurately obtain this geometric shape feature information. For example, for a rectangular pixel unit, accurately measure the length and width dimensions and record the coordinate position of its upper left vertex in the layout.

[0067] Internal element composition feature extraction: Analyze various circuit elements contained within the reusable graphic unit, such as transistors, capacitors, resistors, wires, etc. Determine the type, quantity, size of each element and their position distribution within the graphic unit. For example, through the graphic recognition and element classification functions of the layout, count the number and model of transistors within a pixel unit and mark the position and size of the capacitor. At the same time, attention also needs to be paid to the connection relationships between the elements, record the positions of the connection points and the connection methods (series, parallel, etc.), and these connection relationships are crucial for subsequent circuit analysis and resistance calculation.

[0068] Material characteristic feature extraction: Understanding the material information used in different parts of the reusable graphic unit is crucial for accurately calculating physical parameters such as resistance. Obtain material data from the layout design document or through communication with process engineers, including parameters such as the resistivity and dielectric constant of the material. In the EDA tool, different graphic areas of materials can be marked or property - set so that the corresponding material characteristics can be accurately identified and applied in subsequent processing. For example, for the wires composed of different metal layers, record the resistivity of their materials respectively to provide basic data for resistance calculation.

[0069] 3. According to the characteristics of the reusable graphic unit, calculate the similarity and repeatability of the reusable graphic unit to determine the reusable graphic units on the array layout

[0070] Feature quantization representation: Quantize the extracted features of the reusable graphic unit for mathematical calculation and comparison. For example, for geometric shape features, they can be represented by vectors. For instance, take the length and width of a rectangle as the two components of the vector; for the feature of internal element composition, it can be represented by a matrix, where the rows represent different types of components and the columns represent information such as the quantity and position of the components; for material characteristic features, establish a correspondence between the material parameter list and the graphic area. Through this quantization representation, convert the features of the graphic unit into a data form that can be processed by a computer.

[0071] Similarity metric algorithm selection and application: Select a suitable similarity metric algorithm to calculate the similarity degree between different graphic units. Common algorithms include the Euclidean distance algorithm, cosine similarity algorithm, etc. Select a suitable algorithm according to the data type and characteristics of the graphic unit features. For example, for geometric shape feature vectors, the Euclidean distance algorithm can be used to calculate the shape difference between two rectangular graphic units; for the internal element composition matrix, a similarity algorithm based on matrix operations can be used. Calculate the similarity between each pair of graphic units and set a similarity threshold. When the similarity exceeds this threshold, it is considered that the two graphic units have a high similarity.

[0072] Repeatability Detection and Verification: After determining the similarity, further perform repeatability detection. Examine the distribution pattern of graphic units with similar features in the array layout to see if they exhibit a regular row and column repeat arrangement. By analyzing the position coordinates of the graphic units, calculate the displacement vectors between adjacent graphic units. If the displacement vectors are consistent within a certain error range and the number of similar graphic units is large enough to form a regular array, then these graphic units are considered to have repeatability. At the same time, boundary conditions and special cases need to be considered. For example, there may be some incomplete graphic units at the edge of the array, but if their core features are similar to the internal repeating units, they should also be regarded as part of the reusable graphic units. By comprehensively considering similarity and repeatability, finally determine the reusable graphic units on the array layout, ensuring that the determined reusable graphic units are consistent and reusable throughout the array, providing an accurate basis for subsequent operations such as resistance extraction.

[0073] Optionally, the cutting of the reusable graphic units to generate multiple sub-graphics includes:

[0074] Based on the functional and electrical characteristics of the reusable graphic units, cut the reusable graphic units to generate multiple preliminary cut sub-graphics;

[0075] Determine whether the multiple preliminary cut sub-graphics meet the set cutting valid verification constraints. If they meet, stop the segmentation and use the preliminary cut sub-graphics when the cutting valid verification constraints are met as the sub-graphics. Otherwise, re-cut the reusable graphic units until the preliminary cut sub-graphics that meet the cutting valid verification constraints are obtained.

[0076] Optionally, the cutting valid verification constraint is: the maximum size of a single preliminary cut sub-graphic is less than the layout cells of 3 rows or 3 columns.

[0077] Specifically, the implementation details of each step in cutting the reusable graphic units to generate multiple sub-graphics are as follows:

[0078] 1. Perform preliminary cutting based on the functional and electrical characteristics of the reusable graphic units

[0079] Functional Feature Analysis and Cutting Planning: First, deeply understand the functional role of reusable graphic units in the entire circuit system. For example, in the pixel units of flat panel displays, determine the division of different internal functional modules according to how they implement functions such as brightness and color control during image display. For the wire parts responsible for signal transmission, transistor parts for controlling pixel switches, and capacitor parts for storing charge, etc., conduct preliminary cutting planning based on their functional boundaries. To ensure that the sub-graphics after cutting are relatively independent in function and do not damage the integrity of the original function. For example, cut along the vicinity of the connection points between transistors and wires so that the transistor part and the related wire part can be used as relatively independent preliminary cutting sub-graphics, while still retaining the necessary electrical connection relationship between them for subsequent analysis of their functions and electrical characteristics.

[0080] Electrical Feature Consideration and Cutting Operations: When performing cutting, fully consider the electrical characteristics inside the reusable graphic units. Analyze the current flow path, potential distribution, and electrical connection methods between different components in the graphic unit. For example, for series-connected resistor components, avoid cutting the series connection path between resistors during cutting to maintain the integrity of the current path; for parallel-connected capacitor components, ensure that the parallel relationship of the capacitors in the sub-graphics after cutting is still clearly distinguishable. Utilize the electrical analysis function of EDA design tools to visually observe the current path and potential distribution, and assist in determining reasonable cutting positions. During the cutting process, for complex electrical connection parts, such as areas with multi-layer wiring intersections or closely connected multiple components, adopt layered cutting or step-by-step subdivision methods. First, divide the complex area into larger preliminary cutting sub-graphics, and then further refine the cutting according to the subsequent verification situation.

[0081] 2. Judge Whether the Preliminary Cutting Sub-graphics Meet the Constraints of Cutting Effectiveness Verification

[0082] Establish a Layout Cell Model: To facilitate judging whether the size of the preliminary cutting sub-graphics meets the constraint conditions, establish a layout cell model corresponding to the 3x3 expansion. Divide the area where the reusable graphic unit is located into several virtual layout cells, and the size of each cell can be set according to actual requirements and the complexity of the graphic unit. For example, in a simple pixel unit, it can be divided into smaller square cells to more accurately measure the size of the sub-graphics; for complex circuit modules, different shapes and sizes of cells may need to be used for division according to their internal structural characteristics, but generally, it is necessary to ensure that the concept of the range of 3 rows or 3 columns can be accurately reflected.

[0083] Sub - graphic Dimension Measurement and Judgment: Use the graphic measurement function of the EDA design tool to measure the dimensions of each preliminary cut sub - graphic in the layout cell model. For each sub - graphic, determine the number of layout cells it occupies in the horizontal and vertical directions. If, in the horizontal direction, the number of cells occupied by the sub - graphic is less than 3 columns, and in the vertical direction, the number of cells occupied is less than 3 rows, then the sub - graphic meets the cutting validity verification constraint; conversely, if there is a sub - graphic that occupies 3 rows or 3 columns of layout cells in any one direction, it does not meet the constraint condition. During the measurement process, the boundary conditions of the graphics need to be considered. For the parts of the graphics that cross cell boundaries, accurately calculate the actual cell range they occupy to avoid misjudgment.

[0084] 3. Re - cutting Processing When the Constraint Conditions are not Met

[0085] Adjust the cutting strategy: When it is found that the preliminary cut sub - graphics do not meet the cutting validity verification constraint, it is necessary to re - examine the previous cutting strategy. Analyze the reasons for not meeting the constraint. It may be that the cutting position is not properly selected, resulting in some sub - graphics being too large; or that the distribution characteristics of the graphics are not fully considered during the cutting process in complex areas. Adjust the cutting position and method according to the specific situation. For example, if a sub - graphic is too large due to the complex internal structure of a certain functional module, the cutting method of this functional module can be further refined. Try to increase the number of cuts without affecting the function, and divide the large sub - graphic into smaller parts; if the cutting position is close to the edge of the graphic - dense area, resulting in the sub - graphic spanning multiple cells, the cutting position can be appropriately adjusted, moving towards the inside or sparse area of the graphic to reduce the size of the sub - graphic.

[0086] Iterative Cutting and Verification: After adjusting the cutting strategy, re - cut the reusable graphic unit and re - judge the cutting validity verification constraint for the newly generated preliminary cut sub - graphics. Repeat this process to continuously optimize the cutting scheme until the preliminary cut sub - graphics that meet the constraint conditions are obtained. During the iterative process, record the parameters and results of each cut for comparative analysis of the advantages and disadvantages of different schemes to improve the cutting efficiency. At the same time, as the cutting progresses, closely monitor whether the functions and electrical characteristics of the sub - graphics change to ensure that while meeting the size constraints, the original functions and electrical integrity of the reusable graphic unit are not damaged. Finally, use the preliminary cut sub - graphics that meet the cutting validity verification constraint as the final sub - graphics for subsequent operations such as 3x3 expansion, laying the foundation for accurately extracting large - scale mesh resistors.

[0087] Optionally, the step of performing 3*3 expansion on the reusable graphic unit based on the multiple sub - graphics and merging the overlapping sub - graphics therein to generate a template sub - graph includes:

[0088] Based on the multiple sub - graphics, expand the reusable graphic unit in a 3×3 manner along the row direction and the column direction, and mark the position of each expanded reusable graphic unit;

[0089] Based on the position marks, determine the overlapping sub - graphics in the expanded reusable graphic units to merge the overlapping sub - graphics and generate a template sub - graph accordingly.

[0090] Optionally, the step of determining the overlapping sub - graphics in the expanded reusable graphic units based on the position marks to merge the overlapping sub - graphics and generate a template sub - graph accordingly includes:

[0091] Based on the position marks of all reusable graphic units, assign a square - rectangle region annotation to each reusable graphic unit and record the sub - graphics within the square - rectangle region to generate a position index sequence;

[0092] Based on the position index sequence, determine the overlapping sub - graphics in the expanded reusable graphic units to merge the overlapping sub - graphics and generate a template sub - graph accordingly.

[0093] Specifically, the implementation details of the above steps of expanding the reusable graphic unit in a 3×3 manner based on the multiple sub - graphics and merging the overlapping sub - graphics therein to generate a template sub - graph are as follows:

[0094] 1. Expand in a 3×3 manner based on multiple sub - graphics and mark positions

[0095] 3×3 expansion operation: First, based on the multiple sub - graphics obtained by cutting the reusable graphic unit, perform a 3×3 expansion along the row direction and the column direction. This means that within a virtual 3×3 grid space, the reusable graphic unit (and its sub - graphics) is repeatedly placed to simulate its different position combinations in a large - scale array. For each sub - graphic, according to its relative position and orientation in the original reusable graphic unit, it is accurately placed at the corresponding position in the 3×3 grid. For example, if a sub - graphic is located in the upper - left corner area of the reusable graphic unit, then during the 3×3 expansion, it will be placed at the upper - left corner position (0, 0) of the grid and other relevant positions (such as (0, 1), (1, 0), etc., depending on expansion rules and factors such as the symmetry of the graphic unit). During the expansion process, the relative position relationship between sub - graphics needs to be maintained unchanged to ensure that the placement of each sub - graphic in the 3×3 grid is accurate and logical.

[0096] Position marking method: While performing a 3*3 expansion, position marking is carried out for each reusable graphic unit placed in the grid. An ordered marking system is adopted. For example, starting from the grid position in the upper left corner, it is marked as (0,0), then to the right in sequence as (1,0), (2,0), and then for the next row from left to right as (0,1), (1,1), (2,1), and so on until the grid position (2,2) in the lower right corner. This position marking will serve as an important basis for subsequent determination of the positions of sub-graphics and handling of overlapping situations. At the same time, for the convenience of subsequent operations, the position marking can be associated and stored with the relevant data structure of the reusable graphic unit (or its sub-graphics). For example, in a data record, it simultaneously contains the graphic information of the reusable graphic unit, the information of the sub-graphic to which it belongs, and the corresponding position marking information, so that the required information can be quickly obtained during subsequent queries and processing.

[0097] 2. Generate a position index sequence based on the position marking

[0098] Assign a rectangular area annotation to the square: According to the position marking of the reusable graphic unit, a rectangular area annotation for the square is assigned to each reusable graphic unit. The size and range of this rectangular area are determined based on the size of each small square in the 3*3 grid and the distribution of the reusable graphic unit in the grid. For example, if each small square in the 3*3 grid represents a unit area, then for the reusable graphic unit located at the position (0,0), its rectangular area annotation may be a rectangular area with the upper left corner coordinates (0,0) and the lower right corner coordinates (0 + the maximum size of the reusable graphic unit in the horizontal direction, 0 + the maximum size of the reusable graphic unit in the vertical direction). In this way, the position and range of each reusable graphic unit in the 3*3 grid are represented by a rectangular area, which is convenient for subsequent unified management and analysis of the sub-graphics within the area.

[0099] Sub - graphics within the recording area: For each reusable graphic unit assigned with a square - rectangular area annotation, the sub - graphics contained within its square - rectangular area are recorded in detail. Traverse all the graphic elements within this area, identify the parts belonging to the sub - graphics, and record their relevant information, such as the identification of the sub - graphics, graphic shape, material properties, etc. Organize this sub - graphic information in a certain order to form a sub - graphic record list for this square - rectangular area. For example, within the square - rectangular area of a reusable graphic unit located at position (1, 1), three sub - graphics are found, and information such as their sub - graphic numbers, relative positions within this area, and connection relationships with other sub - graphics are recorded. Combine all the square - rectangular area annotations of the reusable graphic units and their corresponding sub - graphic record lists to generate a position index sequence. This position index sequence comprehensively reflects the distribution of sub - graphics within the area of each reusable graphic unit in the 3 * 3 expanded grid, providing a detailed data basis for determining overlapping sub - graphics later.

[0100] 3. Generate a template sub - graph by merging overlapping sub - graphics based on the position index sequence

[0101] Identification of overlapping sub - graphics: Traverse each square - rectangular area annotation and its corresponding sub - graphic record list in the position index sequence. For any two or more square - rectangular areas, if they have an intersection in space (i.e., partial or complete overlap), it is necessary to check whether the sub - graphics within these overlapping areas overlap. Determine whether there is an overlap by comparing information such as the positions and shapes of the sub - graphics. For example, if two square - rectangular areas partially overlap at position (1, 1), check whether the sub - graphics within this overlapping area have the same coordinate range or overlapping parts. If overlapping sub - graphics are found, mark these overlapping sub - graphics for merging.

[0102] Determination of the merging rules for overlapping sub - graphics: After identifying the overlapping sub - graphics, formulate appropriate merging rules according to the characteristics of the reusable graphic units, circuit connection requirements, and subsequent resistance calculation needs. If the overlapping sub - graphics are of the same material and are electrically continuous, for example, they are all parts of the same - layer metal wire, then they can be merged into a larger graphic, update its graphic shape, size, etc. parameters, and adjust the connection relationships with other relevant sub - graphics. If the overlapping sub - graphics involve different materials but are functionally related, such as a metal wire overlapping with a semiconductor region connected to it, it may be necessary to determine the attributes of the merged graphic according to specific physical models and equivalent circuit principles, such as calculating equivalent resistance, capacitance, etc. parameters, to ensure that the merged template sub - graph can accurately reflect the characteristics of the original reusable graphic unit in terms of electrical characteristics.

[0103] Template sub - figure generation: According to the determined merging rules, perform a merging operation on the marked overlapping sub - figures to generate new template sub - figures. Organize and record the information of the merged template sub - figures, update the sub - figure information in the corresponding area of the position index sequence, and replace the original overlapping sub - figure records with the merged template sub - figures. Continue to traverse the position index sequence to handle other possible overlapping situations until all overlapping sub - figures are merged. In the finally obtained position index sequence, the sub - figures (which may be single sub - figures or merged template sub - figures at this time) within each square rectangular area will serve as the basic units for subsequent array expansion and resistance calculation. These template sub - figures after the merging process can more accurately reflect the equivalent graphic structure of the reusable graphic units after 3 * 3 expansion, laying a foundation for the efficient extraction of large - scale mesh resistance networks.

[0104] Optionally, perform image matching on the template sub - figure to determine the type of array expansion. The types of array expansion include global array expansion type, boundary array expansion type, and corner array expansion type, including:

[0105] Traverse the graphics of each template sub - figure to match with the positions of the 3x3 grid;

[0106] If the graphics of a template sub - figure intersect with the 9 position coordinates of the 3x3 grid, mark it as the global array expansion type;

[0107] If a template sub - figure only intersects with the four - side positions, mark it as the boundary array expansion type;

[0108] If a template sub - figure only appears at the four - corner positions, mark it as the corner array expansion type.

[0109] Specifically, the technical implementation details of each step of performing image matching on the template sub - figure to determine the type of array expansion are as follows:

[0110] 1. Traverse the matching of the template sub - figure graphics with the 3x3 grid positions

[0111] Establish a graphics traversal mechanism: First, an effective mechanism needs to be established to traverse the graphics of each template sub - figure. This can be achieved by using graphic data structures and related algorithms. For example, for template sub - figures represented by vector graphics, a recursive algorithm can be used to traverse each basic graphic element such as line segments and polygons in the graphic; for template sub - figures represented by raster images, the image can be scanned pixel - by - pixel to determine the scope and shape of the graphic. During the traversal process, record the position information of each graphic element, such as the starting and ending coordinates of line segments, the vertex coordinates of polygons, etc., for comparison with the 3x3 grid positions.

[0112] Compare with the 3x3 grid position coordinates: Compare the position coordinates of the graphic elements of the template sub-graph obtained by traversal with the position coordinates of the 3x3 grid one by one. For each graphic element, determine whether it intersects with one or more small squares in the 3x3 grid. This can be determined by checking whether the coordinate range of the graphic element overlaps with the coordinate range of the small square. For example, if the starting coordinate and ending coordinate of a line segment are located in two different small squares, or the vertices of a polygon are distributed in multiple small squares, then it is considered that the graphic element intersects with these small squares. During the comparison process, the boundary conditions of the graphic element need to be considered to ensure accurate determination of the intersection relationship. At the same time, to improve the comparison efficiency, a spatial index data structure can be used to quickly locate the 3x3 grid areas that may intersect with the template sub-graph graphics, reducing unnecessary comparison calculations.

[0113] 2. Mark the array expansion type according to the intersection situation

[0114] Global array expansion type judgment: During the traversal and comparison process, if it is found that the graphics of a template sub-graph intersect with all 9 position coordinates of the 3x3 grid, that is, its graphics cover the entire 3x3 grid area, then mark this template sub-graph as the global array expansion type. This means that this template sub-graph has a wide distribution and influence in the array, and its resistance characteristics will act within the entire array range. After marking as the global array expansion type, record the relevant information of this template sub-graph, such as graphic features, position information, etc., for subsequent targeted array expansion operations.

[0115] Boundary array expansion type judgment: If the graphics of a template sub-graph only intersect with the four-side positions of the 3x3 grid, that is, have an intersection relationship with the small squares located at the grid edges but do not cover the entire grid area, then mark it as the boundary array expansion type. During the judgment process, it is necessary to accurately identify the situation of intersection with the four-side positions, which can be determined by checking whether the coordinates of the graphic elements are within the range of the small squares in the first row, third row, first column, or third column of the grid. For the template sub-graphs marked as the boundary array expansion type, record their detailed information as well, because their resistance characteristics at the array boundary may be different from those inside and need to be specially considered in subsequent processing.

[0116] Four-corner array expansion type judgment: When the graphics of a template sub-graph only appear at the four corners of the 3x3 grid, that is, only intersect with the small squares located at the upper left corner (0, 0), upper right corner (2, 0), lower left corner (0, 2), and lower right corner (2, 2), mark it as the four-corner array expansion type. This type of template sub-graph has unique resistance characteristics at the four corners of the array, and its influence on the entire array resistance network is mainly concentrated in the corner areas. After marking as the four-corner array expansion type, save its relevant information for correct processing during array expansion.

[0117] 3. Generate type indexing

[0118] Establishment of type indexing data structure: Create a data structure for storing type indexing information of template sub - graphs, such as an array or a list. Each element corresponds to a template sub - graph and records its belonging array expansion type (global, boundary or corner) and other relevant information, such as the position index of the template sub - graph in the original array. Through this data structure, it is convenient to classify and query template sub - graphs according to types.

[0119] Optionally, perform finite element meshing on the template sub - graph, and reduce it to obtain a port - based resistance network, and perform array expansion on the template sub - graph based on the port - based resistance network to generate the entire resistance network, including:

[0120] Obtain the port information labeled for each template sub - graph;

[0121] Based on the port information, perform finite element meshing on the corresponding template sub - graph to generate a resistance network;

[0122] Perform equivalent reduction on the resistance network to generate an equivalent port - based resistance network.

[0123] Perform array expansion on the template sub - graph based on the equivalent port - based resistance network to generate the entire resistance network.

[0124] Optionally, the method further includes:

[0125] Obtain the cutting ports when cutting the reusable graphic unit;

[0126] Assign split marks to each cutting port to generate port information labeled for each template sub - graph based on the split marks obtained for each sub - graphic.

[0127] Specifically, the implementation details of the above steps of performing finite element meshing on the template sub - graph, reducing it to obtain a port - based resistance network, and performing array expansion on the template sub - graph based on the port - based resistance network to generate the entire resistance network are as follows:

[0128] (1) Obtain the port information labeled for each template sub - graph on the array - expanded template sub - graph:

[0129] First, it is necessary to determine how to identify and label ports. This can be achieved through the following methods:

[0130] 1. Analyze the graphic features of the array - expanded template sub - graph to determine the possible positions of ports. For example, specific connection points, interfaces with other parts, etc.

[0131] 2. Use image processing and graphic analysis algorithms to detect specific shapes, endpoints or intersections of lines in the template sub - graph, which may be the positions of ports.

[0132] 3. Assign a unique identifier or label to the identified port positions for subsequent processing and identification.

[0133] (2) Based on the port information, perform finite - element meshing on the corresponding template sub - graph to generate a port - based resistance network:

[0134] Here, the Delaunay triangulation algorithm (such as the Bowyer - Watson algorithm) can be used for finite - element meshing. The specific steps are as follows:

[0135] 1. Select a suitable meshing algorithm, such as the Bowyer - Watson algorithm.

[0136] 2. Construct a super - triangle that encloses all the template sub - graphs to be meshed and put it into the triangle linked list.

[0137] 3. Insert the points in the template sub - graph into the triangle linked list in a certain order. When inserting each point, find the triangle whose circum - circle contains the inserted point (i.e., the influence triangle of this point).

[0138] 4. Delete the common edges of the influence triangles, connect the inserted point to all the vertices of the influence triangle, and complete the insertion of a point in the Delaunay triangle linked list.

[0139] 5. Optimize the newly formed triangles according to the optimization criterion (such as the maximum empty - circle criterion). For example, check if there is a situation where four points are concyclic. If so, perform operations such as diagonal swapping.

[0140] 6. Repeat steps 3 to 5 until all points are inserted, thus obtaining the Delaunay triangulation result of the template sub - graph, that is, the resistance network.

[0141] During the meshing process, the following points should be noted:

[0142] 1. According to the port positions and the specific shapes, sizes and other characteristics of the template sub - graph, reasonably control the density of the mesh. In the vicinity of the ports or areas where current may concentrate, appropriately increase the mesh density to improve the accuracy of the meshing.

[0143] 2. Ensure that the triangles after meshing satisfy the characteristics of Delaunay triangulation, that is, no other points are contained within the circum - circle of any triangle, to ensure the quality and stability of the meshing.

[0144] (3) Perform equivalent reduction on the resistance network to generate an equivalent resistance network based on ports:

[0145] Reduction can be carried out by using the method of equivalent circuit. For example:

[0146] 1. Analyze the series and parallel relationships in the resistor network. For series resistors, they can be equivalent to a total resistor according to the resistor series formula Req = R1 + R2 +... + Rn.

[0147] 2. For parallel resistors, calculate the equivalent resistance according to the resistor parallel formula 1 / Req = 1 / R1 + 1 / R2 +... + 1 / Rn.

[0148] 3. For some complex circuit structures, Thevenin's theorem or Norton's theorem can be used to equivalent the active two-terminal network to a circuit model with an ideal voltage source in series with a resistor, or a circuit model with an ideal current source in parallel with a resistor.

[0149] 4. During the reduction process, pay attention to keeping the equivalent characteristics of the ports unchanged, that is, the electrical characteristics of the equivalent resistor network at the ports are the same as those of the original resistor network.

[0150] (4) Expand the template sub-graph in an array based on the equivalent resistor network based on the port and its type to generate the entire resistor network based on the port: The specific implementation of expanding the template sub-graph is as follows:

[0151] 1. Determine the size of the array, such as 100x100.

[0152] 2. Expand the three types of template sub-graphs in an array. Based on the known positions and connection relationships obtained from the processing of the equivalent resistor network based on the port, label the corresponding port information and port connection information for each template sub-graph. In this way, the entire resistor network based on the port is obtained.

[0153] (5) Obtain the cutting ports when cutting the reusable graphic unit:

[0154] During the process of cutting the reusable graphic unit, the cutting ports can be obtained in the following ways:

[0155] 1. Record the positions where the graphic unit intersects the cutting line during the cutting process. These positions may be the cutting ports.

[0156] 2. According to the function or electrical characteristics of the graphic unit, pre-determine the areas where cutting ports may exist, and then focus on these areas during cutting.

[0157] (6) Assign split marks to each cutting port to generate the port information labeled for each template sub-graph based on the split marks obtained for each sub-graphic:

[0158] The specific implementation is as follows:

[0159] 1. Assign a unique segmentation mark to each cutting port.

[0160] 2. During the process of generating sub-graphs, record the segmentation marks corresponding to each sub-graph.

[0161] 3. Determine the positions and connection relationships of the sub-graphs in the template sub-graph according to the segmentation marks of the sub-graphs.

[0162] 4. Based on these positions and connection relationships, label the corresponding port information for each template sub-graph. For example, determine which boundary points of the sub-graphs correspond to the port positions, and label these points with port identifiers or relevant information. In this way, the port information of each template sub-graph can be generated for subsequent operations such as finite element meshing.

[0163] The following combines Figures 2 - 5 , and illustrates the application examples of the above solutions of this application:

[0164] The following combines specific embodiments to elaborate in detail the specific process of the large-scale mesh resistor fast extraction method based on the array layout of the present invention.

[0165] 1) Open a layout, find the reusable graphic unit in its array area, and add cutting ports. Figure 2 Schematic diagram of cutting the reusable graphic unit according to the present invention.

[0166] 2) After the cutting process according to Figure 2 , perform a 3x3 expansion process. Figure 3 According to the schematic diagram of the 3x3 grid position marking of the present invention, increment from left to right and from bottom to top, with the starting value of 0, and mark the 3x3 grid positions.

[0167] 3) After the 3x3 expansion and merging of the graphics, perform graphic matching and confirm the position information of the template sub-graph after matching. Figure 4 Schematic diagram of the 3x3 expansion of the reusable graphic unit and the final template sub-graph according to the present invention. As shown in the figure, the number of merged graphics is 15. Through graphic matching, there are 6 template sub-graphs, which are respectively marked as 1 to 6 in the figure. Among them, 5 is the global array expansion type, and its four graphics intersect with the 9 position coordinates of the 3x3 grid. 1, 2, 4, and 6 are the boundary array expansion types. 1 intersects with the 0, 3, and 6 positions of the 3x3 grid, 2 intersects with the 6, 7, and 8 positions of the 3x3 grid, 4 intersects with the 2, 5, and 8 positions of the 3x3 grid, 6 intersects with the 0, 1, and 3 positions of the 3x3 grid, and 3 is the corner array expansion type, intersecting with the 8 position of the 3x3 grid.

[0168] 4) Take the 3x3 array expansion template sub-graph as an example.Figure 5 Schematic diagram of the resistor network port marking for the sub - graph of the array expansion template according to the present invention. As shown in the figure, there are 27 ports in the array area. The results of obtaining the port information of the template sub - graph are as follows: The template sub - Figure 5 has four groups of port information, which are: <0,1,2,3,4,11>, <3,4,5,6,7,14>, <9,10,11,12,13,20>, <12,13,14,15,16,23>; The template sub - Figure 1 has three groups of port information, which are: <0, 1>, <9, 10>, <18, 19>, The template sub - Figure 2 has two groups of port information, which are: <18, 19, 20, 21, 22>, <21, 22, 23, 24, 25>, The template sub - Figure 4 has two groups of port information, which are: <6, 7, 8, 17>, <15, 16, 17, 26>. The template sub - graph 6 has three groups of port information, which are: <2>, <5>, <8>; The template sub - Figure 3 has one group of port information, which is: <24, 25, 26>. Then, finite - element meshing is performed on each template sub - graph to obtain its resistor network, and it is reduced to an equivalent resistor network based on ports. Taking the template sub - Figure 1 as an example, only the resistance from port 0 to port 1 needs to be calculated, assumed to be 10, then the resistance from port 9 to 10 and from port 18 to 19 is also 10. Thus, through the array expansion of the template sub - graph, the resistor network of the entire array area is obtained. If the resistance from port 2 to 8 is calculated, the resistance can be quickly obtained.

[0169] The embodiment of the present application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of a method for quickly extracting large - scale mesh resistors of a basic array layout as described in the embodiment of the present application are implemented.

[0170] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer - usable storage media (including but not limited to disk memory, CD - ROM, optical memory, etc.) containing computer - usable program code.

[0171] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0172] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0173] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0174] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0175] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A method for rapid extraction of large-scale mesh resistance of a basic array layout, characterized in that: include: Determine reusable graphic units on the array layout; Cutting the reusable graphic unit to generate a plurality of sub-graphics; Based on the multiple sub-graphs, the reusable graphic unit is expanded by 3*3 and the overlapping sub-graphs therein are merged to generate a template sub-graph; Performing image matching on the template sub-image to determine the type of array expansion, wherein the type of array expansion includes at least one of a global array expansion type, a boundary array expansion type, and a four-corner array expansion type; The template subgraph is subjected to finite element segmentation and simplified to obtain a port-based resistor network, and the template subgraph is array-expanded based on the port-based resistor network to generate the entire resistor network.

2. The method for rapidly extracting large-scale mesh resistance of a basic array layout according to claim 1, characterized in that: The step of determining the reusable graphic units on the array layout includes: Dividing the array layout into functional areas to determine the area where the reusable graphic units are located; Extracting features from the area where the reusable graphic unit is located to obtain features of the reusable graphic unit; According to the characteristics of the reusable graphic units, similarity and repeatability calculations of the reusable graphic units are performed to determine the reusable graphic units on the array layout.

3. The method for rapidly extracting large-scale mesh resistance of a basic array layout according to claim 1, characterized in that: The step of cutting the reusable graphic unit to generate a plurality of sub-graphics includes: Based on the functional characteristics and electrical characteristics of the reusable graphic unit, the reusable graphic unit is cut to generate a plurality of preliminary cut sub-graphics; Determine whether multiple preliminary cut sub-graphics satisfy the set cutting validity verification constraints. If so, stop segmentation and use the preliminary cut sub-graphic that satisfies the cutting validity verification constraints as the sub-graphic. Otherwise, re-cut the reusable graphic unit until the preliminary cut sub-graphic that satisfies the cutting validity verification constraints is obtained.

4. The method for rapidly extracting large-scale mesh resistance of a basic array layout according to claim 1, characterized in that: The effective verification constraint of the cutting is that the maximum size of a single preliminary cut sub-graphic is smaller than 3 rows or 3 columns of layout cells.

5. The method for rapidly extracting large-scale mesh resistance of a basic array layout according to claim 1, characterized in that: The step of expanding the reusable graphic unit by 3*3 based on the multiple sub-graphics and merging the overlapping sub-graphics therein to generate a template sub-graphic includes: Based on the multiple sub-graphics, the reusable graphic unit is expanded 3*3 along the row and column directions, and a position mark is performed on each expanded reusable graphic unit; Based on the position mark, the overlapping sub-graphics in the expanded reusable graphic unit are determined to merge the overlapping sub-graphics and generate a template sub-graphic accordingly.

6. The method for rapidly extracting large-scale mesh resistance of a basic array layout according to claim 5, characterized in that: The step of determining the overlapping sub-graphics in the expanded reusable graphic unit based on the position mark to merge the overlapping sub-graphics and generate a template sub-graphic accordingly comprises: Based on the position marks of all reusable graphic units, assign a square rectangular area mark to each reusable graphic unit and record the sub-graphics within the square rectangular area to generate a position index sequence; Based on the position index sequence, overlapping sub-graphics in the expanded reusable graphic unit are determined to merge the overlapping sub-graphics and generate a template sub-graphic accordingly.

7. The method for rapidly extracting large-scale mesh resistance of a basic array layout according to claim 1, characterized in that: The performing image matching on the template sub-image to determine the type of array expansion, wherein the type of array expansion includes a global array expansion type, a boundary array expansion type, and a four-corner array expansion type, includes: Traverse the graph of each template subgraph to match the position of the 3x3 grid; If the shape of a template sub-graph intersects all 9 position coordinates of the 3x3 grid, it is marked as a global array expansion type; If a template subgraph intersects only four edge locations, it is marked as a bounding array expansion type; If a template subgraph appears only at the four corner positions, it is marked as a four-corner array expansion type.

8. The method for rapidly extracting large-scale mesh resistance of a basic array layout according to claim 1, characterized in that: The finite element segmentation is performed on the template subgraph, and the port-based resistor network is simplified, and the array expansion of the template subgraph based on the port resistor network is performed to generate the entire resistor network, including: Get the port information marked for each template sub-image; Based on the port information, finite element segmentation is performed on the corresponding template subgraph to generate a port-based resistor network; Performing equivalent reduction on the resistor network to generate a port-based equivalent resistor network; The template subgraph is array-expanded based on the equivalent resistor network of the ports to generate the entire resistor network.

9. The method for rapidly extracting large-scale mesh resistance of a basic array layout according to claim 8, characterized in that: The method further comprises: Obtaining a cutting port when cutting the reusable graphic unit; A segmentation mark is allocated to each cutting port, so as to generate port information marked on each template sub-graph based on the segmentation mark of each sub-graph.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method for fast extraction of large-scale mesh resistance of a basic array layout as claimed in any one of claims 1 to 9 are implemented.

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