Resistance information extraction method, device and equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses a resistance information extraction method, device and equipment, and the method comprises the steps: obtaining the layout information of each metal layer in a circuit network; determining first layout information of a first type of metal layer and second layout information of a second type of metal layer in the layout information; retaining the graphic information of the signal lines and the standard units in the first layout information, and deleting the graphic information of the signal lines and the standard units in the second layout information; and based on the processed first layout information and the processed second layout information, extracting resistance information of each metal layer in the circuit network. According to the technical scheme provided by the invention, the extraction precision and extraction efficiency of the resistance information can be considered.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular, to a method, apparatus, and device for extracting resistor information. Background Art

[0002] In the field of integrated circuits, when extracting the resistance of a circuit network using a mature process, only the circuit network pattern is usually considered to reduce the processing of graphic data and improve the resistor extraction efficiency.

[0003] With the continuous development of advanced processes, the line width of the process node becomes narrower, and the influence of the etching value on the etched line width becomes greater. If only the circuit network pattern is considered, the accuracy of the extracted resistor will be reduced. However, if all the patterns in the circuit network are considered, the efficiency of resistor extraction will be reduced.

[0004] In view of this, there is an urgent need for a method for extracting resistor information that can balance the extraction accuracy and extraction efficiency. Summary of the Invention

[0005] The present application provides a method, apparatus, and device for extracting resistor information, which can balance the extraction accuracy and extraction efficiency of resistor information.

[0006] In a first aspect of the present application, a method for extracting resistor information is provided. The method includes: obtaining the layout information of each metal layer in a circuit network; determining the first layout information of a first type of metal layer and the second layout information of a second type of metal layer in the layout information; retaining the graphic information of signal lines and standard cells in the first layout information, and deleting the graphic information of signal lines and standard cells in the second layout information; and extracting the resistor information of each metal layer in the circuit network based on the processed first layout information and the processed second layout information.

[0007] In a second aspect of the present application, a method for extracting resistor information is further provided. The method includes: obtaining the original layout information of a target metal layer currently input; based on the original layout information, determining whether to retain the graphic information of signal lines and standard cells in the original layout information, and generating updated layout information of the target metal layer based on the determination result; and extracting the resistor information of the target metal layer according to the updated layout information.

[0008] The third aspect of the present application further provides a device for extracting resistance information. The device includes: a layout information acquisition unit configured to acquire the layout information of each metal layer in a circuit network; an information determination unit configured to determine the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the layout information; an information processing unit configured to retain the graphic information of signal lines and standard cells in the first layout information and delete the graphic information of signal lines and standard cells in the second layout information; and a resistance extraction unit configured to extract the resistance information of each metal layer in the circuit network based on the processed first layout information and the processed second layout information.

[0009] The fourth aspect of the present application further provides a computer device. The computer device includes a memory and a processor. The memory is used to store a computer program, and when the computer program is executed by the processor, the method for extracting resistance information according to the first aspect or the second aspect is implemented.

[0010] The technical solution provided by one or more embodiments of the present application classifies different metal layers of a circuit network, selectively retains the graphic information of signal lines and standard cells, so as to obtain more accurate resistance information. Among them, some metal layers retain the graphic information of signal lines and standard cells to obtain a more accurate pitch, thereby improving the accuracy of resistance extraction, and the other part of the metal layers delete the graphic information of signal lines and standard cells to reduce the graphic information processing task, ensuring the efficiency of resistance extraction while ensuring the accuracy of resistance extraction.

[0011] It can be seen that through the technical solution provided by the embodiments of the present application, the extraction accuracy and extraction efficiency of resistance information can be taken into account. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a schematic diagram of the steps of a method for extracting resistance information provided by an embodiment of the present application; Figure 2 It is a schematic diagram of the structure of a partial cutting area of the first type of metal layer provided by an embodiment of the present application; Figure 3 It is a schematic diagram of the structure of a partial cutting area of the second type of metal layer provided by an embodiment of the present application; Figure 4Schematic diagram of steps of a method for extracting resistance information provided in another embodiment of the present application; Figure 5 Schematic diagram of the structure of a circuit network with four metal layers provided in an embodiment of the present application; Figure 6 Schematic diagram of the structure of a device for extracting resistance information provided in an embodiment of the present application; Figure 7 Schematic diagram of the structure of a computer device provided in an embodiment of the present application. Detailed implementation manners

[0014] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0015] In addition, the descriptions involving "first", "second", etc. in the present application are only for descriptive purposes, and cannot be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more. In addition, the use of "based on" or "according to" means open and inclusive, because a process, step, calculation, or other action "based on" or "according to" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.

[0016] In integrated circuit design, the metal layers in a circuit network have functions such as signal transmission, power distribution, heat dissipation, and electromagnetic shielding. With the increase in the functions of the circuit network and the expansion of the integration scale, the interconnection structure in the circuit network becomes more and more complex, resulting in more and more serious parasitic effects of the interconnections, generating more parasitic resistances. The parasitic resistances will affect the performance of the circuit network. Therefore, improving the accuracy of resistance extraction is crucial for ensuring the performance and reliability of integrated circuits. Generally speaking, when extracting resistance information from a circuit network, the graphics of the integrated circuit are often cut, and the resistances on each of the cut graphics are calculated.

[0017] When calculating resistance in mature processes, usually only the circuit network pattern is considered, while the standard cell pattern and signal line pattern are ignored. The process nodes of mature processes are above 28 nanometers, and their metal widths are relatively large. Ignoring the standard cell pattern and signal line pattern will not affect the resistance accuracy, but can improve the resistance extraction efficiency. However, with the continuous development of advanced processes, their process nodes can reach below 14 nanometers, and the metal widths are relatively small. At this time, ignoring the standard cell pattern and signal line pattern will lead to inaccurate metal pitch search, resulting in loss of resistance accuracy. On the contrary, if all the circuit network pattern, standard cell pattern, and signal line pattern are read and resistance extraction is performed, the efficiency of extracting resistance will decrease.

[0018] It should be noted that the resistance value of the metal grid line will be affected by the metal etching width. When the metal width is small, the size of the etching value will have a greater impact on the metal etching width obtained by etching, and the size of the etching value is determined by the metal pitch. Therefore, when the metal width is small, it is particularly important to clarify the size of the metal pitch for the calculation of resistance accuracy.

[0019] In view of this, how to ensure the resistance extraction efficiency and improve the resistance accuracy of the circuit network under advanced processes is a difficult point that needs to be solved urgently. In practical applications, the circuit network is usually designed as a stacked metal grid line structure to ensure that each component in the electronic device can obtain stable and appropriate power supply, and the current flows from the high-level metal layer to the low-level metal layer. One or more embodiments of the present application provide a method, device, and equipment for extracting resistance information, which can solve the above problems. By classifying and extracting resistance for different metal layers, the extraction accuracy and extraction efficiency of resistance information can be taken into account.

[0020] Please refer to Figure 1 , an embodiment of the present application provides a method for extracting resistance information, and the method may include the following multiple steps.

[0021] S11: Obtain the layout information of each metal layer in the circuit network.

[0022] The above circuit network can be understood as the interconnection structure on the entire chip, which includes multiple metal layers stacked from top to bottom. Each metal layer can be responsible for functions such as power distribution, signal transmission, and heat dissipation. The line widths of each metal layer are different, and their uses and interconnection rules are also different. The above line width can be understood as the width of the metal grid line in each metal layer, and the line width size affects the resistance and inductance of the metal layer. Generally speaking, the metal layers located at higher levels have larger line widths and stronger current-carrying capabilities, and are used to form power and ground networks and provide power and ground connections. The metal layers located at lower levels have smaller line widths, which are convenient for placing standard cells and routing wires, and are used for signal transmission.

[0023] In this embodiment, the layout information of the metal layer may include the layer identification and size information of the metal layer. Among them, the layer identification is used to distinguish different metal layers, and the size information may include the line width of the metal grid lines of the current metal layer, the metal area density, and the spacing between the metal grid lines. The above-mentioned metal area density can be understood as the metal coverage rate on the metal layer, and the size of the metal coverage rate affects the heat dissipation of the chip and the integrity of the transmitted signal. The above-mentioned spacing between the metal grid lines can be understood as the distance between adjacent metal grid lines.

[0024] In addition, the above-mentioned layout information may further include the graphic information of the signal lines and standard cells, and the graphic information of the signal lines and standard cells can be used for subsequent calculation of the target spacing. Among them, the above-mentioned standard cell can be understood as a basic circuit unit formed on the metal layer following specific design rules. The input and output pins of each standard cell can be connected to other units for signal connection, and the graphic information of the standard cell is the distribution information of the metal lines in each standard cell. The graphic information of the above-mentioned signal lines can be understood as the graphics of the signal lines connecting different standard cells and other modules inside the chip on the metal layer, which are used to transmit and process various electrical signals.

[0025] Exemplarily, the layer identification of the metal layer can be character names such as Metal1, Metal2, Metal3, and Metal4. Different metal layers are represented by the layer identification. Metal1 and Metal2 can be understood as the metal layers closest to the silicon substrate, which are used for the interconnection of transistors and underlying components. Metal3 and Metal4 are located above Metal1 and Metal2 and are used to provide interconnections across the chip area, including the connection of signal lines, power supply, and ground wires.

[0026] S13: Determine the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the layout information.

[0027] In this embodiment, the metal layer with a smaller line width among the above-mentioned multiple metal layers is determined as the first type of metal layer, and the metal layer with a larger line width is determined as the second type of metal layer. Specifically, the layout information of different metal layers is different. The different metal layers are classified according to the layout information to facilitate subsequent determination of the resistance calculation method for each type of metal layer. The specific classification method for different metal layers is not limited. Exemplarily, it can be determined according to the specific instructions of the user, or according to the layout information such as the upper and lower layers where different metal layers are located, or the line width of the metal layer. Classifying each of the above-mentioned metal layers as needed facilitates subsequent classification processing of each metal layer according to different layout information.

[0028] Meanwhile, obtain the layout information of each metal layer of the circuit network, extract the layout information of the first type of metal layer and determine it as the first layout information, and extract the layout information of the second type of metal layer and determine it as the second layout information.

[0029] S15: Retain the graphic information of signal lines and standard cells in the first layout information, and delete the graphic information of signal lines and standard cells in the second layout information.

[0030] In this embodiment, retaining the graphic information of signal lines and standard cells in the first layout information can improve the resistance accuracy of the circuit network. The metal width of the metal grid lines in the first type of metal layer is small, and the metal etching width obtained by etching is greatly affected by the etching value. By retaining the graphic information of signal lines and standard cells in the first layout information and considering the graphic information of metal grid lines and signal lines or standard cells when calculating the spacing, the target spacing can be made more accurate, so as to obtain a more accurate etching value, and further ensure the extraction accuracy of resistance information.

[0031] In this embodiment, deleting the graphic information of signal lines and standard cells in the second layout information can ensure the efficiency and performance of the resistance extraction process while improving the resistance extraction accuracy. The metal width of the second type of metal layer is large, and the size of the etching value has little influence on the metal etching width, resulting in a small loss of resistance accuracy. Therefore, by deleting the graphic information of signal lines and standard cells in the second layout information and using the distance between adjacent metal grid lines in the circuit network as the target spacing to estimate the resistance of the second type of metal layer, the processing of the graphic information of signal lines and standard cells in the second layout information can be avoided, thereby improving the resistance extraction efficiency and resistance extraction performance.

[0032] S17: Based on the processed first layout information and the processed second layout information, extract the resistance information of each metal layer in the circuit network.

[0033] In this embodiment, based on the above-mentioned processed first layout information and second layout information, the target spacing of the first type of metal layer and the target spacing of the second type of metal layer can be obtained respectively. Specifically, obtain the etching values corresponding to the above-mentioned respective target spacings in the non-linear look-up table of the process file. According to W = Wdrawn - 2ETCH, the metal etching width can be obtained, where W is the metal etching width, Wdrawn is the metal width of the metal grid line, and ETCH is the etching value. The extracted resistance R can be expressed as R = ρ × L / W × T, where ρ is the resistivity of the current metal grid line, L is the length of the metal grid line, and T is the thickness of the metal grid line. It can be seen that after obtaining the accurate metal etching width, the accuracy of the extracted telecommunications information can be ensured.

[0034] In one embodiment, based on the above step S13, determining the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the layout information may include any of the following methods: Method 1: In response to an input selection instruction, determine the first type of metal layer and the second type of metal layer among the metal layers of the circuit network, and obtain the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the layout information.

[0035] Method 2: Identify the layer identifiers of the metal layers, and determine the metal layers with the specified layer identifiers in the circuit network as the first type of metal layer, and determine the other metal layers in the circuit network except the first type of metal layer as the second type of metal layer. Obtain the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the layout information.

[0036] Method 3: Identify the size description information of the metal layers, and determine the metal layers whose size description information meets the preset conditions as the first type of metal layer, and determine the other metal layers in the circuit network except the first type of metal layer as the second type of metal layer. Obtain the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the layout information, where the size description information is used to characterize at least one of the line width of the metal grid lines in the metal layer, the spacing between adjacent metal grid lines, and the metal area density of the metal layer.

[0037] In this embodiment, the above Method 1 divides the types of metal layers by responding to a user instruction. Specifically, in response to a selection instruction input by the user, each metal layer is divided into the first type of metal layer or the second type of metal layer, where the above selection instruction can be specified by the user according to actual needs, so that the user can directly select the metal layer for which the graphics need to be retained.

[0038] In this embodiment, the above Method 2 divides the types of metal layers according to the layer identifiers of the metal layers. The metal layers with the specified layer identifiers are determined as the first type of metal layer. Preferably, the specified layer identifier can be a layer identifier representing a metal layer located at a higher layer. Since different layer identifiers can represent that the metal layer is located at a higher layer or a lower layer, different metal layers are further distinguished according to the line width, so as to determine the metal layer for which the graphics need to be retained.

[0039] In this embodiment, in the above method three, the first type of metal layers that meet the preset conditions are directly screened according to the size description information of each metal layer. Exemplarily, the screening is performed according to the line width, pitch, or metal area density. Specifically, metal layers with a line width less than the first specified threshold, a ratio of pitch to line width greater than the second specified threshold, or a metal area density greater than the third specified threshold can be determined as the first type of metal layers, and other metal layers can be determined as the second type of metal layers, so as to determine the metal layers for which graphic information needs to be retained. The above first specified threshold, second specified threshold, and third specified threshold can all be flexibly set according to the actual scenario, and the present application does not limit this.

[0040] In one or more embodiments, on the basis of the above step S13, the resistance information of each metal layer in the circuit network can be extracted according to the following two types: Type one: Extract the resistance information for the first type of metal layers.

[0041] Specifically, the first type of metal layers are divided into multiple local cutting regions. For the first metal grid line in the first type of metal layers for which the resistance information needs to be extracted, identify the local cutting region where the first metal grid line is located. The local cutting region includes a second metal grid line adjacent to the first metal grid line. There are one or more third circuit units between the first metal network line and the second metal grid line, and the above third circuit units are signal lines or standard units. Among them, the above first metal grid line and the above second metal grid line are two adjacent metal grid lines in the first type of metal layers. For example, in the power network, the above first metal grid line and second metal grid line can be the VDD (power supply terminal) line and the VSS (ground terminal) line respectively.

[0042] Furthermore, determine the pitch between the first metal grid line and the second metal grid line, and determine the pitch between the first metal grid line and each of the third circuit units, and screen out the target pitch among the determined multiple pitches. According to the requirements of the actual scenario, various methods can be used to flexibly determine the target pitch. Exemplarily, the smallest pitch among the multiple pitches can be determined as the target pitch, or the average value of the multiple pitches can be calculated as the target pitch. Subsequently, determine the etching value matching the first metal grid line according to the target pitch, and use the etching value to extract the resistance information of the first metal grid line. Among them, the above etching value is determined by looking up the non-linear look-up table of the process file. The target pitch corresponds to a unique etching value. Therefore, only by determining the target pitch can the etching value matching the first metal grid line be determined, and the resistance information of the first metal grid line can be determined according to the above etching value.

[0043] Among them, when determining the spacing between the first metal grid line and each third circuit unit, the distance between the adjacent surfaces of the two metal grid lines can be selected, or the distance between the central axes of the two metal grid lines can be selected. Exemplarily, by calculating the distance between the adjacent surfaces, the spacing between the first metal grid line and each third circuit unit is determined. Specifically, for any third circuit unit, the adjacent first adjacent surface and second adjacent surface are determined on the first metal network line and the third circuit unit respectively, and the distance between the first adjacent surface and the second adjacent surface is determined as the spacing between the first metal grid line and the third circuit unit.

[0044] Type two: Extract the resistance information for the second type of metal layer.

[0045] Similarly, the second type of metal layer is also divided into multiple local cutting regions. For the third metal grid line in the second type of metal layer for which the resistance information is to be extracted, the local cutting region where the third metal grid line is located is identified. The local cutting region includes the fourth metal grid line adjacent to the third metal grid line. Among them, the above-mentioned third metal grid line and the above-mentioned fourth metal grid line are two adjacent metal grid lines within the current local cutting region.

[0046] Furthermore, the spacing between the third metal grid line and the fourth metal grid line is determined. Since the second type of metal layer does not contain the graphic information of the signal line and the graphic information of the standard cell, that is, the spacing between the third metal grid line and other circuit units is not considered. Subsequently, the etching value matching the third metal grid line is determined according to the spacing between the third metal grid line and the fourth metal grid line, and the resistance information of the third metal grid line is extracted by using the etching value. Among them, the above-mentioned etching value is determined in the same way as in type one, and is determined by looking up the non-linear look-up table of the process file. The resistance information of the first metal grid line can be determined according to the above-mentioned etching value.

[0047] It should be noted that in the above type one, if there are multiple second adjacent surfaces adjacent to the first adjacent surface on the third circuit unit, the distances between the first adjacent surface and each second adjacent surface are determined in sequence, and the determined multiple distances are used as the multiple spacings between the first metal grid line and the third circuit unit, so as to avoid the problem of inaccurate resistance information caused by ignoring the closest spacing.

[0048] In view of this, in one or more of the above embodiments, each metal layer of the circuit network is divided into two different types of metal layers. One type of metal layer can retain the image information of signal lines and standard cells, thereby improving the accuracy of resistance extraction. The other type of metal layer removes the image information of signal lines and standard cells, thereby ensuring the efficiency of resistance extraction while improving the resistance accuracy. Based on the layout information after retention and deletion, the resistance information of each metal layer in the circuit network can be extracted.

[0049] Please refer to Figure 2 and Figure 3 , this application also provides one or more embodiments to implement a method for extracting resistance information provided in the first aspect above.

[0050] In one embodiment, please refer to Figure 2 , Figure 2 is a schematic diagram of a partial cutting area of the first type of metal layer. As can be seen from Figure 2 , the dotted area is the current partial cutting area, and the graphics of signal lines and standard cells are retained in the partial cutting area. Among them, the VDD line is the first metal network line, the VSS line is the second metal network line adjacent to the first metal network line in the current partial cutting area, Length1 represents the length of the first metal network line in the partial cutting area, W1 represents the width of the first metal network line, Spacing1 represents the spacing between the first metal network line and the second metal network line, Spacing2 represents the spacing between the first metal network line and the nearest standard cell graphic to the first metal network line, and Spacing3 represents the spacing between the first metal network line and the nearest signal line graphic to the first metal network line.

[0051] In this embodiment, a spacing is determined as the target spacing among the above Spacing1, Spacing2, and Spacing3, and the etching value ETCH corresponding to the above target spacing is found in the non-linear look-up table of the process file 1 , so as to determine the etching width W 1 , and the resistance value R can be obtained according to 1 .

[0052] In one implementation manner of this embodiment, the smallest spacing among the above multiple spacings is selected as the target spacing.

[0053] In another implementation manner of this embodiment, the average value of the above multiple spacings is used as the target spacing.

[0054] In another embodiment, please refer to Figure 3 , Figure 3 is a schematic diagram of a partial cutting area of the second type of metal layer. As can be seen from Figure 3It can be known that the local cutting area of the above-mentioned second metal layer does not include the patterns of signal lines and standard cells. Among them, the VDD line is the third metal network line, the VSS line is the fourth metal network line adjacent to the third metal network line in the current local cutting area, Length2 represents the length of the third metal network line in the current local cutting area, W2 represents the width of the third metal network line, and Spacing4 represents the spacing between the third metal network line and the fourth metal network line. In this embodiment, the above-mentioned spacing Spacing4 is determined as the target spacing. Search for the etching value ETCH corresponding to the above-mentioned target spacing in the non-linear look-up table of the process file. 2 , so as to determine the etching width W 2 , and the resistance value R can be obtained according to 2 .

[0055] In a second aspect, please refer to Figure 4 , one or more embodiments of the present application also provide a method for extracting resistance information, and the method is carried out according to the following steps: S31: Obtain the original layout information of the target metal layer currently input.

[0056] S33: Based on the original layout information, determine whether to retain the graphic information of the signal lines and standard cells in the original layout information, and generate the updated layout information of the target metal layer based on the judgment result.

[0057] S35: Extract the resistance information of the target metal layer according to the updated layout information.

[0058] The above-mentioned target metal layer is a single metal layer input in the circuit network, which may be a high-level metal layer or a low-level metal layer. In response to the selection instruction input by the user, determine the target metal layer that needs to perform resistance extraction currently, and obtain the original layout information of the target metal layer currently input. The above-mentioned original layout information may include the layer identification and size information of the current target metal layer, and the above-mentioned size information may include the line width of the metal grid line of the current target metal layer, the metal area density, and the spacing of the metal grid line. In addition, the above-mentioned original layout information also includes the graphic information of signal lines and standard cells.

[0059] In one embodiment, based on the above step S33, determining whether to retain the graphic information of the signal lines and standard cells in the original layout information may include the following two methods: Method 1: Identify the layer identification carried in the original layout information. If the layer identification is within the specified layer identification set, it is determined to retain the graphic information of the signal lines and standard cells in the original layout information.

[0060] Specifically, it is determined whether the layer identifier of the current target metal layer is located in the specified set of layer identifiers. The above-mentioned specified set of layer identifiers is a set of layer identifiers of metal layers that need to retain signal lines and standard cells, which is preset. Preferably, the metal layer located at a higher layer, that is, the metal layer with a larger line width for power distribution, is determined as the metal layer that needs to retain signal lines and standard cells. Therefore, when it is recognized that the layer identifier of the current target metal layer belongs to the specified set of layer identifiers, the graphic information of the signal lines and standard cells of the current metal layer is retained. If the layer identifier of the current target metal layer does not belong to the specified set of layer identifiers, the graphic information of the signal lines and standard cells of the current metal layer is deleted.

[0061] Method 2: Identify the dimension description information in the original layout information. If the dimension description information meets the preset conditions, it is determined to retain the graphic information of the signal lines and standard cells in the original layout information. Among them, the above-mentioned dimension description information is used to characterize at least one of the line width of the metal grid lines in the target metal layer, the spacing between adjacent metal grid lines, and the metal area density of the target metal layer.

[0062] Specifically, it is determined whether the dimension description information of the current target metal layer meets the preset conditions, such as whether it is less than the preset line width, or whether the spacing between adjacent metal grid lines is less than the preset spacing, or whether the metal area density of the target metal layer is greater than the preset density. If at least one of the above conditions is met, the graphic information of the signal lines and standard cells in the original layout information of the current target metal layer is retained. If none of the above preset conditions are met, the signal lines and standard cell graphics of the current target metal layer are deleted.

[0063] In one or more embodiments, based on the above steps S33 and S35, updated layout information of the target metal layer is generated based on the judgment result, and according to the updated layout information, the resistance information of the target metal layer is extracted as follows: In one embodiment, if it is determined to retain the graphic information of the signal lines and standard cells in the original layout information, the original layout information is determined as the updated layout information of the target metal layer, and the resistance information of the target metal layer is extracted according to the above updated layout information. Among them, the above updated layout information includes the dimension description information of the target metal layer and the graphic information of the signal lines and standard cells of the target metal layer. Specifically, for the first metal grid line in the target metal layer for which the resistance information needs to be extracted, the local cutting area where the first metal grid line is located is identified. The above local cutting area includes a second metal grid line adjacent to the first metal grid line. Among them, there are one or more third circuit units between the first metal grid line and the second metal grid line, and the above third circuit unit is a signal line or a standard cell.

[0064] Further, obtain the spacing between the first metal grid line and the second metal grid line, as well as the spacing between the first metal grid line and each third circuit unit, determine a target spacing among the above-mentioned multiple spacings, determine an etching value matching the first metal grid line according to the target spacing, and extract the resistance information of the first metal grid line by using the etching value. Among them, the determination method of the target spacing and the method of determining the resistance information by the etching value are the same as those in the implementation manner described in the first aspect of the present application above, and will not be elaborated here.

[0065] In this embodiment, determining to retain the graphic information of the signal line and the standard cell in the first layout information can improve the accuracy of the extracted resistance of the current metal layer. The metal width of the current metal layer is small, and the metal etching width obtained by etching is greatly affected by the etching value. Determining the original layout information as the updated layout information of the target metal layer and considering the graphic information of the metal grid line and the signal line or the standard cell when calculating the spacing can make the target spacing more accurate, so as to obtain a more accurate etching value, and further ensure the accuracy of the metal etching width, so as to extract more accurate resistance information.

[0066] In another embodiment, if it is determined to delete the graphic information of the signal line and the standard cell in the original layout information, determine the original layout information after deleting the graphic information of the signal line and the standard cell as the updated layout information of the target metal layer, and extract the resistance information of the target metal layer according to the above updated layout information, where the above updated layout information includes the size description information of the target metal layer. Specifically, for the third metal grid line in the target metal layer for which the resistance information is to be extracted, identify the fourth metal grid line adjacent to the third metal grid line in the local cutting area where the third metal grid line is located, determine the spacing between the third metal grid line and the fourth metal grid line as the target spacing, determine an etching value matching the third metal grid line according to the target spacing, and extract the resistance information of the third metal grid line by using the etching value.

[0067] In this embodiment, deleting the graphic information of the signal line and the standard cell in the original layout information can ensure the performance of the resistance calculation process while improving the accuracy of the extracted resistance. The metal width of the target metal layer is large, and the influence of the etching value on the line width is small, and the loss of the resistance accuracy is small. Therefore, determining the original layout information after deleting the graphic information of the signal line and the standard cell as the updated layout information of the target metal layer and using the distance between adjacent metal grid lines in the updated layout information as the target spacing can avoid processing the graphic information of the signal line and the standard cell, and can improve the resistance extraction efficiency and the resistance extraction performance.

[0068] In view of this, in one or more of the above embodiments, it is determined whether the layout information of a single metal layer needs to delete the graphic information of signal lines and standard cells, and retention or deletion processing actions are performed according to the determination result. Based on the layout information after retention and deletion processing, the resistance information of the current target metal layer is extracted. Through the above one or more embodiments, the resistance extraction method for a single metal layer can be determined to improve the resistance extraction accuracy and performance of a single metal layer.

[0069] Exemplarily, please refer to Figure 5 , a circuit network with four metal layers provided in this application is a scenario example adopting the above resistance information extraction method. The layer identifiers of its metal layers are Metal1, Metal2, Metal3, and Metal4 respectively. Among them, Metal1 and Metal2 are lower-layer metal layers closer to the silicon substrate, usually used for local interconnection and signal transmission over shorter distances. Metal3 and Metal4 are upper-layer metal layers, often used for power distribution and input / output connections.

[0070] When performing resistance extraction, the graphic information of signal lines and standard cells of Metal1 and Metal2 metal layers is retained, while the graphic information of signal lines and standard cells of Metal3 and Metal4 metal layers is deleted. In view of this, the resistance extraction process will increase the graphic information by 10%, and its processing time will increase by 10%. While improving the resistance extraction accuracy, it will not cause too much loss to the resistance extraction performance. However, if the graphic information of signal lines and standard cells of all metal layers is processed, it will lead to a more complex and slow resistance calculation process, and the resistance extraction performance will be reduced by 40%, which cannot meet the actual usage requirements. Therefore, only the graphic information of signal lines and standard cells of the lower-layer metal layers used for signal transmission is retained to improve the resistance extraction accuracy while ensuring the resistance extraction performance.

[0071] The above is only a scenario example provided in the specification and does not limit the present invention. Any modifications, equivalent replacements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0072] Based on the above idea, the technical solutions provided in one or more embodiments of this application classify metal layers and calculate resistances in different ways. One way is to retain the graphic information of signal lines and standard cells of the metal layer to determine a more accurate target pitch, thereby improving the resistance extraction accuracy. Another way is to ignore the graphic information of signal lines and standard cells of the metal layer, which can avoid too long information processing time during resistance extraction to ensure the efficiency and performance of resistance extraction while improving the resistance extraction accuracy.

[0073] In the third aspect, please refer toFigure 6 , this application also provides a device for extracting resistance information. The device includes: a layout information acquisition unit 100, configured to acquire the layout information of each metal layer in a circuit network; an information determination unit 200, configured to determine the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the layout information; an information processing unit 300, configured to retain the graphic information of signal lines and standard cells in the first layout information, and delete the graphic information of signal lines and standard cells in the second layout information; a resistance extraction unit 400, configured to extract the resistance information of each metal layer in the circuit network based on the processed first layout information and the processed second layout information.

[0074] Wherein, in one embodiment, the layout information acquisition unit 100 is specifically configured to acquire the layout information of each metal layer in the circuit network. The above layout information includes the layer identifier, size information, and graphic information of signal lines and standard cells of each metal layer, and determines the resistance extraction method of each metal layer according to the above layout information.

[0075] In one embodiment, the information determination unit 200 is specifically configured to determine the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the above layout information. The above first type of metal layer is usually in the lower layer of the circuit network, and it is necessary to retain the graphic information of signal lines and standard cells to determine a more accurate target pitch. The above second type of metal layer is usually in the higher layer of the circuit network and is used for power distribution, and it is not necessary to retain the graphic information of signal lines and standard cells.

[0076] In one embodiment, the information processing unit 300 is specifically configured to retain the graphic information of signal lines and standard cells in the first layout information of the first type of metal layer, and delete the graphic information of signal lines and standard cells in the second layout information of the second type of metal layer, so that in the above second layout information.

[0077] In one embodiment, the resistance extraction unit 400 is specifically configured to obtain the target pitch of the metal grid lines of each metal layer based on the processed first layout information and the processed second layout information, determine the etching value matching the metal grid lines according to the above target pitch, and use the above etching value to extract the resistance information of the metal grid lines.

[0078] The further function descriptions of the above-mentioned modules and units are the same as those in the corresponding method embodiments described above, and will not be elaborated here.

[0079] The extraction device for resistance information in the embodiments of the present application is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, or other devices that can provide the above functions.

[0080] In a fourth aspect, please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a computer device provided by an embodiment of the present application. As Figure 7 shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (such as an array of servers, a set of blade servers, or a multi-processor system). Figure 7 In

[0081] FIG. 10, a processor 10 is taken as an example.

[0082] The processor 10 may be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 may further include a hardware chip. The above hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The above programmable logic device may be a complex programmable logic device, a field programmable gate array, a general array logic, or any combination thereof.

[0083] The memory 20 may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required for at least one function. The data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely disposed relative to the processor 10, and these remote memories may be connected to the computer device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0084] The memory 20 may include a volatile memory, such as a random access memory. The memory may also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive. The memory 20 may further include a combination of the above types of memories.

[0085] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0086] The embodiments of the present application also provide a computer-readable storage medium. The methods according to the embodiments of the present application may be implemented in hardware, firmware, or may be implemented as computer code that can be recorded on a storage medium, or may be implemented as computer code originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and to be stored in a local storage medium, so that the methods described herein can be processed by such software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc. Further, the storage medium may further include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0087] The devices or units illustrated in the above embodiments may be specifically implemented by a computer chip or an entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0088] For the convenience of description, when describing the above device, it is divided into various units according to functions and described separately. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0089] Those skilled in the art should understand that the embodiments of the present application can be provided as a method or a device. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0090] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices, and equipment according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or a plurality of flows and / or blocks

[0091] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the functions specified in Figure 1 one or more of the flows Figure 1 or a plurality of flows and / or blocks

[0092] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or a plurality of flows and / or blocks

[0093] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, commodity or device comprising said element.

[0094] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the relevant part of the method embodiment for the related content.

[0095] The above description is only for the embodiments of the present application and is not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0096] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for extracting resistance information, characterized in that: The method comprises: Obtain layout information of each metal layer in the circuit network; Determining first layout information of the first type of metal layer and second layout information of the second type of metal layer in the layout information; retaining the graphic information of the signal lines and the standard cells in the first layout information, and deleting the graphic information of the signal lines and the standard cells in the second layout information; Based on the processed first layout information and the processed second layout information, resistance information of each metal layer in the circuit network is extracted.

2. The method according to claim 1, characterized in that Determining the first layout information of the first type of metal layer and the second layout information of the second type of metal layer in the layout information includes: In response to the input selection instruction, determine a first type of metal layer and a second type of metal layer in each metal layer of the circuit network, and obtain first layout information of the first type of metal layer and second layout information of the second type of metal layer in the layout information; or Identify the layer identifier of each of the metal layers, determine the metal layers with the specified layer identifier in the circuit network as the first type of metal layers, and determine the other metal layers in the circuit network except the first type of metal layers as the second type of metal layers, and obtain first layout information of the first type of metal layers and second layout information of the second type of metal layers in the layout information; or Identify the size description information of each of the metal layers, and determine the metal layer whose size description information meets preset conditions as a first type of metal layer, and determine the other metal layers in the circuit network except the first type of metal layer as a second type of metal layer, and obtain the first layout information of the first type of metal layer and the second layout information of the second type of metal layer from the layout information, wherein the size description information is used to characterize at least one of the line width of the metal grid lines in the metal layer, the spacing between adjacent metal grid lines, and the metal area density of the metal layer.

3. The method according to claim 1 or 2, characterized in that: Extracting resistance information of each metal layer in the circuit network includes: For a first metal grid line in the first type of metal layer whose resistance information is to be extracted, a local cutting area where the first metal grid line is located is identified, wherein the local cutting area includes a second metal grid line adjacent to the first metal grid line, and one or more third circuit units are provided between the first metal grid line and the second metal grid line, and the third circuit unit is a signal line or a standard unit; Determine a spacing between the first metal grid line and the second metal grid line, and determine a spacing between the first metal grid line and each of the third circuit units, and select a target spacing from the determined multiple spacings; An etching value matching the first metal grid line is determined according to the target spacing, and resistance information of the first metal grid line is extracted using the etching value.

4. The method according to claim 3, characterized in that: Screening out a target spacing from the determined multiple spacings includes: determining the smallest spacing among the multiple spacings as the target spacing.

5. The method according to claim 3, characterized in that: Determining the spacing between the first metal grid lines and each of the third circuit units includes: For any third circuit unit, adjacent first adjacent surfaces and second adjacent surfaces are respectively determined on the first metal grid line and the third circuit unit, and the distance between the first adjacent surface and the second adjacent surface is determined as the spacing between the first metal grid line and the third circuit unit.

6. The method according to claim 5, characterized in that If there are a plurality of second adjacent surfaces adjacent to the first adjacent surface on the third circuit unit, the method further includes: The distances between the first adjacent surface and each of the second adjacent surfaces are determined in sequence, and the determined multiple distances are used as the spacings between the first metal grid line and the third circuit unit.

7. The method according to claim 1 or 2, characterized in that: Extracting resistance information of each metal layer in the circuit network includes: For a third metal grid line whose resistance information is to be extracted in the second type metal layer, identifying a local cutting area where the third metal grid line is located, wherein the local cutting area includes a fourth metal grid line adjacent to the third metal grid line; determining a spacing between the third metal grid line and the fourth metal grid line; An etching value matching the third metal grid line is determined according to the spacing, and resistance information of the third metal grid line is extracted using the etching value.

8. A method for extracting resistance information, characterized in that: The method comprises: Get the original layout information of the currently input target metal layer; Based on the original layout information, determining whether to retain the graphic information of the signal lines and the standard cells in the original layout information, and generating updated layout information of the target metal layer based on the determination result; The resistance information of the target metal layer is extracted according to the updated layout information.

9. The method according to claim 8, characterized in that Determining whether to retain the graphic information of the signal lines and standard cells in the original layout information includes: Identifying a layer identifier carried in the original layout information, and if the layer identifier is within a specified layer identifier set, determining to retain the graphic information of the signal line and the standard cell in the original layout information; or Identify size description information in the original layout information, and if the size description information meets a preset condition, determine to retain the graphic information of the signal lines and standard cells in the original layout information, wherein the size description information is used to characterize at least one of the line width of the metal grid lines in the target metal layer, the spacing between adjacent metal grid lines, and the metal area density of the target metal layer.

10. The method according to claim 8 or 9, characterized in that: Generating updated layout information of the target metal layer based on the judgment result includes: If it is determined that the graphic information of the signal lines and the standard cells in the original layout information is retained, the original layout information is determined as the updated layout information of the target metal layer; If it is determined to delete the graphic information of the signal lines and the standard cells in the original layout information, the original layout information after deleting the graphic information of the signal lines and the standard cells is determined as the updated layout information of the target metal layer.

11. The method according to claim 8, characterized in that Extracting the resistance information of the target metal layer according to the updated layout information includes: If the judgment result indicates that the graphic information of the signal line and the standard unit in the original layout information is retained, for the first metal grid line in the target metal layer, the local cutting area where the first metal grid line is located is identified, the local cutting area includes a second metal grid line adjacent to the first metal grid line, and one or more third circuit units are provided between the first metal grid line and the second metal grid line, and the third circuit unit is a signal line or a standard unit; Determine a spacing between the first metal grid line and the second metal grid line, and determine a spacing between the first metal grid line and each of the third circuit units, and select a target spacing from the determined multiple spacings; An etching value matching the first metal grid line is determined according to the target spacing, and resistance information of the first metal grid line is extracted using the etching value.

12. The method according to claim 8 or 11, characterized in that: Extracting the resistance information of the target metal layer according to the updated layout information includes: If the judgment result indicates that the graphic information of the signal line and the standard cell in the original layout information is deleted, for the third metal grid line in the target metal layer where the resistance information is to be extracted, identifying the local cutting area where the third metal grid line is located, wherein the local cutting area includes a fourth metal grid line adjacent to the third metal grid line; and determining the spacing between the third metal grid line and the fourth metal grid line; An etching value matching the third metal grid line is determined according to the spacing, and resistance information of the third metal grid line is extracted using the etching value.

13. A device for extracting resistance information, characterized in that: The device comprises: A layout information acquisition unit, used to acquire layout information of each metal layer in the circuit network; An information determining unit, configured to determine first layout information of the first type of metal layer and second layout information of the second type of metal layer in the layout information; an information processing unit, configured to retain the graphic information of the signal lines and the standard cells in the first layout information, and delete the graphic information of the signal lines and the standard cells in the second layout information; The resistance extraction unit is used to extract the resistance information of each metal layer in the circuit network based on the processed first layout information and the processed second layout information.

14. A computer device, characterized in that: The computer device includes a memory and a processor, the memory is used to store a computer program, and when the computer program is executed by the processor, the method for extracting resistance information as described in any one of claims 1 to 7 or 8 to 12 is implemented.

Images