Drive circuits, memory devices and their operation methods

Abstract

A driving circuit, a memory device, and a method of operating the same are disclosed. The driving circuit includes a control unit, a switching unit, and a sampling unit. The control unit is connected to a first voltage source and a second voltage source, receives a first control signal from the first voltage source, receives a second control signal from the second voltage source, and is turned on or off according to the first control signal; when on, it applies the second control signal to a first node. The switching unit is connected to the control unit, a third voltage source, and an output terminal, and is turned on or off according to the voltage level of the first node; when the voltage level of the first node is the second control signal, it is turned on to apply a first operating voltage received from the third voltage source to the output terminal. The sampling unit is connected to the output terminal, the third voltage source, and the switching unit, and is turned on or off according to the feedback voltage of the output terminal; when on, it applies the first operating voltage to the first node, such that the switching unit is turned off when the voltage level of the first node is the first operating voltage. This driving circuit reduces power consumption.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a driving circuit, a memory device, and a method of operating the same. Background Technology

[0002] Resistive Random Access Memory (RRAM) is a non-volatile device whose conductance can be adjusted by applying an external stimulus. It can record and store data based on changes in resistance, and features high speed, low power consumption, and small size. RRAM has promising applications in artificial intelligence, neural networks, and memory, and is increasingly attracting attention from academia and industry. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a driving circuit comprising: a control unit, a switching unit, and a sampling unit. The control unit is connected to a first voltage source and a second voltage source and is configured to receive a first control signal from the first voltage source, receive a second control signal from the second voltage source, and turn on or off according to the first control signal, applying the second control signal to a first node when on. The switching unit is connected to the control unit, a third voltage source, and an output terminal and is configured to turn on or off according to the level of the first node, and turn on when the level of the first node is the second control signal to apply a first operating voltage received from the third voltage source to the output terminal. The sampling unit is connected to the output terminal, the third voltage source, and the switching unit and is configured to turn on or off according to a feedback voltage of the output terminal, and apply the first operating voltage to the first node when on, such that the switching unit is off when the level of the first node is the first operating voltage.

[0004] For example, in the driving circuit provided in at least one embodiment of this disclosure, the control unit includes a first transistor, the control electrode of the first transistor is connected to the first voltage source, the first electrode of the first transistor is connected to the second voltage source, and the second electrode of the first transistor is connected to the first node; the switching unit includes a second transistor, the control electrode of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the third voltage source, and the second electrode of the second transistor is connected to the output terminal; the sampling unit includes a third transistor, the control electrode of the third transistor is connected to the output terminal, the first electrode of the third transistor is connected to the third voltage source, and the second electrode of the third transistor is connected to the first node.

[0005] For example, in the driving circuit provided in at least one embodiment of this disclosure, the first transistor, the second transistor, and the third transistor are P-type transistors.

[0006] At least one embodiment of this disclosure also provides a memory device, the memory device comprising: a driving circuit according to any embodiment of this disclosure; a resistive switching memory device, wherein a first terminal of the resistive switching memory device is connected to the output terminal of the driving circuit, and a second terminal of the resistive switching memory device is connected to a fourth voltage source.

[0007] At least one embodiment of this disclosure also provides a method for operating a memory device, the method comprising: receiving a first control signal from a first voltage source and a second control signal from a second voltage source via a control unit; turning on the control unit according to the first control signal and applying the second control signal to a first node to turn on the switching unit; receiving a first operating voltage from a third voltage source via the switching unit and applying the first operating voltage to the resistive switching memory device connected to the output terminal when the switching unit is turned on; turning on the sampling unit according to the feedback voltage of the output terminal and applying the first operating voltage to the first node to turn off the switching unit.

[0008] For example, in an operating method provided in at least one embodiment of this disclosure, the first operating voltage includes an initialization voltage or a set voltage for the resistive switching memory device.

[0009] For example, at least one embodiment of the present disclosure provides an operating method that further includes: changing the resistance value of the resistive switching memory device according to the first operating voltage.

[0010] For example, in the operation method provided in at least one embodiment of this disclosure, the feedback voltage changes in response to the change in the resistance value of the resistive switching memory device. When the resistance value of the resistive switching memory device reaches the target resistance value, the feedback voltage reaches a first threshold voltage to turn on the sampling unit.

[0011] For example, at least one embodiment of the present disclosure provides an operating method that further includes: determining the magnitude of the current-limiting voltage of the second control signal based on the target resistance value of the resistive switching memory device.

[0012] At least one embodiment of this disclosure also provides a memory device, the memory device comprising: a memory array including multiple rows and columns of memory cells arranged in multiple rows and columns, word lines corresponding to each row in the memory array, bit lines corresponding to each row in the memory array, and source lines corresponding to each column in the memory array, wherein each memory cell includes a transistor and a resistive switching memory device, the gate of the transistor is connected to the word line corresponding to the row where the memory cell is located, the first terminal of the transistor is connected to the source line corresponding to the column where the memory cell is located, the second terminal of the transistor is connected to a first terminal of the resistive switching memory device, and the second terminal of the resistive switching memory device is connected to the bit line corresponding to the row where the memory cell is located; and at least one driving circuit according to any of the present disclosure, each driving circuit being coupled to one of the bit lines of the memory array. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0014] Figure 1 This is a schematic diagram of the structure of an exemplary resistive switching memory device provided in at least one embodiment of the present disclosure;

[0015] Figure 2 A schematic diagram of the structure of an exemplary storage unit provided in at least one embodiment of this disclosure;

[0016] Figure 3 A schematic block diagram of a driving circuit provided for at least one embodiment of this disclosure;

[0017] Figure 4 A schematic diagram of an exemplary driving circuit provided for at least one embodiment of this disclosure;

[0018] Figure 5 A schematic diagram of a memory device provided for at least one embodiment of this disclosure; and

[0019] Figure 6 This is a schematic diagram of a memory device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0021] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0022] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, that component is represented by the same or similar reference numerals in each drawing.

[0023] Resistive random access memory (RRAM) devices are considered a promising new type of non-volatile memory due to their fast read / write speed, simple structure, and good compatibility with CMOS technology. They have been widely used in fields such as information storage, logic operations, and neural network computing.

[0024] Figure 1 A schematic diagram of an exemplary resistive switching memory device is shown. (As shown) Figure 1As shown, the resistive switching memory device R1 includes a resistive switching layer 111 and an upper electrode 113 and a lower electrode 114 located on both sides. In at least one example, it may also include a functional layer 112. The functional layer 112 is an optional layer, and its addition or omission can be determined according to the optimization direction of the performance of the resistive switching memory device R1, and it can be designed accordingly. The resistive switching layer 111 can be a single layer, including a single type of binary metal oxide (e.g., NiO, AlOx, etc.), graphene oxide, multi-component perovskite oxide (e.g., STO, SZO, PCMO, etc.), or it can be a multilayer, such as any optional stack of the above materials, for example, a stack of TixN and AlOx.

[0025] Resistive switching memory (RSM) devices can store data based on their resistive switching characteristics. The resistive switching characteristics of an RSM device are related to a conductive filament. By applying a set or reset voltage between the upper and lower electrodes of the RSM device, the conductive filament inside the RSM device can be restored or broken. When the conductive filament is connected, the RSM device exhibits a low resistance state (LRS), in which case it can be used to store data such as 0. When the conductive filament is broken, the RSM device exhibits a high resistance state (HRS), in which case it can be used to store data such as 1.

[0026] For example, after forming a conductive filament inside the resistive random access memory (R1), R1 has an operating threshold voltage. When the amplitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of R1 is less than the operating threshold voltage, the resistance (or conductance) of R1 will not change. In this case, the current stored value of the R1 can be read by applying a read voltage. The current stored value of the R1 can be, for example, the resistance value of the R1. The read voltage is less than the operating threshold voltage of the R1.

[0027] When the amplitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive random access memory (RRAM) device R1 is greater than the operating threshold voltage of RRAM device R1, the resistance (or conductance) value of RRAM device R1 can be changed according to the set voltage or reset voltage applied between the upper electrode 113 and the lower electrode 114 of RRAM device R1. For example, the set voltage is a positive voltage pulse, and the reset voltage is a negative voltage pulse. In the embodiments of this disclosure, applying a set voltage to the RRAM device is called a set operation, and applying a reset voltage to the RRAM device is called a reset operation. One set operation or reset operation can be regarded as one write operation.

[0028] The following is combined Figure 2 The structure of the storage unit and the write operation are described in detail.

[0029] Figure 2 A schematic diagram of an exemplary memory cell is shown. The memory cell includes a transistor M1 and a resistive random access memory (R1). For example, when transistor M1 is an N-type transistor, its gate is connected to the word line WL; for example, transistor M1 is turned on when the word line WL is high. The first terminal of transistor M1 can be the source and is configured to be connected to the source line SL; for example, transistor M1 can receive a reset voltage through the source line SL. The second terminal of transistor M1 can be the drain and is configured to be connected to the second terminal (e.g., the negative terminal) of the resistive random access memory (R1). The first terminal (e.g., the positive terminal) of the resistive random access memory (R1) is connected to the bit line BL; for example, the resistive random access memory (R1) can receive a set voltage through the bit line BL. For example, when transistor M1 is a P-type transistor, its gate is connected to the word line WL. For instance, transistor M1 is turned on when the word line WL inputs a low level. The first terminal of transistor M1 can be the source and is configured to be connected to the source line SL. For instance, transistor M1 can receive a reset voltage through the source line SL. The second terminal of transistor M1 can be the drain and is configured to be connected to the second terminal (e.g., the negative terminal) of resistive random access memory device R1. The first terminal (e.g., the positive terminal) of resistive random access memory device R1 is connected to the bit line BL. For instance, resistive random access memory device R1 can receive a set voltage through the bit line BL. It should be noted that the structure of the memory cell can also be implemented in other ways, such as the structure where the second terminal of resistive random access memory device R1 is connected to the source line SL. The embodiments disclosed herein do not limit this.

[0030] Taking an N-type transistor as an example, the word line WL applies a voltage to the gate of transistor M1, thereby controlling its on or off state. When performing a write operation on the resistive random access memory (R1), such as a set or reset operation, transistor M1 must first be turned on; that is, a turn-on voltage must be applied to the gate of transistor M1 via the word line WL. After transistor M1 is turned on, for example, voltages can be applied to the R1 via the source line SL and the bit line BL to change its resistance state. For example, a set voltage can be applied via the bit line BL to put R1 in a low-resistance state; or a reset voltage can be applied via the source line SL to put R1 in a high-resistance state. For example, the resistance value of the high-resistance state may be more than one hundred times, or even more than one thousand times, the resistance value of the low-resistance state.

[0031] The embodiments of this disclosure do not limit the type or structure of the memory cells. The structure of the memory cells can be 1T1R (including one transistor and one resistive switching memory device), 2T2R (including two transistors and two resistive switching memory devices), or other possible structures. It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors or field-effect transistors (e.g., MOS field-effect transistors) or other switching devices with the same characteristics. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. The embodiments of this disclosure do not limit the type of transistors used.

[0032] Because resistive random access memory (IRRAM) devices do not have conductive filaments inside when they are fabricated, they require an additional initialization process to achieve resistive switching characteristics, unlike other types of memory devices. The initialization process involves applying a high voltage pulse across the terminals of the IRRAM device, inducing the formation of conductive filaments inside. Once these conductive filaments are formed, the IRRAM device can become low-resistance under a set voltage or high-resistance under a reset voltage.

[0033] Initialization is typically performed only once during the lifecycle of a resistive random access memory (IRRAM) device. However, because initialization requires applying a very high voltage pulse (usually greater than the set and reset voltages), and because IRRAM devices vary considerably when first manufactured, the pulse time required for initialization differs for each device. Applying the same pulse voltage for each IRRAM device could lead to initialization failures for some, impacting memory cell performance. Therefore, after initialization, multiple verification operations are usually performed to confirm successful initialization of the IRRAM device.

[0034] Verification involves obtaining the resistance value of a variable resistor-retaining memory (VRAM) device after applying an initialization voltage and checking whether the resistance value has reached the target value. For example, in the current initialization process, an initialization voltage pulse of preset duration and amplitude is applied to a VRAM device. Then, a read voltage is applied to read the current resistance value. If the current resistance value does not reach the target value, the VRAM device has not yet completed initialization. The amplitude of the initialization voltage pulse or the pulse duration applied to the VRAM device needs to be changed, and the initialization and verification operations are repeated until the VRAM device is successfully initialized. After initializing one VRAM device, the above operation is repeated for the next VRAM device until all VRAM devices are successfully initialized. However, multiple verifications make the initialization process very time-consuming, significantly increasing production and testing time costs.

[0035] An effective solution to the above problem is parallel initialization. Parallel initialization refers to simultaneously applying the same initialization voltage pulse to multiple resistive random access memory (IRRAM) devices in a row. The duration of this initialization voltage pulse is set long enough to allow any one IRRAM device to complete initialization. In other words, parallel initialization shortens the total initialization time of multiple IRRAM devices by extending the time of a single initialization operation. However, parallel initialization cannot account for the inherent differences between the IRRAM devices, and the large current introduced by parallel initialization also presents new challenges to circuit design.

[0036] On the one hand, excessive current on the bus can lead to a severe voltage drop (IR Drop) problem, thus limiting the number of resistive random access memory (IRRAM) devices that can be initialized in parallel. Here, voltage drop refers to the voltage difference V = I*R between the near and far ends of a long wire when a large current flows through it due to the wire's resistance. This voltage drop problem causes the IRRAM devices at the far end of the bus to receive a voltage much lower than the preset initialization voltage. For example, since word lines in a memory array are often very long (on the order of millimeters), if the initialization current of each column is tens of microamps, then when a thousand columns are initialized simultaneously, the current on the bus will reach tens of milliamps, resulting in a very large voltage drop. This voltage drop prevents the IRRAM devices at the far end of the bus from receiving a sufficiently high initialization voltage, thus preventing them from being successfully initialized. Therefore, the number of columns in the memory array must be limited to a certain range.

[0037] On the other hand, parallel initialization can also degrade the performance of resistive random access memory (IRRAM) devices. During parallel initialization, to ensure that all IRRAM devices in a row are successfully initialized, the pulse duration of the initialization voltage needs to be set to a relatively long duration to provide sufficient margin. However, during the duration of the initialization voltage pulse, current continuously flows through the IRRAM devices. Even with current-limiting protection measures, applying a high voltage to the IRRAM devices for an extended period can lead to poor consistency or over-initialization. Therefore, the performance of IRRAM devices initialized in parallel is often inferior to that initialized sequentially. Furthermore, prolonged high current on the bus also increases power consumption.

[0038] This disclosure provides at least one embodiment of a driving circuit, a memory device, and a method for operating the same. The driving circuit includes a control unit, a switching unit, and a sampling unit. The control unit is connected to a first voltage source and a second voltage source and is configured to receive a first control signal from the first voltage source, receive a second control signal from the second voltage source, and turn on or off according to the first control signal. When on, the second control signal is applied to a first node. The switching unit is connected to the control unit, a third voltage source, and an output terminal and is configured to turn on or off according to the level of the first node. When the level of the first node is the second control signal, the switching unit turns on to apply a first operating voltage received from the third voltage source to the output terminal. The sampling unit is connected to the output terminal, the third voltage source, and the switching unit and is configured to turn on or off according to a feedback voltage at the output terminal. When on, the sampling unit applies the first operating voltage to the first node, such that the switching unit turns off when the level of the first node is the first operating voltage.

[0039] The driving circuit provided in the above embodiments of this disclosure can limit the voltage value of the output terminal according to the second control signal of the control unit, and automatically turn off the switching unit according to the feedback voltage of the output terminal through the sampling unit, thereby effectively controlling the voltage of the output terminal, realizing the self-stop driving function, and reducing power consumption.

[0040] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0041] Figure 3 This is a schematic block diagram of a driving circuit provided for at least one embodiment of the present disclosure. For example... Figure 3 As shown, the driving circuit 10 provided in at least one embodiment of this disclosure includes a control unit, a switching unit, and a sampling unit.

[0042] The control unit is connected to a first voltage source U1 and a second voltage source U2, and is configured to receive a first control signal FORM from the first voltage source U1 and a second control signal VFORM_I from the second voltage source U2. When the first control signal FORM is turned on or off, the control unit applies the second control signal VFORM_I to the first node V1. That is, the first control signal FORM is used to turn the control unit on or off, and the second control signal VFORM_I is used to turn the switching unit on or off.

[0043] The switching unit is connected to the control unit, the third voltage source U3 and the output terminal OUT, and is configured to be turned on or off according to the level of the first node V1, and to be turned on when the level of the first node V1 is the second control signal VFORM_I so as to apply the first operating voltage VFORM received from the third voltage source U3 to the output terminal OUT.

[0044] The second control signal VFORM_I and the first operating voltage VFORM can jointly regulate the voltage at the output terminal OUT. For example, the output terminal OUT is connected to a load. When the switching unit is turned on, the first operating voltage VFORM is provided to the load, which may be a voltage-modulated device, including but not limited to resistive switching memory devices. The second control signal VFORM_I is used to limit the voltage at the output terminal OUT to a threshold value, which may be, for example, a voltage value that just enables the load function.

[0045] The sampling unit is connected to the output terminal OUT, the third voltage source U3 and the switching unit, and is configured to turn on or off according to the feedback voltage VBL of the output terminal OUT. When it is on, the first operating voltage VFORM is applied to the first node V1, so that the switching unit is off when the level of the first node V1 is the first operating voltage VFORM.

[0046] When the drive circuit 10 is operating, a first control signal FORM is applied to the control unit to turn on the control unit. The control unit then applies the received second control signal VFORM_I to the switching unit to turn on the switching unit. After the switching unit turns on, it applies the first operating voltage VFORM to the output terminal OUT. Simultaneously, the sampling unit receives the feedback voltage VBL returned from the output terminal OUT and converts it into a signal to control the switching unit. When the feedback voltage VBL changes to the threshold voltage, the sampling unit causes the switching unit to turn off, thereby blocking the path between the first operating voltage VFORM and the output terminal, and automatically stopping the application of the drive voltage to the load at the output terminal.

[0047] Figure 4 This is a schematic diagram of an exemplary driving circuit provided for at least one embodiment of the present disclosure. For example... Figure 4As shown, in at least one embodiment of this disclosure, the control unit includes a first transistor T1, the control electrode (e.g., gate) of the first transistor T1 is connected to a first voltage source U1, the first electrode (e.g., source) of the first transistor T1 is connected to a second voltage source U2, and the second electrode (e.g., drain) of the first transistor T1 is connected to a first node V1.

[0048] For example, the switching unit includes a second transistor T2, the control electrode (e.g., gate) of the second transistor T2 is connected to the first node V1, the first electrode (e.g., source) of the second transistor T2 is connected to the third voltage source U3, and the second electrode (e.g., drain) of the second transistor T2 is connected to the output terminal OUT.

[0049] For example, the sampling unit includes a third transistor T3, the control electrode (e.g., gate) of the third transistor T3 is connected to the output terminal OUT, the first electrode (e.g., source) of the third transistor T3 is connected to the third voltage source U3, and the second electrode (e.g., drain) of the third transistor T3 is connected to the first node V1.

[0050] For example, in some embodiments of this disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors. For example, the first transistor T1, the second transistor T2, and the third transistor T3 can all be PMOS transistors.

[0051] For example, in some other embodiments of this disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors. For example, the first transistor T1, the second transistor T2, and the third transistor T3 may all be NMOS transistors.

[0052] For example, in some other embodiments of this disclosure, the functions of the control unit, switching unit, and sampling unit can also be implemented by other switching devices or circuit structures with the same characteristics as transistors. The embodiments of this disclosure do not limit the specific circuit elements and circuit structures in the control unit, switching unit, and sampling unit.

[0053] Figure 5 This is a schematic diagram of a memory device 100 provided for at least one embodiment of the present disclosure. Figure 5 As shown, at least one embodiment of the present disclosure provides a memory device 100 including a drive circuit 10 and a resistive switching memory device R1.

[0054] For example, the first terminal of the resistive variable storage device R1 is connected to the output terminal OUT of the drive circuit 10, and the second terminal of the resistive variable storage device R1 is connected to the fourth voltage source U4. For example, the fourth voltage source U4 is grounded.

[0055] For example, the driving circuit 10 can be used for a resistive random access memory (R1) in a high-resistance state, such as a freshly fabricated R1 without internal conductive filaments. For instance, the driving circuit 10 can switch the R1 from a high-resistance state to a low-resistance state and automatically shut down when the R1 reaches the expected low-resistance state, thus ceasing the supply of driving voltage. That is, when the R1 reaches the expected resistance state, the driving circuit 10 no longer supplies the first operating voltage VFORM to the R1, thereby effectively preventing over-initialization of the R1 and reducing power consumption to some extent.

[0056] At least one embodiment of this disclosure also provides a method for operating a memory device. The method includes: receiving a first control signal from a first voltage source and a second control signal from a second voltage source via a control unit; turning on the control unit according to the first control signal and applying the second control signal to a first node to turn on a switching unit; receiving a first operating voltage from a third voltage source via the switching unit and applying the first operating voltage to a resistive switching memory device connected to an output terminal when the switching unit is turned on; turning on a sampling unit according to a feedback voltage at the output terminal and applying the first operating voltage to the first node to turn off the switching unit.

[0057] For example, in some embodiments of this disclosure, the first operating voltage includes an initialization voltage for the resistive switching memory device.

[0058] For example, in some embodiments of this disclosure, the operation method further includes: changing the resistance value of the resistive switching memory device according to a first operating voltage.

[0059] For example, in some embodiments of this disclosure, the feedback voltage changes in response to a change in the resistance value of the resistive switching memory device. When the resistance value of the resistive switching memory device reaches a target resistance value, the feedback voltage reaches a first threshold voltage to turn on the sampling unit.

[0060] For example, in some embodiments of this disclosure, the method further includes: determining the magnitude of the current-limiting voltage of the second control signal based on the target resistance value of the resistive switching memory device.

[0061] The memory device and its operation method can control the initialization process of the resistive random access memory (RRAM). By limiting the minimum resistance that the RRAM can reach through the second control signal of the control unit, the initialization process of the RRAM is automatically stopped when the resistance of the RRAM reaches the minimum resistance, and the application of initialization voltage to the RRAM is stopped, thereby effectively preventing over-initialization of the RRAM and reducing power consumption.

[0062] The following is combined with Figure 5 The operating method is described in detail for the memory device 100 shown.

[0063] For example, in one example of the embodiments of the present disclosure, the resistive random access memory device R1 is initialized by a driving circuit 10 as shown in Figure 4 FIG. 1. The control unit, the switching unit, and the sampling unit in the driving circuit 10 are the first transistor T1, the second transistor T2, and the third transistor T3 of the P type, respectively.

[0064] First, the driving circuit 10 needs to be turned on. For example, a low-level pulse signal is applied to the first transistor T1 as a first control signal FORM to turn on the first transistor T1, so that a second control signal VFORM_I is provided to the second transistor T2. The level of the second control signal VFORM_I is less than the difference between the first operating voltage VFORM (for example, the initialization voltage) and the threshold voltage VGT3 of the second transistor T2, that is, VFORM_I < VFORM - VGT3. The magnitude of the current-limiting voltage of the second control signal VFORM_I can be determined according to the target resistance value of the resistive random access memory device R1. For example, if it is not desired that the resistance value of the resistive random access memory device R1 after initialization is too low, the current-limiting voltage of the second control signal VFORM_I can be set smaller, making the degree of turning on of the second transistor T2 smaller, thereby preventing the resistive random access memory device R1 from being over-initialized.

[0065] Since the resistance value of the original resistive random access memory device R1 is very large, the second transistor T2 is in the linear region, and can provide the first operating voltage VFORM to the resistive random access memory device R1 almost without loss, and makes the third transistor T3 in the off state.

[0066] As the first operating voltage VFORM is applied to the resistive random access memory device R1, the resistance value of the resistive random access memory device R1 gradually decreases. When the resistance value of the resistive random access memory device R1 decreases to the target resistance value, it indicates that the resistive random access memory device R1 has been successfully initialized. At this time, the first operating voltage VFORM does not need to be applied to the resistive random access memory device R1 anymore. Continuing to apply the first operating voltage VFORM may cause the resistance value of the resistive random access memory device R1 to be too low, resulting in over-initialization, which is not conducive to the performance of the resistive random access memory device.

[0067] In this case, the sampling unit in the driving circuit 10 starts to function. Since the resistance value of the resistive random access memory device R1 is low at this time, the current flowing through the second transistor T2 becomes high, and the feedback voltage VBL at the output terminal OUT decreases. When the feedback voltage VBL is less than the difference between the first operating voltage VFORM and the threshold voltage VGT2 of the third transistor (VBL < VFORM - VGT2), the third transistor T3 conducts. That is to say, the feedback voltage VBL can change corresponding to the change in the resistance value of the resistive random access memory device R1. When the resistance value of the resistive random access memory device R1 reaches the target resistance value, the feedback voltage VBL reaches the threshold to turn on the third transistor T3.

[0068] After the third transistor T3 conducts, the first operating voltage VFORM is transmitted to the first node V1, that is, the first operating voltage VFORM is transmitted to the gate of the second transistor T2, causing the second transistor T2 to quickly turn off, thereby shutting off the conduction path between the third voltage source U3 and the output terminal OUT, and stopping the continuous application of the first operating voltage VFORM to the resistive random access memory device R1.

[0069] After the second transistor T2 turns off, the output terminal OUT is floating, and the charge on the bit line (BL) where the resistive random access memory device R1 is located can be gradually discharged through the gate capacitance of the third transistor T3. Therefore, the bit line returns to a low level, and the initialization process of the resistive random access memory device R1 ends.

[0070] For example, in some embodiments of the present disclosure, the first transistor T1, the second transistor T, and the third transistor T3 can also be NMOS transistors, In this embodiment, the first transistor T1 conducts when the first control signal FORM is at a high level; the level of the second control signal VFORM_I should be greater than the difference between the first operating voltage VFORM and the threshold voltage VGT3 of the second transistor T2, that is, VFORM_I > VFORM - VGT3; when the feedback voltage VBL is greater than the difference between the first operating voltage VFORM and the threshold voltage VGT2 of the third transistor (VBL > VFORM - VGT2), the third transistor T3 conducts. The change processes of other operation steps and circuit elements other than the above differences are similar to those described above, and will not be elaborated here.

[0071] For example, in some embodiments of the present disclosure, the first operating voltage can also be the setting voltage for the resistive random access memory device. For example, this driving circuit can accurately control the resistance value of the resistive random access memory device during the write operation, so that the verification operation after the write operation can be omitted, reducing the time cost. The method of using the driving circuit for the setting operation of the resistive random access memory device can refer to the description of the initialization operation in the above embodiments, and will not be elaborated here.

[0072] At least one embodiment of this disclosure also provides a memory device. The memory device includes a memory array and at least one driving circuit. The memory array includes multiple rows and columns of memory cells arranged in multiple rows and columns, word lines corresponding to each row in the memory array, bit lines corresponding to each row in the memory array, and source lines corresponding to each column in the memory array. Each memory cell includes a transistor and a resistive switching memory device (RSM). The gate of the transistor is connected to the word line corresponding to the row of the memory cell, the first terminal of the transistor is connected to the source line corresponding to the column of the memory cell, and the second terminal of the transistor is connected to a first terminal of the RSM, the second terminal of the RSM being connected to the bit line corresponding to the row of the memory cell. Each driving circuit is coupled to one bit line of the memory array.

[0073] This memory device can perform parallel initialization of the memory array through a driving circuit. During the parallel initialization process, the initialization voltage applied to the already initialized resistive switching memory device is automatically stopped, thereby effectively alleviating the voltage drop problem, shortening the initialization time, improving the uniformity and reliability of multiple resistive switching memory devices during parallel initialization, and reducing power consumption.

[0074] Figure 6 This is a schematic diagram of a memory device 200 provided for at least one embodiment of the present disclosure. Figure 6 As shown, the memory device 100 includes a memory array 20 and a plurality of drive circuits 10. For example, the plurality of drive circuits 10 are used as an initialization module to perform initialization operations on the resistive switching memory devices in the memory array 20.

[0075] For example, memory array 20 includes multiple memory cells forming an M-row, N-column array, where M and N are both positive integers. For example, each memory cell includes a switching element (e.g., a transistor) and a resistive switching memory device. Figure 6 In the diagram, WL[1], WL[2]...WL[m] represent the word lines of the first row, the second row...the Mth row, respectively. The control electrode (e.g., the gate of a transistor) of the switching element in the memory cell of each row is connected to the word line corresponding to that row. BL[1], BL[2]...BL[n] represent the bit lines of the first column, the second column...the Nth column, respectively. One end of the resistive switching memory device in the memory cell of each column is connected to the bit line corresponding to that column (while the other end is connected to the drain of the switching element in the memory cell, for example). SL[1], SL[2]...SL[n] represent the source lines of the first column, the second column...the Nth column, for example, the source of the transistor in the memory cell of each column is connected to the source line corresponding to that column. It should be noted that in the embodiments of this disclosure, the direction of the rows and columns is not limited to the situation shown in the figure, but can be determined as needed. The embodiments of this disclosure do not limit the structure of the memory array 20.

[0076] For example, the outputs of multiple drive circuits 10 are respectively coupled to multiple bit lines of memory array 20, so that the initialization degree of each column of resistive switching memory devices can be automatically controlled when the resistive switching memory devices in memory array 20 are initialized in parallel.

[0077] For example, multiple drive circuits 10 are connected to a bus of initialization voltage to receive a first operating voltage VFORM. For example, multiple drive circuits 10 may receive the same second control voltage VFORM_I, so that the resistance values ​​of multiple resistive resonant storage devices initialized in parallel are approximately the same after initialization.

[0078] The process of initializing each resistive switching memory device by the drive circuit 10 can be referred to the detailed description of the self-stop initialization operation method in the previous embodiment, and will not be repeated here.

[0079] Under normal circumstances, when the parallel initialization operation begins, the current on the VFORM bus increases rapidly. Because the resistance of the wires is low near the bus end, there is no voltage drop issue, so the resistive switching memory devices on the columns near the bus end can receive the maximum VFORM voltage and begin the initialization process under the regulation of this voltage. When the resistance of the resistive switching memory devices in that column drops to a certain value, the initialization of that column automatically stops, and the current drops to 0. As more and more branches (columns) are turned off, the total current on the VFORM bus gradually decreases, thus reducing the total current and alleviating the voltage drop problem at the far end of the bus. Therefore, the memory array 10 can gradually complete the initialization process from the near end of the bus to the far end.

[0080] By using the self-stop initialization operation method provided in the above embodiments of this disclosure, when initializing multiple resistive random access memory devices in a certain row of the memory array 20, when the resistance of a resistive random access memory device in a column drops below a certain value, the drive circuit 10 of that column can automatically stop the initialization process, thereby automatically "shutting off" this branch. This can improve the uniformity and reliability of the resistive random access memory devices after multiple memory cells are initialized at the same time, while avoiding voltage drop problems, reducing the current on the bus, and reducing power consumption.

[0081] It should be noted that, from a statistical distribution perspective, during parallel initialization, resistive random access memory (RRAM) devices closer to the bus in memory array 10 may complete initialization faster, while those farther from the bus may complete initialization slower. However, due to inherent differences among RRAM devices, the initialization order of multiple RRAM devices is usually random. Furthermore, during parallel initialization, the initialization times of multiple RRAM devices in a row are not necessarily the same. However, the resistance values ​​of the initialized RRAM devices can be controlled within a target range by the drive circuit. Therefore, the drive circuit, memory device, and operating method provided in at least one embodiment of this disclosure can improve the accuracy of RRAM device initialization and eliminate the need for additional verification operations, thereby significantly shortening the initialization time and reducing production costs.

[0082] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0083] The following points should be noted regarding this disclosure:

[0084] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0085] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0086] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0087] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A driving circuit, comprising: Control unit, switching unit, and sampling unit, The control unit is connected to a first voltage source and a second voltage source, and is configured to receive a first control signal from the first voltage source, receive a second control signal from the second voltage source, and turn on or off according to the first control signal, and apply the second control signal to the first node when it is turned on; The switching unit is connected to the control unit, the third voltage source, and the output terminal, and is configured to be turned on or off according to the level of the first node, and to be turned on when the level of the first node is the second control signal so as to apply the first operating voltage received from the third voltage source to the output terminal; The sampling unit is connected to the output terminal, the third voltage source, and the switching unit, and is configured to turn on or off according to the feedback voltage of the output terminal, and when turned on, the first operating voltage is applied to the first node so that the switching unit is turned off when the level of the first node is the first operating voltage.

2. The driving circuit according to claim 1, wherein, The control unit includes a first transistor, the control electrode of the first transistor is connected to the first voltage source, the first electrode of the first transistor is connected to the second voltage source, and the second electrode of the first transistor is connected to the first node; The switching unit includes a second transistor, the control electrode of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the third voltage source, and the second electrode of the second transistor is connected to the output terminal. The sampling unit includes a third transistor, the control electrode of the third transistor is connected to the output terminal, the first electrode of the third transistor is connected to the third voltage source, and the second electrode of the third transistor is connected to the first node.

3. The driving circuit according to claim 2, wherein, The first transistor, the second transistor, and the third transistor are P-type transistors.

4. A memory device, comprising: The driving circuit as described in claim 1; A resistive random access memory device, wherein a first terminal of the resistive random access memory device is connected to the output terminal of the driving circuit, and a second terminal of the resistive random access memory device is connected to a fourth voltage source.

5. A method of operating a memory device as described in claim 4, comprising: The control unit receives the first control signal from the first voltage source and the second control signal from the second voltage source. The control unit is activated according to the first control signal, and the second control signal is applied to the first node to activate the switching unit. The first operating voltage is received from the third voltage source through the switching unit, and the first operating voltage is applied to the resistive switching memory device connected to the output terminal when the switching unit is turned on. The sampling unit is turned on according to the feedback voltage at the output terminal, and the first operating voltage is applied to the first node to turn off the switching unit.

6. The operating method according to claim 5, wherein, The first operating voltage includes an initialization voltage or a set voltage for the resistive switching memory device.

7. The operating method according to claim 5 or 6, further comprising: The resistance value of the resistive switching memory device is changed according to the first operating voltage.

8. The operating method according to claim 5 or 6, wherein, The feedback voltage changes in response to a change in the resistance value of the resistive switching memory device. When the resistance value of the resistive switching memory device reaches the target resistance value, the feedback voltage reaches the first threshold voltage to turn on the sampling unit.

9. The operating method according to claim 5 or 6, further comprising: The current-limiting voltage of the second control signal is determined based on the target resistance value of the resistive switching memory device.

10. A memory device, comprising: A memory array includes multiple rows and columns of memory cells, word lines corresponding to each row of the memory array, bit lines corresponding to each row of the memory array, and source lines corresponding to each column of the memory array. Each memory cell includes a transistor and a resistive random access memory (RRAM). The gate of the transistor is connected to the word line corresponding to the row of the memory cell, the first terminal of the transistor is connected to the source line corresponding to the column of the memory cell, the second terminal of the transistor is connected to the first terminal of the RRAM, and the second terminal of the RRAM is connected to the bit line corresponding to the row of the memory cell. At least one driving circuit as claimed in claim 1, each of the driving circuits being coupled to one of the bit lines of the memory array.

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