Flash memory chip write-in method and system based on circuit outage

Abstract

The invention discloses a flash memory chip writing method and system based on circuit outage, when a circuit is in a working state, charging of a capacitor is triggered based on a power supply of the circuit, charging of the capacitor is ensured, power supply of the capacitor to the flash memory chip is facilitated, and the power supply of the circuit and the working state of the circuit are fully utilized. Defining a corresponding power supply mode according to the to-be-written data in the flash memory chip, the electric quantity of the capacitor and the power supply path; the method comprises the steps of receiving a power supply mode of a flash memory chip, triggering a capacitor to supply power to the flash memory chip based on the power supply mode, dynamically optimizing a write-in path of the flash memory chip based on power consumption efficiency of the capacitor, a storage space of the flash memory chip and to-be-written data, and performing different-level control on the to-be-written data according to the optimized write-in path and the storage space of the flash memory chip. The flash memory chip is ensured to fully write the to-be-written data, write path management and control and different-level management and control are carried out on the write-in process of the flash memory chip, and the write-in effect of the flash memory chip based on circuit outage is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory chips, and in particular, to a writing method and system for a flash memory chip based on circuit power-off. Background Art

[0002] With the development of technology, circuits are gradually applied to people's lives and are widely used in various electronic devices. When the circuit is in the working state, the flash memory chip will gradually write data, so there will be data to be written. The data to be written will be gradually written into the flash memory chip. However, when the circuit is in the power-off state, the data to be written cannot be written into the flash memory chip, and it is impossible to ensure that the flash memory chip fully writes the data to be written. Summary of the Invention

[0003] An object of the present invention is to overcome the deficiencies of the prior art, and the present invention provides a writing method and system for a flash memory chip based on circuit power-off.

[0004] An embodiment of the present invention provides a writing method for a flash memory chip based on circuit power-off, which is applied to a writing scenario of a flash memory chip based on circuit power-off;

[0005] The writing method for the flash memory chip based on circuit power-off includes:

[0006] Locating a capacitor and a flash memory chip based on circuit traversal;

[0007] The flash memory chip is associated with a capacitor and the power supply of the circuit, and multiple power supply paths of the flash memory chip are defined;

[0008] Real-time monitoring of the circuit state;

[0009] When the circuit is in the working state, charging the capacitor based on the power supply of the circuit;

[0010] Defining a corresponding power supply mode according to the data to be written in the flash memory chip, the power of the capacitor, and the power supply path;

[0011] Powering the flash memory chip by triggering the capacitor based on the power supply mode, dynamically optimizing the writing path of the flash memory chip based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written, and performing different-level management and control on the data to be written according to the optimized writing path and the storage space of the flash memory chip.

[0012] In addition, an embodiment of the present invention further provides a writing system for a flash memory chip based on circuit power-off, and the writing system for the flash memory chip based on circuit power-off includes:

[0013] A positioning module for locating a capacitor and a flash memory chip based on circuit traversal;

[0014] A power supply path module, which is used to associate a capacitor with a flash memory chip and a power supply of a circuit, and define multiple power supply paths for the flash memory chip;

[0015] A monitoring module, which is used to monitor the state of the circuit in real time;

[0016] A charging module, which is used to trigger the charging of the capacitor based on the power supply of the circuit when the circuit is in a working state;

[0017] A power supply module, which is used to define a corresponding power supply mode according to the data to be written in the flash memory chip, the power of the capacitor, and the power supply path;

[0018] A writing module, which is used to trigger the power supply of the flash memory chip by the capacitor based on the power supply mode, dynamically optimize the writing path of the flash memory chip based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written, and perform different-level control on the data to be written according to the optimized writing path and the storage space of the flash memory chip.

[0019] In an embodiment of the present invention, by the method in the embodiment of the present invention, a capacitor and a flash memory chip are located based on the traversal of the circuit; the capacitor is associated with the flash memory chip and the power supply of the circuit, and multiple power supply paths for the flash memory chip are defined; the state of the circuit is monitored in real time; when the circuit is in a working state, the charging of the capacitor is triggered based on the power supply of the circuit, which ensures the charging of the capacitor, facilitates the power supply of the capacitor to the flash memory chip, and makes full use of the power supply of the circuit and the working state of the circuit.

[0020] Furthermore, a corresponding power supply mode is defined according to the data to be written in the flash memory chip, the power of the capacitor, and the power supply path; the power supply of the flash memory chip by the capacitor is triggered based on the power supply mode, the writing path of the flash memory chip is dynamically optimized based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written, and different-level control is performed on the data to be written according to the optimized writing path and the storage space of the flash memory chip, which ensures the full writing of the data to be written into the flash memory chip, and performs control on the writing path and different-level control on the writing process of the flash memory chip, improving the writing effect of the flash memory chip based on the power-off of the circuit. Description of the Drawings

[0021] Figure 1 is a schematic flowchart of the method for writing a flash memory chip based on power-off of a circuit in an embodiment of the present invention;

[0022] Figure 2 is a schematic flowchart of S11 in the method for writing a flash memory chip based on power-off of a circuit in an embodiment of the present invention;

[0023] Figure 3 is a schematic flowchart of S12 in the method for writing a flash memory chip based on power-off of a circuit in an embodiment of the present invention;

[0024] Figure 4 It is a schematic flowchart of S13 in the write method of the flash memory chip based on power-off of the circuit in the embodiment of the present invention;

[0025] Figure 5 It is a schematic flowchart of S14 in the write method of the flash memory chip based on power-off of the circuit in the embodiment of the present invention;

[0026] Figure 6 It is a schematic flowchart of S15 in the write method of the flash memory chip based on power-off of the circuit in the embodiment of the present invention;

[0027] Figure 7 It is a schematic flowchart of S16 in the write method of the flash memory chip based on power-off of the circuit in the embodiment of the present invention;

[0028] Figure 8 It is a schematic diagram of the structural composition of the write system of the flash memory chip based on power-off of the circuit in the embodiment of the present invention. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention.

[0030] Please refer to Figures 1 to 8 , a write method of a flash memory chip based on power-off of the circuit, which is applied to the write scenario of the flash memory chip based on power-off of the circuit; the write method of the flash memory chip based on power-off of the circuit includes:

[0031] Step S11: Locate the capacitor and the flash memory chip based on the traversal of the circuit;

[0032] Step S12: The flash memory chip associates with the capacitor and the power supply of the circuit, and defines multiple power supply paths of the flash memory chip;

[0033] Step S13: Monitor the state of the circuit in real time;

[0034] Step S14: When the circuit is in the working state, trigger the charging of the capacitor based on the power supply of the circuit;

[0035] Step S15: Define the corresponding power supply mode according to the data to be written in the flash memory chip, the power of the capacitor, and the power supply path;

[0036] Step S16: Trigger the power supply of the capacitor to the flash memory chip based on this power supply mode, dynamically optimize the write path of the flash memory chip based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written, and perform different-level management and control on the data to be written according to the optimized write path and the storage space of the flash memory chip.

[0037] Refer to Figure 2, in step S11, locate the capacitor and the flash memory chip based on the traversal of the circuit;

[0038] In the specific implementation process of the present invention, the specific steps may be as follows:

[0039] S111: Collect the location of the circuit;

[0040] S112: Define a corresponding traversal model according to the detection of the location of the circuit;

[0041] S113: Trigger the traversal of the circuit based on the circuit and the traversal model;

[0042] S114: Locate the capacitor and the flash memory chip based on the traversal of the circuit.

[0043] In the embodiment of the present application, the location of the circuit is collected, the location of the circuit is introduced, and the location of the circuit is controlled. Thus, a corresponding traversal model is defined according to the detection of the location of the circuit, the detection of the location of the circuit is realized, and the accuracy of the traversal model is ensured.

[0044] Specifically, in the system design stage, assign a unique location identifier to each acquisition circuit. This identifier can be a physical coordinate, a logical address, or other information that can uniquely determine the location of the circuit. Record the location information of each acquisition circuit in detail in the system document or database. Ensure that the location information is consistent with the actual layout of the circuit for subsequent detection and management.

[0045] During system operation, implement real-time monitoring of the location of the acquisition circuit. Use sensors, network interfaces, or other technical means to ensure that the location status of the circuit can be obtained in real time. If the circuit location changes (such as maintenance, upgrade, or re-layout), update the location information in a timely manner. Ensure that the location information in the system document and database is consistent with the actual situation.

[0046] Design a traversal model based on the location information of the acquisition circuit. The traversal model should be able to effectively access and process the data of each acquisition circuit according to the actual layout of the circuit. Optimize the traversal model in real time according to the dynamic changes of the circuit location. Ensure that the traversal model can always reflect the actual layout of the circuit to improve the efficiency and accuracy of data access.

[0047] Establish a complete position detection mechanism to ensure the real-time and accurate detection of the position of the acquisition circuit. The position detection mechanism should be able to handle various complex scenarios, such as circuit occlusion, interference, etc. Verify the accuracy of the traversal model through actual operation and testing. Use quality control methods and standard test cases to comprehensively evaluate the traversal model. According to the verification results, make necessary adjustments and optimizations to the traversal model. Ensure that the traversal model can always accurately reflect the actual position of the circuit to improve the overall performance and reliability of the system.

[0048] Therefore, trigger the traversal of the circuit based on the circuit and the traversal model; locate the capacitor and flash memory chip according to the traversal of the circuit, realizing the traversal of the circuit, so as to accurately locate the capacitor and flash memory chip, and then conduct subsequent management and control of the capacitor and flash memory chip, achieving the overall consideration of the circuit, capacitor and flash memory chip.

[0049] Specifically, in the electronic system design stage, construct a traversal model according to the circuit layout and connection relationship. The traversal model should be able to reflect the connection paths and relative positions between various components (including capacitors and flash memory chips) in the circuit. During system operation, start the traversal of the circuit through preset trigger conditions (such as system startup, regular maintenance, or specific events). The traversal process can be an automatic process controlled by software or an operation manually triggered by the user.

[0050] During the circuit traversal process, locate the capacitor and flash memory chip by reading the circuit layout information and component identifiers. These identifiers can be physical marks, logical addresses, or other information that can uniquely identify components. Record the position information of the located capacitor and flash memory chip in the system document or database. If the circuit layout changes (such as component replacement, upgrade, or re-layout), update the position information in a timely manner.

[0051] Regularly monitor the performance of the capacitor and flash memory chip, including key indicators such as capacitance value, flash memory read and write speed, error rate, etc. Use specialized test tools or software to collect and analyze this data to detect and handle potential problems in a timely manner. According to the performance monitoring results, give early warnings for capacitors and flash memory chips that may fail. Develop a fault handling plan, including the preparation of spare components, the replacement of faulty components, and the reconfiguration of the system, etc. Record the maintenance history of the capacitor and flash memory chip, including information such as maintenance time, maintenance content, and maintenance personnel. Track the performance changes of the components after maintenance to evaluate the maintenance effect and optimize the maintenance strategy.

[0052] In the system design phase, factors such as circuit layout, the selection of capacitors and flash memory chips, and performance requirements are comprehensively considered to ensure the overall performance and reliability of the system. Simulation software and simulation tools are used to model and analyze the circuit to predict and optimize the system's performance. In the system integration phase, the circuit, capacitors, and flash memory chips are rigorously tested and verified to ensure that they can work properly and meet the design requirements. Automated test tools and processes are used to improve test efficiency and accuracy. A long-term maintenance plan and support strategy are formulated to ensure the continuous management and optimization of the circuit, capacitors, and flash memory chips throughout the system's life cycle. User training and technical support are provided to help users better understand and use the system.

[0053] Reference Figure 3 , in step S12, the flash memory chip is associated with the capacitor and the power supply of the circuit, and multiple power supply paths of the flash memory chip are defined;

[0054] In the specific implementation process of the present invention, the specific steps may be:

[0055] S121: Freeze the circuit and collect the power supply of the circuit and the capacitor;

[0056] S122: Collect the flash memory chip off, and associate the flash memory chip with the capacitor and the power supply of the circuit;

[0057] S123: Form multiple association paths based on the flash memory chip, the capacitor, and the power supply of the circuit;

[0058] S124: Identify the multiple association paths;

[0059] S125: Define multiple power supply paths of the flash memory chip according to the identification of the multiple association paths.

[0060] In the embodiment of the present application, the circuit is frozen, and the power supply of the circuit and the capacitor are collected, introducing the power supply of the circuit and the capacitor, and controlling the power supply of the circuit and the capacitor. At the same time, the flash memory chip off is collected, and the flash memory chip is associated with the capacitor and the power supply of the circuit, realizing the association of the flash memory chip, the capacitor, and the power supply of the circuit.

[0061] Specifically, a professional tool or software is used to capture the state of the circuit at a specific moment to form a circuit snapshot. This snapshot should contain information such as the complete layout of the circuit, the component connection relationship, and the current working state. The key data in the circuit snapshot is recorded for subsequent analysis and processing. The data recording should cover all components in the circuit, especially the power supply, capacitor, and flash memory chip, etc.

[0062] Identify and collect information about all power supplies in the circuit, such as voltage level, current magnitude, and power supply type, etc. Ensure that the collected power supply information is accurate and up-to-date in real time to reflect changes in the circuit state. Check each capacitor in the circuit one by one and record key parameters such as its capacitance value, polarity, operating temperature range, etc. Ensure that the capacitor information matches the actual circuit layout for subsequent power management and capacitor maintenance.

[0063] Based on the collected power supply information, perform intelligent management of the power supplies in the circuit. This includes functions such as voltage regulation, current control, and power supply fault warning, etc. Regularly check and test the capacitors in the circuit to ensure they are in good working condition. If a decrease in capacitor performance or a fault is found, replace or repair it in a timely manner.

[0064] Identify the flash memory chips in the circuit and record key information such as their storage capacity, read / write speed, interface type, etc. Ensure that the collected flash memory chip information is consistent with the circuit layout and design requirements. Associate the flash memory chips with the power supplies and capacitors in the circuit. This includes establishing the logical connection relationships between them and recording their interactions and influences during operation. Store the associated information in a dedicated database or data structure for subsequent analysis and processing. Update and maintain the associated information in a timely manner as the circuit state changes and components are updated.

[0065] Combine the circuit snapshot, power management, capacitor maintenance, and flash memory chip association information to conduct a comprehensive analysis of the overall performance of the circuit. Identify potential performance bottlenecks and optimization spaces to provide a basis for subsequent circuit improvement. Establish a fault warning mechanism based on the associated information to promptly detect and handle potential faults in the circuit. Develop a fault handling plan to ensure that the circuit can respond quickly and resume normal operation when a fault occurs. Optimize and upgrade the circuit in combination with the actual usage situation and performance requirements of the circuit. This includes, but is not limited to, component selection adjustment, layout optimization, and function expansion, etc.

[0066] By freezing the circuit, collecting capacitor information of the power supply, conducting control, collecting flash memory chip information and establishing associations, we can achieve precise management and optimization of key components in the electronic system. This not only improves the performance and reliability of the system but also provides convenience for subsequent maintenance and upgrade. At the same time, by comprehensively considering the performance and requirements of the circuit, power supply, capacitor, and flash memory chip in all aspects such as system design, maintenance, and management, we can ensure that the overall performance and user experience of the system are optimized to the greatest extent.

[0067] Therefore, multiple association paths are formed based on the flash memory chips, capacitors, and the power supply of the circuit; the multiple association paths are identified; and multiple power supply paths of the flash memory chips are defined according to the identification of the multiple association paths, realizing the identification of the multiple association paths and ensuring the accuracy of the multiple power supply paths of the flash memory chips.

[0068] Specifically, conduct a detailed analysis of the circuit of the electronic system to understand the connection relationship and layout among the power supply, capacitors, and flash memory chips. Determine the key nodes and paths in the circuit, especially the parts related to the power supply of the flash memory chips. Based on the results of the circuit analysis, design multiple associated paths from the power supply to the flash memory chips. These paths should make full use of energy storage components such as capacitors in the circuit to provide additional power stability and redundancy. Use simulation software or actual tests to verify the designed associated paths to ensure that they can work properly in the actual circuit. Adjust and optimize the paths according to the verification results to improve their reliability and stability.

[0069] Use specialized circuit test equipment or software to identify each associated path in the circuit one by one. By measuring parameters such as voltage and current on the path, confirm the effectiveness and stability of each path. Record the information of the identified associated paths, including the starting point, ending point, components passed through, and the electrical characteristics of the path, etc. This information will be used for subsequent power supply path definition and management.

[0070] According to the information of the identified associated paths, plan multiple power supply paths for the flash memory chips. Ensure that each power supply path passes through the verified paths and has sufficient stability and redundancy. Design and implement a switching mechanism for the power supply paths so that it can quickly switch to the backup path when the main power supply path fails. The switching mechanism should ensure the smoothness and seamlessness of the switching process to avoid damage to the flash memory chips or data loss. Monitor the status of the power supply paths in real time, including voltage stability, current magnitude, and whether there are faults on the paths, etc. Adjust the power supply paths in a timely manner according to the monitoring results to ensure that the flash memory chips always obtain a stable power supply.

[0071] Regularly test and verify the power supply paths to ensure that they are still effective and stable. Use professional test equipment and methods to measure and analyze the electrical parameters on the paths. Optimize and upgrade the power supply paths according to the test results and actual requirements, including but not limited to adjusting the path layout, adding energy storage components such as capacitors, and improving the switching mechanism, etc. Record the relevant information of the power supply paths in the document, including the path design, test results, optimization history, etc. As the system is updated and upgraded, update the information in the document in a timely manner to ensure its accuracy and integrity.

[0072] By constructing multiple associated paths, identifying these paths, defining multiple power supply paths for the flash memory chip, and taking measures to ensure the accuracy of these paths, we can ensure that the flash memory chip can obtain a stable power supply under various circumstances. This not only improves the reliability of the system but also provides convenience for subsequent maintenance and upgrades. At the same time, by comprehensively considering factors such as circuit layout, component characteristics, and actual requirements, we can optimize and upgrade the power supply paths to further improve the overall performance and user experience of the system.

[0073] Reference Figure 4 , in step S13, in the floor cleaning space, the state of the circuit is monitored in real time;

[0074] In the specific implementation process of the present invention, the specific steps can be:

[0075] S131: Freeze the circuit;

[0076] S132: Collect the operating parameters of the circuit at different positions;

[0077] S133: Define the state of the circuit based on multiple operating parameters and the corresponding positions. The state of the circuit includes the operating state and the power-off state;

[0078] S134: Monitor the state of the circuit in real time.

[0079] In the embodiment of the present application, freeze the circuit to control the circuit. At the same time, collect the operating parameters of the circuit at different positions; define the state of the circuit based on multiple operating parameters and the corresponding positions. The state of the circuit includes the operating state and the power-off state, which accommodates the overall consideration of multiple operating parameters and the corresponding positions, realizes the multi-dimensional control of multiple operating parameters and the corresponding positions, and ensures the accuracy of the state of the circuit.

[0080] Specifically, use special test equipment or software to perform a freezing operation on the circuit, that is, capture the state of the circuit at a specific moment. The freezing operation should cover all key components and connections in the circuit to ensure the comprehensiveness of subsequent analysis. Establish a circuit control mechanism to monitor and manage the circuit in real time. This includes functions such as circuit switch control, power management, fault warning and handling, etc., to ensure the stable operation of the circuit.

[0081] Set multiple parameter collection points in the circuit. These points should be distributed at key positions in the circuit to comprehensively reflect the operating state of the circuit. The collection points should include measurement points for key parameters such as voltage, current, and temperature. Use sensors and data collection equipment to collect the data of these parameter collection points in real time. Ensure that the collected data is accurate and error-free and update it to the monitoring system in real time.

[0082] Define different states of the circuit based on the collected operating parameters and corresponding location information. The state definition should cover all possible situations of the circuit, including normal operating state, abnormal state, power-off state, etc. Conduct multi-dimensional analysis of the circuit state by combining multiple operating parameters and location information. This includes the change trend of parameters, the correlation between parameters, and the impact of location on parameters. Establish a state verification mechanism to verify and calibrate the defined states. Use historical data and simulation results for comparison and analysis to ensure the accuracy and reliability of the state definition.

[0083] Integrate and analyze the multiple collected operating parameters and location information. Use data analysis tools and algorithms to extract key information and generate a status report. Monitor the status of the circuit in real time and issue warnings according to preset thresholds and rules. The warning information should include the reason for the status change, possible impacts, and recommended handling measures, etc. Conduct fault troubleshooting and handling of the circuit based on the monitoring and warning results. Use professional test equipment and tools to locate the fault point and take corresponding repair measures. Optimize and upgrade the state definition and monitoring mechanism according to the actual operating conditions and requirements of the circuit. This includes adjusting the location of parameter collection points, adding new parameter types, and improving the state analysis algorithm, etc.

[0084] By means of freezing the circuit, controlling the circuit, collecting operating parameters, and defining the circuit state based on these parameters and location, we can achieve multi-dimensional control of the circuit state. This not only improves the accuracy and reliability of circuit management, but also provides strong support for subsequent fault troubleshooting, optimization and upgrade, and system maintenance. At the same time, by comprehensively considering multiple operating parameters and location information, we can more comprehensively understand the operating state of the circuit, and thus make more accurate decisions and actions.

[0085] At the same time, the state of the circuit is introduced, so as to monitor the state of the circuit in real time, monitor the state of the circuit in real time, further control the state of the circuit, and ensure the subsequent processing of the state of the circuit.

[0086] Specifically, based on the working principle and actual operating conditions of the circuit, clarify the various possible states of the circuit, such as normal operating state, abnormal state, power-off state, etc. Set clear definition conditions and judgment criteria for each state. Set identification codes or labels for the circuit states to facilitate quick identification and differentiation of different states in the monitoring system. Ensure the uniqueness and accuracy of the state identifiers.

[0087] Design a dedicated circuit status monitoring system that integrates functions such as data acquisition, status judgment, and warning prompts. Ensure the real-time, accuracy, and reliability of the monitoring system. Deploy sensors and data acquisition devices in the circuit to collect key parameters of the circuit (such as voltage, current, temperature, etc.) in real time. Transmit the collected data to the monitoring system for real-time analysis and processing. The monitoring system analyzes the collected data according to the preset status definition conditions and judgment criteria to determine the current state of the circuit. Update the circuit status information in real time to ensure that the status displayed in the monitoring system is consistent with the actual situation.

[0088] When the circuit status changes, especially when changing from the normal working state to the abnormal state, the monitoring system should immediately trigger the warning mechanism. The warning information should include the time, reason, possible impact, and recommended handling measures of the status change. According to the warning information, conduct fault troubleshooting and location for the circuit. Use professional test equipment and tools to analyze the abnormal parameters and signals in the circuit to determine the fault point. Develop corresponding emergency handling measures for different types of circuit statuses. For example, if the circuit is in an abnormal state, immediately take measures to isolate the fault point to prevent the spread of the fault; if the circuit is in a power-off state, restore power as soon as possible to ensure the stable operation of the system.

[0089] Repair the determined fault point and verify the repair effect. Ensure that the repaired circuit can resume normal working state and meet the system performance requirements. Analyze and summarize the historical data of the circuit status to find out the causes and laws of faults. According to the analysis results, optimize the circuit design, layout, component selection, etc. to improve the reliability and stability of the circuit. Regularly upgrade and maintain the monitoring system to ensure that it can monitor the circuit status in real time and accurately. According to the actual needs and technological development, continuously introduce new monitoring technologies and methods to improve the performance and functions of the monitoring system.

[0090] By introducing the concept of circuit status and monitoring it in real time, we can timely discover potential problems in the circuit and take corresponding measures to control and handle them. This not only improves the efficiency and accuracy of circuit management but also provides a strong guarantee for the stable operation of the system. At the same time, by continuously optimizing the monitoring system and circuit design, we can further improve the reliability and stability of the circuit to meet the requirements of high performance and high reliability of electronic systems.

[0091] Reference Figure 5 ,S14: When the circuit is in the working state, trigger the charging of the power supply trigger capacitor of the circuit;

[0092] In the specific implementation process of the present invention, the specific steps can be:

[0093] S141: Collect the status of the circuit;

[0094] S142: When the circuit is in the working state, freeze the power supply of the freeze circuit;

[0095] S143: Associate the power supply of the circuit and the capacitor;

[0096] S144: Locate the power supply path between the power supply of the circuit and the capacitor;

[0097] S145: Trigger the charging of the capacitor based on this power supply path.

[0098] In the embodiments of the present application, the state of the acquisition circuit is collected, the state of the circuit is introduced, and the state of the circuit is controlled. At the same time, when the circuit is in the working state, the power supply of the circuit is frozen; the power supply of the circuit and the capacitor are associated, the power supply of the circuit and the capacitor are introduced, and the power supply of the circuit and the capacitor are controlled in multiple dimensions.

[0099] Specifically, sensors are deployed in the circuit to collect key parameters (such as voltage, current, temperature, etc.) in real time to reflect the working state of the circuit. Ensure the accuracy and real-time nature of the collected data, providing a reliable basis for subsequent state analysis and control. According to the collected data, different states of the circuit are defined, such as normal working state, warning state, fault state, etc. Clear definition conditions and judgment criteria are set for each state to facilitate subsequent state control and fault handling. Establish a circuit state control mechanism and take corresponding control measures according to the change of the circuit state. For example, when the circuit enters the warning state, the warning prompt is immediately triggered and corresponding preventive measures are taken; when the circuit enters the fault state, the fault troubleshooting and handling process is started.

[0100] Power supply monitoring devices are deployed at key positions of the circuit to collect parameters such as voltage and current of the power supply in real time. Monitor the fluctuation and stability of the power supply to ensure that the circuit obtains a stable power supply during operation. When the circuit is in the working state, freeze the power supply state of the circuit and record key parameters such as voltage and current of the power supply. This helps the subsequent analysis and optimization of the circuit working state and serves as a reference during fault troubleshooting.

[0101] Analyze the circuit layout and component connection relationship to determine the association path between the power supply and the capacitor. Ensure that the capacitor can be correctly connected to the power supply and play roles such as filtering and energy storage in the circuit. Monitor and adjust the voltage and current of the power supply in real time to ensure that they fluctuate within a safe range. Regularly detect and calibrate the capacitance and charge-discharge characteristics of the capacitor to ensure its normal operation. Combine the working state and load conditions of the circuit to dynamically adjust the control strategies of the power supply and the capacitor to improve the stability and reliability of the circuit. Based on the collected data of the power supply, capacitor, and circuit state, conduct comprehensive analysis and evaluation. According to the analysis results, optimize and adjust the circuit layout, component selection, control strategies, etc. to improve the overall performance and stability of the circuit.

[0102] After implementing the above strategies, evaluate the stability, reliability, and overall performance of the circuit. Based on the evaluation results, judge the implementation effect of the strategies, and identify existing problems and improvement directions. Continuously improve and optimize the strategies according to the evaluation results and actual requirements. Introduce new technologies and methods to improve the efficiency and accuracy of circuit state control and power management.

[0103] By collecting circuit states, introducing state control, fixing the power supply of the working state, and associating and multi-dimensionally controlling the power supply and capacitors of the circuit, we can achieve precise control of the circuit state and effective management of the power supply. This not only improves the reliability and stability of the circuit but also provides strong support for subsequent maintenance and upgrades. At the same time, by continuously improving and optimizing the strategies, we can adapt to changing requirements and technological developments to ensure the long-term stable operation of the electronic system.

[0104] Therefore, plan the power supply path for the power supply and capacitors of the circuit to facilitate locating the power supply path between the power supply and capacitors of the circuit, thereby triggering the charging of the capacitor based on this power supply path, achieving the charging of the capacitor, making full use of the working state of the circuit, and facilitating the power supply of the capacitor to the flash memory chip.

[0105] Specifically, carefully study the circuit layout diagram to determine the positions of key components such as the power supply, capacitors, and flash memory chips. Pay attention to the connection relationships and signal flows between the components to lay the foundation for subsequent power supply path planning. According to the circuit layout and component requirements, plan the power supply paths from the power supply to the capacitors and from the capacitors to the flash memory chips. Ensure that the power supply paths are as short and direct as possible to reduce energy loss and signal interference. Introduce redundancy and backup mechanisms in the power supply paths to improve the fault tolerance and reliability of the system. For example, set multiple capacitors or power supply inputs on the critical path to ensure power supply can still be maintained in case of a single component failure.

[0106] Deploy state monitoring devices to collect key parameters such as the voltage and current of the circuit in real time. Based on the collected data, judge the current working state of the circuit, such as startup, operation, standby, etc. Develop a charging strategy for the capacitor according to the working state and load requirements of the circuit. For example, during the circuit startup phase, give priority to charging the capacitor to ensure a stable power supply can be provided when the load suddenly increases. When the circuit state meets the charging conditions, trigger a charging signal to make the power supply charge the capacitor through the power supply path. Monitor the charging process to ensure that the capacitor is fully charged within a safe range and is ready to supply power to the flash memory chip.

[0107] Dynamically adjust the power supply strategy of the capacitor according to the working state of the circuit and the load change. For example, when the circuit is running at high load, preferentially use the capacitor energy storage to supply power to the flash memory chip to reduce the power burden and maintain stable power supply. Deploy power supply quality monitoring equipment to collect parameters such as the power supply voltage and current of the flash memory chip in real time. According to the monitoring results, evaluate the power supply quality and take corresponding adjustment measures to ensure the normal operation of the flash memory chip. Optimize and adjust the circuit design and power supply path according to the actual operation situation and monitoring data. Such as increasing the capacitor capacity, improving the power supply path layout, introducing more efficient power management and other measures to improve the overall performance and stability of the system.

[0108] After implementing the above strategy, comprehensively evaluate the power supply quality, stability and overall performance of the circuit. According to the evaluation results, judge the implementation effect of the strategy, and identify existing problems and improvement directions. Continuously improve and optimize the strategy according to the evaluation results and actual needs. Introduce new technologies and methods to improve the flexibility and reliability of the circuit design to adapt to the changing needs and technological development.

[0109] By reasonably planning the power supply path, triggering the capacitor charging and using the circuit working state to realize the power supply of the capacitor to the flash memory chip, we can significantly improve the stability and reliability of the electronic system. This not only helps to extend the system life, but also enhances the user experience and system performance. At the same time, by continuously improving and optimizing the strategy, we can adapt to the changing needs and technological development and ensure the long-term stable operation of the electronic system.

[0110] Reference Figure 6 , S15: Define the corresponding power supply mode according to the data to be written in the flash memory chip, the power of the capacitor and the power supply path;

[0111] In the specific implementation process of the present invention, the specific steps can be:

[0112] S151: Freeze the capacitor;

[0113] S152: Collect the power of the capacitor;

[0114] S153: Correlate the data to be written in the flash memory chip, the power of the capacitor and the power supply path;

[0115] S154: Define the first mode parameter according to the data to be written in the flash memory chip and the power of the capacitor;

[0116] S155: Define the second mode parameter according to the power of the capacitor and the power supply path;

[0117] S156: Define the corresponding power supply mode according to the first mode parameter and the second mode parameter.

[0118] In the embodiments of the present application, a freeze capacitor is used to control the capacitor, thereby collecting the charge of the capacitor; the data to be written in the flash memory chip, the charge of the capacitor, and the power supply path are associated, realizing the association of the data to be written in the flash memory chip, the charge of the capacitor, and the power supply path, and overall consideration is given to the data to be written in the flash memory chip, the charge of the capacitor, and the power supply path.

[0119] Specifically, according to the requirements of the system and the circuit design, select a suitable type and specification of the capacitor. Carefully layout the capacitor to ensure that the connection path between it and the power supply and the flash memory chip is as short and direct as possible. Use a dedicated circuit or sensor to freeze the state of the capacitor, including key parameters such as its voltage, current, and charge. Ensure the real-time monitoring and accurate recording of these parameters to provide a basis for subsequent data processing and power supply strategy formulation. By freezing the capacitor state, collect the charge information of the capacitor. Process and analyze the collected charge data to evaluate the energy storage state and remaining charge of the capacitor.

[0120] According to the amount and type of data to be written in the flash memory chip, evaluate the required power supply amount and time. Determine the key stages during the data writing process and potential peaks in power supply demand. Associate the charge information of the capacitor with the data to be written in the flash memory chip. According to the data writing requirements and the charge state of the capacitor, formulate a power supply strategy to ensure that the capacitor can provide stable power support during the data writing process. Combine the capacitor charge and data writing requirements to optimize the power supply path. Ensure the efficiency and reliability of the power supply path, reducing the risk of energy loss and power supply interruption.

[0121] Conduct a comprehensive evaluation of the data to be written in the flash memory chip, the capacitor charge, and the power supply path. According to the evaluation results, optimize and adjust the system design and power supply strategy to improve the success rate and efficiency of data writing. Formulate a detailed power supply strategy, including the charging and discharging strategies of the capacitor, the timing arrangement of data writing, etc. Ensure that the implementation of the strategy matches the actual needs of the system and make dynamic adjustments and optimizations according to the actual situation. Deploy monitoring devices to monitor the operating state and key parameters of the system in real time. According to the monitoring results, promptly discover problems and handle them, and at the same time collect feedback data for subsequent strategy optimization and improvement.

[0122] By freezing the capacitor, collecting the charge, and associating and overall considering the data to be written in the flash memory chip, the capacitor charge, and the power supply path, we can formulate a more reasonable and efficient power supply strategy. This not only helps to ensure the stable writing of the flash memory chip, but also improves the overall performance and reliability of the system. At the same time, through continuous monitoring and feedback mechanisms, we can continuously optimize and improve the strategy to adapt to changing requirements and technological developments.

[0123] Therefore, define the first mode parameter according to the data to be written in the flash memory chip and the charge of the capacitor; define the second mode parameter according to the charge of the capacitor and the power supply path; define the corresponding power supply mode according to the first mode parameter and the second mode parameter, which takes into account the data to be written in the flash memory chip, the charge of the capacitor, and the power supply path as a whole, ensures multi-dimensional control of the data to be written in the flash memory chip, the charge of the capacitor, and the power supply path, realizes precise control of the power supply mode, and ensures the accuracy of the power supply mode.

[0124] Specifically, the amount and type of data to be written in the flash memory chip. Define the first mode parameter according to the writing requirements of the data (such as data volume, writing speed, writing priority, etc.). These parameters will reflect the requirements of data writing for power supply stability and power. The charge of the capacitor and the efficiency of the power supply path. Define the second mode parameter according to the current charge of the capacitor, the charging speed, and the reliability and efficiency of the power supply path. These parameters will reflect the energy storage state of the capacitor and the power supply capacity of the power supply path.

[0125] Combine the first mode parameter and the second mode parameter to define multiple power supply modes. Each power supply mode corresponds to specific data writing requirements, capacitor charge status, and power supply path. The power supply modes should include but are not limited to: high-speed writing mode (suitable for quickly writing a large amount of data, sufficient capacitor charge, and efficient power supply path), energy-saving writing mode (suitable for a small amount of data or low writing priority, limited capacitor charge, and need to optimize energy use), stable writing mode (suitable for medium data writing requirements, medium capacitor charge, and medium power supply path), etc. During system operation, dynamically select the appropriate power supply mode according to the real-time first mode parameter and second mode parameter. Implement automatic selection and switching of the power supply mode through an algorithm or a controller to ensure stable power supply of the flash memory chip under different data writing requirements, capacitor charge status, and power supply path.

[0126] During the selection and switching of the power supply mode, comprehensively consider multiple dimensions such as the data to be written in the flash memory chip, the charge of the capacitor, and the power supply path. Through real-time monitoring and data analysis, ensure that each dimension receives sufficient attention and control. Use high-precision sensors and algorithms to monitor and calculate the first mode parameter and the second mode parameter. Through the calibration and verification process, ensure that the selection and switching of the power supply mode have high precision and reliability.

[0127] Integrate the defined power supply mode and selection strategy into the control software of the electronic system. During system operation, automatically implement the selection and switching of the power supply mode through software algorithms. Through actual testing and data collection, evaluate whether the selection and switching of the power supply mode are accurate and efficient. According to the evaluation results, make necessary adjustments and optimizations to the power supply mode and selection strategy.

[0128] By defining the first mode parameter and the second mode parameter, and defining and selecting the power supply mode based on these parameters, we can achieve multi-dimensional control over the data to be written in the flash memory chip, the charge of the capacitor, and the power supply path. This not only helps to ensure the stable writing and data integrity of the flash memory chip, but also improves the overall performance and energy utilization efficiency of the system. At the same time, through precise power supply mode selection and switching strategies, we can ensure the accuracy of the power supply mode, thereby further enhancing the reliability and stability of the system.

[0129] Reference Figure 7 , S16: Trigger the power supply of the capacitor to the flash memory chip based on this power supply mode, dynamically optimize the writing path of the flash memory chip based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written, and perform different levels of control over the data to be written according to the optimized writing path and the storage space of the flash memory chip;

[0130] In the specific implementation process of the present invention, the specific steps can be:

[0131] S161: Freeze this power supply mode;

[0132] S162: Trigger the power supply of the capacitor to the flash memory chip according to this power supply mode;

[0133] S163: Realize the temporary protection of the flash memory chip based on the power supply of the capacitor to the flash memory chip;

[0134] S164: Correlate the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written;

[0135] S165: Dynamically optimize the writing path of the flash memory chip according to the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written;

[0136] S166: Perform different levels of control over the data to be written based on the optimized writing path and the storage space of the flash memory chip.

[0137] At this time, freeze this power supply mode; trigger the power supply of the capacitor to the flash memory chip according to this power supply mode, so as to facilitate the power supply of the capacitor to the flash memory chip, realize the temporary power supply of the capacitor to the flash memory chip, and be compatible with the normal use in the case of the circuit being in an open state, and then realize the temporary protection of the flash memory chip based on the power supply of the capacitor to the flash memory chip.

[0138] Specifically, according to the power consumption characteristics of the flash memory chip, the energy storage capacity of the capacitor, and the actual application scenario of the system, a specific power supply mode is designed. This mode should be able to ensure that the flash memory chip obtains sufficient power support both in the normal power supply and open circuit states of the circuit. Write the designed power supply mode into the control software of the system, and realize the fixation of the mode through the configuration of the hardware circuit. Ensure that when the system starts or resets, the power supply mode can be automatically loaded and activated.

[0139] When the system is working normally, charge the capacitor through the charging circuit to ensure sufficient energy storage. Real-time monitor the power state of the capacitor. When the power is lower than the preset threshold, trigger the charging process to ensure that the capacitor always maintains the best energy storage state. When the circuit is in the open circuit state, the system control software detects the power interruption signal. According to the fixed power supply mode, immediately trigger the capacitor to supply power to the flash memory chip. This is usually achieved by switching the power path or enabling the backup power supply circuit.

[0140] After being triggered, the capacitor starts to release the stored electrical energy to provide temporary power supply for the flash memory chip. Through the power management circuit, ensure the stability of the supply voltage and current of the capacitor to meet the working requirements of the flash memory chip. During the capacitor power supply period, the flash memory chip continues to perform its data writing, reading, or erasing operations. At the same time, the system control software starts data protection mechanisms such as write caching and data verification to ensure the integrity and reliability of the data. Real-time monitor the power state of the capacitor and the working state of the flash memory chip. When the capacitor power is close to exhaustion, the system control software issues a warning signal and prepares to switch to other power supply methods (such as backup battery or external power supply).

[0141] The system has a circuit open circuit detection function and can real-time monitor the state of the power line. When a circuit open circuit is detected, immediately trigger the capacitor power supply mechanism and adjust the working mode of the system to adapt to the temporary power supply conditions. In the circuit open circuit state, the system notifies the user through an indicator light, buzzer, or other user interface devices. At the same time, start the data saving mechanism to write key data into the flash memory chip or transfer it to an external storage device to ensure data security. When the circuit resumes normal power supply, the system performs a reset operation and checks the status of each component. According to the inspection results, restore the normal working mode of the system or perform necessary fault handling.

[0142] In summary, by fixing a specific power supply mode, triggering the capacitor to supply power to the flash memory chip, and realizing the temporary power supply of the capacitor and the temporary protection of the flash memory chip, we can ensure the normal use and data security of the flash memory chip when the circuit is in the open circuit state. This not only improves the reliability and stability of the system but also provides a better user experience for users.

[0143] Furthermore, the power consumption efficiency of the associated capacitor, the storage space of the flash memory chip, and the data to be written are correlated; the writing path of the flash memory chip is dynamically optimized according to the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written; different levels of control are performed on the data to be written based on the optimized writing path and the storage space of the flash memory chip, ensuring the full writing of the data to be written by the flash memory chip, and performing control of the writing path and different levels of control on the writing process of the flash memory chip, improving the writing effect of the flash memory chip based on power-off of the circuit.

[0144] Specifically, the power consumption efficiency of the capacitor directly affects the time it can provide temporary power supply for the flash memory chip. It is necessary to monitor the power state of the capacitor in real time and adjust the charging strategy and power supply duration according to its power consumption efficiency. The storage space of the flash memory chip determines the amount of data that can be stored. When optimizing the writing path, it is necessary to consider the utilization rate and remaining capacity of the storage space to ensure that data can be stored efficiently and orderly. The characteristics of the data to be written (such as data volume, data type, writing priority, etc.) have an important impact on the selection of the writing path. It is necessary to dynamically adjust the writing strategy according to the characteristics of the data to optimize the writing efficiency and data security.

[0145] During system operation, the storage space usage of the flash memory chip and the characteristics of the data to be written are monitored in real time. Based on this information, the optimal writing path is analyzed and selected to minimize power consumption and maximize storage space utilization. Based on the power consumption efficiency of the capacitor, the length and complexity of the writing path are adjusted to balance power consumption and writing speed. Considering factors such as the storage architecture and I / O bit width of the flash memory chip, the way and order of data writing are optimized.

[0146] The optimized writing path is monitored and managed in real time to ensure that data is written to the flash memory chip according to the predetermined path and strategy. During the writing process, any potential path conflicts or errors are detected and processed in a timely manner to ensure the stability and reliability of the writing process. According to the remaining amount of storage space of the flash memory chip and the priority of the data to be written, the data is divided into different levels. High-level data (such as critical business data, emergency data, etc.) is preferentially allocated storage space and ensured to be written quickly; low-level data can be written appropriately later or compressed to save storage space.

[0147] When the circuit is powered off, immediately trigger the temporary power supply mechanism of the capacitor to the flash memory chip. Ensure that during the capacitor power supply, the flash memory chip can continue to perform data writing operations. During the capacitor power supply, start data protection mechanisms such as write cache and data verification to ensure data integrity and reliability. When the capacitor runs out of power or the circuit resumes normal power supply, the system can automatically switch to an appropriate power supply mode and resume data writing. Through actual testing and data collection, evaluate the effects of write path optimization and different-level control strategies. According to the evaluation results, make necessary adjustments and optimizations to the strategies to improve the write efficiency and data security of the flash memory chip in the case of circuit power off.

[0148] In summary, by correlating the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written, and dynamically optimizing the write path of the flash memory chip and implementing different-level control strategies based on these factors, we can improve the write effect of the flash memory chip in the case of circuit power off while ensuring efficient and secure data writing. This not only enhances the reliability and stability of the system but also provides users with a better usage experience and data security guarantee.

[0149] In a specific embodiment, when the circuit is powered on and the voltage has not reached the normal operating voltage of the flash chip, the circuit is turned off to ensure that the voltage quickly rises from zero to the operating voltage. When the voltage reaches the normal operating voltage of the flash chip, the circuit conducts and the voltage charges the capacitor. When the power supply is cut off, the circuit remains conducting and the capacitor discharges externally, causing the VCC voltage to drop slowly to ensure that the flash chip can complete the current read and write operations.

[0150] Connect the energy storage first capacitor through a floating gate transistor. The capacitance value of the first capacitor is determined by the duration and current magnitude that the flash memory chip needs to operate after power-off. Two diodes connected in reverse are connected to the second capacitor. The sum of the forward conduction voltage and the reverse conduction voltage of the diodes is higher than the minimum operating voltage of the flash memory chip and lower than the maximum power supply voltage. The control gate of the floating gate transistor is connected between the diode and the second capacitor. The other ends of the floating gate transistor and the diode are connected to the power supply, and the other ends of the first capacitor and the second capacitor are grounded. This circuit can be made on a circuit board with discrete components or integrated into a chip.

[0151] The working principle is as follows:

[0152] When the circuit starts, electrons are stored in the floating gate of the floating gate transistor. At this time, the floating gate transistor is in the off state and the diode is also in the cut-off state. Before the power supply rises from 0 to the operating voltage VCC, the capacitors are not connected in parallel to the power supply line, so it will not affect the startup time.

[0153] When the power supply reaches the forward conduction voltage of the diode plus the reverse conduction voltage, the diode pair conducts, and the second capacitor is charged. Since the power supply voltage has exceeded the minimum operating voltage of the flash memory chip at this time, it does not affect the startup time. At the same time, holes enter the floating gate of the floating gate transistor through the power supply, first neutralize the original electrons in the floating gate, and then fill the floating gate with holes. At this time, the floating gate transistor conducts, and the power supply charges the first capacitor.

[0154] When the power supply is turned off, since the floating gate of the floating gate transistor is full of holes, the floating gate transistor remains conducting, and the first capacitor discharges externally, maintaining the port voltage of the flash memory chip higher than its minimum operating voltage for a period of time.

[0155] The first capacitor continues to discharge externally until it is completely discharged. When the power supply line voltage is lower than the forward conduction voltage of the diode plus the reverse conduction voltage, the diode pair turns off, and the voltage on the second capacitor is maintained at a voltage value. When the electricity in the first capacitor is completely discharged, the voltage on the second capacitor will inject electrons into the floating gate, neutralize the holes in the floating gate, and fill the floating gate with electrons. At this time, the floating gate transistor will be in the off state, waiting for the next circuit startup.

[0156] Therefore, the circuit of the present invention is simple. Only one floating gate transistor, two diodes and two capacitors are needed to ensure that the flash starts quickly when the power supply starts, and when the power supply (accidentally) disconnects, the VCC voltage drops slowly, ensuring that the flash completes the current read and write operations and avoiding chip damage caused by accidental power-off during the chip read and write stage. This circuit can also be extended to the protection of hard disks and high-value electrical appliances.

[0157] In the embodiment of the present invention, through the method in the embodiment of the present invention, the capacitor and the flash memory chip are located based on the traversal of the circuit; the capacitor is associated with the flash memory chip and the power supply of the circuit, and multiple power supply paths of the flash memory chip are defined; the state of the circuit is monitored in real time; when the circuit is in the working state, the charging of the capacitor is triggered based on the power supply of the circuit, ensuring the charging of the capacitor for the power supply of the flash memory chip, and making full use of the power supply of the circuit and the working state of the circuit.

[0158] Furthermore, according to the data to be written in the flash memory chip, the power of the capacitor, and the power supply path, the corresponding power supply mode is defined; the power supply of the capacitor to the flash memory chip is triggered based on this power supply mode, the writing path of the flash memory chip is dynamically optimized based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written, and different levels of control are performed on the data to be written according to the optimized writing path and the storage space of the flash memory chip, ensuring the full writing of the data to be written into the flash memory chip, and performing control on the writing path and different levels of control on the writing process of the flash memory chip, improving the writing effect of the flash memory chip based on circuit power-off.

[0159] Please refer toFigure 8 , Figure 8 It is a schematic diagram of the structural composition of the write system of the flash memory chip based on circuit power-off in the embodiments of the present invention.

[0160] As Figure 8 shown, a write system for a flash memory chip based on circuit power-off, the write system for the flash memory chip based on circuit power-off includes:

[0161] A positioning module 21, configured to locate the capacitor and the flash memory chip based on the traversal of the circuit;

[0162] A power supply path module 22, configured to associate the capacitor and the power supply of the circuit with the flash memory chip, and define multiple power supply paths for the flash memory chip;

[0163] A monitoring module 23, configured to monitor the state of the circuit in real time;

[0164] A charging module 24, configured to trigger the charging of the capacitor based on the power supply of the circuit when the circuit is in a working state;

[0165] A power supply module 25, configured to define a corresponding power supply mode according to the data to be written in the flash memory chip, the power of the capacitor, and the power supply path;

[0166] A writing module 26, configured to trigger the power supply of the capacitor to the flash memory chip based on the power supply mode, dynamically optimize the writing path of the flash memory chip based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip, and the data to be written, and perform different-level control on the data to be written according to the optimized writing path and the storage space of the flash memory chip.

[0167] The above has introduced in detail the write method and system for the flash memory chip based on circuit power-off provided by the embodiments of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A flash memory chip writing method based on circuit power off, characterized in that: Applicable to flash memory chip writing scenarios based on circuit power failure; The flash memory chip writing method based on circuit power-off includes: Locating capacitors and flash memory chips based on circuit traversal; The flash memory chip is associated with capacitors and power supplies of the circuit, and multiple power supply paths of the flash memory chip are defined; Monitor the status of the circuit in real time; When the circuit is in working state, the charging of the capacitor is triggered based on the power supply of the circuit; Define a corresponding power supply mode according to the data to be written in the flash memory chip, the amount of electricity of the capacitor, and the power supply path; Based on this power supply mode, the capacitor is triggered to supply power to the flash memory chip. The write path of the flash memory chip is dynamically optimized based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip and the data to be written. Different levels of control are performed on the data to be written according to the optimized write path and the storage space of the flash memory chip.

2. The flash memory chip writing method based on circuit power off according to claim 1, characterized in that: The method of locating capacitors and flash memory chips based on circuit traversal includes: The location of the acquisition circuit; Defining a corresponding traversal model according to the detection of the location of the circuit; Triggering circuit traversal based on the circuit and traversal model; Capacitors and flash memory chips are positioned according to the circuit traversal.

3. The flash memory chip writing method based on circuit power off according to claim 2, characterized in that: The flash memory chip is associated with a capacitor and a power supply of a circuit, and defines multiple power supply paths of the flash memory chip, including: Freeze the circuit and collect the power supply and capacitance of the circuit; Collect the flash memory chip, connect the flash memory chip to the capacitor and the power supply of the circuit; A plurality of associated paths are formed based on the flash memory chip, the capacitor, and the power supply of the circuit; Identify multiple association paths; A plurality of power supply paths of the flash memory chip are defined based on the identification of the plurality of associated paths.

4. The flash memory chip writing method based on circuit power off according to claim 3, characterized in that: The state of the real-time monitoring circuit includes: Fixed frame circuit; Collect the working parameters of the circuit at different positions; Defining the state of the circuit based on a plurality of working parameters and corresponding positions, the state of the circuit including a working state and a power-off state; Real-time monitoring of the circuit status.

5. The flash memory chip writing method based on circuit power off according to claim 4, characterized in that: The charging of the capacitor based on the power supply of the circuit when the circuit is in the working state includes: Acquisition circuit status; When the circuit is in working state, the power supply of the circuit is fixed; Power supplies and capacitors for associated circuits; Locate the circuit's power supply and the power supply path between capacitors; Charging of the capacitor is triggered based on the power supply path.

6. The flash memory chip writing method based on circuit power off according to claim 5, characterized in that: Defining a corresponding power supply mode according to the data to be written in the flash memory chip, the amount of electricity of the capacitor, and the power supply path includes: Rated capacitance; Collect the electric quantity of the capacitor; The data to be written in the flash memory chip, the amount of electricity in the capacitor, and the power supply path are associated.

7. The flash memory chip writing method based on circuit power off according to claim 6, characterized in that: The method further comprises: defining a corresponding power supply mode according to the data to be written in the flash memory chip, the amount of electricity of the capacitor, and the power supply path; Defining first mode parameters according to the data to be written in the flash memory chip and the amount of electricity of the capacitor; Defining the second mode parameters according to the amount of electricity of the capacitor and the power supply path; A corresponding power supply mode is defined according to the first mode parameter and the second mode parameter.

8. The flash memory chip writing method based on circuit power off according to claim 7, characterized in that: The power supply of the capacitor to the flash memory chip is triggered based on the power supply mode, the write path of the flash memory chip is dynamically optimized based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip and the data to be written, and different levels of control are performed on the data to be written according to the optimized write path and the storage space of the flash memory chip, including: Freeze the power supply mode; The capacitor is triggered to supply power to the flash memory chip according to the power supply mode; Temporary protection of the flash memory chip is achieved by supplying power to the flash memory chip based on the capacitor.

9. The flash memory chip writing method based on circuit power off according to claim 8, characterized in that: The power supply of the capacitor to the flash memory chip is triggered based on the power supply mode, the write path of the flash memory chip is dynamically optimized based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip and the data to be written, and different levels of control are performed on the data to be written according to the optimized write path and the storage space of the flash memory chip, and also includes: The power consumption efficiency of the associated capacitor, the storage space of the flash memory chip, and the data to be written; Dynamically optimize the writing path of the flash memory chip according to the power consumption efficiency of the capacitor, the storage space of the flash memory chip and the data to be written; Based on the optimized write path and the storage space of the flash memory chip, different levels of management and control are performed on the data to be written.

10. A flash memory chip writing system based on circuit power off, characterized in that: The flash memory chip writing system based on circuit power failure is applied to the flash memory chip writing method based on circuit power failure as claimed in any one of claims 1 to 9, and the flash memory chip writing system based on circuit power failure includes: A positioning module, used for locating capacitors and flash memory chips based on circuit traversal; A power supply path module is used for the power supply of the capacitors and circuits associated with the flash memory chip, and defines multiple power supply paths for the flash memory chip; A monitoring module, used to monitor the status of the circuit in real time; A charging module, used for triggering the charging of the capacitor based on the power supply of the circuit when the circuit is in working state; A power supply module, used to define a corresponding power supply mode according to the data to be written in the flash memory chip, the amount of electricity of the capacitor, and the power supply path; The write module is used to trigger the capacitor to supply power to the flash memory chip based on the power supply mode, dynamically optimize the write path of the flash memory chip based on the power consumption efficiency of the capacitor, the storage space of the flash memory chip and the data to be written, and perform different levels of management and control on the data to be written according to the optimized write path and the storage space of the flash memory chip.

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